smp.c 10 KB

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  1. /*
  2. * SMP initialisation and IPI support
  3. * Based on arch/arm/kernel/smp.c
  4. *
  5. * Copyright (C) 2012 ARM Ltd.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include <linux/delay.h>
  20. #include <linux/init.h>
  21. #include <linux/spinlock.h>
  22. #include <linux/sched.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/cache.h>
  25. #include <linux/profile.h>
  26. #include <linux/errno.h>
  27. #include <linux/mm.h>
  28. #include <linux/err.h>
  29. #include <linux/cpu.h>
  30. #include <linux/smp.h>
  31. #include <linux/seq_file.h>
  32. #include <linux/irq.h>
  33. #include <linux/percpu.h>
  34. #include <linux/clockchips.h>
  35. #include <linux/completion.h>
  36. #include <linux/of.h>
  37. #include <asm/atomic.h>
  38. #include <asm/cacheflush.h>
  39. #include <asm/cputype.h>
  40. #include <asm/mmu_context.h>
  41. #include <asm/pgtable.h>
  42. #include <asm/pgalloc.h>
  43. #include <asm/processor.h>
  44. #include <asm/sections.h>
  45. #include <asm/tlbflush.h>
  46. #include <asm/ptrace.h>
  47. /*
  48. * as from 2.5, kernels no longer have an init_tasks structure
  49. * so we need some other way of telling a new secondary core
  50. * where to place its SVC stack
  51. */
  52. struct secondary_data secondary_data;
  53. volatile unsigned long secondary_holding_pen_release = -1;
  54. enum ipi_msg_type {
  55. IPI_RESCHEDULE,
  56. IPI_CALL_FUNC,
  57. IPI_CALL_FUNC_SINGLE,
  58. IPI_CPU_STOP,
  59. };
  60. static DEFINE_RAW_SPINLOCK(boot_lock);
  61. /*
  62. * Write secondary_holding_pen_release in a way that is guaranteed to be
  63. * visible to all observers, irrespective of whether they're taking part
  64. * in coherency or not. This is necessary for the hotplug code to work
  65. * reliably.
  66. */
  67. static void __cpuinit write_pen_release(int val)
  68. {
  69. void *start = (void *)&secondary_holding_pen_release;
  70. unsigned long size = sizeof(secondary_holding_pen_release);
  71. secondary_holding_pen_release = val;
  72. __flush_dcache_area(start, size);
  73. }
  74. /*
  75. * Boot a secondary CPU, and assign it the specified idle task.
  76. * This also gives us the initial stack to use for this CPU.
  77. */
  78. static int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
  79. {
  80. unsigned long timeout;
  81. /*
  82. * Set synchronisation state between this boot processor
  83. * and the secondary one
  84. */
  85. raw_spin_lock(&boot_lock);
  86. /*
  87. * Update the pen release flag.
  88. */
  89. write_pen_release(cpu);
  90. /*
  91. * Send an event, causing the secondaries to read pen_release.
  92. */
  93. sev();
  94. timeout = jiffies + (1 * HZ);
  95. while (time_before(jiffies, timeout)) {
  96. if (secondary_holding_pen_release == -1UL)
  97. break;
  98. udelay(10);
  99. }
  100. /*
  101. * Now the secondary core is starting up let it run its
  102. * calibrations, then wait for it to finish
  103. */
  104. raw_spin_unlock(&boot_lock);
  105. return secondary_holding_pen_release != -1 ? -ENOSYS : 0;
  106. }
  107. static DECLARE_COMPLETION(cpu_running);
  108. int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
  109. {
  110. int ret;
  111. /*
  112. * We need to tell the secondary core where to find its stack and the
  113. * page tables.
  114. */
  115. secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
  116. __flush_dcache_area(&secondary_data, sizeof(secondary_data));
  117. /*
  118. * Now bring the CPU into our world.
  119. */
  120. ret = boot_secondary(cpu, idle);
  121. if (ret == 0) {
  122. /*
  123. * CPU was successfully started, wait for it to come online or
  124. * time out.
  125. */
  126. wait_for_completion_timeout(&cpu_running,
  127. msecs_to_jiffies(1000));
  128. if (!cpu_online(cpu)) {
  129. pr_crit("CPU%u: failed to come online\n", cpu);
  130. ret = -EIO;
  131. }
  132. } else {
  133. pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
  134. }
  135. secondary_data.stack = NULL;
  136. return ret;
  137. }
  138. /*
  139. * This is the secondary CPU boot entry. We're using this CPUs
  140. * idle thread stack, but a set of temporary page tables.
  141. */
  142. asmlinkage void __cpuinit secondary_start_kernel(void)
  143. {
  144. struct mm_struct *mm = &init_mm;
  145. unsigned int cpu = smp_processor_id();
  146. printk("CPU%u: Booted secondary processor\n", cpu);
  147. /*
  148. * All kernel threads share the same mm context; grab a
  149. * reference and switch to it.
  150. */
  151. atomic_inc(&mm->mm_count);
  152. current->active_mm = mm;
  153. cpumask_set_cpu(cpu, mm_cpumask(mm));
  154. /*
  155. * TTBR0 is only used for the identity mapping at this stage. Make it
  156. * point to zero page to avoid speculatively fetching new entries.
  157. */
  158. cpu_set_reserved_ttbr0();
  159. flush_tlb_all();
  160. preempt_disable();
  161. trace_hardirqs_off();
  162. /*
  163. * Let the primary processor know we're out of the
  164. * pen, then head off into the C entry point
  165. */
  166. write_pen_release(-1);
  167. /*
  168. * Synchronise with the boot thread.
  169. */
  170. raw_spin_lock(&boot_lock);
  171. raw_spin_unlock(&boot_lock);
  172. /*
  173. * Enable local interrupts.
  174. */
  175. notify_cpu_starting(cpu);
  176. local_irq_enable();
  177. local_fiq_enable();
  178. /*
  179. * OK, now it's safe to let the boot CPU continue. Wait for
  180. * the CPU migration code to notice that the CPU is online
  181. * before we continue.
  182. */
  183. set_cpu_online(cpu, true);
  184. complete(&cpu_running);
  185. /*
  186. * OK, it's off to the idle thread for us
  187. */
  188. cpu_idle();
  189. }
  190. void __init smp_cpus_done(unsigned int max_cpus)
  191. {
  192. unsigned long bogosum = loops_per_jiffy * num_online_cpus();
  193. pr_info("SMP: Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
  194. num_online_cpus(), bogosum / (500000/HZ),
  195. (bogosum / (5000/HZ)) % 100);
  196. }
  197. void __init smp_prepare_boot_cpu(void)
  198. {
  199. }
  200. static void (*smp_cross_call)(const struct cpumask *, unsigned int);
  201. static phys_addr_t cpu_release_addr[NR_CPUS];
  202. /*
  203. * Enumerate the possible CPU set from the device tree.
  204. */
  205. void __init smp_init_cpus(void)
  206. {
  207. const char *enable_method;
  208. struct device_node *dn = NULL;
  209. int cpu = 0;
  210. while ((dn = of_find_node_by_type(dn, "cpu"))) {
  211. if (cpu >= NR_CPUS)
  212. goto next;
  213. /*
  214. * We currently support only the "spin-table" enable-method.
  215. */
  216. enable_method = of_get_property(dn, "enable-method", NULL);
  217. if (!enable_method || strcmp(enable_method, "spin-table")) {
  218. pr_err("CPU %d: missing or invalid enable-method property: %s\n",
  219. cpu, enable_method);
  220. goto next;
  221. }
  222. /*
  223. * Determine the address from which the CPU is polling.
  224. */
  225. if (of_property_read_u64(dn, "cpu-release-addr",
  226. &cpu_release_addr[cpu])) {
  227. pr_err("CPU %d: missing or invalid cpu-release-addr property\n",
  228. cpu);
  229. goto next;
  230. }
  231. set_cpu_possible(cpu, true);
  232. next:
  233. cpu++;
  234. }
  235. /* sanity check */
  236. if (cpu > NR_CPUS)
  237. pr_warning("no. of cores (%d) greater than configured maximum of %d - clipping\n",
  238. cpu, NR_CPUS);
  239. }
  240. void __init smp_prepare_cpus(unsigned int max_cpus)
  241. {
  242. int cpu;
  243. void **release_addr;
  244. unsigned int ncores = num_possible_cpus();
  245. /*
  246. * are we trying to boot more cores than exist?
  247. */
  248. if (max_cpus > ncores)
  249. max_cpus = ncores;
  250. /*
  251. * Initialise the present map (which describes the set of CPUs
  252. * actually populated at the present time) and release the
  253. * secondaries from the bootloader.
  254. */
  255. for_each_possible_cpu(cpu) {
  256. if (max_cpus == 0)
  257. break;
  258. if (!cpu_release_addr[cpu])
  259. continue;
  260. release_addr = __va(cpu_release_addr[cpu]);
  261. release_addr[0] = (void *)__pa(secondary_holding_pen);
  262. __flush_dcache_area(release_addr, sizeof(release_addr[0]));
  263. set_cpu_present(cpu, true);
  264. max_cpus--;
  265. }
  266. /*
  267. * Send an event to wake up the secondaries.
  268. */
  269. sev();
  270. }
  271. void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
  272. {
  273. smp_cross_call = fn;
  274. }
  275. void arch_send_call_function_ipi_mask(const struct cpumask *mask)
  276. {
  277. smp_cross_call(mask, IPI_CALL_FUNC);
  278. }
  279. void arch_send_call_function_single_ipi(int cpu)
  280. {
  281. smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE);
  282. }
  283. static const char *ipi_types[NR_IPI] = {
  284. #define S(x,s) [x - IPI_RESCHEDULE] = s
  285. S(IPI_RESCHEDULE, "Rescheduling interrupts"),
  286. S(IPI_CALL_FUNC, "Function call interrupts"),
  287. S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts"),
  288. S(IPI_CPU_STOP, "CPU stop interrupts"),
  289. };
  290. void show_ipi_list(struct seq_file *p, int prec)
  291. {
  292. unsigned int cpu, i;
  293. for (i = 0; i < NR_IPI; i++) {
  294. seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i + IPI_RESCHEDULE,
  295. prec >= 4 ? " " : "");
  296. for_each_present_cpu(cpu)
  297. seq_printf(p, "%10u ",
  298. __get_irq_stat(cpu, ipi_irqs[i]));
  299. seq_printf(p, " %s\n", ipi_types[i]);
  300. }
  301. }
  302. u64 smp_irq_stat_cpu(unsigned int cpu)
  303. {
  304. u64 sum = 0;
  305. int i;
  306. for (i = 0; i < NR_IPI; i++)
  307. sum += __get_irq_stat(cpu, ipi_irqs[i]);
  308. return sum;
  309. }
  310. static DEFINE_RAW_SPINLOCK(stop_lock);
  311. /*
  312. * ipi_cpu_stop - handle IPI from smp_send_stop()
  313. */
  314. static void ipi_cpu_stop(unsigned int cpu)
  315. {
  316. if (system_state == SYSTEM_BOOTING ||
  317. system_state == SYSTEM_RUNNING) {
  318. raw_spin_lock(&stop_lock);
  319. pr_crit("CPU%u: stopping\n", cpu);
  320. dump_stack();
  321. raw_spin_unlock(&stop_lock);
  322. }
  323. set_cpu_online(cpu, false);
  324. local_fiq_disable();
  325. local_irq_disable();
  326. while (1)
  327. cpu_relax();
  328. }
  329. /*
  330. * Main handler for inter-processor interrupts
  331. */
  332. void handle_IPI(int ipinr, struct pt_regs *regs)
  333. {
  334. unsigned int cpu = smp_processor_id();
  335. struct pt_regs *old_regs = set_irq_regs(regs);
  336. if (ipinr >= IPI_RESCHEDULE && ipinr < IPI_RESCHEDULE + NR_IPI)
  337. __inc_irq_stat(cpu, ipi_irqs[ipinr - IPI_RESCHEDULE]);
  338. switch (ipinr) {
  339. case IPI_RESCHEDULE:
  340. scheduler_ipi();
  341. break;
  342. case IPI_CALL_FUNC:
  343. irq_enter();
  344. generic_smp_call_function_interrupt();
  345. irq_exit();
  346. break;
  347. case IPI_CALL_FUNC_SINGLE:
  348. irq_enter();
  349. generic_smp_call_function_single_interrupt();
  350. irq_exit();
  351. break;
  352. case IPI_CPU_STOP:
  353. irq_enter();
  354. ipi_cpu_stop(cpu);
  355. irq_exit();
  356. break;
  357. default:
  358. pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr);
  359. break;
  360. }
  361. set_irq_regs(old_regs);
  362. }
  363. void smp_send_reschedule(int cpu)
  364. {
  365. smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
  366. }
  367. void smp_send_stop(void)
  368. {
  369. unsigned long timeout;
  370. if (num_online_cpus() > 1) {
  371. cpumask_t mask;
  372. cpumask_copy(&mask, cpu_online_mask);
  373. cpu_clear(smp_processor_id(), mask);
  374. smp_cross_call(&mask, IPI_CPU_STOP);
  375. }
  376. /* Wait up to one second for other CPUs to stop */
  377. timeout = USEC_PER_SEC;
  378. while (num_online_cpus() > 1 && timeout--)
  379. udelay(1);
  380. if (num_online_cpus() > 1)
  381. pr_warning("SMP: failed to stop secondary CPUs\n");
  382. }
  383. /*
  384. * not supported here
  385. */
  386. int setup_profiling_timer(unsigned int multiplier)
  387. {
  388. return -EINVAL;
  389. }