tlbflush.h 3.2 KB

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  1. /*
  2. * Based on arch/arm/include/asm/tlbflush.h
  3. *
  4. * Copyright (C) 1999-2003 Russell King
  5. * Copyright (C) 2012 ARM Ltd.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #ifndef __ASM_TLBFLUSH_H
  20. #define __ASM_TLBFLUSH_H
  21. #ifndef __ASSEMBLY__
  22. #include <linux/sched.h>
  23. #include <asm/cputype.h>
  24. extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
  25. extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);
  26. extern struct cpu_tlb_fns cpu_tlb;
  27. /*
  28. * TLB Management
  29. * ==============
  30. *
  31. * The arch/arm64/mm/tlb.S files implement these methods.
  32. *
  33. * The TLB specific code is expected to perform whatever tests it needs
  34. * to determine if it should invalidate the TLB for each call. Start
  35. * addresses are inclusive and end addresses are exclusive; it is safe to
  36. * round these addresses down.
  37. *
  38. * flush_tlb_all()
  39. *
  40. * Invalidate the entire TLB.
  41. *
  42. * flush_tlb_mm(mm)
  43. *
  44. * Invalidate all TLB entries in a particular address space.
  45. * - mm - mm_struct describing address space
  46. *
  47. * flush_tlb_range(mm,start,end)
  48. *
  49. * Invalidate a range of TLB entries in the specified address
  50. * space.
  51. * - mm - mm_struct describing address space
  52. * - start - start address (may not be aligned)
  53. * - end - end address (exclusive, may not be aligned)
  54. *
  55. * flush_tlb_page(vaddr,vma)
  56. *
  57. * Invalidate the specified page in the specified address range.
  58. * - vaddr - virtual address (may not be aligned)
  59. * - vma - vma_struct describing address range
  60. *
  61. * flush_kern_tlb_page(kaddr)
  62. *
  63. * Invalidate the TLB entry for the specified page. The address
  64. * will be in the kernels virtual memory space. Current uses
  65. * only require the D-TLB to be invalidated.
  66. * - kaddr - Kernel virtual memory address
  67. */
  68. static inline void flush_tlb_all(void)
  69. {
  70. dsb();
  71. asm("tlbi vmalle1is");
  72. dsb();
  73. isb();
  74. }
  75. static inline void flush_tlb_mm(struct mm_struct *mm)
  76. {
  77. unsigned long asid = (unsigned long)ASID(mm) << 48;
  78. dsb();
  79. asm("tlbi aside1is, %0" : : "r" (asid));
  80. dsb();
  81. }
  82. static inline void flush_tlb_page(struct vm_area_struct *vma,
  83. unsigned long uaddr)
  84. {
  85. unsigned long addr = uaddr >> 12 |
  86. ((unsigned long)ASID(vma->vm_mm) << 48);
  87. dsb();
  88. asm("tlbi vae1is, %0" : : "r" (addr));
  89. dsb();
  90. }
  91. /*
  92. * Convert calls to our calling convention.
  93. */
  94. #define flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma)
  95. #define flush_tlb_kernel_range(s,e) __cpu_flush_kern_tlb_range(s,e)
  96. /*
  97. * On AArch64, the cache coherency is handled via the set_pte_at() function.
  98. */
  99. static inline void update_mmu_cache(struct vm_area_struct *vma,
  100. unsigned long addr, pte_t *ptep)
  101. {
  102. /*
  103. * set_pte() does not have a DSB, so make sure that the page table
  104. * write is visible.
  105. */
  106. dsb();
  107. }
  108. #endif
  109. #endif