cpu-tegra.c 6.6 KB

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  1. /*
  2. * arch/arm/mach-tegra/cpu-tegra.c
  3. *
  4. * Copyright (C) 2010 Google, Inc.
  5. *
  6. * Author:
  7. * Colin Cross <ccross@google.com>
  8. * Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
  9. *
  10. * This software is licensed under the terms of the GNU General Public
  11. * License version 2, as published by the Free Software Foundation, and
  12. * may be copied, distributed, and modified under those terms.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/module.h>
  22. #include <linux/types.h>
  23. #include <linux/sched.h>
  24. #include <linux/cpufreq.h>
  25. #include <linux/delay.h>
  26. #include <linux/init.h>
  27. #include <linux/err.h>
  28. #include <linux/clk.h>
  29. #include <linux/io.h>
  30. #include <linux/suspend.h>
  31. /* Frequency table index must be sequential starting at 0 */
  32. static struct cpufreq_frequency_table freq_table[] = {
  33. { 0, 216000 },
  34. { 1, 312000 },
  35. { 2, 456000 },
  36. { 3, 608000 },
  37. { 4, 760000 },
  38. { 5, 816000 },
  39. { 6, 912000 },
  40. { 7, 1000000 },
  41. { 8, CPUFREQ_TABLE_END },
  42. };
  43. #define NUM_CPUS 2
  44. static struct clk *cpu_clk;
  45. static struct clk *pll_x_clk;
  46. static struct clk *pll_p_clk;
  47. static struct clk *emc_clk;
  48. static unsigned long target_cpu_speed[NUM_CPUS];
  49. static DEFINE_MUTEX(tegra_cpu_lock);
  50. static bool is_suspended;
  51. static int tegra_verify_speed(struct cpufreq_policy *policy)
  52. {
  53. return cpufreq_frequency_table_verify(policy, freq_table);
  54. }
  55. static unsigned int tegra_getspeed(unsigned int cpu)
  56. {
  57. unsigned long rate;
  58. if (cpu >= NUM_CPUS)
  59. return 0;
  60. rate = clk_get_rate(cpu_clk) / 1000;
  61. return rate;
  62. }
  63. static int tegra_cpu_clk_set_rate(unsigned long rate)
  64. {
  65. int ret;
  66. /*
  67. * Take an extra reference to the main pll so it doesn't turn
  68. * off when we move the cpu off of it
  69. */
  70. clk_prepare_enable(pll_x_clk);
  71. ret = clk_set_parent(cpu_clk, pll_p_clk);
  72. if (ret) {
  73. pr_err("Failed to switch cpu to clock pll_p\n");
  74. goto out;
  75. }
  76. if (rate == clk_get_rate(pll_p_clk))
  77. goto out;
  78. ret = clk_set_rate(pll_x_clk, rate);
  79. if (ret) {
  80. pr_err("Failed to change pll_x to %lu\n", rate);
  81. goto out;
  82. }
  83. ret = clk_set_parent(cpu_clk, pll_x_clk);
  84. if (ret) {
  85. pr_err("Failed to switch cpu to clock pll_x\n");
  86. goto out;
  87. }
  88. out:
  89. clk_disable_unprepare(pll_x_clk);
  90. return ret;
  91. }
  92. static int tegra_update_cpu_speed(unsigned long rate)
  93. {
  94. int ret = 0;
  95. struct cpufreq_freqs freqs;
  96. freqs.old = tegra_getspeed(0);
  97. freqs.new = rate;
  98. if (freqs.old == freqs.new)
  99. return ret;
  100. /*
  101. * Vote on memory bus frequency based on cpu frequency
  102. * This sets the minimum frequency, display or avp may request higher
  103. */
  104. if (rate >= 816000)
  105. clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
  106. else if (rate >= 456000)
  107. clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
  108. else
  109. clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */
  110. for_each_online_cpu(freqs.cpu)
  111. cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
  112. #ifdef CONFIG_CPU_FREQ_DEBUG
  113. printk(KERN_DEBUG "cpufreq-tegra: transition: %u --> %u\n",
  114. freqs.old, freqs.new);
  115. #endif
  116. ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
  117. if (ret) {
  118. pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
  119. freqs.new);
  120. return ret;
  121. }
  122. for_each_online_cpu(freqs.cpu)
  123. cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
  124. return 0;
  125. }
  126. static unsigned long tegra_cpu_highest_speed(void)
  127. {
  128. unsigned long rate = 0;
  129. int i;
  130. for_each_online_cpu(i)
  131. rate = max(rate, target_cpu_speed[i]);
  132. return rate;
  133. }
  134. static int tegra_target(struct cpufreq_policy *policy,
  135. unsigned int target_freq,
  136. unsigned int relation)
  137. {
  138. unsigned int idx;
  139. unsigned int freq;
  140. int ret = 0;
  141. mutex_lock(&tegra_cpu_lock);
  142. if (is_suspended) {
  143. ret = -EBUSY;
  144. goto out;
  145. }
  146. cpufreq_frequency_table_target(policy, freq_table, target_freq,
  147. relation, &idx);
  148. freq = freq_table[idx].frequency;
  149. target_cpu_speed[policy->cpu] = freq;
  150. ret = tegra_update_cpu_speed(tegra_cpu_highest_speed());
  151. out:
  152. mutex_unlock(&tegra_cpu_lock);
  153. return ret;
  154. }
  155. static int tegra_pm_notify(struct notifier_block *nb, unsigned long event,
  156. void *dummy)
  157. {
  158. mutex_lock(&tegra_cpu_lock);
  159. if (event == PM_SUSPEND_PREPARE) {
  160. is_suspended = true;
  161. pr_info("Tegra cpufreq suspend: setting frequency to %d kHz\n",
  162. freq_table[0].frequency);
  163. tegra_update_cpu_speed(freq_table[0].frequency);
  164. } else if (event == PM_POST_SUSPEND) {
  165. is_suspended = false;
  166. }
  167. mutex_unlock(&tegra_cpu_lock);
  168. return NOTIFY_OK;
  169. }
  170. static struct notifier_block tegra_cpu_pm_notifier = {
  171. .notifier_call = tegra_pm_notify,
  172. };
  173. static int tegra_cpu_init(struct cpufreq_policy *policy)
  174. {
  175. if (policy->cpu >= NUM_CPUS)
  176. return -EINVAL;
  177. cpu_clk = clk_get_sys(NULL, "cpu");
  178. if (IS_ERR(cpu_clk))
  179. return PTR_ERR(cpu_clk);
  180. pll_x_clk = clk_get_sys(NULL, "pll_x");
  181. if (IS_ERR(pll_x_clk))
  182. return PTR_ERR(pll_x_clk);
  183. pll_p_clk = clk_get_sys(NULL, "pll_p");
  184. if (IS_ERR(pll_p_clk))
  185. return PTR_ERR(pll_p_clk);
  186. emc_clk = clk_get_sys("cpu", "emc");
  187. if (IS_ERR(emc_clk)) {
  188. clk_put(cpu_clk);
  189. return PTR_ERR(emc_clk);
  190. }
  191. clk_prepare_enable(emc_clk);
  192. clk_prepare_enable(cpu_clk);
  193. cpufreq_frequency_table_cpuinfo(policy, freq_table);
  194. cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
  195. policy->cur = tegra_getspeed(policy->cpu);
  196. target_cpu_speed[policy->cpu] = policy->cur;
  197. /* FIXME: what's the actual transition time? */
  198. policy->cpuinfo.transition_latency = 300 * 1000;
  199. policy->shared_type = CPUFREQ_SHARED_TYPE_ALL;
  200. cpumask_copy(policy->related_cpus, cpu_possible_mask);
  201. if (policy->cpu == 0)
  202. register_pm_notifier(&tegra_cpu_pm_notifier);
  203. return 0;
  204. }
  205. static int tegra_cpu_exit(struct cpufreq_policy *policy)
  206. {
  207. cpufreq_frequency_table_cpuinfo(policy, freq_table);
  208. clk_disable_unprepare(emc_clk);
  209. clk_put(emc_clk);
  210. clk_put(cpu_clk);
  211. return 0;
  212. }
  213. static struct freq_attr *tegra_cpufreq_attr[] = {
  214. &cpufreq_freq_attr_scaling_available_freqs,
  215. NULL,
  216. };
  217. static struct cpufreq_driver tegra_cpufreq_driver = {
  218. .verify = tegra_verify_speed,
  219. .target = tegra_target,
  220. .get = tegra_getspeed,
  221. .init = tegra_cpu_init,
  222. .exit = tegra_cpu_exit,
  223. .name = "tegra",
  224. .attr = tegra_cpufreq_attr,
  225. };
  226. static int __init tegra_cpufreq_init(void)
  227. {
  228. return cpufreq_register_driver(&tegra_cpufreq_driver);
  229. }
  230. static void __exit tegra_cpufreq_exit(void)
  231. {
  232. cpufreq_unregister_driver(&tegra_cpufreq_driver);
  233. }
  234. MODULE_AUTHOR("Colin Cross <ccross@android.com>");
  235. MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
  236. MODULE_LICENSE("GPL");
  237. module_init(tegra_cpufreq_init);
  238. module_exit(tegra_cpufreq_exit);