board-3430sdp.c 15 KB

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  1. /*
  2. * linux/arch/arm/mach-omap2/board-3430sdp.c
  3. *
  4. * Copyright (C) 2007 Texas Instruments
  5. *
  6. * Modified from mach-omap2/board-generic.c
  7. *
  8. * Initial code: Syed Mohammed Khasim
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/delay.h>
  18. #include <linux/input.h>
  19. #include <linux/input/matrix_keypad.h>
  20. #include <linux/spi/spi.h>
  21. #include <linux/i2c/twl.h>
  22. #include <linux/regulator/machine.h>
  23. #include <linux/io.h>
  24. #include <linux/gpio.h>
  25. #include <linux/mmc/host.h>
  26. #include <linux/platform_data/spi-omap2-mcspi.h>
  27. #include <asm/mach-types.h>
  28. #include <asm/mach/arch.h>
  29. #include <asm/mach/map.h>
  30. #include "common.h"
  31. #include <linux/omap-dma.h>
  32. #include <video/omapdss.h>
  33. #include <video/omap-panel-tfp410.h>
  34. #include "gpmc.h"
  35. #include "gpmc-smc91x.h"
  36. #include "soc.h"
  37. #include "board-flash.h"
  38. #include "mux.h"
  39. #include "sdram-qimonda-hyb18m512160af-6.h"
  40. #include "hsmmc.h"
  41. #include "pm.h"
  42. #include "control.h"
  43. #include "common-board-devices.h"
  44. #define CONFIG_DISABLE_HFCLK 1
  45. #define SDP3430_TS_GPIO_IRQ_SDPV1 3
  46. #define SDP3430_TS_GPIO_IRQ_SDPV2 2
  47. #define ENABLE_VAUX3_DEDICATED 0x03
  48. #define ENABLE_VAUX3_DEV_GRP 0x20
  49. #define TWL4030_MSECURE_GPIO 22
  50. static uint32_t board_keymap[] = {
  51. KEY(0, 0, KEY_LEFT),
  52. KEY(0, 1, KEY_RIGHT),
  53. KEY(0, 2, KEY_A),
  54. KEY(0, 3, KEY_B),
  55. KEY(0, 4, KEY_C),
  56. KEY(1, 0, KEY_DOWN),
  57. KEY(1, 1, KEY_UP),
  58. KEY(1, 2, KEY_E),
  59. KEY(1, 3, KEY_F),
  60. KEY(1, 4, KEY_G),
  61. KEY(2, 0, KEY_ENTER),
  62. KEY(2, 1, KEY_I),
  63. KEY(2, 2, KEY_J),
  64. KEY(2, 3, KEY_K),
  65. KEY(2, 4, KEY_3),
  66. KEY(3, 0, KEY_M),
  67. KEY(3, 1, KEY_N),
  68. KEY(3, 2, KEY_O),
  69. KEY(3, 3, KEY_P),
  70. KEY(3, 4, KEY_Q),
  71. KEY(4, 0, KEY_R),
  72. KEY(4, 1, KEY_4),
  73. KEY(4, 2, KEY_T),
  74. KEY(4, 3, KEY_U),
  75. KEY(4, 4, KEY_D),
  76. KEY(5, 0, KEY_V),
  77. KEY(5, 1, KEY_W),
  78. KEY(5, 2, KEY_L),
  79. KEY(5, 3, KEY_S),
  80. KEY(5, 4, KEY_H),
  81. 0
  82. };
  83. static struct matrix_keymap_data board_map_data = {
  84. .keymap = board_keymap,
  85. .keymap_size = ARRAY_SIZE(board_keymap),
  86. };
  87. static struct twl4030_keypad_data sdp3430_kp_data = {
  88. .keymap_data = &board_map_data,
  89. .rows = 5,
  90. .cols = 6,
  91. .rep = 1,
  92. };
  93. #define SDP3430_LCD_PANEL_BACKLIGHT_GPIO 8
  94. #define SDP3430_LCD_PANEL_ENABLE_GPIO 5
  95. static struct gpio sdp3430_dss_gpios[] __initdata = {
  96. {SDP3430_LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW, "LCD reset" },
  97. {SDP3430_LCD_PANEL_BACKLIGHT_GPIO, GPIOF_OUT_INIT_LOW, "LCD Backlight"},
  98. };
  99. static void __init sdp3430_display_init(void)
  100. {
  101. int r;
  102. r = gpio_request_array(sdp3430_dss_gpios,
  103. ARRAY_SIZE(sdp3430_dss_gpios));
  104. if (r)
  105. printk(KERN_ERR "failed to get LCD control GPIOs\n");
  106. }
  107. static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev)
  108. {
  109. gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 1);
  110. gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 1);
  111. return 0;
  112. }
  113. static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev)
  114. {
  115. gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 0);
  116. gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 0);
  117. }
  118. static int sdp3430_panel_enable_tv(struct omap_dss_device *dssdev)
  119. {
  120. return 0;
  121. }
  122. static void sdp3430_panel_disable_tv(struct omap_dss_device *dssdev)
  123. {
  124. }
  125. static struct omap_dss_device sdp3430_lcd_device = {
  126. .name = "lcd",
  127. .driver_name = "sharp_ls_panel",
  128. .type = OMAP_DISPLAY_TYPE_DPI,
  129. .phy.dpi.data_lines = 16,
  130. .platform_enable = sdp3430_panel_enable_lcd,
  131. .platform_disable = sdp3430_panel_disable_lcd,
  132. };
  133. static struct tfp410_platform_data dvi_panel = {
  134. .power_down_gpio = -1,
  135. .i2c_bus_num = -1,
  136. };
  137. static struct omap_dss_device sdp3430_dvi_device = {
  138. .name = "dvi",
  139. .type = OMAP_DISPLAY_TYPE_DPI,
  140. .driver_name = "tfp410",
  141. .data = &dvi_panel,
  142. .phy.dpi.data_lines = 24,
  143. };
  144. static struct omap_dss_device sdp3430_tv_device = {
  145. .name = "tv",
  146. .driver_name = "venc",
  147. .type = OMAP_DISPLAY_TYPE_VENC,
  148. .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
  149. .platform_enable = sdp3430_panel_enable_tv,
  150. .platform_disable = sdp3430_panel_disable_tv,
  151. };
  152. static struct omap_dss_device *sdp3430_dss_devices[] = {
  153. &sdp3430_lcd_device,
  154. &sdp3430_dvi_device,
  155. &sdp3430_tv_device,
  156. };
  157. static struct omap_dss_board_info sdp3430_dss_data = {
  158. .num_devices = ARRAY_SIZE(sdp3430_dss_devices),
  159. .devices = sdp3430_dss_devices,
  160. .default_device = &sdp3430_lcd_device,
  161. };
  162. static struct omap2_hsmmc_info mmc[] = {
  163. {
  164. .mmc = 1,
  165. /* 8 bits (default) requires S6.3 == ON,
  166. * so the SIM card isn't used; else 4 bits.
  167. */
  168. .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
  169. .gpio_wp = 4,
  170. .deferred = true,
  171. },
  172. {
  173. .mmc = 2,
  174. .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
  175. .gpio_wp = 7,
  176. .deferred = true,
  177. },
  178. {} /* Terminator */
  179. };
  180. static int sdp3430_twl_gpio_setup(struct device *dev,
  181. unsigned gpio, unsigned ngpio)
  182. {
  183. /* gpio + 0 is "mmc0_cd" (input/IRQ),
  184. * gpio + 1 is "mmc1_cd" (input/IRQ)
  185. */
  186. mmc[0].gpio_cd = gpio + 0;
  187. mmc[1].gpio_cd = gpio + 1;
  188. omap_hsmmc_late_init(mmc);
  189. /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */
  190. gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "sub_lcd_en_bkl");
  191. /* gpio + 15 is "sub_lcd_nRST" (output) */
  192. gpio_request_one(gpio + 15, GPIOF_OUT_INIT_LOW, "sub_lcd_nRST");
  193. return 0;
  194. }
  195. static struct twl4030_gpio_platform_data sdp3430_gpio_data = {
  196. .pulldowns = BIT(2) | BIT(6) | BIT(8) | BIT(13)
  197. | BIT(16) | BIT(17),
  198. .setup = sdp3430_twl_gpio_setup,
  199. };
  200. /* regulator consumer mappings */
  201. /* ads7846 on SPI */
  202. static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
  203. REGULATOR_SUPPLY("vcc", "spi1.0"),
  204. };
  205. static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
  206. REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
  207. };
  208. static struct regulator_consumer_supply sdp3430_vsim_supplies[] = {
  209. REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
  210. };
  211. static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = {
  212. REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
  213. };
  214. /*
  215. * Apply all the fixed voltages since most versions of U-Boot
  216. * don't bother with that initialization.
  217. */
  218. /* VAUX1 for mainboard (irda and sub-lcd) */
  219. static struct regulator_init_data sdp3430_vaux1 = {
  220. .constraints = {
  221. .min_uV = 2800000,
  222. .max_uV = 2800000,
  223. .apply_uV = true,
  224. .valid_modes_mask = REGULATOR_MODE_NORMAL
  225. | REGULATOR_MODE_STANDBY,
  226. .valid_ops_mask = REGULATOR_CHANGE_MODE
  227. | REGULATOR_CHANGE_STATUS,
  228. },
  229. };
  230. /* VAUX2 for camera module */
  231. static struct regulator_init_data sdp3430_vaux2 = {
  232. .constraints = {
  233. .min_uV = 2800000,
  234. .max_uV = 2800000,
  235. .apply_uV = true,
  236. .valid_modes_mask = REGULATOR_MODE_NORMAL
  237. | REGULATOR_MODE_STANDBY,
  238. .valid_ops_mask = REGULATOR_CHANGE_MODE
  239. | REGULATOR_CHANGE_STATUS,
  240. },
  241. };
  242. /* VAUX3 for LCD board */
  243. static struct regulator_init_data sdp3430_vaux3 = {
  244. .constraints = {
  245. .min_uV = 2800000,
  246. .max_uV = 2800000,
  247. .apply_uV = true,
  248. .valid_modes_mask = REGULATOR_MODE_NORMAL
  249. | REGULATOR_MODE_STANDBY,
  250. .valid_ops_mask = REGULATOR_CHANGE_MODE
  251. | REGULATOR_CHANGE_STATUS,
  252. },
  253. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vaux3_supplies),
  254. .consumer_supplies = sdp3430_vaux3_supplies,
  255. };
  256. /* VAUX4 for OMAP VDD_CSI2 (camera) */
  257. static struct regulator_init_data sdp3430_vaux4 = {
  258. .constraints = {
  259. .min_uV = 1800000,
  260. .max_uV = 1800000,
  261. .apply_uV = true,
  262. .valid_modes_mask = REGULATOR_MODE_NORMAL
  263. | REGULATOR_MODE_STANDBY,
  264. .valid_ops_mask = REGULATOR_CHANGE_MODE
  265. | REGULATOR_CHANGE_STATUS,
  266. },
  267. };
  268. /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
  269. static struct regulator_init_data sdp3430_vmmc1 = {
  270. .constraints = {
  271. .min_uV = 1850000,
  272. .max_uV = 3150000,
  273. .valid_modes_mask = REGULATOR_MODE_NORMAL
  274. | REGULATOR_MODE_STANDBY,
  275. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
  276. | REGULATOR_CHANGE_MODE
  277. | REGULATOR_CHANGE_STATUS,
  278. },
  279. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc1_supplies),
  280. .consumer_supplies = sdp3430_vmmc1_supplies,
  281. };
  282. /* VMMC2 for MMC2 card */
  283. static struct regulator_init_data sdp3430_vmmc2 = {
  284. .constraints = {
  285. .min_uV = 1850000,
  286. .max_uV = 1850000,
  287. .apply_uV = true,
  288. .valid_modes_mask = REGULATOR_MODE_NORMAL
  289. | REGULATOR_MODE_STANDBY,
  290. .valid_ops_mask = REGULATOR_CHANGE_MODE
  291. | REGULATOR_CHANGE_STATUS,
  292. },
  293. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc2_supplies),
  294. .consumer_supplies = sdp3430_vmmc2_supplies,
  295. };
  296. /* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
  297. static struct regulator_init_data sdp3430_vsim = {
  298. .constraints = {
  299. .min_uV = 1800000,
  300. .max_uV = 3000000,
  301. .valid_modes_mask = REGULATOR_MODE_NORMAL
  302. | REGULATOR_MODE_STANDBY,
  303. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
  304. | REGULATOR_CHANGE_MODE
  305. | REGULATOR_CHANGE_STATUS,
  306. },
  307. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vsim_supplies),
  308. .consumer_supplies = sdp3430_vsim_supplies,
  309. };
  310. static struct twl4030_platform_data sdp3430_twldata = {
  311. /* platform_data for children goes here */
  312. .gpio = &sdp3430_gpio_data,
  313. .keypad = &sdp3430_kp_data,
  314. .vaux1 = &sdp3430_vaux1,
  315. .vaux2 = &sdp3430_vaux2,
  316. .vaux3 = &sdp3430_vaux3,
  317. .vaux4 = &sdp3430_vaux4,
  318. .vmmc1 = &sdp3430_vmmc1,
  319. .vmmc2 = &sdp3430_vmmc2,
  320. .vsim = &sdp3430_vsim,
  321. };
  322. static int __init omap3430_i2c_init(void)
  323. {
  324. /* i2c1 for PMIC only */
  325. omap3_pmic_get_config(&sdp3430_twldata,
  326. TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI |
  327. TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO,
  328. TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
  329. sdp3430_twldata.vdac->constraints.apply_uV = true;
  330. sdp3430_twldata.vpll2->constraints.apply_uV = true;
  331. sdp3430_twldata.vpll2->constraints.name = "VDVI";
  332. omap3_pmic_init("twl4030", &sdp3430_twldata);
  333. /* i2c2 on camera connector (for sensor control) and optional isp1301 */
  334. omap_register_i2c_bus(2, 400, NULL, 0);
  335. /* i2c3 on display connector (for DVI, tfp410) */
  336. omap_register_i2c_bus(3, 400, NULL, 0);
  337. return 0;
  338. }
  339. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  340. static struct omap_smc91x_platform_data board_smc91x_data = {
  341. .cs = 3,
  342. .flags = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 |
  343. IORESOURCE_IRQ_LOWLEVEL,
  344. };
  345. static void __init board_smc91x_init(void)
  346. {
  347. if (omap_rev() > OMAP3430_REV_ES1_0)
  348. board_smc91x_data.gpio_irq = 6;
  349. else
  350. board_smc91x_data.gpio_irq = 29;
  351. gpmc_smc91x_init(&board_smc91x_data);
  352. }
  353. #else
  354. static inline void board_smc91x_init(void)
  355. {
  356. }
  357. #endif
  358. static void enable_board_wakeup_source(void)
  359. {
  360. /* T2 interrupt line (keypad) */
  361. omap_mux_init_signal("sys_nirq",
  362. OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
  363. }
  364. static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
  365. .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
  366. .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
  367. .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
  368. .phy_reset = true,
  369. .reset_gpio_port[0] = 57,
  370. .reset_gpio_port[1] = 61,
  371. .reset_gpio_port[2] = -EINVAL
  372. };
  373. #ifdef CONFIG_OMAP_MUX
  374. static struct omap_board_mux board_mux[] __initdata = {
  375. { .reg_offset = OMAP_MUX_TERMINATOR },
  376. };
  377. #else
  378. #define board_mux NULL
  379. #endif
  380. /*
  381. * SDP3430 V2 Board CS organization
  382. * Different from SDP3430 V1. Now 4 switches used to specify CS
  383. *
  384. * See also the Switch S8 settings in the comments.
  385. */
  386. static char chip_sel_3430[][GPMC_CS_NUM] = {
  387. {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */
  388. {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */
  389. {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */
  390. };
  391. static struct mtd_partition sdp_nor_partitions[] = {
  392. /* bootloader (U-Boot, etc) in first sector */
  393. {
  394. .name = "Bootloader-NOR",
  395. .offset = 0,
  396. .size = SZ_256K,
  397. .mask_flags = MTD_WRITEABLE, /* force read-only */
  398. },
  399. /* bootloader params in the next sector */
  400. {
  401. .name = "Params-NOR",
  402. .offset = MTDPART_OFS_APPEND,
  403. .size = SZ_256K,
  404. .mask_flags = 0,
  405. },
  406. /* kernel */
  407. {
  408. .name = "Kernel-NOR",
  409. .offset = MTDPART_OFS_APPEND,
  410. .size = SZ_2M,
  411. .mask_flags = 0
  412. },
  413. /* file system */
  414. {
  415. .name = "Filesystem-NOR",
  416. .offset = MTDPART_OFS_APPEND,
  417. .size = MTDPART_SIZ_FULL,
  418. .mask_flags = 0
  419. }
  420. };
  421. static struct mtd_partition sdp_onenand_partitions[] = {
  422. {
  423. .name = "X-Loader-OneNAND",
  424. .offset = 0,
  425. .size = 4 * (64 * 2048),
  426. .mask_flags = MTD_WRITEABLE /* force read-only */
  427. },
  428. {
  429. .name = "U-Boot-OneNAND",
  430. .offset = MTDPART_OFS_APPEND,
  431. .size = 2 * (64 * 2048),
  432. .mask_flags = MTD_WRITEABLE /* force read-only */
  433. },
  434. {
  435. .name = "U-Boot Environment-OneNAND",
  436. .offset = MTDPART_OFS_APPEND,
  437. .size = 1 * (64 * 2048),
  438. },
  439. {
  440. .name = "Kernel-OneNAND",
  441. .offset = MTDPART_OFS_APPEND,
  442. .size = 16 * (64 * 2048),
  443. },
  444. {
  445. .name = "File System-OneNAND",
  446. .offset = MTDPART_OFS_APPEND,
  447. .size = MTDPART_SIZ_FULL,
  448. },
  449. };
  450. static struct mtd_partition sdp_nand_partitions[] = {
  451. /* All the partition sizes are listed in terms of NAND block size */
  452. {
  453. .name = "X-Loader-NAND",
  454. .offset = 0,
  455. .size = 4 * (64 * 2048),
  456. .mask_flags = MTD_WRITEABLE, /* force read-only */
  457. },
  458. {
  459. .name = "U-Boot-NAND",
  460. .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
  461. .size = 10 * (64 * 2048),
  462. .mask_flags = MTD_WRITEABLE, /* force read-only */
  463. },
  464. {
  465. .name = "Boot Env-NAND",
  466. .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */
  467. .size = 6 * (64 * 2048),
  468. },
  469. {
  470. .name = "Kernel-NAND",
  471. .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
  472. .size = 40 * (64 * 2048),
  473. },
  474. {
  475. .name = "File System - NAND",
  476. .size = MTDPART_SIZ_FULL,
  477. .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */
  478. },
  479. };
  480. static struct flash_partitions sdp_flash_partitions[] = {
  481. {
  482. .parts = sdp_nor_partitions,
  483. .nr_parts = ARRAY_SIZE(sdp_nor_partitions),
  484. },
  485. {
  486. .parts = sdp_onenand_partitions,
  487. .nr_parts = ARRAY_SIZE(sdp_onenand_partitions),
  488. },
  489. {
  490. .parts = sdp_nand_partitions,
  491. .nr_parts = ARRAY_SIZE(sdp_nand_partitions),
  492. },
  493. };
  494. static void __init omap_3430sdp_init(void)
  495. {
  496. int gpio_pendown;
  497. omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
  498. omap_hsmmc_init(mmc);
  499. omap3430_i2c_init();
  500. omap_display_init(&sdp3430_dss_data);
  501. if (omap_rev() > OMAP3430_REV_ES1_0)
  502. gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV2;
  503. else
  504. gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1;
  505. omap_ads7846_init(1, gpio_pendown, 310, NULL);
  506. omap_serial_init();
  507. omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL);
  508. usb_musb_init(NULL);
  509. board_smc91x_init();
  510. board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
  511. sdp3430_display_init();
  512. enable_board_wakeup_source();
  513. usbhs_init(&usbhs_bdata);
  514. }
  515. MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
  516. /* Maintainer: Syed Khasim - Texas Instruments Inc */
  517. .atag_offset = 0x100,
  518. .reserve = omap_reserve,
  519. .map_io = omap3_map_io,
  520. .init_early = omap3430_init_early,
  521. .init_irq = omap3_init_irq,
  522. .handle_irq = omap3_intc_handle_irq,
  523. .init_machine = omap_3430sdp_init,
  524. .init_late = omap3430_init_late,
  525. .timer = &omap3_timer,
  526. .restart = omap3xxx_restart,
  527. MACHINE_END