mach-imx6q.c 6.1 KB

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  1. /*
  2. * Copyright 2011 Freescale Semiconductor, Inc.
  3. * Copyright 2011 Linaro Ltd.
  4. *
  5. * The code contained herein is licensed under the GNU General Public
  6. * License. You may obtain a copy of the GNU General Public License
  7. * Version 2 or later at the following locations:
  8. *
  9. * http://www.opensource.org/licenses/gpl-license.html
  10. * http://www.gnu.org/copyleft/gpl.html
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/clkdev.h>
  14. #include <linux/cpuidle.h>
  15. #include <linux/delay.h>
  16. #include <linux/export.h>
  17. #include <linux/init.h>
  18. #include <linux/io.h>
  19. #include <linux/irq.h>
  20. #include <linux/of.h>
  21. #include <linux/of_address.h>
  22. #include <linux/of_irq.h>
  23. #include <linux/of_platform.h>
  24. #include <linux/phy.h>
  25. #include <linux/regmap.h>
  26. #include <linux/micrel_phy.h>
  27. #include <linux/mfd/syscon.h>
  28. #include <asm/cpuidle.h>
  29. #include <asm/smp_twd.h>
  30. #include <asm/hardware/cache-l2x0.h>
  31. #include <asm/hardware/gic.h>
  32. #include <asm/mach/arch.h>
  33. #include <asm/mach/time.h>
  34. #include <asm/system_misc.h>
  35. #include "common.h"
  36. #include "cpuidle.h"
  37. #include "hardware.h"
  38. #define IMX6Q_ANALOG_DIGPROG 0x260
  39. static int imx6q_revision(void)
  40. {
  41. struct device_node *np;
  42. void __iomem *base;
  43. static u32 rev;
  44. if (!rev) {
  45. np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
  46. if (!np)
  47. return IMX_CHIP_REVISION_UNKNOWN;
  48. base = of_iomap(np, 0);
  49. if (!base) {
  50. of_node_put(np);
  51. return IMX_CHIP_REVISION_UNKNOWN;
  52. }
  53. rev = readl_relaxed(base + IMX6Q_ANALOG_DIGPROG);
  54. iounmap(base);
  55. of_node_put(np);
  56. }
  57. switch (rev & 0xff) {
  58. case 0:
  59. return IMX_CHIP_REVISION_1_0;
  60. case 1:
  61. return IMX_CHIP_REVISION_1_1;
  62. case 2:
  63. return IMX_CHIP_REVISION_1_2;
  64. default:
  65. return IMX_CHIP_REVISION_UNKNOWN;
  66. }
  67. }
  68. void imx6q_restart(char mode, const char *cmd)
  69. {
  70. struct device_node *np;
  71. void __iomem *wdog_base;
  72. np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
  73. wdog_base = of_iomap(np, 0);
  74. if (!wdog_base)
  75. goto soft;
  76. imx_src_prepare_restart();
  77. /* enable wdog */
  78. writew_relaxed(1 << 2, wdog_base);
  79. /* write twice to ensure the request will not get ignored */
  80. writew_relaxed(1 << 2, wdog_base);
  81. /* wait for reset to assert ... */
  82. mdelay(500);
  83. pr_err("Watchdog reset failed to assert reset\n");
  84. /* delay to allow the serial port to show the message */
  85. mdelay(50);
  86. soft:
  87. /* we'll take a jump through zero as a poor second */
  88. soft_restart(0);
  89. }
  90. /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
  91. static int ksz9021rn_phy_fixup(struct phy_device *phydev)
  92. {
  93. if (IS_BUILTIN(CONFIG_PHYLIB)) {
  94. /* min rx data delay */
  95. phy_write(phydev, 0x0b, 0x8105);
  96. phy_write(phydev, 0x0c, 0x0000);
  97. /* max rx/tx clock delay, min rx/tx control delay */
  98. phy_write(phydev, 0x0b, 0x8104);
  99. phy_write(phydev, 0x0c, 0xf0f0);
  100. phy_write(phydev, 0x0b, 0x104);
  101. }
  102. return 0;
  103. }
  104. static void __init imx6q_sabrelite_cko1_setup(void)
  105. {
  106. struct clk *cko1_sel, *ahb, *cko1;
  107. unsigned long rate;
  108. cko1_sel = clk_get_sys(NULL, "cko1_sel");
  109. ahb = clk_get_sys(NULL, "ahb");
  110. cko1 = clk_get_sys(NULL, "cko1");
  111. if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) {
  112. pr_err("cko1 setup failed!\n");
  113. goto put_clk;
  114. }
  115. clk_set_parent(cko1_sel, ahb);
  116. rate = clk_round_rate(cko1, 16000000);
  117. clk_set_rate(cko1, rate);
  118. put_clk:
  119. if (!IS_ERR(cko1_sel))
  120. clk_put(cko1_sel);
  121. if (!IS_ERR(ahb))
  122. clk_put(ahb);
  123. if (!IS_ERR(cko1))
  124. clk_put(cko1);
  125. }
  126. static void __init imx6q_sabrelite_init(void)
  127. {
  128. if (IS_BUILTIN(CONFIG_PHYLIB))
  129. phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
  130. ksz9021rn_phy_fixup);
  131. imx6q_sabrelite_cko1_setup();
  132. }
  133. static void __init imx6q_1588_init(void)
  134. {
  135. struct regmap *gpr;
  136. gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
  137. if (!IS_ERR(gpr))
  138. regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21);
  139. else
  140. pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
  141. }
  142. static void __init imx6q_usb_init(void)
  143. {
  144. struct regmap *anatop;
  145. #define HW_ANADIG_USB1_CHRG_DETECT 0x000001b0
  146. #define HW_ANADIG_USB2_CHRG_DETECT 0x00000210
  147. #define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x00100000
  148. #define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x00080000
  149. anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
  150. if (!IS_ERR(anatop)) {
  151. /*
  152. * The external charger detector needs to be disabled,
  153. * or the signal at DP will be poor
  154. */
  155. regmap_write(anatop, HW_ANADIG_USB1_CHRG_DETECT,
  156. BM_ANADIG_USB_CHRG_DETECT_EN_B
  157. | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
  158. regmap_write(anatop, HW_ANADIG_USB2_CHRG_DETECT,
  159. BM_ANADIG_USB_CHRG_DETECT_EN_B |
  160. BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
  161. } else {
  162. pr_warn("failed to find fsl,imx6q-anatop regmap\n");
  163. }
  164. }
  165. static void __init imx6q_init_machine(void)
  166. {
  167. if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
  168. imx6q_sabrelite_init();
  169. of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
  170. imx6q_pm_init();
  171. imx6q_usb_init();
  172. imx6q_1588_init();
  173. }
  174. static struct cpuidle_driver imx6q_cpuidle_driver = {
  175. .name = "imx6q_cpuidle",
  176. .owner = THIS_MODULE,
  177. .en_core_tk_irqen = 1,
  178. .states[0] = ARM_CPUIDLE_WFI_STATE,
  179. .state_count = 1,
  180. };
  181. static void __init imx6q_init_late(void)
  182. {
  183. imx_cpuidle_init(&imx6q_cpuidle_driver);
  184. }
  185. static void __init imx6q_map_io(void)
  186. {
  187. imx_lluart_map_io();
  188. imx_scu_map_io();
  189. imx6q_clock_map_io();
  190. }
  191. static const struct of_device_id imx6q_irq_match[] __initconst = {
  192. { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
  193. { /* sentinel */ }
  194. };
  195. static void __init imx6q_init_irq(void)
  196. {
  197. l2x0_of_init(0, ~0UL);
  198. imx_src_init();
  199. imx_gpc_init();
  200. of_irq_init(imx6q_irq_match);
  201. }
  202. static void __init imx6q_timer_init(void)
  203. {
  204. mx6q_clocks_init();
  205. twd_local_timer_of_register();
  206. imx_print_silicon_rev("i.MX6Q", imx6q_revision());
  207. }
  208. static struct sys_timer imx6q_timer = {
  209. .init = imx6q_timer_init,
  210. };
  211. static const char *imx6q_dt_compat[] __initdata = {
  212. "fsl,imx6q",
  213. NULL,
  214. };
  215. DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad (Device Tree)")
  216. .smp = smp_ops(imx_smp_ops),
  217. .map_io = imx6q_map_io,
  218. .init_irq = imx6q_init_irq,
  219. .handle_irq = imx6q_handle_irq,
  220. .timer = &imx6q_timer,
  221. .init_machine = imx6q_init_machine,
  222. .init_late = imx6q_init_late,
  223. .dt_compat = imx6q_dt_compat,
  224. .restart = imx6q_restart,
  225. MACHINE_END