tegra20-harmony.dts 12 KB

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  1. /dts-v1/;
  2. /include/ "tegra20.dtsi"
  3. / {
  4. model = "NVIDIA Tegra2 Harmony evaluation board";
  5. compatible = "nvidia,harmony", "nvidia,tegra20";
  6. memory {
  7. reg = <0x00000000 0x40000000>;
  8. };
  9. host1x {
  10. hdmi {
  11. status = "okay";
  12. vdd-supply = <&hdmi_vdd_reg>;
  13. pll-supply = <&hdmi_pll_reg>;
  14. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  15. nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
  16. };
  17. };
  18. pinmux {
  19. pinctrl-names = "default";
  20. pinctrl-0 = <&state_default>;
  21. state_default: pinmux {
  22. ata {
  23. nvidia,pins = "ata";
  24. nvidia,function = "ide";
  25. };
  26. atb {
  27. nvidia,pins = "atb", "gma", "gme";
  28. nvidia,function = "sdio4";
  29. };
  30. atc {
  31. nvidia,pins = "atc";
  32. nvidia,function = "nand";
  33. };
  34. atd {
  35. nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
  36. "spia", "spib", "spic";
  37. nvidia,function = "gmi";
  38. };
  39. cdev1 {
  40. nvidia,pins = "cdev1";
  41. nvidia,function = "plla_out";
  42. };
  43. cdev2 {
  44. nvidia,pins = "cdev2";
  45. nvidia,function = "pllp_out4";
  46. };
  47. crtp {
  48. nvidia,pins = "crtp";
  49. nvidia,function = "crt";
  50. };
  51. csus {
  52. nvidia,pins = "csus";
  53. nvidia,function = "vi_sensor_clk";
  54. };
  55. dap1 {
  56. nvidia,pins = "dap1";
  57. nvidia,function = "dap1";
  58. };
  59. dap2 {
  60. nvidia,pins = "dap2";
  61. nvidia,function = "dap2";
  62. };
  63. dap3 {
  64. nvidia,pins = "dap3";
  65. nvidia,function = "dap3";
  66. };
  67. dap4 {
  68. nvidia,pins = "dap4";
  69. nvidia,function = "dap4";
  70. };
  71. ddc {
  72. nvidia,pins = "ddc";
  73. nvidia,function = "i2c2";
  74. };
  75. dta {
  76. nvidia,pins = "dta", "dtd";
  77. nvidia,function = "sdio2";
  78. };
  79. dtb {
  80. nvidia,pins = "dtb", "dtc", "dte";
  81. nvidia,function = "rsvd1";
  82. };
  83. dtf {
  84. nvidia,pins = "dtf";
  85. nvidia,function = "i2c3";
  86. };
  87. gmc {
  88. nvidia,pins = "gmc";
  89. nvidia,function = "uartd";
  90. };
  91. gpu7 {
  92. nvidia,pins = "gpu7";
  93. nvidia,function = "rtck";
  94. };
  95. gpv {
  96. nvidia,pins = "gpv", "slxa", "slxk";
  97. nvidia,function = "pcie";
  98. };
  99. hdint {
  100. nvidia,pins = "hdint", "pta";
  101. nvidia,function = "hdmi";
  102. };
  103. i2cp {
  104. nvidia,pins = "i2cp";
  105. nvidia,function = "i2cp";
  106. };
  107. irrx {
  108. nvidia,pins = "irrx", "irtx";
  109. nvidia,function = "uarta";
  110. };
  111. kbca {
  112. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  113. "kbce", "kbcf";
  114. nvidia,function = "kbc";
  115. };
  116. lcsn {
  117. nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
  118. "ld3", "ld4", "ld5", "ld6", "ld7",
  119. "ld8", "ld9", "ld10", "ld11", "ld12",
  120. "ld13", "ld14", "ld15", "ld16", "ld17",
  121. "ldc", "ldi", "lhp0", "lhp1", "lhp2",
  122. "lhs", "lm0", "lm1", "lpp", "lpw0",
  123. "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
  124. "lsda", "lsdi", "lspi", "lvp0", "lvp1",
  125. "lvs";
  126. nvidia,function = "displaya";
  127. };
  128. owc {
  129. nvidia,pins = "owc", "spdi", "spdo", "uac";
  130. nvidia,function = "rsvd2";
  131. };
  132. pmc {
  133. nvidia,pins = "pmc";
  134. nvidia,function = "pwr_on";
  135. };
  136. rm {
  137. nvidia,pins = "rm";
  138. nvidia,function = "i2c1";
  139. };
  140. sdb {
  141. nvidia,pins = "sdb", "sdc", "sdd";
  142. nvidia,function = "pwm";
  143. };
  144. sdio1 {
  145. nvidia,pins = "sdio1";
  146. nvidia,function = "sdio1";
  147. };
  148. slxc {
  149. nvidia,pins = "slxc", "slxd";
  150. nvidia,function = "spdif";
  151. };
  152. spid {
  153. nvidia,pins = "spid", "spie", "spif";
  154. nvidia,function = "spi1";
  155. };
  156. spig {
  157. nvidia,pins = "spig", "spih";
  158. nvidia,function = "spi2_alt";
  159. };
  160. uaa {
  161. nvidia,pins = "uaa", "uab", "uda";
  162. nvidia,function = "ulpi";
  163. };
  164. uad {
  165. nvidia,pins = "uad";
  166. nvidia,function = "irda";
  167. };
  168. uca {
  169. nvidia,pins = "uca", "ucb";
  170. nvidia,function = "uartc";
  171. };
  172. conf_ata {
  173. nvidia,pins = "ata", "atb", "atc", "atd", "ate",
  174. "cdev1", "cdev2", "dap1", "dtb", "gma",
  175. "gmb", "gmc", "gmd", "gme", "gpu7",
  176. "gpv", "i2cp", "pta", "rm", "slxa",
  177. "slxk", "spia", "spib", "uac";
  178. nvidia,pull = <0>;
  179. nvidia,tristate = <0>;
  180. };
  181. conf_ck32 {
  182. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  183. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  184. nvidia,pull = <0>;
  185. };
  186. conf_csus {
  187. nvidia,pins = "csus", "spid", "spif";
  188. nvidia,pull = <1>;
  189. nvidia,tristate = <1>;
  190. };
  191. conf_crtp {
  192. nvidia,pins = "crtp", "dap2", "dap3", "dap4",
  193. "dtc", "dte", "dtf", "gpu", "sdio1",
  194. "slxc", "slxd", "spdi", "spdo", "spig",
  195. "uda";
  196. nvidia,pull = <0>;
  197. nvidia,tristate = <1>;
  198. };
  199. conf_ddc {
  200. nvidia,pins = "ddc", "dta", "dtd", "kbca",
  201. "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
  202. "sdc";
  203. nvidia,pull = <2>;
  204. nvidia,tristate = <0>;
  205. };
  206. conf_hdint {
  207. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  208. "lpw1", "lsc1", "lsck", "lsda", "lsdi",
  209. "lvp0", "owc", "sdb";
  210. nvidia,tristate = <1>;
  211. };
  212. conf_irrx {
  213. nvidia,pins = "irrx", "irtx", "sdd", "spic",
  214. "spie", "spih", "uaa", "uab", "uad",
  215. "uca", "ucb";
  216. nvidia,pull = <2>;
  217. nvidia,tristate = <1>;
  218. };
  219. conf_lc {
  220. nvidia,pins = "lc", "ls";
  221. nvidia,pull = <2>;
  222. };
  223. conf_ld0 {
  224. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  225. "ld5", "ld6", "ld7", "ld8", "ld9",
  226. "ld10", "ld11", "ld12", "ld13", "ld14",
  227. "ld15", "ld16", "ld17", "ldi", "lhp0",
  228. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  229. "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
  230. "lvs", "pmc";
  231. nvidia,tristate = <0>;
  232. };
  233. conf_ld17_0 {
  234. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  235. "ld23_22";
  236. nvidia,pull = <1>;
  237. };
  238. };
  239. };
  240. i2s@70002800 {
  241. status = "okay";
  242. };
  243. serial@70006300 {
  244. status = "okay";
  245. clock-frequency = <216000000>;
  246. };
  247. i2c@7000c000 {
  248. status = "okay";
  249. clock-frequency = <400000>;
  250. wm8903: wm8903@1a {
  251. compatible = "wlf,wm8903";
  252. reg = <0x1a>;
  253. interrupt-parent = <&gpio>;
  254. interrupts = <187 0x04>;
  255. gpio-controller;
  256. #gpio-cells = <2>;
  257. micdet-cfg = <0>;
  258. micdet-delay = <100>;
  259. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  260. };
  261. };
  262. hdmi_ddc: i2c@7000c400 {
  263. status = "okay";
  264. clock-frequency = <100000>;
  265. };
  266. i2c@7000c500 {
  267. status = "okay";
  268. clock-frequency = <400000>;
  269. };
  270. i2c@7000d000 {
  271. status = "okay";
  272. clock-frequency = <400000>;
  273. pmic: tps6586x@34 {
  274. compatible = "ti,tps6586x";
  275. reg = <0x34>;
  276. interrupts = <0 86 0x4>;
  277. ti,system-power-controller;
  278. #gpio-cells = <2>;
  279. gpio-controller;
  280. sys-supply = <&vdd_5v0_reg>;
  281. vin-sm0-supply = <&sys_reg>;
  282. vin-sm1-supply = <&sys_reg>;
  283. vin-sm2-supply = <&sys_reg>;
  284. vinldo01-supply = <&sm2_reg>;
  285. vinldo23-supply = <&sm2_reg>;
  286. vinldo4-supply = <&sm2_reg>;
  287. vinldo678-supply = <&sm2_reg>;
  288. vinldo9-supply = <&sm2_reg>;
  289. regulators {
  290. sys_reg: sys {
  291. regulator-name = "vdd_sys";
  292. regulator-always-on;
  293. };
  294. sm0 {
  295. regulator-name = "vdd_sm0,vdd_core";
  296. regulator-min-microvolt = <1200000>;
  297. regulator-max-microvolt = <1200000>;
  298. regulator-always-on;
  299. };
  300. sm1 {
  301. regulator-name = "vdd_sm1,vdd_cpu";
  302. regulator-min-microvolt = <1000000>;
  303. regulator-max-microvolt = <1000000>;
  304. regulator-always-on;
  305. };
  306. sm2_reg: sm2 {
  307. regulator-name = "vdd_sm2,vin_ldo*";
  308. regulator-min-microvolt = <3700000>;
  309. regulator-max-microvolt = <3700000>;
  310. regulator-always-on;
  311. };
  312. ldo0 {
  313. regulator-name = "vdd_ldo0,vddio_pex_clk";
  314. regulator-min-microvolt = <3300000>;
  315. regulator-max-microvolt = <3300000>;
  316. };
  317. ldo1 {
  318. regulator-name = "vdd_ldo1,avdd_pll*";
  319. regulator-min-microvolt = <1100000>;
  320. regulator-max-microvolt = <1100000>;
  321. regulator-always-on;
  322. };
  323. ldo2 {
  324. regulator-name = "vdd_ldo2,vdd_rtc";
  325. regulator-min-microvolt = <1200000>;
  326. regulator-max-microvolt = <1200000>;
  327. };
  328. ldo3 {
  329. regulator-name = "vdd_ldo3,avdd_usb*";
  330. regulator-min-microvolt = <3300000>;
  331. regulator-max-microvolt = <3300000>;
  332. regulator-always-on;
  333. };
  334. ldo4 {
  335. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  336. regulator-min-microvolt = <1800000>;
  337. regulator-max-microvolt = <1800000>;
  338. regulator-always-on;
  339. };
  340. ldo5 {
  341. regulator-name = "vdd_ldo5,vcore_mmc";
  342. regulator-min-microvolt = <2850000>;
  343. regulator-max-microvolt = <2850000>;
  344. regulator-always-on;
  345. };
  346. ldo6 {
  347. regulator-name = "vdd_ldo6,avdd_vdac";
  348. regulator-min-microvolt = <1800000>;
  349. regulator-max-microvolt = <1800000>;
  350. };
  351. hdmi_vdd_reg: ldo7 {
  352. regulator-name = "vdd_ldo7,avdd_hdmi";
  353. regulator-min-microvolt = <3300000>;
  354. regulator-max-microvolt = <3300000>;
  355. };
  356. hdmi_pll_reg: ldo8 {
  357. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  358. regulator-min-microvolt = <1800000>;
  359. regulator-max-microvolt = <1800000>;
  360. };
  361. ldo9 {
  362. regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
  363. regulator-min-microvolt = <2850000>;
  364. regulator-max-microvolt = <2850000>;
  365. regulator-always-on;
  366. };
  367. ldo_rtc {
  368. regulator-name = "vdd_rtc_out,vdd_cell";
  369. regulator-min-microvolt = <3300000>;
  370. regulator-max-microvolt = <3300000>;
  371. regulator-always-on;
  372. };
  373. };
  374. };
  375. temperature-sensor@4c {
  376. compatible = "adi,adt7461";
  377. reg = <0x4c>;
  378. };
  379. };
  380. pmc {
  381. nvidia,invert-interrupt;
  382. };
  383. usb@c5000000 {
  384. status = "okay";
  385. };
  386. usb@c5004000 {
  387. status = "okay";
  388. nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
  389. };
  390. usb@c5008000 {
  391. status = "okay";
  392. };
  393. sdhci@c8000200 {
  394. status = "okay";
  395. cd-gpios = <&gpio 69 0>; /* gpio PI5 */
  396. wp-gpios = <&gpio 57 0>; /* gpio PH1 */
  397. power-gpios = <&gpio 155 0>; /* gpio PT3 */
  398. bus-width = <4>;
  399. };
  400. sdhci@c8000600 {
  401. status = "okay";
  402. cd-gpios = <&gpio 58 0>; /* gpio PH2 */
  403. wp-gpios = <&gpio 59 0>; /* gpio PH3 */
  404. power-gpios = <&gpio 70 0>; /* gpio PI6 */
  405. bus-width = <8>;
  406. };
  407. regulators {
  408. compatible = "simple-bus";
  409. #address-cells = <1>;
  410. #size-cells = <0>;
  411. vdd_5v0_reg: regulator@0 {
  412. compatible = "regulator-fixed";
  413. reg = <0>;
  414. regulator-name = "vdd_5v0";
  415. regulator-min-microvolt = <5000000>;
  416. regulator-max-microvolt = <5000000>;
  417. regulator-always-on;
  418. };
  419. regulator@1 {
  420. compatible = "regulator-fixed";
  421. reg = <1>;
  422. regulator-name = "vdd_1v5";
  423. regulator-min-microvolt = <1500000>;
  424. regulator-max-microvolt = <1500000>;
  425. gpio = <&pmic 0 0>;
  426. };
  427. regulator@2 {
  428. compatible = "regulator-fixed";
  429. reg = <2>;
  430. regulator-name = "vdd_1v2";
  431. regulator-min-microvolt = <1200000>;
  432. regulator-max-microvolt = <1200000>;
  433. gpio = <&pmic 1 0>;
  434. enable-active-high;
  435. };
  436. regulator@3 {
  437. compatible = "regulator-fixed";
  438. reg = <3>;
  439. regulator-name = "vdd_1v05";
  440. regulator-min-microvolt = <1050000>;
  441. regulator-max-microvolt = <1050000>;
  442. gpio = <&pmic 2 0>;
  443. enable-active-high;
  444. /* Hack until board-harmony-pcie.c is removed */
  445. status = "disabled";
  446. };
  447. regulator@4 {
  448. compatible = "regulator-fixed";
  449. reg = <4>;
  450. regulator-name = "vdd_pnl";
  451. regulator-min-microvolt = <2800000>;
  452. regulator-max-microvolt = <2800000>;
  453. gpio = <&gpio 22 0>; /* gpio PC6 */
  454. enable-active-high;
  455. };
  456. regulator@5 {
  457. compatible = "regulator-fixed";
  458. reg = <5>;
  459. regulator-name = "vdd_bl";
  460. regulator-min-microvolt = <2800000>;
  461. regulator-max-microvolt = <2800000>;
  462. gpio = <&gpio 176 0>; /* gpio PW0 */
  463. enable-active-high;
  464. };
  465. };
  466. sound {
  467. compatible = "nvidia,tegra-audio-wm8903-harmony",
  468. "nvidia,tegra-audio-wm8903";
  469. nvidia,model = "NVIDIA Tegra Harmony";
  470. nvidia,audio-routing =
  471. "Headphone Jack", "HPOUTR",
  472. "Headphone Jack", "HPOUTL",
  473. "Int Spk", "ROP",
  474. "Int Spk", "RON",
  475. "Int Spk", "LOP",
  476. "Int Spk", "LON",
  477. "Mic Jack", "MICBIAS",
  478. "IN1L", "Mic Jack";
  479. nvidia,i2s-controller = <&tegra_i2s1>;
  480. nvidia,audio-codec = <&wm8903>;
  481. nvidia,spkr-en-gpios = <&wm8903 2 0>;
  482. nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
  483. nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
  484. nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
  485. };
  486. };