spear600.dtsi 4.5 KB

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  1. /*
  2. * Copyright 2012 Stefan Roese <sr@denx.de>
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. compatible = "st,spear600";
  14. cpus {
  15. cpu@0 {
  16. compatible = "arm,arm926ejs";
  17. };
  18. };
  19. memory {
  20. device_type = "memory";
  21. reg = <0 0x40000000>;
  22. };
  23. ahb {
  24. #address-cells = <1>;
  25. #size-cells = <1>;
  26. compatible = "simple-bus";
  27. ranges = <0xd0000000 0xd0000000 0x30000000>;
  28. vic0: interrupt-controller@f1100000 {
  29. compatible = "arm,pl190-vic";
  30. interrupt-controller;
  31. reg = <0xf1100000 0x1000>;
  32. #interrupt-cells = <1>;
  33. };
  34. vic1: interrupt-controller@f1000000 {
  35. compatible = "arm,pl190-vic";
  36. interrupt-controller;
  37. reg = <0xf1000000 0x1000>;
  38. #interrupt-cells = <1>;
  39. };
  40. clcd@fc200000 {
  41. compatible = "arm,pl110", "arm,primecell";
  42. reg = <0xfc200000 0x1000>;
  43. interrupt-parent = <&vic1>;
  44. interrupts = <12>;
  45. status = "disabled";
  46. };
  47. dma@fc400000 {
  48. compatible = "arm,pl080", "arm,primecell";
  49. reg = <0xfc400000 0x1000>;
  50. interrupt-parent = <&vic1>;
  51. interrupts = <10>;
  52. status = "disabled";
  53. };
  54. gmac: ethernet@e0800000 {
  55. compatible = "st,spear600-gmac";
  56. reg = <0xe0800000 0x8000>;
  57. interrupt-parent = <&vic1>;
  58. interrupts = <24 23>;
  59. interrupt-names = "macirq", "eth_wake_irq";
  60. phy-mode = "gmii";
  61. status = "disabled";
  62. };
  63. fsmc: flash@d1800000 {
  64. compatible = "st,spear600-fsmc-nand";
  65. #address-cells = <1>;
  66. #size-cells = <1>;
  67. reg = <0xd1800000 0x1000 /* FSMC Register */
  68. 0xd2000000 0x0010 /* NAND Base DATA */
  69. 0xd2020000 0x0010 /* NAND Base ADDR */
  70. 0xd2010000 0x0010>; /* NAND Base CMD */
  71. reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
  72. status = "disabled";
  73. };
  74. smi: flash@fc000000 {
  75. compatible = "st,spear600-smi";
  76. #address-cells = <1>;
  77. #size-cells = <1>;
  78. reg = <0xfc000000 0x1000>;
  79. interrupt-parent = <&vic1>;
  80. interrupts = <12>;
  81. status = "disabled";
  82. };
  83. ehci@e1800000 {
  84. compatible = "st,spear600-ehci", "usb-ehci";
  85. reg = <0xe1800000 0x1000>;
  86. interrupt-parent = <&vic1>;
  87. interrupts = <27>;
  88. status = "disabled";
  89. };
  90. ehci@e2000000 {
  91. compatible = "st,spear600-ehci", "usb-ehci";
  92. reg = <0xe2000000 0x1000>;
  93. interrupt-parent = <&vic1>;
  94. interrupts = <29>;
  95. status = "disabled";
  96. };
  97. ohci@e1900000 {
  98. compatible = "st,spear600-ohci", "usb-ohci";
  99. reg = <0xe1900000 0x1000>;
  100. interrupt-parent = <&vic1>;
  101. interrupts = <26>;
  102. status = "disabled";
  103. };
  104. ohci@e2100000 {
  105. compatible = "st,spear600-ohci", "usb-ohci";
  106. reg = <0xe2100000 0x1000>;
  107. interrupt-parent = <&vic1>;
  108. interrupts = <28>;
  109. status = "disabled";
  110. };
  111. apb {
  112. #address-cells = <1>;
  113. #size-cells = <1>;
  114. compatible = "simple-bus";
  115. ranges = <0xd0000000 0xd0000000 0x30000000>;
  116. serial@d0000000 {
  117. compatible = "arm,pl011", "arm,primecell";
  118. reg = <0xd0000000 0x1000>;
  119. interrupt-parent = <&vic0>;
  120. interrupts = <24>;
  121. status = "disabled";
  122. };
  123. serial@d0080000 {
  124. compatible = "arm,pl011", "arm,primecell";
  125. reg = <0xd0080000 0x1000>;
  126. interrupt-parent = <&vic0>;
  127. interrupts = <25>;
  128. status = "disabled";
  129. };
  130. /* local/cpu GPIO */
  131. gpio0: gpio@f0100000 {
  132. #gpio-cells = <2>;
  133. compatible = "arm,pl061", "arm,primecell";
  134. gpio-controller;
  135. reg = <0xf0100000 0x1000>;
  136. interrupt-parent = <&vic0>;
  137. interrupts = <18>;
  138. };
  139. /* basic GPIO */
  140. gpio1: gpio@fc980000 {
  141. #gpio-cells = <2>;
  142. compatible = "arm,pl061", "arm,primecell";
  143. gpio-controller;
  144. reg = <0xfc980000 0x1000>;
  145. interrupt-parent = <&vic1>;
  146. interrupts = <19>;
  147. };
  148. /* appl GPIO */
  149. gpio2: gpio@d8100000 {
  150. #gpio-cells = <2>;
  151. compatible = "arm,pl061", "arm,primecell";
  152. gpio-controller;
  153. reg = <0xd8100000 0x1000>;
  154. interrupt-parent = <&vic1>;
  155. interrupts = <4>;
  156. };
  157. i2c@d0200000 {
  158. #address-cells = <1>;
  159. #size-cells = <0>;
  160. compatible = "snps,designware-i2c";
  161. reg = <0xd0200000 0x1000>;
  162. interrupt-parent = <&vic0>;
  163. interrupts = <28>;
  164. status = "disabled";
  165. };
  166. rtc@fc900000 {
  167. compatible = "st,spear600-rtc";
  168. reg = <0xfc900000 0x1000>;
  169. interrupts = <10>;
  170. status = "disabled";
  171. };
  172. timer@f0000000 {
  173. compatible = "st,spear-timer";
  174. reg = <0xf0000000 0x400>;
  175. interrupt-parent = <&vic0>;
  176. interrupts = <16>;
  177. };
  178. };
  179. };
  180. };