spear1310.dtsi 5.1 KB

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  1. /*
  2. * DTS file for all SPEAr1310 SoCs
  3. *
  4. * Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
  5. *
  6. * The code contained herein is licensed under the GNU General Public
  7. * License. You may obtain a copy of the GNU General Public License
  8. * Version 2 or later at the following locations:
  9. *
  10. * http://www.opensource.org/licenses/gpl-license.html
  11. * http://www.gnu.org/copyleft/gpl.html
  12. */
  13. /include/ "spear13xx.dtsi"
  14. / {
  15. compatible = "st,spear1310";
  16. ahb {
  17. spics: spics@e0700000{
  18. compatible = "st,spear-spics-gpio";
  19. reg = <0xe0700000 0x1000>;
  20. st-spics,peripcfg-reg = <0x3b0>;
  21. st-spics,sw-enable-bit = <12>;
  22. st-spics,cs-value-bit = <11>;
  23. st-spics,cs-enable-mask = <3>;
  24. st-spics,cs-enable-shift = <8>;
  25. gpio-controller;
  26. #gpio-cells = <2>;
  27. };
  28. ahci@b1000000 {
  29. compatible = "snps,spear-ahci";
  30. reg = <0xb1000000 0x10000>;
  31. interrupts = <0 68 0x4>;
  32. status = "disabled";
  33. };
  34. ahci@b1800000 {
  35. compatible = "snps,spear-ahci";
  36. reg = <0xb1800000 0x10000>;
  37. interrupts = <0 69 0x4>;
  38. status = "disabled";
  39. };
  40. ahci@b4000000 {
  41. compatible = "snps,spear-ahci";
  42. reg = <0xb4000000 0x10000>;
  43. interrupts = <0 70 0x4>;
  44. status = "disabled";
  45. };
  46. gmac1: eth@5c400000 {
  47. compatible = "st,spear600-gmac";
  48. reg = <0x5c400000 0x8000>;
  49. interrupts = <0 95 0x4>;
  50. interrupt-names = "macirq";
  51. phy-mode = "mii";
  52. status = "disabled";
  53. };
  54. gmac2: eth@5c500000 {
  55. compatible = "st,spear600-gmac";
  56. reg = <0x5c500000 0x8000>;
  57. interrupts = <0 96 0x4>;
  58. interrupt-names = "macirq";
  59. phy-mode = "mii";
  60. status = "disabled";
  61. };
  62. gmac3: eth@5c600000 {
  63. compatible = "st,spear600-gmac";
  64. reg = <0x5c600000 0x8000>;
  65. interrupts = <0 97 0x4>;
  66. interrupt-names = "macirq";
  67. phy-mode = "rmii";
  68. status = "disabled";
  69. };
  70. gmac4: eth@5c700000 {
  71. compatible = "st,spear600-gmac";
  72. reg = <0x5c700000 0x8000>;
  73. interrupts = <0 98 0x4>;
  74. interrupt-names = "macirq";
  75. phy-mode = "rgmii";
  76. status = "disabled";
  77. };
  78. pinmux: pinmux@e0700000 {
  79. compatible = "st,spear1310-pinmux";
  80. reg = <0xe0700000 0x1000>;
  81. #gpio-range-cells = <2>;
  82. };
  83. apb {
  84. i2c1: i2c@5cd00000 {
  85. #address-cells = <1>;
  86. #size-cells = <0>;
  87. compatible = "snps,designware-i2c";
  88. reg = <0x5cd00000 0x1000>;
  89. interrupts = <0 87 0x4>;
  90. status = "disabled";
  91. };
  92. i2c2: i2c@5ce00000 {
  93. #address-cells = <1>;
  94. #size-cells = <0>;
  95. compatible = "snps,designware-i2c";
  96. reg = <0x5ce00000 0x1000>;
  97. interrupts = <0 88 0x4>;
  98. status = "disabled";
  99. };
  100. i2c3: i2c@5cf00000 {
  101. #address-cells = <1>;
  102. #size-cells = <0>;
  103. compatible = "snps,designware-i2c";
  104. reg = <0x5cf00000 0x1000>;
  105. interrupts = <0 89 0x4>;
  106. status = "disabled";
  107. };
  108. i2c4: i2c@5d000000 {
  109. #address-cells = <1>;
  110. #size-cells = <0>;
  111. compatible = "snps,designware-i2c";
  112. reg = <0x5d000000 0x1000>;
  113. interrupts = <0 90 0x4>;
  114. status = "disabled";
  115. };
  116. i2c5: i2c@5d100000 {
  117. #address-cells = <1>;
  118. #size-cells = <0>;
  119. compatible = "snps,designware-i2c";
  120. reg = <0x5d100000 0x1000>;
  121. interrupts = <0 91 0x4>;
  122. status = "disabled";
  123. };
  124. i2c6: i2c@5d200000 {
  125. #address-cells = <1>;
  126. #size-cells = <0>;
  127. compatible = "snps,designware-i2c";
  128. reg = <0x5d200000 0x1000>;
  129. interrupts = <0 92 0x4>;
  130. status = "disabled";
  131. };
  132. i2c7: i2c@5d300000 {
  133. #address-cells = <1>;
  134. #size-cells = <0>;
  135. compatible = "snps,designware-i2c";
  136. reg = <0x5d300000 0x1000>;
  137. interrupts = <0 93 0x4>;
  138. status = "disabled";
  139. };
  140. spi1: spi@5d400000 {
  141. compatible = "arm,pl022", "arm,primecell";
  142. reg = <0x5d400000 0x1000>;
  143. interrupts = <0 99 0x4>;
  144. #address-cells = <1>;
  145. #size-cells = <0>;
  146. status = "disabled";
  147. };
  148. serial@5c800000 {
  149. compatible = "arm,pl011", "arm,primecell";
  150. reg = <0x5c800000 0x1000>;
  151. interrupts = <0 82 0x4>;
  152. status = "disabled";
  153. };
  154. serial@5c900000 {
  155. compatible = "arm,pl011", "arm,primecell";
  156. reg = <0x5c900000 0x1000>;
  157. interrupts = <0 83 0x4>;
  158. status = "disabled";
  159. };
  160. serial@5ca00000 {
  161. compatible = "arm,pl011", "arm,primecell";
  162. reg = <0x5ca00000 0x1000>;
  163. interrupts = <0 84 0x4>;
  164. status = "disabled";
  165. };
  166. serial@5cb00000 {
  167. compatible = "arm,pl011", "arm,primecell";
  168. reg = <0x5cb00000 0x1000>;
  169. interrupts = <0 85 0x4>;
  170. status = "disabled";
  171. };
  172. serial@5cc00000 {
  173. compatible = "arm,pl011", "arm,primecell";
  174. reg = <0x5cc00000 0x1000>;
  175. interrupts = <0 86 0x4>;
  176. status = "disabled";
  177. };
  178. thermal@e07008c4 {
  179. st,thermal-flags = <0x7000>;
  180. };
  181. gpiopinctrl: gpio@d8400000 {
  182. compatible = "st,spear-plgpio";
  183. reg = <0xd8400000 0x1000>;
  184. interrupts = <0 100 0x4>;
  185. #interrupt-cells = <1>;
  186. interrupt-controller;
  187. gpio-controller;
  188. #gpio-cells = <2>;
  189. gpio-ranges = <&pinmux 0 246>;
  190. status = "disabled";
  191. st-plgpio,ngpio = <246>;
  192. st-plgpio,enb-reg = <0xd0>;
  193. st-plgpio,wdata-reg = <0x90>;
  194. st-plgpio,dir-reg = <0xb0>;
  195. st-plgpio,ie-reg = <0x30>;
  196. st-plgpio,rdata-reg = <0x70>;
  197. st-plgpio,mis-reg = <0x10>;
  198. st-plgpio,eit-reg = <0x50>;
  199. };
  200. };
  201. };
  202. };