pxa910.dtsi 3.0 KB

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  1. /*
  2. * Copyright (C) 2012 Marvell Technology Group Ltd.
  3. * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * publishhed by the Free Software Foundation.
  8. */
  9. /include/ "skeleton.dtsi"
  10. / {
  11. aliases {
  12. serial0 = &uart1;
  13. serial1 = &uart2;
  14. serial2 = &uart3;
  15. i2c0 = &twsi1;
  16. i2c1 = &twsi2;
  17. };
  18. soc {
  19. #address-cells = <1>;
  20. #size-cells = <1>;
  21. compatible = "simple-bus";
  22. interrupt-parent = <&intc>;
  23. ranges;
  24. L2: l2-cache {
  25. compatible = "marvell,tauros2-cache";
  26. marvell,tauros2-cache-features = <0x3>;
  27. };
  28. axi@d4200000 { /* AXI */
  29. compatible = "mrvl,axi-bus", "simple-bus";
  30. #address-cells = <1>;
  31. #size-cells = <1>;
  32. reg = <0xd4200000 0x00200000>;
  33. ranges;
  34. intc: interrupt-controller@d4282000 {
  35. compatible = "mrvl,mmp-intc";
  36. interrupt-controller;
  37. #interrupt-cells = <1>;
  38. reg = <0xd4282000 0x1000>;
  39. mrvl,intc-nr-irqs = <64>;
  40. };
  41. };
  42. apb@d4000000 { /* APB */
  43. compatible = "mrvl,apb-bus", "simple-bus";
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. reg = <0xd4000000 0x00200000>;
  47. ranges;
  48. timer0: timer@d4014000 {
  49. compatible = "mrvl,mmp-timer";
  50. reg = <0xd4014000 0x100>;
  51. interrupts = <13>;
  52. };
  53. timer1: timer@d4016000 {
  54. compatible = "mrvl,mmp-timer";
  55. reg = <0xd4016000 0x100>;
  56. interrupts = <29>;
  57. status = "disabled";
  58. };
  59. uart1: uart@d4017000 {
  60. compatible = "mrvl,mmp-uart";
  61. reg = <0xd4017000 0x1000>;
  62. interrupts = <27>;
  63. status = "disabled";
  64. };
  65. uart2: uart@d4018000 {
  66. compatible = "mrvl,mmp-uart";
  67. reg = <0xd4018000 0x1000>;
  68. interrupts = <28>;
  69. status = "disabled";
  70. };
  71. uart3: uart@d4036000 {
  72. compatible = "mrvl,mmp-uart";
  73. reg = <0xd4036000 0x1000>;
  74. interrupts = <59>;
  75. status = "disabled";
  76. };
  77. gpio@d4019000 {
  78. compatible = "mrvl,mmp-gpio";
  79. #address-cells = <1>;
  80. #size-cells = <1>;
  81. reg = <0xd4019000 0x1000>;
  82. gpio-controller;
  83. #gpio-cells = <2>;
  84. interrupts = <49>;
  85. interrupt-names = "gpio_mux";
  86. interrupt-controller;
  87. #interrupt-cells = <1>;
  88. ranges;
  89. gcb0: gpio@d4019000 {
  90. reg = <0xd4019000 0x4>;
  91. };
  92. gcb1: gpio@d4019004 {
  93. reg = <0xd4019004 0x4>;
  94. };
  95. gcb2: gpio@d4019008 {
  96. reg = <0xd4019008 0x4>;
  97. };
  98. gcb3: gpio@d4019100 {
  99. reg = <0xd4019100 0x4>;
  100. };
  101. };
  102. twsi1: i2c@d4011000 {
  103. compatible = "mrvl,mmp-twsi";
  104. #address-cells = <1>;
  105. #size-cells = <0>;
  106. reg = <0xd4011000 0x1000>;
  107. interrupts = <7>;
  108. mrvl,i2c-fast-mode;
  109. status = "disabled";
  110. };
  111. twsi2: i2c@d4037000 {
  112. compatible = "mrvl,mmp-twsi";
  113. #address-cells = <1>;
  114. #size-cells = <0>;
  115. reg = <0xd4037000 0x1000>;
  116. interrupts = <54>;
  117. status = "disabled";
  118. };
  119. rtc: rtc@d4010000 {
  120. compatible = "mrvl,mmp-rtc";
  121. reg = <0xd4010000 0x1000>;
  122. interrupts = <5 6>;
  123. interrupt-names = "rtc 1Hz", "rtc alarm";
  124. status = "disabled";
  125. };
  126. };
  127. };
  128. };