at91sam9x5.dtsi 12 KB

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  1. /*
  2. * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
  3. * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
  4. * AT91SAM9X25, AT91SAM9X35 SoC
  5. *
  6. * Copyright (C) 2012 Atmel,
  7. * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. model = "Atmel AT91SAM9x5 family SoC";
  14. compatible = "atmel,at91sam9x5";
  15. interrupt-parent = <&aic>;
  16. aliases {
  17. serial0 = &dbgu;
  18. serial1 = &usart0;
  19. serial2 = &usart1;
  20. serial3 = &usart2;
  21. gpio0 = &pioA;
  22. gpio1 = &pioB;
  23. gpio2 = &pioC;
  24. gpio3 = &pioD;
  25. tcb0 = &tcb0;
  26. tcb1 = &tcb1;
  27. i2c0 = &i2c0;
  28. i2c1 = &i2c1;
  29. i2c2 = &i2c2;
  30. ssc0 = &ssc0;
  31. };
  32. cpus {
  33. cpu@0 {
  34. compatible = "arm,arm926ejs";
  35. };
  36. };
  37. memory {
  38. reg = <0x20000000 0x10000000>;
  39. };
  40. ahb {
  41. compatible = "simple-bus";
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. ranges;
  45. apb {
  46. compatible = "simple-bus";
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. ranges;
  50. aic: interrupt-controller@fffff000 {
  51. #interrupt-cells = <3>;
  52. compatible = "atmel,at91rm9200-aic";
  53. interrupt-controller;
  54. reg = <0xfffff000 0x200>;
  55. atmel,external-irqs = <31>;
  56. };
  57. ramc0: ramc@ffffe800 {
  58. compatible = "atmel,at91sam9g45-ddramc";
  59. reg = <0xffffe800 0x200>;
  60. };
  61. pmc: pmc@fffffc00 {
  62. compatible = "atmel,at91rm9200-pmc";
  63. reg = <0xfffffc00 0x100>;
  64. };
  65. rstc@fffffe00 {
  66. compatible = "atmel,at91sam9g45-rstc";
  67. reg = <0xfffffe00 0x10>;
  68. };
  69. shdwc@fffffe10 {
  70. compatible = "atmel,at91sam9x5-shdwc";
  71. reg = <0xfffffe10 0x10>;
  72. };
  73. pit: timer@fffffe30 {
  74. compatible = "atmel,at91sam9260-pit";
  75. reg = <0xfffffe30 0xf>;
  76. interrupts = <1 4 7>;
  77. };
  78. ssc0: ssc@f0010000 {
  79. compatible = "atmel,at91sam9g45-ssc";
  80. reg = <0xf0010000 0x4000>;
  81. interrupts = <28 4 5>;
  82. status = "disabled";
  83. };
  84. tcb0: timer@f8008000 {
  85. compatible = "atmel,at91sam9x5-tcb";
  86. reg = <0xf8008000 0x100>;
  87. interrupts = <17 4 0>;
  88. };
  89. tcb1: timer@f800c000 {
  90. compatible = "atmel,at91sam9x5-tcb";
  91. reg = <0xf800c000 0x100>;
  92. interrupts = <17 4 0>;
  93. };
  94. dma0: dma-controller@ffffec00 {
  95. compatible = "atmel,at91sam9g45-dma";
  96. reg = <0xffffec00 0x200>;
  97. interrupts = <20 4 0>;
  98. };
  99. dma1: dma-controller@ffffee00 {
  100. compatible = "atmel,at91sam9g45-dma";
  101. reg = <0xffffee00 0x200>;
  102. interrupts = <21 4 0>;
  103. };
  104. pinctrl@fffff400 {
  105. #address-cells = <1>;
  106. #size-cells = <1>;
  107. compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
  108. ranges = <0xfffff400 0xfffff400 0x800>;
  109. /* shared pinctrl settings */
  110. dbgu {
  111. pinctrl_dbgu: dbgu-0 {
  112. atmel,pins =
  113. <0 9 0x1 0x0 /* PA9 periph A */
  114. 0 10 0x1 0x1>; /* PA10 periph A with pullup */
  115. };
  116. };
  117. usart0 {
  118. pinctrl_usart0: usart0-0 {
  119. atmel,pins =
  120. <0 0 0x1 0x1 /* PA0 periph A with pullup */
  121. 0 1 0x1 0x0>; /* PA1 periph A */
  122. };
  123. pinctrl_usart0_rts: usart0_rts-0 {
  124. atmel,pins =
  125. <0 2 0x1 0x0>; /* PA2 periph A */
  126. };
  127. pinctrl_usart0_cts: usart0_cts-0 {
  128. atmel,pins =
  129. <0 3 0x1 0x0>; /* PA3 periph A */
  130. };
  131. };
  132. usart1 {
  133. pinctrl_usart1: usart1-0 {
  134. atmel,pins =
  135. <0 5 0x1 0x1 /* PA5 periph A with pullup */
  136. 0 6 0x1 0x0>; /* PA6 periph A */
  137. };
  138. pinctrl_usart1_rts: usart1_rts-0 {
  139. atmel,pins =
  140. <3 27 0x3 0x0>; /* PC27 periph C */
  141. };
  142. pinctrl_usart1_cts: usart1_cts-0 {
  143. atmel,pins =
  144. <3 28 0x3 0x0>; /* PC28 periph C */
  145. };
  146. };
  147. usart2 {
  148. pinctrl_usart2: usart2-0 {
  149. atmel,pins =
  150. <0 7 0x1 0x1 /* PA7 periph A with pullup */
  151. 0 8 0x1 0x0>; /* PA8 periph A */
  152. };
  153. pinctrl_uart2_rts: uart2_rts-0 {
  154. atmel,pins =
  155. <0 0 0x2 0x0>; /* PB0 periph B */
  156. };
  157. pinctrl_uart2_cts: uart2_cts-0 {
  158. atmel,pins =
  159. <0 1 0x2 0x0>; /* PB1 periph B */
  160. };
  161. };
  162. usart3 {
  163. pinctrl_uart3: usart3-0 {
  164. atmel,pins =
  165. <3 23 0x2 0x1 /* PC22 periph B with pullup */
  166. 3 23 0x2 0x0>; /* PC23 periph B */
  167. };
  168. pinctrl_usart3_rts: usart3_rts-0 {
  169. atmel,pins =
  170. <3 24 0x2 0x0>; /* PC24 periph B */
  171. };
  172. pinctrl_usart3_cts: usart3_cts-0 {
  173. atmel,pins =
  174. <3 25 0x2 0x0>; /* PC25 periph B */
  175. };
  176. };
  177. uart0 {
  178. pinctrl_uart0: uart0-0 {
  179. atmel,pins =
  180. <3 8 0x3 0x0 /* PC8 periph C */
  181. 3 9 0x3 0x1>; /* PC9 periph C with pullup */
  182. };
  183. };
  184. uart1 {
  185. pinctrl_uart1: uart1-0 {
  186. atmel,pins =
  187. <3 16 0x3 0x0 /* PC16 periph C */
  188. 3 17 0x3 0x1>; /* PC17 periph C with pullup */
  189. };
  190. };
  191. nand {
  192. pinctrl_nand: nand-0 {
  193. atmel,pins =
  194. <3 4 0x0 0x1 /* PD5 gpio RDY pin pull_up */
  195. 3 5 0x0 0x1>; /* PD4 gpio enable pin pull_up */
  196. };
  197. };
  198. macb0 {
  199. pinctrl_macb0_rmii: macb0_rmii-0 {
  200. atmel,pins =
  201. <1 0 0x1 0x0 /* PB0 periph A */
  202. 1 1 0x1 0x0 /* PB1 periph A */
  203. 1 2 0x1 0x0 /* PB2 periph A */
  204. 1 3 0x1 0x0 /* PB3 periph A */
  205. 1 4 0x1 0x0 /* PB4 periph A */
  206. 1 5 0x1 0x0 /* PB5 periph A */
  207. 1 6 0x1 0x0 /* PB6 periph A */
  208. 1 7 0x1 0x0 /* PB7 periph A */
  209. 1 9 0x1 0x0 /* PB9 periph A */
  210. 1 10 0x1 0x0>; /* PB10 periph A */
  211. };
  212. pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
  213. atmel,pins =
  214. <1 8 0x1 0x0 /* PA8 periph A */
  215. 1 11 0x1 0x0 /* PA11 periph A */
  216. 1 12 0x1 0x0 /* PA12 periph A */
  217. 1 13 0x1 0x0 /* PA13 periph A */
  218. 1 14 0x1 0x0 /* PA14 periph A */
  219. 1 15 0x1 0x0 /* PA15 periph A */
  220. 1 16 0x1 0x0 /* PA16 periph A */
  221. 1 17 0x1 0x0>; /* PA17 periph A */
  222. };
  223. };
  224. mmc0 {
  225. pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
  226. atmel,pins =
  227. <0 17 0x1 0x0 /* PA17 periph A */
  228. 0 16 0x1 0x1 /* PA16 periph A with pullup */
  229. 0 15 0x1 0x1>; /* PA15 periph A with pullup */
  230. };
  231. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  232. atmel,pins =
  233. <0 18 0x1 0x1 /* PA18 periph A with pullup */
  234. 0 19 0x1 0x1 /* PA19 periph A with pullup */
  235. 0 20 0x1 0x1>; /* PA20 periph A with pullup */
  236. };
  237. };
  238. mmc1 {
  239. pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
  240. atmel,pins =
  241. <0 13 0x2 0x0 /* PA13 periph B */
  242. 0 12 0x2 0x1 /* PA12 periph B with pullup */
  243. 0 11 0x2 0x1>; /* PA11 periph B with pullup */
  244. };
  245. pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
  246. atmel,pins =
  247. <0 2 0x2 0x1 /* PA2 periph B with pullup */
  248. 0 3 0x2 0x1 /* PA3 periph B with pullup */
  249. 0 4 0x2 0x1>; /* PA4 periph B with pullup */
  250. };
  251. };
  252. pioA: gpio@fffff400 {
  253. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  254. reg = <0xfffff400 0x200>;
  255. interrupts = <2 4 1>;
  256. #gpio-cells = <2>;
  257. gpio-controller;
  258. interrupt-controller;
  259. #interrupt-cells = <2>;
  260. };
  261. pioB: gpio@fffff600 {
  262. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  263. reg = <0xfffff600 0x200>;
  264. interrupts = <2 4 1>;
  265. #gpio-cells = <2>;
  266. gpio-controller;
  267. #gpio-lines = <19>;
  268. interrupt-controller;
  269. #interrupt-cells = <2>;
  270. };
  271. pioC: gpio@fffff800 {
  272. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  273. reg = <0xfffff800 0x200>;
  274. interrupts = <3 4 1>;
  275. #gpio-cells = <2>;
  276. gpio-controller;
  277. interrupt-controller;
  278. #interrupt-cells = <2>;
  279. };
  280. pioD: gpio@fffffa00 {
  281. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  282. reg = <0xfffffa00 0x200>;
  283. interrupts = <3 4 1>;
  284. #gpio-cells = <2>;
  285. gpio-controller;
  286. #gpio-lines = <22>;
  287. interrupt-controller;
  288. #interrupt-cells = <2>;
  289. };
  290. };
  291. mmc0: mmc@f0008000 {
  292. compatible = "atmel,hsmci";
  293. reg = <0xf0008000 0x600>;
  294. interrupts = <12 4 0>;
  295. #address-cells = <1>;
  296. #size-cells = <0>;
  297. status = "disabled";
  298. };
  299. mmc1: mmc@f000c000 {
  300. compatible = "atmel,hsmci";
  301. reg = <0xf000c000 0x600>;
  302. interrupts = <26 4 0>;
  303. #address-cells = <1>;
  304. #size-cells = <0>;
  305. status = "disabled";
  306. };
  307. dbgu: serial@fffff200 {
  308. compatible = "atmel,at91sam9260-usart";
  309. reg = <0xfffff200 0x200>;
  310. interrupts = <1 4 7>;
  311. pinctrl-names = "default";
  312. pinctrl-0 = <&pinctrl_dbgu>;
  313. status = "disabled";
  314. };
  315. usart0: serial@f801c000 {
  316. compatible = "atmel,at91sam9260-usart";
  317. reg = <0xf801c000 0x200>;
  318. interrupts = <5 4 5>;
  319. atmel,use-dma-rx;
  320. atmel,use-dma-tx;
  321. pinctrl-names = "default";
  322. pinctrl-0 = <&pinctrl_usart0>;
  323. status = "disabled";
  324. };
  325. usart1: serial@f8020000 {
  326. compatible = "atmel,at91sam9260-usart";
  327. reg = <0xf8020000 0x200>;
  328. interrupts = <6 4 5>;
  329. atmel,use-dma-rx;
  330. atmel,use-dma-tx;
  331. pinctrl-names = "default";
  332. pinctrl-0 = <&pinctrl_usart1>;
  333. status = "disabled";
  334. };
  335. usart2: serial@f8024000 {
  336. compatible = "atmel,at91sam9260-usart";
  337. reg = <0xf8024000 0x200>;
  338. interrupts = <7 4 5>;
  339. atmel,use-dma-rx;
  340. atmel,use-dma-tx;
  341. pinctrl-names = "default";
  342. pinctrl-0 = <&pinctrl_usart2>;
  343. status = "disabled";
  344. };
  345. macb0: ethernet@f802c000 {
  346. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  347. reg = <0xf802c000 0x100>;
  348. interrupts = <24 4 3>;
  349. pinctrl-names = "default";
  350. pinctrl-0 = <&pinctrl_macb0_rmii>;
  351. status = "disabled";
  352. };
  353. macb1: ethernet@f8030000 {
  354. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  355. reg = <0xf8030000 0x100>;
  356. interrupts = <27 4 3>;
  357. status = "disabled";
  358. };
  359. i2c0: i2c@f8010000 {
  360. compatible = "atmel,at91sam9x5-i2c";
  361. reg = <0xf8010000 0x100>;
  362. interrupts = <9 4 6>;
  363. #address-cells = <1>;
  364. #size-cells = <0>;
  365. status = "disabled";
  366. };
  367. i2c1: i2c@f8014000 {
  368. compatible = "atmel,at91sam9x5-i2c";
  369. reg = <0xf8014000 0x100>;
  370. interrupts = <10 4 6>;
  371. #address-cells = <1>;
  372. #size-cells = <0>;
  373. status = "disabled";
  374. };
  375. i2c2: i2c@f8018000 {
  376. compatible = "atmel,at91sam9x5-i2c";
  377. reg = <0xf8018000 0x100>;
  378. interrupts = <11 4 6>;
  379. #address-cells = <1>;
  380. #size-cells = <0>;
  381. status = "disabled";
  382. };
  383. adc0: adc@f804c000 {
  384. compatible = "atmel,at91sam9260-adc";
  385. reg = <0xf804c000 0x100>;
  386. interrupts = <19 4 0>;
  387. atmel,adc-use-external;
  388. atmel,adc-channels-used = <0xffff>;
  389. atmel,adc-vref = <3300>;
  390. atmel,adc-num-channels = <12>;
  391. atmel,adc-startup-time = <40>;
  392. atmel,adc-channel-base = <0x50>;
  393. atmel,adc-drdy-mask = <0x1000000>;
  394. atmel,adc-status-register = <0x30>;
  395. atmel,adc-trigger-register = <0xc0>;
  396. trigger@0 {
  397. trigger-name = "external-rising";
  398. trigger-value = <0x1>;
  399. trigger-external;
  400. };
  401. trigger@1 {
  402. trigger-name = "external-falling";
  403. trigger-value = <0x2>;
  404. trigger-external;
  405. };
  406. trigger@2 {
  407. trigger-name = "external-any";
  408. trigger-value = <0x3>;
  409. trigger-external;
  410. };
  411. trigger@3 {
  412. trigger-name = "continuous";
  413. trigger-value = <0x6>;
  414. };
  415. };
  416. };
  417. nand0: nand@40000000 {
  418. compatible = "atmel,at91rm9200-nand";
  419. #address-cells = <1>;
  420. #size-cells = <1>;
  421. reg = <0x40000000 0x10000000
  422. >;
  423. atmel,nand-addr-offset = <21>;
  424. atmel,nand-cmd-offset = <22>;
  425. pinctrl-names = "default";
  426. pinctrl-0 = <&pinctrl_nand>;
  427. gpios = <&pioD 5 0
  428. &pioD 4 0
  429. 0
  430. >;
  431. status = "disabled";
  432. };
  433. usb0: ohci@00600000 {
  434. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  435. reg = <0x00600000 0x100000>;
  436. interrupts = <22 4 2>;
  437. status = "disabled";
  438. };
  439. usb1: ehci@00700000 {
  440. compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  441. reg = <0x00700000 0x100000>;
  442. interrupts = <22 4 2>;
  443. status = "disabled";
  444. };
  445. };
  446. i2c@0 {
  447. compatible = "i2c-gpio";
  448. gpios = <&pioA 30 0 /* sda */
  449. &pioA 31 0 /* scl */
  450. >;
  451. i2c-gpio,sda-open-drain;
  452. i2c-gpio,scl-open-drain;
  453. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  454. #address-cells = <1>;
  455. #size-cells = <0>;
  456. status = "disabled";
  457. };
  458. i2c@1 {
  459. compatible = "i2c-gpio";
  460. gpios = <&pioC 0 0 /* sda */
  461. &pioC 1 0 /* scl */
  462. >;
  463. i2c-gpio,sda-open-drain;
  464. i2c-gpio,scl-open-drain;
  465. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  466. #address-cells = <1>;
  467. #size-cells = <0>;
  468. status = "disabled";
  469. };
  470. i2c@2 {
  471. compatible = "i2c-gpio";
  472. gpios = <&pioB 4 0 /* sda */
  473. &pioB 5 0 /* scl */
  474. >;
  475. i2c-gpio,sda-open-drain;
  476. i2c-gpio,scl-open-drain;
  477. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  478. #address-cells = <1>;
  479. #size-cells = <0>;
  480. status = "disabled";
  481. };
  482. };