at91sam9n12.dtsi 9.0 KB

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  1. /*
  2. * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
  3. *
  4. * Copyright (C) 2012 Atmel,
  5. * 2012 Hong Xu <hong.xu@atmel.com>
  6. *
  7. * Licensed under GPLv2 or later.
  8. */
  9. /include/ "skeleton.dtsi"
  10. / {
  11. model = "Atmel AT91SAM9N12 SoC";
  12. compatible = "atmel,at91sam9n12";
  13. interrupt-parent = <&aic>;
  14. aliases {
  15. serial0 = &dbgu;
  16. serial1 = &usart0;
  17. serial2 = &usart1;
  18. serial3 = &usart2;
  19. serial4 = &usart3;
  20. gpio0 = &pioA;
  21. gpio1 = &pioB;
  22. gpio2 = &pioC;
  23. gpio3 = &pioD;
  24. tcb0 = &tcb0;
  25. tcb1 = &tcb1;
  26. i2c0 = &i2c0;
  27. i2c1 = &i2c1;
  28. };
  29. cpus {
  30. cpu@0 {
  31. compatible = "arm,arm926ejs";
  32. };
  33. };
  34. memory {
  35. reg = <0x20000000 0x10000000>;
  36. };
  37. ahb {
  38. compatible = "simple-bus";
  39. #address-cells = <1>;
  40. #size-cells = <1>;
  41. ranges;
  42. apb {
  43. compatible = "simple-bus";
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. ranges;
  47. aic: interrupt-controller@fffff000 {
  48. #interrupt-cells = <3>;
  49. compatible = "atmel,at91rm9200-aic";
  50. interrupt-controller;
  51. reg = <0xfffff000 0x200>;
  52. };
  53. ramc0: ramc@ffffe800 {
  54. compatible = "atmel,at91sam9g45-ddramc";
  55. reg = <0xffffe800 0x200>;
  56. };
  57. pmc: pmc@fffffc00 {
  58. compatible = "atmel,at91rm9200-pmc";
  59. reg = <0xfffffc00 0x100>;
  60. };
  61. rstc@fffffe00 {
  62. compatible = "atmel,at91sam9g45-rstc";
  63. reg = <0xfffffe00 0x10>;
  64. };
  65. pit: timer@fffffe30 {
  66. compatible = "atmel,at91sam9260-pit";
  67. reg = <0xfffffe30 0xf>;
  68. interrupts = <1 4 7>;
  69. };
  70. shdwc@fffffe10 {
  71. compatible = "atmel,at91sam9x5-shdwc";
  72. reg = <0xfffffe10 0x10>;
  73. };
  74. mmc0: mmc@f0008000 {
  75. compatible = "atmel,hsmci";
  76. reg = <0xf0008000 0x600>;
  77. interrupts = <12 4 0>;
  78. #address-cells = <1>;
  79. #size-cells = <0>;
  80. status = "disabled";
  81. };
  82. tcb0: timer@f8008000 {
  83. compatible = "atmel,at91sam9x5-tcb";
  84. reg = <0xf8008000 0x100>;
  85. interrupts = <17 4 0>;
  86. };
  87. tcb1: timer@f800c000 {
  88. compatible = "atmel,at91sam9x5-tcb";
  89. reg = <0xf800c000 0x100>;
  90. interrupts = <17 4 0>;
  91. };
  92. dma: dma-controller@ffffec00 {
  93. compatible = "atmel,at91sam9g45-dma";
  94. reg = <0xffffec00 0x200>;
  95. interrupts = <20 4 0>;
  96. };
  97. pinctrl@fffff400 {
  98. #address-cells = <1>;
  99. #size-cells = <1>;
  100. compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
  101. ranges = <0xfffff400 0xfffff400 0x800>;
  102. atmel,mux-mask = <
  103. /* A B C */
  104. 0xffffffff 0xffe07983 0x00000000 /* pioA */
  105. 0x00040000 0x00047e0f 0x00000000 /* pioB */
  106. 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
  107. 0x003fffff 0x003f8000 0x00000000 /* pioD */
  108. >;
  109. /* shared pinctrl settings */
  110. dbgu {
  111. pinctrl_dbgu: dbgu-0 {
  112. atmel,pins =
  113. <0 9 0x1 0x0 /* PA9 periph A */
  114. 0 10 0x1 0x1>; /* PA10 periph with pullup */
  115. };
  116. };
  117. usart0 {
  118. pinctrl_usart0: usart0-0 {
  119. atmel,pins =
  120. <0 1 0x1 0x1 /* PA1 periph A with pullup */
  121. 0 0 0x1 0x0>; /* PA0 periph A */
  122. };
  123. pinctrl_usart0_rts: usart0_rts-0 {
  124. atmel,pins =
  125. <0 2 0x1 0x0>; /* PA2 periph A */
  126. };
  127. pinctrl_usart0_cts: usart0_cts-0 {
  128. atmel,pins =
  129. <0 3 0x1 0x0>; /* PA3 periph A */
  130. };
  131. };
  132. usart1 {
  133. pinctrl_usart1: usart1-0 {
  134. atmel,pins =
  135. <0 6 0x1 0x1 /* PA6 periph A with pullup */
  136. 0 5 0x1 0x0>; /* PA5 periph A */
  137. };
  138. };
  139. usart2 {
  140. pinctrl_usart2: usart2-0 {
  141. atmel,pins =
  142. <0 8 0x1 0x1 /* PA8 periph A with pullup */
  143. 0 7 0x1 0x0>; /* PA7 periph A */
  144. };
  145. pinctrl_usart2_rts: usart2_rts-0 {
  146. atmel,pins =
  147. <1 0 0x2 0x0>; /* PB0 periph B */
  148. };
  149. pinctrl_usart2_cts: usart2_cts-0 {
  150. atmel,pins =
  151. <1 1 0x2 0x0>; /* PB1 periph B */
  152. };
  153. };
  154. usart3 {
  155. pinctrl_usart3: usart3-0 {
  156. atmel,pins =
  157. <2 23 0x2 0x1 /* PC23 periph B with pullup */
  158. 2 22 0x2 0x0>; /* PC22 periph B */
  159. };
  160. pinctrl_usart3_rts: usart3_rts-0 {
  161. atmel,pins =
  162. <2 24 0x2 0x0>; /* PC24 periph B */
  163. };
  164. pinctrl_usart3_cts: usart3_cts-0 {
  165. atmel,pins =
  166. <2 25 0x2 0x0>; /* PC25 periph B */
  167. };
  168. };
  169. uart0 {
  170. pinctrl_uart0: uart0-0 {
  171. atmel,pins =
  172. <2 9 0x3 0x1 /* PC9 periph C with pullup */
  173. 2 8 0x3 0x0>; /* PC8 periph C */
  174. };
  175. };
  176. uart1 {
  177. pinctrl_uart1: uart1-0 {
  178. atmel,pins =
  179. <2 16 0x3 0x1 /* PC17 periph C with pullup */
  180. 2 17 0x3 0x0>; /* PC16 periph C */
  181. };
  182. };
  183. nand {
  184. pinctrl_nand: nand-0 {
  185. atmel,pins =
  186. <3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up*/
  187. 3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */
  188. };
  189. };
  190. mmc0 {
  191. pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
  192. atmel,pins =
  193. <0 17 0x1 0x0 /* PA17 periph A */
  194. 0 16 0x1 0x1 /* PA16 periph A with pullup */
  195. 0 15 0x1 0x1>; /* PA15 periph A with pullup */
  196. };
  197. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  198. atmel,pins =
  199. <0 18 0x1 0x1 /* PA18 periph A with pullup */
  200. 0 19 0x1 0x1 /* PA19 periph A with pullup */
  201. 0 20 0x1 0x1>; /* PA20 periph A with pullup */
  202. };
  203. pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
  204. atmel,pins =
  205. <0 11 0x2 0x1 /* PA11 periph B with pullup */
  206. 0 12 0x2 0x1 /* PA12 periph B with pullup */
  207. 0 13 0x2 0x1 /* PA13 periph B with pullup */
  208. 0 14 0x2 0x1>; /* PA14 periph B with pullup */
  209. };
  210. };
  211. pioA: gpio@fffff400 {
  212. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  213. reg = <0xfffff400 0x200>;
  214. interrupts = <2 4 1>;
  215. #gpio-cells = <2>;
  216. gpio-controller;
  217. interrupt-controller;
  218. #interrupt-cells = <2>;
  219. };
  220. pioB: gpio@fffff600 {
  221. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  222. reg = <0xfffff600 0x200>;
  223. interrupts = <2 4 1>;
  224. #gpio-cells = <2>;
  225. gpio-controller;
  226. interrupt-controller;
  227. #interrupt-cells = <2>;
  228. };
  229. pioC: gpio@fffff800 {
  230. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  231. reg = <0xfffff800 0x200>;
  232. interrupts = <3 4 1>;
  233. #gpio-cells = <2>;
  234. gpio-controller;
  235. interrupt-controller;
  236. #interrupt-cells = <2>;
  237. };
  238. pioD: gpio@fffffa00 {
  239. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  240. reg = <0xfffffa00 0x200>;
  241. interrupts = <3 4 1>;
  242. #gpio-cells = <2>;
  243. gpio-controller;
  244. interrupt-controller;
  245. #interrupt-cells = <2>;
  246. };
  247. };
  248. dbgu: serial@fffff200 {
  249. compatible = "atmel,at91sam9260-usart";
  250. reg = <0xfffff200 0x200>;
  251. interrupts = <1 4 7>;
  252. pinctrl-names = "default";
  253. pinctrl-0 = <&pinctrl_dbgu>;
  254. status = "disabled";
  255. };
  256. usart0: serial@f801c000 {
  257. compatible = "atmel,at91sam9260-usart";
  258. reg = <0xf801c000 0x4000>;
  259. interrupts = <5 4 5>;
  260. atmel,use-dma-rx;
  261. atmel,use-dma-tx;
  262. pinctrl-names = "default";
  263. pinctrl-0 = <&pinctrl_usart0>;
  264. status = "disabled";
  265. };
  266. usart1: serial@f8020000 {
  267. compatible = "atmel,at91sam9260-usart";
  268. reg = <0xf8020000 0x4000>;
  269. interrupts = <6 4 5>;
  270. atmel,use-dma-rx;
  271. atmel,use-dma-tx;
  272. pinctrl-names = "default";
  273. pinctrl-0 = <&pinctrl_usart1>;
  274. status = "disabled";
  275. };
  276. usart2: serial@f8024000 {
  277. compatible = "atmel,at91sam9260-usart";
  278. reg = <0xf8024000 0x4000>;
  279. interrupts = <7 4 5>;
  280. atmel,use-dma-rx;
  281. atmel,use-dma-tx;
  282. pinctrl-names = "default";
  283. pinctrl-0 = <&pinctrl_usart2>;
  284. status = "disabled";
  285. };
  286. usart3: serial@f8028000 {
  287. compatible = "atmel,at91sam9260-usart";
  288. reg = <0xf8028000 0x4000>;
  289. interrupts = <8 4 5>;
  290. atmel,use-dma-rx;
  291. atmel,use-dma-tx;
  292. pinctrl-names = "default";
  293. pinctrl-0 = <&pinctrl_usart3>;
  294. status = "disabled";
  295. };
  296. i2c0: i2c@f8010000 {
  297. compatible = "atmel,at91sam9x5-i2c";
  298. reg = <0xf8010000 0x100>;
  299. interrupts = <9 4 6>;
  300. #address-cells = <1>;
  301. #size-cells = <0>;
  302. status = "disabled";
  303. };
  304. i2c1: i2c@f8014000 {
  305. compatible = "atmel,at91sam9x5-i2c";
  306. reg = <0xf8014000 0x100>;
  307. interrupts = <10 4 6>;
  308. #address-cells = <1>;
  309. #size-cells = <0>;
  310. status = "disabled";
  311. };
  312. };
  313. nand0: nand@40000000 {
  314. compatible = "atmel,at91rm9200-nand";
  315. #address-cells = <1>;
  316. #size-cells = <1>;
  317. reg = < 0x40000000 0x10000000
  318. 0xffffe000 0x00000600
  319. 0xffffe600 0x00000200
  320. 0x00100000 0x00100000
  321. >;
  322. atmel,nand-addr-offset = <21>;
  323. atmel,nand-cmd-offset = <22>;
  324. pinctrl-names = "default";
  325. pinctrl-0 = <&pinctrl_nand>;
  326. gpios = <&pioD 5 0
  327. &pioD 4 0
  328. 0
  329. >;
  330. status = "disabled";
  331. };
  332. usb0: ohci@00500000 {
  333. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  334. reg = <0x00500000 0x00100000>;
  335. interrupts = <22 4 2>;
  336. status = "disabled";
  337. };
  338. };
  339. i2c@0 {
  340. compatible = "i2c-gpio";
  341. gpios = <&pioA 30 0 /* sda */
  342. &pioA 31 0 /* scl */
  343. >;
  344. i2c-gpio,sda-open-drain;
  345. i2c-gpio,scl-open-drain;
  346. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  347. #address-cells = <1>;
  348. #size-cells = <0>;
  349. status = "disabled";
  350. };
  351. };