tegra20_spdif.c 9.5 KB

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  1. /*
  2. * tegra20_spdif.c - Tegra20 SPDIF driver
  3. *
  4. * Author: Stephen Warren <swarren@nvidia.com>
  5. * Copyright (C) 2011-2012 - NVIDIA, Inc.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * version 2 as published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  19. * 02110-1301 USA
  20. *
  21. */
  22. #include <linux/clk.h>
  23. #include <linux/debugfs.h>
  24. #include <linux/device.h>
  25. #include <linux/io.h>
  26. #include <linux/module.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/pm_runtime.h>
  29. #include <linux/seq_file.h>
  30. #include <linux/slab.h>
  31. #include <sound/core.h>
  32. #include <sound/pcm.h>
  33. #include <sound/pcm_params.h>
  34. #include <sound/soc.h>
  35. #include "tegra20_spdif.h"
  36. #define DRV_NAME "tegra20-spdif"
  37. static inline void tegra20_spdif_write(struct tegra20_spdif *spdif, u32 reg,
  38. u32 val)
  39. {
  40. __raw_writel(val, spdif->regs + reg);
  41. }
  42. static inline u32 tegra20_spdif_read(struct tegra20_spdif *spdif, u32 reg)
  43. {
  44. return __raw_readl(spdif->regs + reg);
  45. }
  46. static int tegra20_spdif_runtime_suspend(struct device *dev)
  47. {
  48. struct tegra20_spdif *spdif = dev_get_drvdata(dev);
  49. clk_disable(spdif->clk_spdif_out);
  50. return 0;
  51. }
  52. static int tegra20_spdif_runtime_resume(struct device *dev)
  53. {
  54. struct tegra20_spdif *spdif = dev_get_drvdata(dev);
  55. int ret;
  56. ret = clk_enable(spdif->clk_spdif_out);
  57. if (ret) {
  58. dev_err(dev, "clk_enable failed: %d\n", ret);
  59. return ret;
  60. }
  61. return 0;
  62. }
  63. #ifdef CONFIG_DEBUG_FS
  64. static int tegra20_spdif_show(struct seq_file *s, void *unused)
  65. {
  66. #define REG(r) { r, #r }
  67. static const struct {
  68. int offset;
  69. const char *name;
  70. } regs[] = {
  71. REG(TEGRA20_SPDIF_CTRL),
  72. REG(TEGRA20_SPDIF_STATUS),
  73. REG(TEGRA20_SPDIF_STROBE_CTRL),
  74. REG(TEGRA20_SPDIF_DATA_FIFO_CSR),
  75. REG(TEGRA20_SPDIF_CH_STA_RX_A),
  76. REG(TEGRA20_SPDIF_CH_STA_RX_B),
  77. REG(TEGRA20_SPDIF_CH_STA_RX_C),
  78. REG(TEGRA20_SPDIF_CH_STA_RX_D),
  79. REG(TEGRA20_SPDIF_CH_STA_RX_E),
  80. REG(TEGRA20_SPDIF_CH_STA_RX_F),
  81. REG(TEGRA20_SPDIF_CH_STA_TX_A),
  82. REG(TEGRA20_SPDIF_CH_STA_TX_B),
  83. REG(TEGRA20_SPDIF_CH_STA_TX_C),
  84. REG(TEGRA20_SPDIF_CH_STA_TX_D),
  85. REG(TEGRA20_SPDIF_CH_STA_TX_E),
  86. REG(TEGRA20_SPDIF_CH_STA_TX_F),
  87. };
  88. #undef REG
  89. struct tegra20_spdif *spdif = s->private;
  90. int i;
  91. for (i = 0; i < ARRAY_SIZE(regs); i++) {
  92. u32 val = tegra20_spdif_read(spdif, regs[i].offset);
  93. seq_printf(s, "%s = %08x\n", regs[i].name, val);
  94. }
  95. return 0;
  96. }
  97. static int tegra20_spdif_debug_open(struct inode *inode, struct file *file)
  98. {
  99. return single_open(file, tegra20_spdif_show, inode->i_private);
  100. }
  101. static const struct file_operations tegra20_spdif_debug_fops = {
  102. .open = tegra20_spdif_debug_open,
  103. .read = seq_read,
  104. .llseek = seq_lseek,
  105. .release = single_release,
  106. };
  107. static void tegra20_spdif_debug_add(struct tegra20_spdif *spdif)
  108. {
  109. spdif->debug = debugfs_create_file(DRV_NAME, S_IRUGO,
  110. snd_soc_debugfs_root, spdif,
  111. &tegra20_spdif_debug_fops);
  112. }
  113. static void tegra20_spdif_debug_remove(struct tegra20_spdif *spdif)
  114. {
  115. if (spdif->debug)
  116. debugfs_remove(spdif->debug);
  117. }
  118. #else
  119. static inline void tegra20_spdif_debug_add(struct tegra20_spdif *spdif)
  120. {
  121. }
  122. static inline void tegra20_spdif_debug_remove(struct tegra20_spdif *spdif)
  123. {
  124. }
  125. #endif
  126. static int tegra20_spdif_hw_params(struct snd_pcm_substream *substream,
  127. struct snd_pcm_hw_params *params,
  128. struct snd_soc_dai *dai)
  129. {
  130. struct device *dev = substream->pcm->card->dev;
  131. struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai);
  132. int ret, spdifclock;
  133. spdif->reg_ctrl &= ~TEGRA20_SPDIF_CTRL_PACK;
  134. spdif->reg_ctrl &= ~TEGRA20_SPDIF_CTRL_BIT_MODE_MASK;
  135. switch (params_format(params)) {
  136. case SNDRV_PCM_FORMAT_S16_LE:
  137. spdif->reg_ctrl |= TEGRA20_SPDIF_CTRL_PACK;
  138. spdif->reg_ctrl |= TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT;
  139. break;
  140. default:
  141. return -EINVAL;
  142. }
  143. switch (params_rate(params)) {
  144. case 32000:
  145. spdifclock = 4096000;
  146. break;
  147. case 44100:
  148. spdifclock = 5644800;
  149. break;
  150. case 48000:
  151. spdifclock = 6144000;
  152. break;
  153. case 88200:
  154. spdifclock = 11289600;
  155. break;
  156. case 96000:
  157. spdifclock = 12288000;
  158. break;
  159. case 176400:
  160. spdifclock = 22579200;
  161. break;
  162. case 192000:
  163. spdifclock = 24576000;
  164. break;
  165. default:
  166. return -EINVAL;
  167. }
  168. ret = clk_set_rate(spdif->clk_spdif_out, spdifclock);
  169. if (ret) {
  170. dev_err(dev, "Can't set SPDIF clock rate: %d\n", ret);
  171. return ret;
  172. }
  173. return 0;
  174. }
  175. static void tegra20_spdif_start_playback(struct tegra20_spdif *spdif)
  176. {
  177. spdif->reg_ctrl |= TEGRA20_SPDIF_CTRL_TX_EN;
  178. tegra20_spdif_write(spdif, TEGRA20_SPDIF_CTRL, spdif->reg_ctrl);
  179. }
  180. static void tegra20_spdif_stop_playback(struct tegra20_spdif *spdif)
  181. {
  182. spdif->reg_ctrl &= ~TEGRA20_SPDIF_CTRL_TX_EN;
  183. tegra20_spdif_write(spdif, TEGRA20_SPDIF_CTRL, spdif->reg_ctrl);
  184. }
  185. static int tegra20_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
  186. struct snd_soc_dai *dai)
  187. {
  188. struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai);
  189. switch (cmd) {
  190. case SNDRV_PCM_TRIGGER_START:
  191. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  192. case SNDRV_PCM_TRIGGER_RESUME:
  193. tegra20_spdif_start_playback(spdif);
  194. break;
  195. case SNDRV_PCM_TRIGGER_STOP:
  196. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  197. case SNDRV_PCM_TRIGGER_SUSPEND:
  198. tegra20_spdif_stop_playback(spdif);
  199. break;
  200. default:
  201. return -EINVAL;
  202. }
  203. return 0;
  204. }
  205. static int tegra20_spdif_probe(struct snd_soc_dai *dai)
  206. {
  207. struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai);
  208. dai->capture_dma_data = NULL;
  209. dai->playback_dma_data = &spdif->playback_dma_data;
  210. return 0;
  211. }
  212. static const struct snd_soc_dai_ops tegra20_spdif_dai_ops = {
  213. .hw_params = tegra20_spdif_hw_params,
  214. .trigger = tegra20_spdif_trigger,
  215. };
  216. static struct snd_soc_dai_driver tegra20_spdif_dai = {
  217. .name = DRV_NAME,
  218. .probe = tegra20_spdif_probe,
  219. .playback = {
  220. .channels_min = 2,
  221. .channels_max = 2,
  222. .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
  223. SNDRV_PCM_RATE_48000,
  224. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  225. },
  226. .ops = &tegra20_spdif_dai_ops,
  227. };
  228. static __devinit int tegra20_spdif_platform_probe(struct platform_device *pdev)
  229. {
  230. struct tegra20_spdif *spdif;
  231. struct resource *mem, *memregion, *dmareq;
  232. int ret;
  233. spdif = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_spdif),
  234. GFP_KERNEL);
  235. if (!spdif) {
  236. dev_err(&pdev->dev, "Can't allocate tegra20_spdif\n");
  237. ret = -ENOMEM;
  238. goto err;
  239. }
  240. dev_set_drvdata(&pdev->dev, spdif);
  241. spdif->clk_spdif_out = clk_get(&pdev->dev, "spdif_out");
  242. if (IS_ERR(spdif->clk_spdif_out)) {
  243. pr_err("Can't retrieve spdif clock\n");
  244. ret = PTR_ERR(spdif->clk_spdif_out);
  245. goto err;
  246. }
  247. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  248. if (!mem) {
  249. dev_err(&pdev->dev, "No memory resource\n");
  250. ret = -ENODEV;
  251. goto err_clk_put;
  252. }
  253. dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  254. if (!dmareq) {
  255. dev_err(&pdev->dev, "No DMA resource\n");
  256. ret = -ENODEV;
  257. goto err_clk_put;
  258. }
  259. memregion = devm_request_mem_region(&pdev->dev, mem->start,
  260. resource_size(mem), DRV_NAME);
  261. if (!memregion) {
  262. dev_err(&pdev->dev, "Memory region already claimed\n");
  263. ret = -EBUSY;
  264. goto err_clk_put;
  265. }
  266. spdif->regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
  267. if (!spdif->regs) {
  268. dev_err(&pdev->dev, "ioremap failed\n");
  269. ret = -ENOMEM;
  270. goto err_clk_put;
  271. }
  272. spdif->playback_dma_data.addr = mem->start + TEGRA20_SPDIF_DATA_OUT;
  273. spdif->playback_dma_data.wrap = 4;
  274. spdif->playback_dma_data.width = 32;
  275. spdif->playback_dma_data.req_sel = dmareq->start;
  276. pm_runtime_enable(&pdev->dev);
  277. if (!pm_runtime_enabled(&pdev->dev)) {
  278. ret = tegra20_spdif_runtime_resume(&pdev->dev);
  279. if (ret)
  280. goto err_pm_disable;
  281. }
  282. ret = snd_soc_register_dai(&pdev->dev, &tegra20_spdif_dai);
  283. if (ret) {
  284. dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
  285. ret = -ENOMEM;
  286. goto err_suspend;
  287. }
  288. ret = tegra_pcm_platform_register(&pdev->dev);
  289. if (ret) {
  290. dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
  291. goto err_unregister_dai;
  292. }
  293. tegra20_spdif_debug_add(spdif);
  294. return 0;
  295. err_unregister_dai:
  296. snd_soc_unregister_dai(&pdev->dev);
  297. err_suspend:
  298. if (!pm_runtime_status_suspended(&pdev->dev))
  299. tegra20_spdif_runtime_suspend(&pdev->dev);
  300. err_pm_disable:
  301. pm_runtime_disable(&pdev->dev);
  302. err_clk_put:
  303. clk_put(spdif->clk_spdif_out);
  304. err:
  305. return ret;
  306. }
  307. static int __devexit tegra20_spdif_platform_remove(struct platform_device *pdev)
  308. {
  309. struct tegra20_spdif *spdif = dev_get_drvdata(&pdev->dev);
  310. pm_runtime_disable(&pdev->dev);
  311. if (!pm_runtime_status_suspended(&pdev->dev))
  312. tegra20_spdif_runtime_suspend(&pdev->dev);
  313. tegra_pcm_platform_unregister(&pdev->dev);
  314. snd_soc_unregister_dai(&pdev->dev);
  315. tegra20_spdif_debug_remove(spdif);
  316. clk_put(spdif->clk_spdif_out);
  317. return 0;
  318. }
  319. static const struct dev_pm_ops tegra20_spdif_pm_ops __devinitconst = {
  320. SET_RUNTIME_PM_OPS(tegra20_spdif_runtime_suspend,
  321. tegra20_spdif_runtime_resume, NULL)
  322. };
  323. static struct platform_driver tegra20_spdif_driver = {
  324. .driver = {
  325. .name = DRV_NAME,
  326. .owner = THIS_MODULE,
  327. .pm = &tegra20_spdif_pm_ops,
  328. },
  329. .probe = tegra20_spdif_platform_probe,
  330. .remove = __devexit_p(tegra20_spdif_platform_remove),
  331. };
  332. module_platform_driver(tegra20_spdif_driver);
  333. MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
  334. MODULE_DESCRIPTION("Tegra20 SPDIF ASoC driver");
  335. MODULE_LICENSE("GPL");
  336. MODULE_ALIAS("platform:" DRV_NAME);