qla_os.c 110 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2011 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include <linux/moduleparam.h>
  9. #include <linux/vmalloc.h>
  10. #include <linux/delay.h>
  11. #include <linux/kthread.h>
  12. #include <linux/mutex.h>
  13. #include <linux/kobject.h>
  14. #include <linux/slab.h>
  15. #include <scsi/scsi_tcq.h>
  16. #include <scsi/scsicam.h>
  17. #include <scsi/scsi_transport.h>
  18. #include <scsi/scsi_transport_fc.h>
  19. /*
  20. * Driver version
  21. */
  22. char qla2x00_version_str[40];
  23. static int apidev_major;
  24. /*
  25. * SRB allocation cache
  26. */
  27. static struct kmem_cache *srb_cachep;
  28. /*
  29. * CT6 CTX allocation cache
  30. */
  31. static struct kmem_cache *ctx_cachep;
  32. int ql2xlogintimeout = 20;
  33. module_param(ql2xlogintimeout, int, S_IRUGO);
  34. MODULE_PARM_DESC(ql2xlogintimeout,
  35. "Login timeout value in seconds.");
  36. int qlport_down_retry;
  37. module_param(qlport_down_retry, int, S_IRUGO);
  38. MODULE_PARM_DESC(qlport_down_retry,
  39. "Maximum number of command retries to a port that returns "
  40. "a PORT-DOWN status.");
  41. int ql2xplogiabsentdevice;
  42. module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
  43. MODULE_PARM_DESC(ql2xplogiabsentdevice,
  44. "Option to enable PLOGI to devices that are not present after "
  45. "a Fabric scan. This is needed for several broken switches. "
  46. "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
  47. int ql2xloginretrycount = 0;
  48. module_param(ql2xloginretrycount, int, S_IRUGO);
  49. MODULE_PARM_DESC(ql2xloginretrycount,
  50. "Specify an alternate value for the NVRAM login retry count.");
  51. int ql2xallocfwdump = 1;
  52. module_param(ql2xallocfwdump, int, S_IRUGO);
  53. MODULE_PARM_DESC(ql2xallocfwdump,
  54. "Option to enable allocation of memory for a firmware dump "
  55. "during HBA initialization. Memory allocation requirements "
  56. "vary by ISP type. Default is 1 - allocate memory.");
  57. int ql2xextended_error_logging;
  58. module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
  59. MODULE_PARM_DESC(ql2xextended_error_logging,
  60. "Option to enable extended error logging, "
  61. "Default is 0 - no logging. 1 - log errors.");
  62. int ql2xshiftctondsd = 6;
  63. module_param(ql2xshiftctondsd, int, S_IRUGO);
  64. MODULE_PARM_DESC(ql2xshiftctondsd,
  65. "Set to control shifting of command type processing "
  66. "based on total number of SG elements.");
  67. static void qla2x00_free_device(scsi_qla_host_t *);
  68. int ql2xfdmienable=1;
  69. module_param(ql2xfdmienable, int, S_IRUGO);
  70. MODULE_PARM_DESC(ql2xfdmienable,
  71. "Enables FDMI registrations. "
  72. "0 - no FDMI. Default is 1 - perform FDMI.");
  73. #define MAX_Q_DEPTH 32
  74. static int ql2xmaxqdepth = MAX_Q_DEPTH;
  75. module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
  76. MODULE_PARM_DESC(ql2xmaxqdepth,
  77. "Maximum queue depth to report for target devices.");
  78. /* Do not change the value of this after module load */
  79. int ql2xenabledif = 1;
  80. module_param(ql2xenabledif, int, S_IRUGO|S_IWUSR);
  81. MODULE_PARM_DESC(ql2xenabledif,
  82. " Enable T10-CRC-DIF "
  83. " Default is 0 - No DIF Support. 1 - Enable it");
  84. int ql2xenablehba_err_chk;
  85. module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
  86. MODULE_PARM_DESC(ql2xenablehba_err_chk,
  87. " Enable T10-CRC-DIF Error isolation by HBA"
  88. " Default is 0 - Error isolation disabled, 1 - Enable it");
  89. int ql2xiidmaenable=1;
  90. module_param(ql2xiidmaenable, int, S_IRUGO);
  91. MODULE_PARM_DESC(ql2xiidmaenable,
  92. "Enables iIDMA settings "
  93. "Default is 1 - perform iIDMA. 0 - no iIDMA.");
  94. int ql2xmaxqueues = 1;
  95. module_param(ql2xmaxqueues, int, S_IRUGO);
  96. MODULE_PARM_DESC(ql2xmaxqueues,
  97. "Enables MQ settings "
  98. "Default is 1 for single queue. Set it to number "
  99. "of queues in MQ mode.");
  100. int ql2xmultique_tag;
  101. module_param(ql2xmultique_tag, int, S_IRUGO);
  102. MODULE_PARM_DESC(ql2xmultique_tag,
  103. "Enables CPU affinity settings for the driver "
  104. "Default is 0 for no affinity of request and response IO. "
  105. "Set it to 1 to turn on the cpu affinity.");
  106. int ql2xfwloadbin;
  107. module_param(ql2xfwloadbin, int, S_IRUGO);
  108. MODULE_PARM_DESC(ql2xfwloadbin,
  109. "Option to specify location from which to load ISP firmware:\n"
  110. " 2 -- load firmware via the request_firmware() (hotplug)\n"
  111. " interface.\n"
  112. " 1 -- load firmware from flash.\n"
  113. " 0 -- use default semantics.\n");
  114. int ql2xetsenable;
  115. module_param(ql2xetsenable, int, S_IRUGO);
  116. MODULE_PARM_DESC(ql2xetsenable,
  117. "Enables firmware ETS burst."
  118. "Default is 0 - skip ETS enablement.");
  119. int ql2xdbwr = 1;
  120. module_param(ql2xdbwr, int, S_IRUGO);
  121. MODULE_PARM_DESC(ql2xdbwr,
  122. "Option to specify scheme for request queue posting\n"
  123. " 0 -- Regular doorbell.\n"
  124. " 1 -- CAMRAM doorbell (faster).\n");
  125. int ql2xtargetreset = 1;
  126. module_param(ql2xtargetreset, int, S_IRUGO);
  127. MODULE_PARM_DESC(ql2xtargetreset,
  128. "Enable target reset."
  129. "Default is 1 - use hw defaults.");
  130. int ql2xgffidenable;
  131. module_param(ql2xgffidenable, int, S_IRUGO);
  132. MODULE_PARM_DESC(ql2xgffidenable,
  133. "Enables GFF_ID checks of port type. "
  134. "Default is 0 - Do not use GFF_ID information.");
  135. int ql2xasynctmfenable;
  136. module_param(ql2xasynctmfenable, int, S_IRUGO);
  137. MODULE_PARM_DESC(ql2xasynctmfenable,
  138. "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
  139. "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
  140. int ql2xdontresethba;
  141. module_param(ql2xdontresethba, int, S_IRUGO);
  142. MODULE_PARM_DESC(ql2xdontresethba,
  143. "Option to specify reset behaviour\n"
  144. " 0 (Default) -- Reset on failure.\n"
  145. " 1 -- Do not reset on failure.\n");
  146. uint ql2xmaxlun = MAX_LUNS;
  147. module_param(ql2xmaxlun, uint, S_IRUGO);
  148. MODULE_PARM_DESC(ql2xmaxlun,
  149. "Defines the maximum LU number to register with the SCSI "
  150. "midlayer. Default is 65535.");
  151. /*
  152. * SCSI host template entry points
  153. */
  154. static int qla2xxx_slave_configure(struct scsi_device * device);
  155. static int qla2xxx_slave_alloc(struct scsi_device *);
  156. static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
  157. static void qla2xxx_scan_start(struct Scsi_Host *);
  158. static void qla2xxx_slave_destroy(struct scsi_device *);
  159. static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
  160. static int qla2xxx_eh_abort(struct scsi_cmnd *);
  161. static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
  162. static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
  163. static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
  164. static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
  165. static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
  166. static int qla2x00_change_queue_type(struct scsi_device *, int);
  167. struct scsi_host_template qla2xxx_driver_template = {
  168. .module = THIS_MODULE,
  169. .name = QLA2XXX_DRIVER_NAME,
  170. .queuecommand = qla2xxx_queuecommand,
  171. .eh_abort_handler = qla2xxx_eh_abort,
  172. .eh_device_reset_handler = qla2xxx_eh_device_reset,
  173. .eh_target_reset_handler = qla2xxx_eh_target_reset,
  174. .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
  175. .eh_host_reset_handler = qla2xxx_eh_host_reset,
  176. .slave_configure = qla2xxx_slave_configure,
  177. .slave_alloc = qla2xxx_slave_alloc,
  178. .slave_destroy = qla2xxx_slave_destroy,
  179. .scan_finished = qla2xxx_scan_finished,
  180. .scan_start = qla2xxx_scan_start,
  181. .change_queue_depth = qla2x00_change_queue_depth,
  182. .change_queue_type = qla2x00_change_queue_type,
  183. .this_id = -1,
  184. .cmd_per_lun = 3,
  185. .use_clustering = ENABLE_CLUSTERING,
  186. .sg_tablesize = SG_ALL,
  187. .max_sectors = 0xFFFF,
  188. .shost_attrs = qla2x00_host_attrs,
  189. };
  190. static struct scsi_transport_template *qla2xxx_transport_template = NULL;
  191. struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
  192. /* TODO Convert to inlines
  193. *
  194. * Timer routines
  195. */
  196. __inline__ void
  197. qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
  198. {
  199. init_timer(&vha->timer);
  200. vha->timer.expires = jiffies + interval * HZ;
  201. vha->timer.data = (unsigned long)vha;
  202. vha->timer.function = (void (*)(unsigned long))func;
  203. add_timer(&vha->timer);
  204. vha->timer_active = 1;
  205. }
  206. static inline void
  207. qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
  208. {
  209. /* Currently used for 82XX only. */
  210. if (vha->device_flags & DFLG_DEV_FAILED)
  211. return;
  212. mod_timer(&vha->timer, jiffies + interval * HZ);
  213. }
  214. static __inline__ void
  215. qla2x00_stop_timer(scsi_qla_host_t *vha)
  216. {
  217. del_timer_sync(&vha->timer);
  218. vha->timer_active = 0;
  219. }
  220. static int qla2x00_do_dpc(void *data);
  221. static void qla2x00_rst_aen(scsi_qla_host_t *);
  222. static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
  223. struct req_que **, struct rsp_que **);
  224. static void qla2x00_free_fw_dump(struct qla_hw_data *);
  225. static void qla2x00_mem_free(struct qla_hw_data *);
  226. static void qla2x00_sp_free_dma(srb_t *);
  227. /* -------------------------------------------------------------------------- */
  228. static int qla2x00_alloc_queues(struct qla_hw_data *ha)
  229. {
  230. ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
  231. GFP_KERNEL);
  232. if (!ha->req_q_map) {
  233. qla_printk(KERN_WARNING, ha,
  234. "Unable to allocate memory for request queue ptrs\n");
  235. goto fail_req_map;
  236. }
  237. ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
  238. GFP_KERNEL);
  239. if (!ha->rsp_q_map) {
  240. qla_printk(KERN_WARNING, ha,
  241. "Unable to allocate memory for response queue ptrs\n");
  242. goto fail_rsp_map;
  243. }
  244. set_bit(0, ha->rsp_qid_map);
  245. set_bit(0, ha->req_qid_map);
  246. return 1;
  247. fail_rsp_map:
  248. kfree(ha->req_q_map);
  249. ha->req_q_map = NULL;
  250. fail_req_map:
  251. return -ENOMEM;
  252. }
  253. static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
  254. {
  255. if (req && req->ring)
  256. dma_free_coherent(&ha->pdev->dev,
  257. (req->length + 1) * sizeof(request_t),
  258. req->ring, req->dma);
  259. kfree(req);
  260. req = NULL;
  261. }
  262. static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
  263. {
  264. if (rsp && rsp->ring)
  265. dma_free_coherent(&ha->pdev->dev,
  266. (rsp->length + 1) * sizeof(response_t),
  267. rsp->ring, rsp->dma);
  268. kfree(rsp);
  269. rsp = NULL;
  270. }
  271. static void qla2x00_free_queues(struct qla_hw_data *ha)
  272. {
  273. struct req_que *req;
  274. struct rsp_que *rsp;
  275. int cnt;
  276. for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
  277. req = ha->req_q_map[cnt];
  278. qla2x00_free_req_que(ha, req);
  279. }
  280. kfree(ha->req_q_map);
  281. ha->req_q_map = NULL;
  282. for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
  283. rsp = ha->rsp_q_map[cnt];
  284. qla2x00_free_rsp_que(ha, rsp);
  285. }
  286. kfree(ha->rsp_q_map);
  287. ha->rsp_q_map = NULL;
  288. }
  289. static int qla25xx_setup_mode(struct scsi_qla_host *vha)
  290. {
  291. uint16_t options = 0;
  292. int ques, req, ret;
  293. struct qla_hw_data *ha = vha->hw;
  294. if (!(ha->fw_attributes & BIT_6)) {
  295. qla_printk(KERN_INFO, ha,
  296. "Firmware is not multi-queue capable\n");
  297. goto fail;
  298. }
  299. if (ql2xmultique_tag) {
  300. /* create a request queue for IO */
  301. options |= BIT_7;
  302. req = qla25xx_create_req_que(ha, options, 0, 0, -1,
  303. QLA_DEFAULT_QUE_QOS);
  304. if (!req) {
  305. qla_printk(KERN_WARNING, ha,
  306. "Can't create request queue\n");
  307. goto fail;
  308. }
  309. ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
  310. vha->req = ha->req_q_map[req];
  311. options |= BIT_1;
  312. for (ques = 1; ques < ha->max_rsp_queues; ques++) {
  313. ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
  314. if (!ret) {
  315. qla_printk(KERN_WARNING, ha,
  316. "Response Queue create failed\n");
  317. goto fail2;
  318. }
  319. }
  320. ha->flags.cpu_affinity_enabled = 1;
  321. DEBUG2(qla_printk(KERN_INFO, ha,
  322. "CPU affinity mode enabled, no. of response"
  323. " queues:%d, no. of request queues:%d\n",
  324. ha->max_rsp_queues, ha->max_req_queues));
  325. }
  326. return 0;
  327. fail2:
  328. qla25xx_delete_queues(vha);
  329. destroy_workqueue(ha->wq);
  330. ha->wq = NULL;
  331. fail:
  332. ha->mqenable = 0;
  333. kfree(ha->req_q_map);
  334. kfree(ha->rsp_q_map);
  335. ha->max_req_queues = ha->max_rsp_queues = 1;
  336. return 1;
  337. }
  338. static char *
  339. qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
  340. {
  341. struct qla_hw_data *ha = vha->hw;
  342. static char *pci_bus_modes[] = {
  343. "33", "66", "100", "133",
  344. };
  345. uint16_t pci_bus;
  346. strcpy(str, "PCI");
  347. pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
  348. if (pci_bus) {
  349. strcat(str, "-X (");
  350. strcat(str, pci_bus_modes[pci_bus]);
  351. } else {
  352. pci_bus = (ha->pci_attr & BIT_8) >> 8;
  353. strcat(str, " (");
  354. strcat(str, pci_bus_modes[pci_bus]);
  355. }
  356. strcat(str, " MHz)");
  357. return (str);
  358. }
  359. static char *
  360. qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
  361. {
  362. static char *pci_bus_modes[] = { "33", "66", "100", "133", };
  363. struct qla_hw_data *ha = vha->hw;
  364. uint32_t pci_bus;
  365. int pcie_reg;
  366. pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
  367. if (pcie_reg) {
  368. char lwstr[6];
  369. uint16_t pcie_lstat, lspeed, lwidth;
  370. pcie_reg += 0x12;
  371. pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
  372. lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
  373. lwidth = (pcie_lstat &
  374. (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
  375. strcpy(str, "PCIe (");
  376. if (lspeed == 1)
  377. strcat(str, "2.5GT/s ");
  378. else if (lspeed == 2)
  379. strcat(str, "5.0GT/s ");
  380. else
  381. strcat(str, "<unknown> ");
  382. snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
  383. strcat(str, lwstr);
  384. return str;
  385. }
  386. strcpy(str, "PCI");
  387. pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
  388. if (pci_bus == 0 || pci_bus == 8) {
  389. strcat(str, " (");
  390. strcat(str, pci_bus_modes[pci_bus >> 3]);
  391. } else {
  392. strcat(str, "-X ");
  393. if (pci_bus & BIT_2)
  394. strcat(str, "Mode 2");
  395. else
  396. strcat(str, "Mode 1");
  397. strcat(str, " (");
  398. strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
  399. }
  400. strcat(str, " MHz)");
  401. return str;
  402. }
  403. static char *
  404. qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
  405. {
  406. char un_str[10];
  407. struct qla_hw_data *ha = vha->hw;
  408. sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
  409. ha->fw_minor_version,
  410. ha->fw_subminor_version);
  411. if (ha->fw_attributes & BIT_9) {
  412. strcat(str, "FLX");
  413. return (str);
  414. }
  415. switch (ha->fw_attributes & 0xFF) {
  416. case 0x7:
  417. strcat(str, "EF");
  418. break;
  419. case 0x17:
  420. strcat(str, "TP");
  421. break;
  422. case 0x37:
  423. strcat(str, "IP");
  424. break;
  425. case 0x77:
  426. strcat(str, "VI");
  427. break;
  428. default:
  429. sprintf(un_str, "(%x)", ha->fw_attributes);
  430. strcat(str, un_str);
  431. break;
  432. }
  433. if (ha->fw_attributes & 0x100)
  434. strcat(str, "X");
  435. return (str);
  436. }
  437. static char *
  438. qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
  439. {
  440. struct qla_hw_data *ha = vha->hw;
  441. sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
  442. ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
  443. return str;
  444. }
  445. static inline srb_t *
  446. qla2x00_get_new_sp(scsi_qla_host_t *vha, fc_port_t *fcport,
  447. struct scsi_cmnd *cmd)
  448. {
  449. srb_t *sp;
  450. struct qla_hw_data *ha = vha->hw;
  451. sp = mempool_alloc(ha->srb_mempool, GFP_ATOMIC);
  452. if (!sp)
  453. return sp;
  454. atomic_set(&sp->ref_count, 1);
  455. sp->fcport = fcport;
  456. sp->cmd = cmd;
  457. sp->flags = 0;
  458. CMD_SP(cmd) = (void *)sp;
  459. sp->ctx = NULL;
  460. return sp;
  461. }
  462. static int
  463. qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
  464. {
  465. scsi_qla_host_t *vha = shost_priv(host);
  466. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  467. struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
  468. struct qla_hw_data *ha = vha->hw;
  469. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  470. srb_t *sp;
  471. int rval;
  472. if (ha->flags.eeh_busy) {
  473. if (ha->flags.pci_channel_io_perm_failure)
  474. cmd->result = DID_NO_CONNECT << 16;
  475. else
  476. cmd->result = DID_REQUEUE << 16;
  477. goto qc24_fail_command;
  478. }
  479. rval = fc_remote_port_chkready(rport);
  480. if (rval) {
  481. cmd->result = rval;
  482. goto qc24_fail_command;
  483. }
  484. if (!vha->flags.difdix_supported &&
  485. scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
  486. DEBUG2(qla_printk(KERN_ERR, ha,
  487. "DIF Cap Not Reg, fail DIF capable cmd's:%x\n",
  488. cmd->cmnd[0]));
  489. cmd->result = DID_NO_CONNECT << 16;
  490. goto qc24_fail_command;
  491. }
  492. if (atomic_read(&fcport->state) != FCS_ONLINE) {
  493. if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
  494. atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
  495. cmd->result = DID_NO_CONNECT << 16;
  496. goto qc24_fail_command;
  497. }
  498. goto qc24_target_busy;
  499. }
  500. sp = qla2x00_get_new_sp(base_vha, fcport, cmd);
  501. if (!sp)
  502. goto qc24_host_busy;
  503. rval = ha->isp_ops->start_scsi(sp);
  504. if (rval != QLA_SUCCESS)
  505. goto qc24_host_busy_free_sp;
  506. return 0;
  507. qc24_host_busy_free_sp:
  508. qla2x00_sp_free_dma(sp);
  509. mempool_free(sp, ha->srb_mempool);
  510. qc24_host_busy:
  511. return SCSI_MLQUEUE_HOST_BUSY;
  512. qc24_target_busy:
  513. return SCSI_MLQUEUE_TARGET_BUSY;
  514. qc24_fail_command:
  515. cmd->scsi_done(cmd);
  516. return 0;
  517. }
  518. /*
  519. * qla2x00_eh_wait_on_command
  520. * Waits for the command to be returned by the Firmware for some
  521. * max time.
  522. *
  523. * Input:
  524. * cmd = Scsi Command to wait on.
  525. *
  526. * Return:
  527. * Not Found : 0
  528. * Found : 1
  529. */
  530. static int
  531. qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
  532. {
  533. #define ABORT_POLLING_PERIOD 1000
  534. #define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
  535. unsigned long wait_iter = ABORT_WAIT_ITER;
  536. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  537. struct qla_hw_data *ha = vha->hw;
  538. int ret = QLA_SUCCESS;
  539. if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
  540. DEBUG17(qla_printk(KERN_WARNING, ha, "return:eh_wait\n"));
  541. return ret;
  542. }
  543. while (CMD_SP(cmd) && wait_iter--) {
  544. msleep(ABORT_POLLING_PERIOD);
  545. }
  546. if (CMD_SP(cmd))
  547. ret = QLA_FUNCTION_FAILED;
  548. return ret;
  549. }
  550. /*
  551. * qla2x00_wait_for_hba_online
  552. * Wait till the HBA is online after going through
  553. * <= MAX_RETRIES_OF_ISP_ABORT or
  554. * finally HBA is disabled ie marked offline
  555. *
  556. * Input:
  557. * ha - pointer to host adapter structure
  558. *
  559. * Note:
  560. * Does context switching-Release SPIN_LOCK
  561. * (if any) before calling this routine.
  562. *
  563. * Return:
  564. * Success (Adapter is online) : 0
  565. * Failed (Adapter is offline/disabled) : 1
  566. */
  567. int
  568. qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
  569. {
  570. int return_status;
  571. unsigned long wait_online;
  572. struct qla_hw_data *ha = vha->hw;
  573. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  574. wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  575. while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
  576. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  577. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  578. ha->dpc_active) && time_before(jiffies, wait_online)) {
  579. msleep(1000);
  580. }
  581. if (base_vha->flags.online)
  582. return_status = QLA_SUCCESS;
  583. else
  584. return_status = QLA_FUNCTION_FAILED;
  585. return (return_status);
  586. }
  587. /*
  588. * qla2x00_wait_for_reset_ready
  589. * Wait till the HBA is online after going through
  590. * <= MAX_RETRIES_OF_ISP_ABORT or
  591. * finally HBA is disabled ie marked offline or flash
  592. * operations are in progress.
  593. *
  594. * Input:
  595. * ha - pointer to host adapter structure
  596. *
  597. * Note:
  598. * Does context switching-Release SPIN_LOCK
  599. * (if any) before calling this routine.
  600. *
  601. * Return:
  602. * Success (Adapter is online/no flash ops) : 0
  603. * Failed (Adapter is offline/disabled/flash ops in progress) : 1
  604. */
  605. static int
  606. qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
  607. {
  608. int return_status;
  609. unsigned long wait_online;
  610. struct qla_hw_data *ha = vha->hw;
  611. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  612. wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  613. while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
  614. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  615. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  616. ha->optrom_state != QLA_SWAITING ||
  617. ha->dpc_active) && time_before(jiffies, wait_online))
  618. msleep(1000);
  619. if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
  620. return_status = QLA_SUCCESS;
  621. else
  622. return_status = QLA_FUNCTION_FAILED;
  623. DEBUG2(printk("%s return_status=%d\n", __func__, return_status));
  624. return return_status;
  625. }
  626. int
  627. qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
  628. {
  629. int return_status;
  630. unsigned long wait_reset;
  631. struct qla_hw_data *ha = vha->hw;
  632. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  633. wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  634. while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
  635. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  636. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  637. ha->dpc_active) && time_before(jiffies, wait_reset)) {
  638. msleep(1000);
  639. if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
  640. ha->flags.chip_reset_done)
  641. break;
  642. }
  643. if (ha->flags.chip_reset_done)
  644. return_status = QLA_SUCCESS;
  645. else
  646. return_status = QLA_FUNCTION_FAILED;
  647. return return_status;
  648. }
  649. /*
  650. * qla2x00_wait_for_loop_ready
  651. * Wait for MAX_LOOP_TIMEOUT(5 min) value for loop
  652. * to be in LOOP_READY state.
  653. * Input:
  654. * ha - pointer to host adapter structure
  655. *
  656. * Note:
  657. * Does context switching-Release SPIN_LOCK
  658. * (if any) before calling this routine.
  659. *
  660. *
  661. * Return:
  662. * Success (LOOP_READY) : 0
  663. * Failed (LOOP_NOT_READY) : 1
  664. */
  665. static inline int
  666. qla2x00_wait_for_loop_ready(scsi_qla_host_t *vha)
  667. {
  668. int return_status = QLA_SUCCESS;
  669. unsigned long loop_timeout ;
  670. struct qla_hw_data *ha = vha->hw;
  671. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  672. /* wait for 5 min at the max for loop to be ready */
  673. loop_timeout = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  674. while ((!atomic_read(&base_vha->loop_down_timer) &&
  675. atomic_read(&base_vha->loop_state) == LOOP_DOWN) ||
  676. atomic_read(&base_vha->loop_state) != LOOP_READY) {
  677. if (atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
  678. return_status = QLA_FUNCTION_FAILED;
  679. break;
  680. }
  681. msleep(1000);
  682. if (time_after_eq(jiffies, loop_timeout)) {
  683. return_status = QLA_FUNCTION_FAILED;
  684. break;
  685. }
  686. }
  687. return (return_status);
  688. }
  689. static void
  690. sp_get(struct srb *sp)
  691. {
  692. atomic_inc(&sp->ref_count);
  693. }
  694. /**************************************************************************
  695. * qla2xxx_eh_abort
  696. *
  697. * Description:
  698. * The abort function will abort the specified command.
  699. *
  700. * Input:
  701. * cmd = Linux SCSI command packet to be aborted.
  702. *
  703. * Returns:
  704. * Either SUCCESS or FAILED.
  705. *
  706. * Note:
  707. * Only return FAILED if command not returned by firmware.
  708. **************************************************************************/
  709. static int
  710. qla2xxx_eh_abort(struct scsi_cmnd *cmd)
  711. {
  712. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  713. srb_t *sp;
  714. int ret;
  715. unsigned int id, lun;
  716. unsigned long flags;
  717. int wait = 0;
  718. struct qla_hw_data *ha = vha->hw;
  719. if (!CMD_SP(cmd))
  720. return SUCCESS;
  721. ret = fc_block_scsi_eh(cmd);
  722. if (ret != 0)
  723. return ret;
  724. ret = SUCCESS;
  725. id = cmd->device->id;
  726. lun = cmd->device->lun;
  727. spin_lock_irqsave(&ha->hardware_lock, flags);
  728. sp = (srb_t *) CMD_SP(cmd);
  729. if (!sp) {
  730. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  731. return SUCCESS;
  732. }
  733. DEBUG2(printk("%s(%ld): aborting sp %p from RISC.",
  734. __func__, vha->host_no, sp));
  735. /* Get a reference to the sp and drop the lock.*/
  736. sp_get(sp);
  737. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  738. if (ha->isp_ops->abort_command(sp)) {
  739. DEBUG2(printk("%s(%ld): abort_command "
  740. "mbx failed.\n", __func__, vha->host_no));
  741. ret = FAILED;
  742. } else {
  743. DEBUG3(printk("%s(%ld): abort_command "
  744. "mbx success.\n", __func__, vha->host_no));
  745. wait = 1;
  746. }
  747. qla2x00_sp_compl(ha, sp);
  748. /* Wait for the command to be returned. */
  749. if (wait) {
  750. if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
  751. qla_printk(KERN_ERR, ha,
  752. "scsi(%ld:%d:%d): Abort handler timed out -- %x.\n",
  753. vha->host_no, id, lun, ret);
  754. ret = FAILED;
  755. }
  756. }
  757. qla_printk(KERN_INFO, ha,
  758. "scsi(%ld:%d:%d): Abort command issued -- %d %x.\n",
  759. vha->host_no, id, lun, wait, ret);
  760. return ret;
  761. }
  762. int
  763. qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
  764. unsigned int l, enum nexus_wait_type type)
  765. {
  766. int cnt, match, status;
  767. unsigned long flags;
  768. struct qla_hw_data *ha = vha->hw;
  769. struct req_que *req;
  770. srb_t *sp;
  771. status = QLA_SUCCESS;
  772. spin_lock_irqsave(&ha->hardware_lock, flags);
  773. req = vha->req;
  774. for (cnt = 1; status == QLA_SUCCESS &&
  775. cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
  776. sp = req->outstanding_cmds[cnt];
  777. if (!sp)
  778. continue;
  779. if ((sp->ctx) && !IS_PROT_IO(sp))
  780. continue;
  781. if (vha->vp_idx != sp->fcport->vha->vp_idx)
  782. continue;
  783. match = 0;
  784. switch (type) {
  785. case WAIT_HOST:
  786. match = 1;
  787. break;
  788. case WAIT_TARGET:
  789. match = sp->cmd->device->id == t;
  790. break;
  791. case WAIT_LUN:
  792. match = (sp->cmd->device->id == t &&
  793. sp->cmd->device->lun == l);
  794. break;
  795. }
  796. if (!match)
  797. continue;
  798. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  799. status = qla2x00_eh_wait_on_command(sp->cmd);
  800. spin_lock_irqsave(&ha->hardware_lock, flags);
  801. }
  802. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  803. return status;
  804. }
  805. static char *reset_errors[] = {
  806. "HBA not online",
  807. "HBA not ready",
  808. "Task management failed",
  809. "Waiting for command completions",
  810. };
  811. static int
  812. __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
  813. struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
  814. {
  815. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  816. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  817. int err;
  818. if (!fcport)
  819. return FAILED;
  820. err = fc_block_scsi_eh(cmd);
  821. if (err != 0)
  822. return err;
  823. qla_printk(KERN_INFO, vha->hw, "scsi(%ld:%d:%d): %s RESET ISSUED.\n",
  824. vha->host_no, cmd->device->id, cmd->device->lun, name);
  825. err = 0;
  826. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS)
  827. goto eh_reset_failed;
  828. err = 1;
  829. if (qla2x00_wait_for_loop_ready(vha) != QLA_SUCCESS)
  830. goto eh_reset_failed;
  831. err = 2;
  832. if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
  833. != QLA_SUCCESS)
  834. goto eh_reset_failed;
  835. err = 3;
  836. if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
  837. cmd->device->lun, type) != QLA_SUCCESS)
  838. goto eh_reset_failed;
  839. qla_printk(KERN_INFO, vha->hw, "scsi(%ld:%d:%d): %s RESET SUCCEEDED.\n",
  840. vha->host_no, cmd->device->id, cmd->device->lun, name);
  841. return SUCCESS;
  842. eh_reset_failed:
  843. qla_printk(KERN_INFO, vha->hw, "scsi(%ld:%d:%d): %s RESET FAILED: %s.\n"
  844. , vha->host_no, cmd->device->id, cmd->device->lun, name,
  845. reset_errors[err]);
  846. return FAILED;
  847. }
  848. static int
  849. qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
  850. {
  851. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  852. struct qla_hw_data *ha = vha->hw;
  853. return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
  854. ha->isp_ops->lun_reset);
  855. }
  856. static int
  857. qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
  858. {
  859. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  860. struct qla_hw_data *ha = vha->hw;
  861. return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
  862. ha->isp_ops->target_reset);
  863. }
  864. /**************************************************************************
  865. * qla2xxx_eh_bus_reset
  866. *
  867. * Description:
  868. * The bus reset function will reset the bus and abort any executing
  869. * commands.
  870. *
  871. * Input:
  872. * cmd = Linux SCSI command packet of the command that cause the
  873. * bus reset.
  874. *
  875. * Returns:
  876. * SUCCESS/FAILURE (defined as macro in scsi.h).
  877. *
  878. **************************************************************************/
  879. static int
  880. qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
  881. {
  882. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  883. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  884. int ret = FAILED;
  885. unsigned int id, lun;
  886. id = cmd->device->id;
  887. lun = cmd->device->lun;
  888. if (!fcport)
  889. return ret;
  890. ret = fc_block_scsi_eh(cmd);
  891. if (ret != 0)
  892. return ret;
  893. ret = FAILED;
  894. qla_printk(KERN_INFO, vha->hw,
  895. "scsi(%ld:%d:%d): BUS RESET ISSUED.\n", vha->host_no, id, lun);
  896. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
  897. DEBUG2(printk("%s failed:board disabled\n",__func__));
  898. goto eh_bus_reset_done;
  899. }
  900. if (qla2x00_wait_for_loop_ready(vha) == QLA_SUCCESS) {
  901. if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
  902. ret = SUCCESS;
  903. }
  904. if (ret == FAILED)
  905. goto eh_bus_reset_done;
  906. /* Flush outstanding commands. */
  907. if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
  908. QLA_SUCCESS)
  909. ret = FAILED;
  910. eh_bus_reset_done:
  911. qla_printk(KERN_INFO, vha->hw, "%s: reset %s\n", __func__,
  912. (ret == FAILED) ? "failed" : "succeeded");
  913. return ret;
  914. }
  915. /**************************************************************************
  916. * qla2xxx_eh_host_reset
  917. *
  918. * Description:
  919. * The reset function will reset the Adapter.
  920. *
  921. * Input:
  922. * cmd = Linux SCSI command packet of the command that cause the
  923. * adapter reset.
  924. *
  925. * Returns:
  926. * Either SUCCESS or FAILED.
  927. *
  928. * Note:
  929. **************************************************************************/
  930. static int
  931. qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
  932. {
  933. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  934. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  935. struct qla_hw_data *ha = vha->hw;
  936. int ret = FAILED;
  937. unsigned int id, lun;
  938. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  939. id = cmd->device->id;
  940. lun = cmd->device->lun;
  941. if (!fcport)
  942. return ret;
  943. ret = fc_block_scsi_eh(cmd);
  944. if (ret != 0)
  945. return ret;
  946. ret = FAILED;
  947. qla_printk(KERN_INFO, ha,
  948. "scsi(%ld:%d:%d): ADAPTER RESET ISSUED.\n", vha->host_no, id, lun);
  949. if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
  950. goto eh_host_reset_lock;
  951. /*
  952. * Fixme-may be dpc thread is active and processing
  953. * loop_resync,so wait a while for it to
  954. * be completed and then issue big hammer.Otherwise
  955. * it may cause I/O failure as big hammer marks the
  956. * devices as lost kicking of the port_down_timer
  957. * while dpc is stuck for the mailbox to complete.
  958. */
  959. qla2x00_wait_for_loop_ready(vha);
  960. if (vha != base_vha) {
  961. if (qla2x00_vp_abort_isp(vha))
  962. goto eh_host_reset_lock;
  963. } else {
  964. if (IS_QLA82XX(vha->hw)) {
  965. if (!qla82xx_fcoe_ctx_reset(vha)) {
  966. /* Ctx reset success */
  967. ret = SUCCESS;
  968. goto eh_host_reset_lock;
  969. }
  970. /* fall thru if ctx reset failed */
  971. }
  972. if (ha->wq)
  973. flush_workqueue(ha->wq);
  974. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  975. if (ha->isp_ops->abort_isp(base_vha)) {
  976. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  977. /* failed. schedule dpc to try */
  978. set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
  979. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS)
  980. goto eh_host_reset_lock;
  981. }
  982. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  983. }
  984. /* Waiting for command to be returned to OS.*/
  985. if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
  986. QLA_SUCCESS)
  987. ret = SUCCESS;
  988. eh_host_reset_lock:
  989. qla_printk(KERN_INFO, ha, "%s: reset %s\n", __func__,
  990. (ret == FAILED) ? "failed" : "succeeded");
  991. return ret;
  992. }
  993. /*
  994. * qla2x00_loop_reset
  995. * Issue loop reset.
  996. *
  997. * Input:
  998. * ha = adapter block pointer.
  999. *
  1000. * Returns:
  1001. * 0 = success
  1002. */
  1003. int
  1004. qla2x00_loop_reset(scsi_qla_host_t *vha)
  1005. {
  1006. int ret;
  1007. struct fc_port *fcport;
  1008. struct qla_hw_data *ha = vha->hw;
  1009. if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
  1010. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1011. if (fcport->port_type != FCT_TARGET)
  1012. continue;
  1013. ret = ha->isp_ops->target_reset(fcport, 0, 0);
  1014. if (ret != QLA_SUCCESS) {
  1015. DEBUG2_3(printk("%s(%ld): bus_reset failed: "
  1016. "target_reset=%d d_id=%x.\n", __func__,
  1017. vha->host_no, ret, fcport->d_id.b24));
  1018. }
  1019. }
  1020. }
  1021. if (ha->flags.enable_lip_full_login && !IS_QLA8XXX_TYPE(ha)) {
  1022. ret = qla2x00_full_login_lip(vha);
  1023. if (ret != QLA_SUCCESS) {
  1024. DEBUG2_3(printk("%s(%ld): failed: "
  1025. "full_login_lip=%d.\n", __func__, vha->host_no,
  1026. ret));
  1027. }
  1028. atomic_set(&vha->loop_state, LOOP_DOWN);
  1029. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  1030. qla2x00_mark_all_devices_lost(vha, 0);
  1031. qla2x00_wait_for_loop_ready(vha);
  1032. }
  1033. if (ha->flags.enable_lip_reset) {
  1034. ret = qla2x00_lip_reset(vha);
  1035. if (ret != QLA_SUCCESS) {
  1036. DEBUG2_3(printk("%s(%ld): failed: "
  1037. "lip_reset=%d.\n", __func__, vha->host_no, ret));
  1038. } else
  1039. qla2x00_wait_for_loop_ready(vha);
  1040. }
  1041. /* Issue marker command only when we are going to start the I/O */
  1042. vha->marker_needed = 1;
  1043. return QLA_SUCCESS;
  1044. }
  1045. void
  1046. qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
  1047. {
  1048. int que, cnt;
  1049. unsigned long flags;
  1050. srb_t *sp;
  1051. struct srb_ctx *ctx;
  1052. struct qla_hw_data *ha = vha->hw;
  1053. struct req_que *req;
  1054. spin_lock_irqsave(&ha->hardware_lock, flags);
  1055. for (que = 0; que < ha->max_req_queues; que++) {
  1056. req = ha->req_q_map[que];
  1057. if (!req)
  1058. continue;
  1059. for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
  1060. sp = req->outstanding_cmds[cnt];
  1061. if (sp) {
  1062. req->outstanding_cmds[cnt] = NULL;
  1063. if (!sp->ctx ||
  1064. (sp->flags & SRB_FCP_CMND_DMA_VALID) ||
  1065. IS_PROT_IO(sp)) {
  1066. sp->cmd->result = res;
  1067. qla2x00_sp_compl(ha, sp);
  1068. } else {
  1069. ctx = sp->ctx;
  1070. if (ctx->type == SRB_LOGIN_CMD ||
  1071. ctx->type == SRB_LOGOUT_CMD) {
  1072. ctx->u.iocb_cmd->free(sp);
  1073. } else {
  1074. struct fc_bsg_job *bsg_job =
  1075. ctx->u.bsg_job;
  1076. if (bsg_job->request->msgcode
  1077. == FC_BSG_HST_CT)
  1078. kfree(sp->fcport);
  1079. bsg_job->req->errors = 0;
  1080. bsg_job->reply->result = res;
  1081. bsg_job->job_done(bsg_job);
  1082. kfree(sp->ctx);
  1083. mempool_free(sp,
  1084. ha->srb_mempool);
  1085. }
  1086. }
  1087. }
  1088. }
  1089. }
  1090. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1091. }
  1092. static int
  1093. qla2xxx_slave_alloc(struct scsi_device *sdev)
  1094. {
  1095. struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
  1096. if (!rport || fc_remote_port_chkready(rport))
  1097. return -ENXIO;
  1098. sdev->hostdata = *(fc_port_t **)rport->dd_data;
  1099. return 0;
  1100. }
  1101. static int
  1102. qla2xxx_slave_configure(struct scsi_device *sdev)
  1103. {
  1104. scsi_qla_host_t *vha = shost_priv(sdev->host);
  1105. struct req_que *req = vha->req;
  1106. if (sdev->tagged_supported)
  1107. scsi_activate_tcq(sdev, req->max_q_depth);
  1108. else
  1109. scsi_deactivate_tcq(sdev, req->max_q_depth);
  1110. return 0;
  1111. }
  1112. static void
  1113. qla2xxx_slave_destroy(struct scsi_device *sdev)
  1114. {
  1115. sdev->hostdata = NULL;
  1116. }
  1117. static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
  1118. {
  1119. fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
  1120. if (!scsi_track_queue_full(sdev, qdepth))
  1121. return;
  1122. DEBUG2(qla_printk(KERN_INFO, fcport->vha->hw,
  1123. "scsi(%ld:%d:%d:%d): Queue depth adjusted-down to %d.\n",
  1124. fcport->vha->host_no, sdev->channel, sdev->id, sdev->lun,
  1125. sdev->queue_depth));
  1126. }
  1127. static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
  1128. {
  1129. fc_port_t *fcport = sdev->hostdata;
  1130. struct scsi_qla_host *vha = fcport->vha;
  1131. struct qla_hw_data *ha = vha->hw;
  1132. struct req_que *req = NULL;
  1133. req = vha->req;
  1134. if (!req)
  1135. return;
  1136. if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
  1137. return;
  1138. if (sdev->ordered_tags)
  1139. scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
  1140. else
  1141. scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
  1142. DEBUG2(qla_printk(KERN_INFO, ha,
  1143. "scsi(%ld:%d:%d:%d): Queue depth adjusted-up to %d.\n",
  1144. fcport->vha->host_no, sdev->channel, sdev->id, sdev->lun,
  1145. sdev->queue_depth));
  1146. }
  1147. static int
  1148. qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
  1149. {
  1150. switch (reason) {
  1151. case SCSI_QDEPTH_DEFAULT:
  1152. scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
  1153. break;
  1154. case SCSI_QDEPTH_QFULL:
  1155. qla2x00_handle_queue_full(sdev, qdepth);
  1156. break;
  1157. case SCSI_QDEPTH_RAMP_UP:
  1158. qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
  1159. break;
  1160. default:
  1161. return -EOPNOTSUPP;
  1162. }
  1163. return sdev->queue_depth;
  1164. }
  1165. static int
  1166. qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
  1167. {
  1168. if (sdev->tagged_supported) {
  1169. scsi_set_tag_type(sdev, tag_type);
  1170. if (tag_type)
  1171. scsi_activate_tcq(sdev, sdev->queue_depth);
  1172. else
  1173. scsi_deactivate_tcq(sdev, sdev->queue_depth);
  1174. } else
  1175. tag_type = 0;
  1176. return tag_type;
  1177. }
  1178. /**
  1179. * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
  1180. * @ha: HA context
  1181. *
  1182. * At exit, the @ha's flags.enable_64bit_addressing set to indicated
  1183. * supported addressing method.
  1184. */
  1185. static void
  1186. qla2x00_config_dma_addressing(struct qla_hw_data *ha)
  1187. {
  1188. /* Assume a 32bit DMA mask. */
  1189. ha->flags.enable_64bit_addressing = 0;
  1190. if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
  1191. /* Any upper-dword bits set? */
  1192. if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
  1193. !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
  1194. /* Ok, a 64bit DMA mask is applicable. */
  1195. ha->flags.enable_64bit_addressing = 1;
  1196. ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
  1197. ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
  1198. return;
  1199. }
  1200. }
  1201. dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
  1202. pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
  1203. }
  1204. static void
  1205. qla2x00_enable_intrs(struct qla_hw_data *ha)
  1206. {
  1207. unsigned long flags = 0;
  1208. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1209. spin_lock_irqsave(&ha->hardware_lock, flags);
  1210. ha->interrupts_on = 1;
  1211. /* enable risc and host interrupts */
  1212. WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
  1213. RD_REG_WORD(&reg->ictrl);
  1214. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1215. }
  1216. static void
  1217. qla2x00_disable_intrs(struct qla_hw_data *ha)
  1218. {
  1219. unsigned long flags = 0;
  1220. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1221. spin_lock_irqsave(&ha->hardware_lock, flags);
  1222. ha->interrupts_on = 0;
  1223. /* disable risc and host interrupts */
  1224. WRT_REG_WORD(&reg->ictrl, 0);
  1225. RD_REG_WORD(&reg->ictrl);
  1226. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1227. }
  1228. static void
  1229. qla24xx_enable_intrs(struct qla_hw_data *ha)
  1230. {
  1231. unsigned long flags = 0;
  1232. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  1233. spin_lock_irqsave(&ha->hardware_lock, flags);
  1234. ha->interrupts_on = 1;
  1235. WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
  1236. RD_REG_DWORD(&reg->ictrl);
  1237. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1238. }
  1239. static void
  1240. qla24xx_disable_intrs(struct qla_hw_data *ha)
  1241. {
  1242. unsigned long flags = 0;
  1243. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  1244. if (IS_NOPOLLING_TYPE(ha))
  1245. return;
  1246. spin_lock_irqsave(&ha->hardware_lock, flags);
  1247. ha->interrupts_on = 0;
  1248. WRT_REG_DWORD(&reg->ictrl, 0);
  1249. RD_REG_DWORD(&reg->ictrl);
  1250. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1251. }
  1252. static struct isp_operations qla2100_isp_ops = {
  1253. .pci_config = qla2100_pci_config,
  1254. .reset_chip = qla2x00_reset_chip,
  1255. .chip_diag = qla2x00_chip_diag,
  1256. .config_rings = qla2x00_config_rings,
  1257. .reset_adapter = qla2x00_reset_adapter,
  1258. .nvram_config = qla2x00_nvram_config,
  1259. .update_fw_options = qla2x00_update_fw_options,
  1260. .load_risc = qla2x00_load_risc,
  1261. .pci_info_str = qla2x00_pci_info_str,
  1262. .fw_version_str = qla2x00_fw_version_str,
  1263. .intr_handler = qla2100_intr_handler,
  1264. .enable_intrs = qla2x00_enable_intrs,
  1265. .disable_intrs = qla2x00_disable_intrs,
  1266. .abort_command = qla2x00_abort_command,
  1267. .target_reset = qla2x00_abort_target,
  1268. .lun_reset = qla2x00_lun_reset,
  1269. .fabric_login = qla2x00_login_fabric,
  1270. .fabric_logout = qla2x00_fabric_logout,
  1271. .calc_req_entries = qla2x00_calc_iocbs_32,
  1272. .build_iocbs = qla2x00_build_scsi_iocbs_32,
  1273. .prep_ms_iocb = qla2x00_prep_ms_iocb,
  1274. .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
  1275. .read_nvram = qla2x00_read_nvram_data,
  1276. .write_nvram = qla2x00_write_nvram_data,
  1277. .fw_dump = qla2100_fw_dump,
  1278. .beacon_on = NULL,
  1279. .beacon_off = NULL,
  1280. .beacon_blink = NULL,
  1281. .read_optrom = qla2x00_read_optrom_data,
  1282. .write_optrom = qla2x00_write_optrom_data,
  1283. .get_flash_version = qla2x00_get_flash_version,
  1284. .start_scsi = qla2x00_start_scsi,
  1285. .abort_isp = qla2x00_abort_isp,
  1286. };
  1287. static struct isp_operations qla2300_isp_ops = {
  1288. .pci_config = qla2300_pci_config,
  1289. .reset_chip = qla2x00_reset_chip,
  1290. .chip_diag = qla2x00_chip_diag,
  1291. .config_rings = qla2x00_config_rings,
  1292. .reset_adapter = qla2x00_reset_adapter,
  1293. .nvram_config = qla2x00_nvram_config,
  1294. .update_fw_options = qla2x00_update_fw_options,
  1295. .load_risc = qla2x00_load_risc,
  1296. .pci_info_str = qla2x00_pci_info_str,
  1297. .fw_version_str = qla2x00_fw_version_str,
  1298. .intr_handler = qla2300_intr_handler,
  1299. .enable_intrs = qla2x00_enable_intrs,
  1300. .disable_intrs = qla2x00_disable_intrs,
  1301. .abort_command = qla2x00_abort_command,
  1302. .target_reset = qla2x00_abort_target,
  1303. .lun_reset = qla2x00_lun_reset,
  1304. .fabric_login = qla2x00_login_fabric,
  1305. .fabric_logout = qla2x00_fabric_logout,
  1306. .calc_req_entries = qla2x00_calc_iocbs_32,
  1307. .build_iocbs = qla2x00_build_scsi_iocbs_32,
  1308. .prep_ms_iocb = qla2x00_prep_ms_iocb,
  1309. .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
  1310. .read_nvram = qla2x00_read_nvram_data,
  1311. .write_nvram = qla2x00_write_nvram_data,
  1312. .fw_dump = qla2300_fw_dump,
  1313. .beacon_on = qla2x00_beacon_on,
  1314. .beacon_off = qla2x00_beacon_off,
  1315. .beacon_blink = qla2x00_beacon_blink,
  1316. .read_optrom = qla2x00_read_optrom_data,
  1317. .write_optrom = qla2x00_write_optrom_data,
  1318. .get_flash_version = qla2x00_get_flash_version,
  1319. .start_scsi = qla2x00_start_scsi,
  1320. .abort_isp = qla2x00_abort_isp,
  1321. };
  1322. static struct isp_operations qla24xx_isp_ops = {
  1323. .pci_config = qla24xx_pci_config,
  1324. .reset_chip = qla24xx_reset_chip,
  1325. .chip_diag = qla24xx_chip_diag,
  1326. .config_rings = qla24xx_config_rings,
  1327. .reset_adapter = qla24xx_reset_adapter,
  1328. .nvram_config = qla24xx_nvram_config,
  1329. .update_fw_options = qla24xx_update_fw_options,
  1330. .load_risc = qla24xx_load_risc,
  1331. .pci_info_str = qla24xx_pci_info_str,
  1332. .fw_version_str = qla24xx_fw_version_str,
  1333. .intr_handler = qla24xx_intr_handler,
  1334. .enable_intrs = qla24xx_enable_intrs,
  1335. .disable_intrs = qla24xx_disable_intrs,
  1336. .abort_command = qla24xx_abort_command,
  1337. .target_reset = qla24xx_abort_target,
  1338. .lun_reset = qla24xx_lun_reset,
  1339. .fabric_login = qla24xx_login_fabric,
  1340. .fabric_logout = qla24xx_fabric_logout,
  1341. .calc_req_entries = NULL,
  1342. .build_iocbs = NULL,
  1343. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1344. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1345. .read_nvram = qla24xx_read_nvram_data,
  1346. .write_nvram = qla24xx_write_nvram_data,
  1347. .fw_dump = qla24xx_fw_dump,
  1348. .beacon_on = qla24xx_beacon_on,
  1349. .beacon_off = qla24xx_beacon_off,
  1350. .beacon_blink = qla24xx_beacon_blink,
  1351. .read_optrom = qla24xx_read_optrom_data,
  1352. .write_optrom = qla24xx_write_optrom_data,
  1353. .get_flash_version = qla24xx_get_flash_version,
  1354. .start_scsi = qla24xx_start_scsi,
  1355. .abort_isp = qla2x00_abort_isp,
  1356. };
  1357. static struct isp_operations qla25xx_isp_ops = {
  1358. .pci_config = qla25xx_pci_config,
  1359. .reset_chip = qla24xx_reset_chip,
  1360. .chip_diag = qla24xx_chip_diag,
  1361. .config_rings = qla24xx_config_rings,
  1362. .reset_adapter = qla24xx_reset_adapter,
  1363. .nvram_config = qla24xx_nvram_config,
  1364. .update_fw_options = qla24xx_update_fw_options,
  1365. .load_risc = qla24xx_load_risc,
  1366. .pci_info_str = qla24xx_pci_info_str,
  1367. .fw_version_str = qla24xx_fw_version_str,
  1368. .intr_handler = qla24xx_intr_handler,
  1369. .enable_intrs = qla24xx_enable_intrs,
  1370. .disable_intrs = qla24xx_disable_intrs,
  1371. .abort_command = qla24xx_abort_command,
  1372. .target_reset = qla24xx_abort_target,
  1373. .lun_reset = qla24xx_lun_reset,
  1374. .fabric_login = qla24xx_login_fabric,
  1375. .fabric_logout = qla24xx_fabric_logout,
  1376. .calc_req_entries = NULL,
  1377. .build_iocbs = NULL,
  1378. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1379. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1380. .read_nvram = qla25xx_read_nvram_data,
  1381. .write_nvram = qla25xx_write_nvram_data,
  1382. .fw_dump = qla25xx_fw_dump,
  1383. .beacon_on = qla24xx_beacon_on,
  1384. .beacon_off = qla24xx_beacon_off,
  1385. .beacon_blink = qla24xx_beacon_blink,
  1386. .read_optrom = qla25xx_read_optrom_data,
  1387. .write_optrom = qla24xx_write_optrom_data,
  1388. .get_flash_version = qla24xx_get_flash_version,
  1389. .start_scsi = qla24xx_dif_start_scsi,
  1390. .abort_isp = qla2x00_abort_isp,
  1391. };
  1392. static struct isp_operations qla81xx_isp_ops = {
  1393. .pci_config = qla25xx_pci_config,
  1394. .reset_chip = qla24xx_reset_chip,
  1395. .chip_diag = qla24xx_chip_diag,
  1396. .config_rings = qla24xx_config_rings,
  1397. .reset_adapter = qla24xx_reset_adapter,
  1398. .nvram_config = qla81xx_nvram_config,
  1399. .update_fw_options = qla81xx_update_fw_options,
  1400. .load_risc = qla81xx_load_risc,
  1401. .pci_info_str = qla24xx_pci_info_str,
  1402. .fw_version_str = qla24xx_fw_version_str,
  1403. .intr_handler = qla24xx_intr_handler,
  1404. .enable_intrs = qla24xx_enable_intrs,
  1405. .disable_intrs = qla24xx_disable_intrs,
  1406. .abort_command = qla24xx_abort_command,
  1407. .target_reset = qla24xx_abort_target,
  1408. .lun_reset = qla24xx_lun_reset,
  1409. .fabric_login = qla24xx_login_fabric,
  1410. .fabric_logout = qla24xx_fabric_logout,
  1411. .calc_req_entries = NULL,
  1412. .build_iocbs = NULL,
  1413. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1414. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1415. .read_nvram = NULL,
  1416. .write_nvram = NULL,
  1417. .fw_dump = qla81xx_fw_dump,
  1418. .beacon_on = qla24xx_beacon_on,
  1419. .beacon_off = qla24xx_beacon_off,
  1420. .beacon_blink = qla24xx_beacon_blink,
  1421. .read_optrom = qla25xx_read_optrom_data,
  1422. .write_optrom = qla24xx_write_optrom_data,
  1423. .get_flash_version = qla24xx_get_flash_version,
  1424. .start_scsi = qla24xx_dif_start_scsi,
  1425. .abort_isp = qla2x00_abort_isp,
  1426. };
  1427. static struct isp_operations qla82xx_isp_ops = {
  1428. .pci_config = qla82xx_pci_config,
  1429. .reset_chip = qla82xx_reset_chip,
  1430. .chip_diag = qla24xx_chip_diag,
  1431. .config_rings = qla82xx_config_rings,
  1432. .reset_adapter = qla24xx_reset_adapter,
  1433. .nvram_config = qla81xx_nvram_config,
  1434. .update_fw_options = qla24xx_update_fw_options,
  1435. .load_risc = qla82xx_load_risc,
  1436. .pci_info_str = qla82xx_pci_info_str,
  1437. .fw_version_str = qla24xx_fw_version_str,
  1438. .intr_handler = qla82xx_intr_handler,
  1439. .enable_intrs = qla82xx_enable_intrs,
  1440. .disable_intrs = qla82xx_disable_intrs,
  1441. .abort_command = qla24xx_abort_command,
  1442. .target_reset = qla24xx_abort_target,
  1443. .lun_reset = qla24xx_lun_reset,
  1444. .fabric_login = qla24xx_login_fabric,
  1445. .fabric_logout = qla24xx_fabric_logout,
  1446. .calc_req_entries = NULL,
  1447. .build_iocbs = NULL,
  1448. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1449. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1450. .read_nvram = qla24xx_read_nvram_data,
  1451. .write_nvram = qla24xx_write_nvram_data,
  1452. .fw_dump = qla24xx_fw_dump,
  1453. .beacon_on = qla24xx_beacon_on,
  1454. .beacon_off = qla24xx_beacon_off,
  1455. .beacon_blink = qla24xx_beacon_blink,
  1456. .read_optrom = qla82xx_read_optrom_data,
  1457. .write_optrom = qla82xx_write_optrom_data,
  1458. .get_flash_version = qla24xx_get_flash_version,
  1459. .start_scsi = qla82xx_start_scsi,
  1460. .abort_isp = qla82xx_abort_isp,
  1461. };
  1462. static inline void
  1463. qla2x00_set_isp_flags(struct qla_hw_data *ha)
  1464. {
  1465. ha->device_type = DT_EXTENDED_IDS;
  1466. switch (ha->pdev->device) {
  1467. case PCI_DEVICE_ID_QLOGIC_ISP2100:
  1468. ha->device_type |= DT_ISP2100;
  1469. ha->device_type &= ~DT_EXTENDED_IDS;
  1470. ha->fw_srisc_address = RISC_START_ADDRESS_2100;
  1471. break;
  1472. case PCI_DEVICE_ID_QLOGIC_ISP2200:
  1473. ha->device_type |= DT_ISP2200;
  1474. ha->device_type &= ~DT_EXTENDED_IDS;
  1475. ha->fw_srisc_address = RISC_START_ADDRESS_2100;
  1476. break;
  1477. case PCI_DEVICE_ID_QLOGIC_ISP2300:
  1478. ha->device_type |= DT_ISP2300;
  1479. ha->device_type |= DT_ZIO_SUPPORTED;
  1480. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1481. break;
  1482. case PCI_DEVICE_ID_QLOGIC_ISP2312:
  1483. ha->device_type |= DT_ISP2312;
  1484. ha->device_type |= DT_ZIO_SUPPORTED;
  1485. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1486. break;
  1487. case PCI_DEVICE_ID_QLOGIC_ISP2322:
  1488. ha->device_type |= DT_ISP2322;
  1489. ha->device_type |= DT_ZIO_SUPPORTED;
  1490. if (ha->pdev->subsystem_vendor == 0x1028 &&
  1491. ha->pdev->subsystem_device == 0x0170)
  1492. ha->device_type |= DT_OEM_001;
  1493. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1494. break;
  1495. case PCI_DEVICE_ID_QLOGIC_ISP6312:
  1496. ha->device_type |= DT_ISP6312;
  1497. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1498. break;
  1499. case PCI_DEVICE_ID_QLOGIC_ISP6322:
  1500. ha->device_type |= DT_ISP6322;
  1501. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1502. break;
  1503. case PCI_DEVICE_ID_QLOGIC_ISP2422:
  1504. ha->device_type |= DT_ISP2422;
  1505. ha->device_type |= DT_ZIO_SUPPORTED;
  1506. ha->device_type |= DT_FWI2;
  1507. ha->device_type |= DT_IIDMA;
  1508. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1509. break;
  1510. case PCI_DEVICE_ID_QLOGIC_ISP2432:
  1511. ha->device_type |= DT_ISP2432;
  1512. ha->device_type |= DT_ZIO_SUPPORTED;
  1513. ha->device_type |= DT_FWI2;
  1514. ha->device_type |= DT_IIDMA;
  1515. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1516. break;
  1517. case PCI_DEVICE_ID_QLOGIC_ISP8432:
  1518. ha->device_type |= DT_ISP8432;
  1519. ha->device_type |= DT_ZIO_SUPPORTED;
  1520. ha->device_type |= DT_FWI2;
  1521. ha->device_type |= DT_IIDMA;
  1522. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1523. break;
  1524. case PCI_DEVICE_ID_QLOGIC_ISP5422:
  1525. ha->device_type |= DT_ISP5422;
  1526. ha->device_type |= DT_FWI2;
  1527. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1528. break;
  1529. case PCI_DEVICE_ID_QLOGIC_ISP5432:
  1530. ha->device_type |= DT_ISP5432;
  1531. ha->device_type |= DT_FWI2;
  1532. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1533. break;
  1534. case PCI_DEVICE_ID_QLOGIC_ISP2532:
  1535. ha->device_type |= DT_ISP2532;
  1536. ha->device_type |= DT_ZIO_SUPPORTED;
  1537. ha->device_type |= DT_FWI2;
  1538. ha->device_type |= DT_IIDMA;
  1539. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1540. break;
  1541. case PCI_DEVICE_ID_QLOGIC_ISP8001:
  1542. ha->device_type |= DT_ISP8001;
  1543. ha->device_type |= DT_ZIO_SUPPORTED;
  1544. ha->device_type |= DT_FWI2;
  1545. ha->device_type |= DT_IIDMA;
  1546. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1547. break;
  1548. case PCI_DEVICE_ID_QLOGIC_ISP8021:
  1549. ha->device_type |= DT_ISP8021;
  1550. ha->device_type |= DT_ZIO_SUPPORTED;
  1551. ha->device_type |= DT_FWI2;
  1552. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1553. /* Initialize 82XX ISP flags */
  1554. qla82xx_init_flags(ha);
  1555. break;
  1556. }
  1557. if (IS_QLA82XX(ha))
  1558. ha->port_no = !(ha->portnum & 1);
  1559. else
  1560. /* Get adapter physical port no from interrupt pin register. */
  1561. pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
  1562. if (ha->port_no & 1)
  1563. ha->flags.port0 = 1;
  1564. else
  1565. ha->flags.port0 = 0;
  1566. }
  1567. static int
  1568. qla2x00_iospace_config(struct qla_hw_data *ha)
  1569. {
  1570. resource_size_t pio;
  1571. uint16_t msix;
  1572. int cpus;
  1573. if (IS_QLA82XX(ha))
  1574. return qla82xx_iospace_config(ha);
  1575. if (pci_request_selected_regions(ha->pdev, ha->bars,
  1576. QLA2XXX_DRIVER_NAME)) {
  1577. qla_printk(KERN_WARNING, ha,
  1578. "Failed to reserve PIO/MMIO regions (%s)\n",
  1579. pci_name(ha->pdev));
  1580. goto iospace_error_exit;
  1581. }
  1582. if (!(ha->bars & 1))
  1583. goto skip_pio;
  1584. /* We only need PIO for Flash operations on ISP2312 v2 chips. */
  1585. pio = pci_resource_start(ha->pdev, 0);
  1586. if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
  1587. if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
  1588. qla_printk(KERN_WARNING, ha,
  1589. "Invalid PCI I/O region size (%s)...\n",
  1590. pci_name(ha->pdev));
  1591. pio = 0;
  1592. }
  1593. } else {
  1594. qla_printk(KERN_WARNING, ha,
  1595. "region #0 not a PIO resource (%s)...\n",
  1596. pci_name(ha->pdev));
  1597. pio = 0;
  1598. }
  1599. ha->pio_address = pio;
  1600. skip_pio:
  1601. /* Use MMIO operations for all accesses. */
  1602. if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
  1603. qla_printk(KERN_ERR, ha,
  1604. "region #1 not an MMIO resource (%s), aborting\n",
  1605. pci_name(ha->pdev));
  1606. goto iospace_error_exit;
  1607. }
  1608. if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
  1609. qla_printk(KERN_ERR, ha,
  1610. "Invalid PCI mem region size (%s), aborting\n",
  1611. pci_name(ha->pdev));
  1612. goto iospace_error_exit;
  1613. }
  1614. ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
  1615. if (!ha->iobase) {
  1616. qla_printk(KERN_ERR, ha,
  1617. "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
  1618. goto iospace_error_exit;
  1619. }
  1620. /* Determine queue resources */
  1621. ha->max_req_queues = ha->max_rsp_queues = 1;
  1622. if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
  1623. (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
  1624. (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
  1625. goto mqiobase_exit;
  1626. ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
  1627. pci_resource_len(ha->pdev, 3));
  1628. if (ha->mqiobase) {
  1629. /* Read MSIX vector size of the board */
  1630. pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
  1631. ha->msix_count = msix;
  1632. /* Max queues are bounded by available msix vectors */
  1633. /* queue 0 uses two msix vectors */
  1634. if (ql2xmultique_tag) {
  1635. cpus = num_online_cpus();
  1636. ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
  1637. (cpus + 1) : (ha->msix_count - 1);
  1638. ha->max_req_queues = 2;
  1639. } else if (ql2xmaxqueues > 1) {
  1640. ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
  1641. QLA_MQ_SIZE : ql2xmaxqueues;
  1642. DEBUG2(qla_printk(KERN_INFO, ha, "QoS mode set, max no"
  1643. " of request queues:%d\n", ha->max_req_queues));
  1644. }
  1645. qla_printk(KERN_INFO, ha,
  1646. "MSI-X vector count: %d\n", msix);
  1647. } else
  1648. qla_printk(KERN_INFO, ha, "BAR 3 not enabled\n");
  1649. mqiobase_exit:
  1650. ha->msix_count = ha->max_rsp_queues + 1;
  1651. return (0);
  1652. iospace_error_exit:
  1653. return (-ENOMEM);
  1654. }
  1655. static void
  1656. qla2xxx_scan_start(struct Scsi_Host *shost)
  1657. {
  1658. scsi_qla_host_t *vha = shost_priv(shost);
  1659. if (vha->hw->flags.running_gold_fw)
  1660. return;
  1661. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1662. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  1663. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  1664. set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
  1665. }
  1666. static int
  1667. qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
  1668. {
  1669. scsi_qla_host_t *vha = shost_priv(shost);
  1670. if (!vha->host)
  1671. return 1;
  1672. if (time > vha->hw->loop_reset_delay * HZ)
  1673. return 1;
  1674. return atomic_read(&vha->loop_state) == LOOP_READY;
  1675. }
  1676. /*
  1677. * PCI driver interface
  1678. */
  1679. static int __devinit
  1680. qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
  1681. {
  1682. int ret = -ENODEV;
  1683. struct Scsi_Host *host;
  1684. scsi_qla_host_t *base_vha = NULL;
  1685. struct qla_hw_data *ha;
  1686. char pci_info[30];
  1687. char fw_str[30];
  1688. struct scsi_host_template *sht;
  1689. int bars, max_id, mem_only = 0;
  1690. uint16_t req_length = 0, rsp_length = 0;
  1691. struct req_que *req = NULL;
  1692. struct rsp_que *rsp = NULL;
  1693. bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
  1694. sht = &qla2xxx_driver_template;
  1695. if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
  1696. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
  1697. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
  1698. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
  1699. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
  1700. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
  1701. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
  1702. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021) {
  1703. bars = pci_select_bars(pdev, IORESOURCE_MEM);
  1704. mem_only = 1;
  1705. }
  1706. if (mem_only) {
  1707. if (pci_enable_device_mem(pdev))
  1708. goto probe_out;
  1709. } else {
  1710. if (pci_enable_device(pdev))
  1711. goto probe_out;
  1712. }
  1713. /* This may fail but that's ok */
  1714. pci_enable_pcie_error_reporting(pdev);
  1715. ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
  1716. if (!ha) {
  1717. DEBUG(printk("Unable to allocate memory for ha\n"));
  1718. goto probe_out;
  1719. }
  1720. ha->pdev = pdev;
  1721. /* Clear our data area */
  1722. ha->bars = bars;
  1723. ha->mem_only = mem_only;
  1724. spin_lock_init(&ha->hardware_lock);
  1725. spin_lock_init(&ha->vport_slock);
  1726. /* Set ISP-type information. */
  1727. qla2x00_set_isp_flags(ha);
  1728. /* Set EEH reset type to fundamental if required by hba */
  1729. if ( IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha)) {
  1730. pdev->needs_freset = 1;
  1731. }
  1732. /* Configure PCI I/O space */
  1733. ret = qla2x00_iospace_config(ha);
  1734. if (ret)
  1735. goto probe_hw_failed;
  1736. qla_printk(KERN_INFO, ha,
  1737. "Found an ISP%04X, irq %d, iobase 0x%p\n", pdev->device, pdev->irq,
  1738. ha->iobase);
  1739. ha->prev_topology = 0;
  1740. ha->init_cb_size = sizeof(init_cb_t);
  1741. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  1742. ha->optrom_size = OPTROM_SIZE_2300;
  1743. /* Assign ISP specific operations. */
  1744. max_id = MAX_TARGETS_2200;
  1745. if (IS_QLA2100(ha)) {
  1746. max_id = MAX_TARGETS_2100;
  1747. ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
  1748. req_length = REQUEST_ENTRY_CNT_2100;
  1749. rsp_length = RESPONSE_ENTRY_CNT_2100;
  1750. ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
  1751. ha->gid_list_info_size = 4;
  1752. ha->flash_conf_off = ~0;
  1753. ha->flash_data_off = ~0;
  1754. ha->nvram_conf_off = ~0;
  1755. ha->nvram_data_off = ~0;
  1756. ha->isp_ops = &qla2100_isp_ops;
  1757. } else if (IS_QLA2200(ha)) {
  1758. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1759. req_length = REQUEST_ENTRY_CNT_2200;
  1760. rsp_length = RESPONSE_ENTRY_CNT_2100;
  1761. ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
  1762. ha->gid_list_info_size = 4;
  1763. ha->flash_conf_off = ~0;
  1764. ha->flash_data_off = ~0;
  1765. ha->nvram_conf_off = ~0;
  1766. ha->nvram_data_off = ~0;
  1767. ha->isp_ops = &qla2100_isp_ops;
  1768. } else if (IS_QLA23XX(ha)) {
  1769. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1770. req_length = REQUEST_ENTRY_CNT_2200;
  1771. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1772. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1773. ha->gid_list_info_size = 6;
  1774. if (IS_QLA2322(ha) || IS_QLA6322(ha))
  1775. ha->optrom_size = OPTROM_SIZE_2322;
  1776. ha->flash_conf_off = ~0;
  1777. ha->flash_data_off = ~0;
  1778. ha->nvram_conf_off = ~0;
  1779. ha->nvram_data_off = ~0;
  1780. ha->isp_ops = &qla2300_isp_ops;
  1781. } else if (IS_QLA24XX_TYPE(ha)) {
  1782. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1783. req_length = REQUEST_ENTRY_CNT_24XX;
  1784. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1785. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1786. ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
  1787. ha->gid_list_info_size = 8;
  1788. ha->optrom_size = OPTROM_SIZE_24XX;
  1789. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
  1790. ha->isp_ops = &qla24xx_isp_ops;
  1791. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  1792. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  1793. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  1794. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  1795. } else if (IS_QLA25XX(ha)) {
  1796. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1797. req_length = REQUEST_ENTRY_CNT_24XX;
  1798. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1799. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1800. ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
  1801. ha->gid_list_info_size = 8;
  1802. ha->optrom_size = OPTROM_SIZE_25XX;
  1803. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  1804. ha->isp_ops = &qla25xx_isp_ops;
  1805. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  1806. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  1807. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  1808. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  1809. } else if (IS_QLA81XX(ha)) {
  1810. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1811. req_length = REQUEST_ENTRY_CNT_24XX;
  1812. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1813. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1814. ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
  1815. ha->gid_list_info_size = 8;
  1816. ha->optrom_size = OPTROM_SIZE_81XX;
  1817. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  1818. ha->isp_ops = &qla81xx_isp_ops;
  1819. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
  1820. ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
  1821. ha->nvram_conf_off = ~0;
  1822. ha->nvram_data_off = ~0;
  1823. } else if (IS_QLA82XX(ha)) {
  1824. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1825. req_length = REQUEST_ENTRY_CNT_82XX;
  1826. rsp_length = RESPONSE_ENTRY_CNT_82XX;
  1827. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1828. ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
  1829. ha->gid_list_info_size = 8;
  1830. ha->optrom_size = OPTROM_SIZE_82XX;
  1831. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  1832. ha->isp_ops = &qla82xx_isp_ops;
  1833. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  1834. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  1835. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  1836. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  1837. }
  1838. mutex_init(&ha->vport_lock);
  1839. init_completion(&ha->mbx_cmd_comp);
  1840. complete(&ha->mbx_cmd_comp);
  1841. init_completion(&ha->mbx_intr_comp);
  1842. init_completion(&ha->dcbx_comp);
  1843. set_bit(0, (unsigned long *) ha->vp_idx_map);
  1844. qla2x00_config_dma_addressing(ha);
  1845. ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
  1846. if (!ret) {
  1847. qla_printk(KERN_WARNING, ha,
  1848. "[ERROR] Failed to allocate memory for adapter\n");
  1849. goto probe_hw_failed;
  1850. }
  1851. req->max_q_depth = MAX_Q_DEPTH;
  1852. if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
  1853. req->max_q_depth = ql2xmaxqdepth;
  1854. base_vha = qla2x00_create_host(sht, ha);
  1855. if (!base_vha) {
  1856. qla_printk(KERN_WARNING, ha,
  1857. "[ERROR] Failed to allocate memory for scsi_host\n");
  1858. ret = -ENOMEM;
  1859. qla2x00_mem_free(ha);
  1860. qla2x00_free_req_que(ha, req);
  1861. qla2x00_free_rsp_que(ha, rsp);
  1862. goto probe_hw_failed;
  1863. }
  1864. pci_set_drvdata(pdev, base_vha);
  1865. host = base_vha->host;
  1866. base_vha->req = req;
  1867. host->can_queue = req->length + 128;
  1868. if (IS_QLA2XXX_MIDTYPE(ha))
  1869. base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
  1870. else
  1871. base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
  1872. base_vha->vp_idx;
  1873. /* Set the SG table size based on ISP type */
  1874. if (!IS_FWI2_CAPABLE(ha)) {
  1875. if (IS_QLA2100(ha))
  1876. host->sg_tablesize = 32;
  1877. } else {
  1878. if (!IS_QLA82XX(ha))
  1879. host->sg_tablesize = QLA_SG_ALL;
  1880. }
  1881. host->max_id = max_id;
  1882. host->this_id = 255;
  1883. host->cmd_per_lun = 3;
  1884. host->unique_id = host->host_no;
  1885. if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && ql2xenabledif)
  1886. host->max_cmd_len = 32;
  1887. else
  1888. host->max_cmd_len = MAX_CMDSZ;
  1889. host->max_channel = MAX_BUSES - 1;
  1890. host->max_lun = ql2xmaxlun;
  1891. host->transportt = qla2xxx_transport_template;
  1892. sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
  1893. /* Set up the irqs */
  1894. ret = qla2x00_request_irqs(ha, rsp);
  1895. if (ret)
  1896. goto probe_init_failed;
  1897. pci_save_state(pdev);
  1898. /* Alloc arrays of request and response ring ptrs */
  1899. que_init:
  1900. if (!qla2x00_alloc_queues(ha)) {
  1901. qla_printk(KERN_WARNING, ha,
  1902. "[ERROR] Failed to allocate memory for queue"
  1903. " pointers\n");
  1904. goto probe_init_failed;
  1905. }
  1906. ha->rsp_q_map[0] = rsp;
  1907. ha->req_q_map[0] = req;
  1908. rsp->req = req;
  1909. req->rsp = rsp;
  1910. set_bit(0, ha->req_qid_map);
  1911. set_bit(0, ha->rsp_qid_map);
  1912. /* FWI2-capable only. */
  1913. req->req_q_in = &ha->iobase->isp24.req_q_in;
  1914. req->req_q_out = &ha->iobase->isp24.req_q_out;
  1915. rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
  1916. rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
  1917. if (ha->mqenable) {
  1918. req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
  1919. req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
  1920. rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
  1921. rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
  1922. }
  1923. if (IS_QLA82XX(ha)) {
  1924. req->req_q_out = &ha->iobase->isp82.req_q_out[0];
  1925. rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
  1926. rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
  1927. }
  1928. if (qla2x00_initialize_adapter(base_vha)) {
  1929. qla_printk(KERN_WARNING, ha,
  1930. "Failed to initialize adapter\n");
  1931. DEBUG2(printk("scsi(%ld): Failed to initialize adapter - "
  1932. "Adapter flags %x.\n",
  1933. base_vha->host_no, base_vha->device_flags));
  1934. if (IS_QLA82XX(ha)) {
  1935. qla82xx_idc_lock(ha);
  1936. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  1937. QLA82XX_DEV_FAILED);
  1938. qla82xx_idc_unlock(ha);
  1939. qla_printk(KERN_INFO, ha, "HW State: FAILED\n");
  1940. }
  1941. ret = -ENODEV;
  1942. goto probe_failed;
  1943. }
  1944. if (ha->mqenable) {
  1945. if (qla25xx_setup_mode(base_vha)) {
  1946. qla_printk(KERN_WARNING, ha,
  1947. "Can't create queues, falling back to single"
  1948. " queue mode\n");
  1949. goto que_init;
  1950. }
  1951. }
  1952. if (ha->flags.running_gold_fw)
  1953. goto skip_dpc;
  1954. /*
  1955. * Startup the kernel thread for this host adapter
  1956. */
  1957. ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
  1958. "%s_dpc", base_vha->host_str);
  1959. if (IS_ERR(ha->dpc_thread)) {
  1960. qla_printk(KERN_WARNING, ha,
  1961. "Unable to start DPC thread!\n");
  1962. ret = PTR_ERR(ha->dpc_thread);
  1963. goto probe_failed;
  1964. }
  1965. skip_dpc:
  1966. list_add_tail(&base_vha->list, &ha->vp_list);
  1967. base_vha->host->irq = ha->pdev->irq;
  1968. /* Initialized the timer */
  1969. qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
  1970. DEBUG2(printk("DEBUG: detect hba %ld at address = %p\n",
  1971. base_vha->host_no, ha));
  1972. if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && ql2xenabledif) {
  1973. if (ha->fw_attributes & BIT_4) {
  1974. base_vha->flags.difdix_supported = 1;
  1975. DEBUG18(qla_printk(KERN_INFO, ha,
  1976. "Registering for DIF/DIX type 1 and 3"
  1977. " protection.\n"));
  1978. scsi_host_set_prot(host,
  1979. SHOST_DIF_TYPE1_PROTECTION
  1980. | SHOST_DIF_TYPE2_PROTECTION
  1981. | SHOST_DIF_TYPE3_PROTECTION
  1982. | SHOST_DIX_TYPE1_PROTECTION
  1983. | SHOST_DIX_TYPE2_PROTECTION
  1984. | SHOST_DIX_TYPE3_PROTECTION);
  1985. scsi_host_set_guard(host, SHOST_DIX_GUARD_CRC);
  1986. } else
  1987. base_vha->flags.difdix_supported = 0;
  1988. }
  1989. ha->isp_ops->enable_intrs(ha);
  1990. ret = scsi_add_host(host, &pdev->dev);
  1991. if (ret)
  1992. goto probe_failed;
  1993. base_vha->flags.init_done = 1;
  1994. base_vha->flags.online = 1;
  1995. scsi_scan_host(host);
  1996. qla2x00_alloc_sysfs_attr(base_vha);
  1997. qla2x00_init_host_attr(base_vha);
  1998. qla2x00_dfs_setup(base_vha);
  1999. qla_printk(KERN_INFO, ha, "\n"
  2000. " QLogic Fibre Channel HBA Driver: %s\n"
  2001. " QLogic %s - %s\n"
  2002. " ISP%04X: %s @ %s hdma%c, host#=%ld, fw=%s\n",
  2003. qla2x00_version_str, ha->model_number,
  2004. ha->model_desc ? ha->model_desc : "", pdev->device,
  2005. ha->isp_ops->pci_info_str(base_vha, pci_info), pci_name(pdev),
  2006. ha->flags.enable_64bit_addressing ? '+' : '-', base_vha->host_no,
  2007. ha->isp_ops->fw_version_str(base_vha, fw_str));
  2008. return 0;
  2009. probe_init_failed:
  2010. qla2x00_free_req_que(ha, req);
  2011. qla2x00_free_rsp_que(ha, rsp);
  2012. ha->max_req_queues = ha->max_rsp_queues = 0;
  2013. probe_failed:
  2014. if (base_vha->timer_active)
  2015. qla2x00_stop_timer(base_vha);
  2016. base_vha->flags.online = 0;
  2017. if (ha->dpc_thread) {
  2018. struct task_struct *t = ha->dpc_thread;
  2019. ha->dpc_thread = NULL;
  2020. kthread_stop(t);
  2021. }
  2022. qla2x00_free_device(base_vha);
  2023. scsi_host_put(base_vha->host);
  2024. probe_hw_failed:
  2025. if (IS_QLA82XX(ha)) {
  2026. qla82xx_idc_lock(ha);
  2027. qla82xx_clear_drv_active(ha);
  2028. qla82xx_idc_unlock(ha);
  2029. iounmap((device_reg_t __iomem *)ha->nx_pcibase);
  2030. if (!ql2xdbwr)
  2031. iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
  2032. } else {
  2033. if (ha->iobase)
  2034. iounmap(ha->iobase);
  2035. }
  2036. pci_release_selected_regions(ha->pdev, ha->bars);
  2037. kfree(ha);
  2038. ha = NULL;
  2039. probe_out:
  2040. pci_disable_device(pdev);
  2041. return ret;
  2042. }
  2043. static void
  2044. qla2x00_shutdown(struct pci_dev *pdev)
  2045. {
  2046. scsi_qla_host_t *vha;
  2047. struct qla_hw_data *ha;
  2048. vha = pci_get_drvdata(pdev);
  2049. ha = vha->hw;
  2050. /* Turn-off FCE trace */
  2051. if (ha->flags.fce_enabled) {
  2052. qla2x00_disable_fce_trace(vha, NULL, NULL);
  2053. ha->flags.fce_enabled = 0;
  2054. }
  2055. /* Turn-off EFT trace */
  2056. if (ha->eft)
  2057. qla2x00_disable_eft_trace(vha);
  2058. /* Stop currently executing firmware. */
  2059. qla2x00_try_to_stop_firmware(vha);
  2060. /* Turn adapter off line */
  2061. vha->flags.online = 0;
  2062. /* turn-off interrupts on the card */
  2063. if (ha->interrupts_on) {
  2064. vha->flags.init_done = 0;
  2065. ha->isp_ops->disable_intrs(ha);
  2066. }
  2067. qla2x00_free_irqs(vha);
  2068. qla2x00_free_fw_dump(ha);
  2069. }
  2070. static void
  2071. qla2x00_remove_one(struct pci_dev *pdev)
  2072. {
  2073. scsi_qla_host_t *base_vha, *vha;
  2074. struct qla_hw_data *ha;
  2075. unsigned long flags;
  2076. base_vha = pci_get_drvdata(pdev);
  2077. ha = base_vha->hw;
  2078. mutex_lock(&ha->vport_lock);
  2079. while (ha->cur_vport_count) {
  2080. struct Scsi_Host *scsi_host;
  2081. spin_lock_irqsave(&ha->vport_slock, flags);
  2082. BUG_ON(base_vha->list.next == &ha->vp_list);
  2083. /* This assumes first entry in ha->vp_list is always base vha */
  2084. vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
  2085. scsi_host = scsi_host_get(vha->host);
  2086. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2087. mutex_unlock(&ha->vport_lock);
  2088. fc_vport_terminate(vha->fc_vport);
  2089. scsi_host_put(vha->host);
  2090. mutex_lock(&ha->vport_lock);
  2091. }
  2092. mutex_unlock(&ha->vport_lock);
  2093. set_bit(UNLOADING, &base_vha->dpc_flags);
  2094. qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
  2095. qla2x00_dfs_remove(base_vha);
  2096. qla84xx_put_chip(base_vha);
  2097. /* Disable timer */
  2098. if (base_vha->timer_active)
  2099. qla2x00_stop_timer(base_vha);
  2100. base_vha->flags.online = 0;
  2101. /* Flush the work queue and remove it */
  2102. if (ha->wq) {
  2103. flush_workqueue(ha->wq);
  2104. destroy_workqueue(ha->wq);
  2105. ha->wq = NULL;
  2106. }
  2107. /* Kill the kernel thread for this host */
  2108. if (ha->dpc_thread) {
  2109. struct task_struct *t = ha->dpc_thread;
  2110. /*
  2111. * qla2xxx_wake_dpc checks for ->dpc_thread
  2112. * so we need to zero it out.
  2113. */
  2114. ha->dpc_thread = NULL;
  2115. kthread_stop(t);
  2116. }
  2117. qla2x00_free_sysfs_attr(base_vha);
  2118. fc_remove_host(base_vha->host);
  2119. scsi_remove_host(base_vha->host);
  2120. qla2x00_free_device(base_vha);
  2121. scsi_host_put(base_vha->host);
  2122. if (IS_QLA82XX(ha)) {
  2123. qla82xx_idc_lock(ha);
  2124. qla82xx_clear_drv_active(ha);
  2125. qla82xx_idc_unlock(ha);
  2126. iounmap((device_reg_t __iomem *)ha->nx_pcibase);
  2127. if (!ql2xdbwr)
  2128. iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
  2129. } else {
  2130. if (ha->iobase)
  2131. iounmap(ha->iobase);
  2132. if (ha->mqiobase)
  2133. iounmap(ha->mqiobase);
  2134. }
  2135. pci_release_selected_regions(ha->pdev, ha->bars);
  2136. kfree(ha);
  2137. ha = NULL;
  2138. pci_disable_pcie_error_reporting(pdev);
  2139. pci_disable_device(pdev);
  2140. pci_set_drvdata(pdev, NULL);
  2141. }
  2142. static void
  2143. qla2x00_free_device(scsi_qla_host_t *vha)
  2144. {
  2145. struct qla_hw_data *ha = vha->hw;
  2146. qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
  2147. /* Disable timer */
  2148. if (vha->timer_active)
  2149. qla2x00_stop_timer(vha);
  2150. /* Kill the kernel thread for this host */
  2151. if (ha->dpc_thread) {
  2152. struct task_struct *t = ha->dpc_thread;
  2153. /*
  2154. * qla2xxx_wake_dpc checks for ->dpc_thread
  2155. * so we need to zero it out.
  2156. */
  2157. ha->dpc_thread = NULL;
  2158. kthread_stop(t);
  2159. }
  2160. qla25xx_delete_queues(vha);
  2161. if (ha->flags.fce_enabled)
  2162. qla2x00_disable_fce_trace(vha, NULL, NULL);
  2163. if (ha->eft)
  2164. qla2x00_disable_eft_trace(vha);
  2165. /* Stop currently executing firmware. */
  2166. qla2x00_try_to_stop_firmware(vha);
  2167. vha->flags.online = 0;
  2168. /* turn-off interrupts on the card */
  2169. if (ha->interrupts_on) {
  2170. vha->flags.init_done = 0;
  2171. ha->isp_ops->disable_intrs(ha);
  2172. }
  2173. qla2x00_free_irqs(vha);
  2174. qla2x00_free_fcports(vha);
  2175. qla2x00_mem_free(ha);
  2176. qla2x00_free_queues(ha);
  2177. }
  2178. void qla2x00_free_fcports(struct scsi_qla_host *vha)
  2179. {
  2180. fc_port_t *fcport, *tfcport;
  2181. list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
  2182. list_del(&fcport->list);
  2183. kfree(fcport);
  2184. fcport = NULL;
  2185. }
  2186. }
  2187. static inline void
  2188. qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
  2189. int defer)
  2190. {
  2191. struct fc_rport *rport;
  2192. scsi_qla_host_t *base_vha;
  2193. unsigned long flags;
  2194. if (!fcport->rport)
  2195. return;
  2196. rport = fcport->rport;
  2197. if (defer) {
  2198. base_vha = pci_get_drvdata(vha->hw->pdev);
  2199. spin_lock_irqsave(vha->host->host_lock, flags);
  2200. fcport->drport = rport;
  2201. spin_unlock_irqrestore(vha->host->host_lock, flags);
  2202. set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
  2203. qla2xxx_wake_dpc(base_vha);
  2204. } else
  2205. fc_remote_port_delete(rport);
  2206. }
  2207. /*
  2208. * qla2x00_mark_device_lost Updates fcport state when device goes offline.
  2209. *
  2210. * Input: ha = adapter block pointer. fcport = port structure pointer.
  2211. *
  2212. * Return: None.
  2213. *
  2214. * Context:
  2215. */
  2216. void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
  2217. int do_login, int defer)
  2218. {
  2219. if (atomic_read(&fcport->state) == FCS_ONLINE &&
  2220. vha->vp_idx == fcport->vp_idx) {
  2221. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  2222. qla2x00_schedule_rport_del(vha, fcport, defer);
  2223. }
  2224. /*
  2225. * We may need to retry the login, so don't change the state of the
  2226. * port but do the retries.
  2227. */
  2228. if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
  2229. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  2230. if (!do_login)
  2231. return;
  2232. if (fcport->login_retry == 0) {
  2233. fcport->login_retry = vha->hw->login_retry_count;
  2234. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  2235. DEBUG(printk("scsi(%ld): Port login retry: "
  2236. "%02x%02x%02x%02x%02x%02x%02x%02x, "
  2237. "id = 0x%04x retry cnt=%d\n",
  2238. vha->host_no,
  2239. fcport->port_name[0],
  2240. fcport->port_name[1],
  2241. fcport->port_name[2],
  2242. fcport->port_name[3],
  2243. fcport->port_name[4],
  2244. fcport->port_name[5],
  2245. fcport->port_name[6],
  2246. fcport->port_name[7],
  2247. fcport->loop_id,
  2248. fcport->login_retry));
  2249. }
  2250. }
  2251. /*
  2252. * qla2x00_mark_all_devices_lost
  2253. * Updates fcport state when device goes offline.
  2254. *
  2255. * Input:
  2256. * ha = adapter block pointer.
  2257. * fcport = port structure pointer.
  2258. *
  2259. * Return:
  2260. * None.
  2261. *
  2262. * Context:
  2263. */
  2264. void
  2265. qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
  2266. {
  2267. fc_port_t *fcport;
  2268. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2269. if (vha->vp_idx != 0 && vha->vp_idx != fcport->vp_idx)
  2270. continue;
  2271. /*
  2272. * No point in marking the device as lost, if the device is
  2273. * already DEAD.
  2274. */
  2275. if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
  2276. continue;
  2277. if (atomic_read(&fcport->state) == FCS_ONLINE) {
  2278. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  2279. if (defer)
  2280. qla2x00_schedule_rport_del(vha, fcport, defer);
  2281. else if (vha->vp_idx == fcport->vp_idx)
  2282. qla2x00_schedule_rport_del(vha, fcport, defer);
  2283. }
  2284. }
  2285. }
  2286. /*
  2287. * qla2x00_mem_alloc
  2288. * Allocates adapter memory.
  2289. *
  2290. * Returns:
  2291. * 0 = success.
  2292. * !0 = failure.
  2293. */
  2294. static int
  2295. qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
  2296. struct req_que **req, struct rsp_que **rsp)
  2297. {
  2298. char name[16];
  2299. ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
  2300. &ha->init_cb_dma, GFP_KERNEL);
  2301. if (!ha->init_cb)
  2302. goto fail;
  2303. ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, GID_LIST_SIZE,
  2304. &ha->gid_list_dma, GFP_KERNEL);
  2305. if (!ha->gid_list)
  2306. goto fail_free_init_cb;
  2307. ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
  2308. if (!ha->srb_mempool)
  2309. goto fail_free_gid_list;
  2310. if (IS_QLA82XX(ha)) {
  2311. /* Allocate cache for CT6 Ctx. */
  2312. if (!ctx_cachep) {
  2313. ctx_cachep = kmem_cache_create("qla2xxx_ctx",
  2314. sizeof(struct ct6_dsd), 0,
  2315. SLAB_HWCACHE_ALIGN, NULL);
  2316. if (!ctx_cachep)
  2317. goto fail_free_gid_list;
  2318. }
  2319. ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
  2320. ctx_cachep);
  2321. if (!ha->ctx_mempool)
  2322. goto fail_free_srb_mempool;
  2323. }
  2324. /* Get memory for cached NVRAM */
  2325. ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
  2326. if (!ha->nvram)
  2327. goto fail_free_ctx_mempool;
  2328. snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
  2329. ha->pdev->device);
  2330. ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  2331. DMA_POOL_SIZE, 8, 0);
  2332. if (!ha->s_dma_pool)
  2333. goto fail_free_nvram;
  2334. if (IS_QLA82XX(ha) || ql2xenabledif) {
  2335. ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  2336. DSD_LIST_DMA_POOL_SIZE, 8, 0);
  2337. if (!ha->dl_dma_pool) {
  2338. qla_printk(KERN_WARNING, ha,
  2339. "Memory Allocation failed - dl_dma_pool\n");
  2340. goto fail_s_dma_pool;
  2341. }
  2342. ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  2343. FCP_CMND_DMA_POOL_SIZE, 8, 0);
  2344. if (!ha->fcp_cmnd_dma_pool) {
  2345. qla_printk(KERN_WARNING, ha,
  2346. "Memory Allocation failed - fcp_cmnd_dma_pool\n");
  2347. goto fail_dl_dma_pool;
  2348. }
  2349. }
  2350. /* Allocate memory for SNS commands */
  2351. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  2352. /* Get consistent memory allocated for SNS commands */
  2353. ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
  2354. sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
  2355. if (!ha->sns_cmd)
  2356. goto fail_dma_pool;
  2357. } else {
  2358. /* Get consistent memory allocated for MS IOCB */
  2359. ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  2360. &ha->ms_iocb_dma);
  2361. if (!ha->ms_iocb)
  2362. goto fail_dma_pool;
  2363. /* Get consistent memory allocated for CT SNS commands */
  2364. ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
  2365. sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
  2366. if (!ha->ct_sns)
  2367. goto fail_free_ms_iocb;
  2368. }
  2369. /* Allocate memory for request ring */
  2370. *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
  2371. if (!*req) {
  2372. DEBUG(printk("Unable to allocate memory for req\n"));
  2373. goto fail_req;
  2374. }
  2375. (*req)->length = req_len;
  2376. (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
  2377. ((*req)->length + 1) * sizeof(request_t),
  2378. &(*req)->dma, GFP_KERNEL);
  2379. if (!(*req)->ring) {
  2380. DEBUG(printk("Unable to allocate memory for req_ring\n"));
  2381. goto fail_req_ring;
  2382. }
  2383. /* Allocate memory for response ring */
  2384. *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
  2385. if (!*rsp) {
  2386. qla_printk(KERN_WARNING, ha,
  2387. "Unable to allocate memory for rsp\n");
  2388. goto fail_rsp;
  2389. }
  2390. (*rsp)->hw = ha;
  2391. (*rsp)->length = rsp_len;
  2392. (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
  2393. ((*rsp)->length + 1) * sizeof(response_t),
  2394. &(*rsp)->dma, GFP_KERNEL);
  2395. if (!(*rsp)->ring) {
  2396. qla_printk(KERN_WARNING, ha,
  2397. "Unable to allocate memory for rsp_ring\n");
  2398. goto fail_rsp_ring;
  2399. }
  2400. (*req)->rsp = *rsp;
  2401. (*rsp)->req = *req;
  2402. /* Allocate memory for NVRAM data for vports */
  2403. if (ha->nvram_npiv_size) {
  2404. ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
  2405. ha->nvram_npiv_size, GFP_KERNEL);
  2406. if (!ha->npiv_info) {
  2407. qla_printk(KERN_WARNING, ha,
  2408. "Unable to allocate memory for npiv info\n");
  2409. goto fail_npiv_info;
  2410. }
  2411. } else
  2412. ha->npiv_info = NULL;
  2413. /* Get consistent memory allocated for EX-INIT-CB. */
  2414. if (IS_QLA8XXX_TYPE(ha)) {
  2415. ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  2416. &ha->ex_init_cb_dma);
  2417. if (!ha->ex_init_cb)
  2418. goto fail_ex_init_cb;
  2419. }
  2420. INIT_LIST_HEAD(&ha->gbl_dsd_list);
  2421. /* Get consistent memory allocated for Async Port-Database. */
  2422. if (!IS_FWI2_CAPABLE(ha)) {
  2423. ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  2424. &ha->async_pd_dma);
  2425. if (!ha->async_pd)
  2426. goto fail_async_pd;
  2427. }
  2428. INIT_LIST_HEAD(&ha->vp_list);
  2429. return 1;
  2430. fail_async_pd:
  2431. dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
  2432. fail_ex_init_cb:
  2433. kfree(ha->npiv_info);
  2434. fail_npiv_info:
  2435. dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
  2436. sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
  2437. (*rsp)->ring = NULL;
  2438. (*rsp)->dma = 0;
  2439. fail_rsp_ring:
  2440. kfree(*rsp);
  2441. fail_rsp:
  2442. dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
  2443. sizeof(request_t), (*req)->ring, (*req)->dma);
  2444. (*req)->ring = NULL;
  2445. (*req)->dma = 0;
  2446. fail_req_ring:
  2447. kfree(*req);
  2448. fail_req:
  2449. dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
  2450. ha->ct_sns, ha->ct_sns_dma);
  2451. ha->ct_sns = NULL;
  2452. ha->ct_sns_dma = 0;
  2453. fail_free_ms_iocb:
  2454. dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
  2455. ha->ms_iocb = NULL;
  2456. ha->ms_iocb_dma = 0;
  2457. fail_dma_pool:
  2458. if (IS_QLA82XX(ha) || ql2xenabledif) {
  2459. dma_pool_destroy(ha->fcp_cmnd_dma_pool);
  2460. ha->fcp_cmnd_dma_pool = NULL;
  2461. }
  2462. fail_dl_dma_pool:
  2463. if (IS_QLA82XX(ha) || ql2xenabledif) {
  2464. dma_pool_destroy(ha->dl_dma_pool);
  2465. ha->dl_dma_pool = NULL;
  2466. }
  2467. fail_s_dma_pool:
  2468. dma_pool_destroy(ha->s_dma_pool);
  2469. ha->s_dma_pool = NULL;
  2470. fail_free_nvram:
  2471. kfree(ha->nvram);
  2472. ha->nvram = NULL;
  2473. fail_free_ctx_mempool:
  2474. mempool_destroy(ha->ctx_mempool);
  2475. ha->ctx_mempool = NULL;
  2476. fail_free_srb_mempool:
  2477. mempool_destroy(ha->srb_mempool);
  2478. ha->srb_mempool = NULL;
  2479. fail_free_gid_list:
  2480. dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
  2481. ha->gid_list_dma);
  2482. ha->gid_list = NULL;
  2483. ha->gid_list_dma = 0;
  2484. fail_free_init_cb:
  2485. dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
  2486. ha->init_cb_dma);
  2487. ha->init_cb = NULL;
  2488. ha->init_cb_dma = 0;
  2489. fail:
  2490. DEBUG(printk("%s: Memory allocation failure\n", __func__));
  2491. return -ENOMEM;
  2492. }
  2493. /*
  2494. * qla2x00_free_fw_dump
  2495. * Frees fw dump stuff.
  2496. *
  2497. * Input:
  2498. * ha = adapter block pointer.
  2499. */
  2500. static void
  2501. qla2x00_free_fw_dump(struct qla_hw_data *ha)
  2502. {
  2503. if (ha->fce)
  2504. dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
  2505. ha->fce_dma);
  2506. if (ha->fw_dump) {
  2507. if (ha->eft)
  2508. dma_free_coherent(&ha->pdev->dev,
  2509. ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
  2510. vfree(ha->fw_dump);
  2511. }
  2512. ha->fce = NULL;
  2513. ha->fce_dma = 0;
  2514. ha->eft = NULL;
  2515. ha->eft_dma = 0;
  2516. ha->fw_dump = NULL;
  2517. ha->fw_dumped = 0;
  2518. ha->fw_dump_reading = 0;
  2519. }
  2520. /*
  2521. * qla2x00_mem_free
  2522. * Frees all adapter allocated memory.
  2523. *
  2524. * Input:
  2525. * ha = adapter block pointer.
  2526. */
  2527. static void
  2528. qla2x00_mem_free(struct qla_hw_data *ha)
  2529. {
  2530. qla2x00_free_fw_dump(ha);
  2531. if (ha->srb_mempool)
  2532. mempool_destroy(ha->srb_mempool);
  2533. if (ha->dcbx_tlv)
  2534. dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
  2535. ha->dcbx_tlv, ha->dcbx_tlv_dma);
  2536. if (ha->xgmac_data)
  2537. dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
  2538. ha->xgmac_data, ha->xgmac_data_dma);
  2539. if (ha->sns_cmd)
  2540. dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
  2541. ha->sns_cmd, ha->sns_cmd_dma);
  2542. if (ha->ct_sns)
  2543. dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
  2544. ha->ct_sns, ha->ct_sns_dma);
  2545. if (ha->sfp_data)
  2546. dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
  2547. if (ha->edc_data)
  2548. dma_pool_free(ha->s_dma_pool, ha->edc_data, ha->edc_data_dma);
  2549. if (ha->ms_iocb)
  2550. dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
  2551. if (ha->ex_init_cb)
  2552. dma_pool_free(ha->s_dma_pool,
  2553. ha->ex_init_cb, ha->ex_init_cb_dma);
  2554. if (ha->async_pd)
  2555. dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
  2556. if (ha->s_dma_pool)
  2557. dma_pool_destroy(ha->s_dma_pool);
  2558. if (ha->gid_list)
  2559. dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
  2560. ha->gid_list_dma);
  2561. if (IS_QLA82XX(ha)) {
  2562. if (!list_empty(&ha->gbl_dsd_list)) {
  2563. struct dsd_dma *dsd_ptr, *tdsd_ptr;
  2564. /* clean up allocated prev pool */
  2565. list_for_each_entry_safe(dsd_ptr,
  2566. tdsd_ptr, &ha->gbl_dsd_list, list) {
  2567. dma_pool_free(ha->dl_dma_pool,
  2568. dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
  2569. list_del(&dsd_ptr->list);
  2570. kfree(dsd_ptr);
  2571. }
  2572. }
  2573. }
  2574. if (ha->dl_dma_pool)
  2575. dma_pool_destroy(ha->dl_dma_pool);
  2576. if (ha->fcp_cmnd_dma_pool)
  2577. dma_pool_destroy(ha->fcp_cmnd_dma_pool);
  2578. if (ha->ctx_mempool)
  2579. mempool_destroy(ha->ctx_mempool);
  2580. if (ha->init_cb)
  2581. dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
  2582. ha->init_cb, ha->init_cb_dma);
  2583. vfree(ha->optrom_buffer);
  2584. kfree(ha->nvram);
  2585. kfree(ha->npiv_info);
  2586. ha->srb_mempool = NULL;
  2587. ha->ctx_mempool = NULL;
  2588. ha->sns_cmd = NULL;
  2589. ha->sns_cmd_dma = 0;
  2590. ha->ct_sns = NULL;
  2591. ha->ct_sns_dma = 0;
  2592. ha->ms_iocb = NULL;
  2593. ha->ms_iocb_dma = 0;
  2594. ha->init_cb = NULL;
  2595. ha->init_cb_dma = 0;
  2596. ha->ex_init_cb = NULL;
  2597. ha->ex_init_cb_dma = 0;
  2598. ha->async_pd = NULL;
  2599. ha->async_pd_dma = 0;
  2600. ha->s_dma_pool = NULL;
  2601. ha->dl_dma_pool = NULL;
  2602. ha->fcp_cmnd_dma_pool = NULL;
  2603. ha->gid_list = NULL;
  2604. ha->gid_list_dma = 0;
  2605. }
  2606. struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
  2607. struct qla_hw_data *ha)
  2608. {
  2609. struct Scsi_Host *host;
  2610. struct scsi_qla_host *vha = NULL;
  2611. host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
  2612. if (host == NULL) {
  2613. printk(KERN_WARNING
  2614. "qla2xxx: Couldn't allocate host from scsi layer!\n");
  2615. goto fail;
  2616. }
  2617. /* Clear our data area */
  2618. vha = shost_priv(host);
  2619. memset(vha, 0, sizeof(scsi_qla_host_t));
  2620. vha->host = host;
  2621. vha->host_no = host->host_no;
  2622. vha->hw = ha;
  2623. INIT_LIST_HEAD(&vha->vp_fcports);
  2624. INIT_LIST_HEAD(&vha->work_list);
  2625. INIT_LIST_HEAD(&vha->list);
  2626. spin_lock_init(&vha->work_lock);
  2627. sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
  2628. return vha;
  2629. fail:
  2630. return vha;
  2631. }
  2632. static struct qla_work_evt *
  2633. qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
  2634. {
  2635. struct qla_work_evt *e;
  2636. uint8_t bail;
  2637. QLA_VHA_MARK_BUSY(vha, bail);
  2638. if (bail)
  2639. return NULL;
  2640. e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
  2641. if (!e) {
  2642. QLA_VHA_MARK_NOT_BUSY(vha);
  2643. return NULL;
  2644. }
  2645. INIT_LIST_HEAD(&e->list);
  2646. e->type = type;
  2647. e->flags = QLA_EVT_FLAG_FREE;
  2648. return e;
  2649. }
  2650. static int
  2651. qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
  2652. {
  2653. unsigned long flags;
  2654. spin_lock_irqsave(&vha->work_lock, flags);
  2655. list_add_tail(&e->list, &vha->work_list);
  2656. spin_unlock_irqrestore(&vha->work_lock, flags);
  2657. qla2xxx_wake_dpc(vha);
  2658. return QLA_SUCCESS;
  2659. }
  2660. int
  2661. qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
  2662. u32 data)
  2663. {
  2664. struct qla_work_evt *e;
  2665. e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
  2666. if (!e)
  2667. return QLA_FUNCTION_FAILED;
  2668. e->u.aen.code = code;
  2669. e->u.aen.data = data;
  2670. return qla2x00_post_work(vha, e);
  2671. }
  2672. int
  2673. qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
  2674. {
  2675. struct qla_work_evt *e;
  2676. e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
  2677. if (!e)
  2678. return QLA_FUNCTION_FAILED;
  2679. memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
  2680. return qla2x00_post_work(vha, e);
  2681. }
  2682. #define qla2x00_post_async_work(name, type) \
  2683. int qla2x00_post_async_##name##_work( \
  2684. struct scsi_qla_host *vha, \
  2685. fc_port_t *fcport, uint16_t *data) \
  2686. { \
  2687. struct qla_work_evt *e; \
  2688. \
  2689. e = qla2x00_alloc_work(vha, type); \
  2690. if (!e) \
  2691. return QLA_FUNCTION_FAILED; \
  2692. \
  2693. e->u.logio.fcport = fcport; \
  2694. if (data) { \
  2695. e->u.logio.data[0] = data[0]; \
  2696. e->u.logio.data[1] = data[1]; \
  2697. } \
  2698. return qla2x00_post_work(vha, e); \
  2699. }
  2700. qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
  2701. qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
  2702. qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
  2703. qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
  2704. qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
  2705. qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
  2706. int
  2707. qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
  2708. {
  2709. struct qla_work_evt *e;
  2710. e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
  2711. if (!e)
  2712. return QLA_FUNCTION_FAILED;
  2713. e->u.uevent.code = code;
  2714. return qla2x00_post_work(vha, e);
  2715. }
  2716. static void
  2717. qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
  2718. {
  2719. char event_string[40];
  2720. char *envp[] = { event_string, NULL };
  2721. switch (code) {
  2722. case QLA_UEVENT_CODE_FW_DUMP:
  2723. snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
  2724. vha->host_no);
  2725. break;
  2726. default:
  2727. /* do nothing */
  2728. break;
  2729. }
  2730. kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
  2731. }
  2732. void
  2733. qla2x00_do_work(struct scsi_qla_host *vha)
  2734. {
  2735. struct qla_work_evt *e, *tmp;
  2736. unsigned long flags;
  2737. LIST_HEAD(work);
  2738. spin_lock_irqsave(&vha->work_lock, flags);
  2739. list_splice_init(&vha->work_list, &work);
  2740. spin_unlock_irqrestore(&vha->work_lock, flags);
  2741. list_for_each_entry_safe(e, tmp, &work, list) {
  2742. list_del_init(&e->list);
  2743. switch (e->type) {
  2744. case QLA_EVT_AEN:
  2745. fc_host_post_event(vha->host, fc_get_event_number(),
  2746. e->u.aen.code, e->u.aen.data);
  2747. break;
  2748. case QLA_EVT_IDC_ACK:
  2749. qla81xx_idc_ack(vha, e->u.idc_ack.mb);
  2750. break;
  2751. case QLA_EVT_ASYNC_LOGIN:
  2752. qla2x00_async_login(vha, e->u.logio.fcport,
  2753. e->u.logio.data);
  2754. break;
  2755. case QLA_EVT_ASYNC_LOGIN_DONE:
  2756. qla2x00_async_login_done(vha, e->u.logio.fcport,
  2757. e->u.logio.data);
  2758. break;
  2759. case QLA_EVT_ASYNC_LOGOUT:
  2760. qla2x00_async_logout(vha, e->u.logio.fcport);
  2761. break;
  2762. case QLA_EVT_ASYNC_LOGOUT_DONE:
  2763. qla2x00_async_logout_done(vha, e->u.logio.fcport,
  2764. e->u.logio.data);
  2765. break;
  2766. case QLA_EVT_ASYNC_ADISC:
  2767. qla2x00_async_adisc(vha, e->u.logio.fcport,
  2768. e->u.logio.data);
  2769. break;
  2770. case QLA_EVT_ASYNC_ADISC_DONE:
  2771. qla2x00_async_adisc_done(vha, e->u.logio.fcport,
  2772. e->u.logio.data);
  2773. break;
  2774. case QLA_EVT_UEVENT:
  2775. qla2x00_uevent_emit(vha, e->u.uevent.code);
  2776. break;
  2777. }
  2778. if (e->flags & QLA_EVT_FLAG_FREE)
  2779. kfree(e);
  2780. /* For each work completed decrement vha ref count */
  2781. QLA_VHA_MARK_NOT_BUSY(vha);
  2782. }
  2783. }
  2784. /* Relogins all the fcports of a vport
  2785. * Context: dpc thread
  2786. */
  2787. void qla2x00_relogin(struct scsi_qla_host *vha)
  2788. {
  2789. fc_port_t *fcport;
  2790. int status;
  2791. uint16_t next_loopid = 0;
  2792. struct qla_hw_data *ha = vha->hw;
  2793. uint16_t data[2];
  2794. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2795. /*
  2796. * If the port is not ONLINE then try to login
  2797. * to it if we haven't run out of retries.
  2798. */
  2799. if (atomic_read(&fcport->state) != FCS_ONLINE &&
  2800. fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
  2801. fcport->login_retry--;
  2802. if (fcport->flags & FCF_FABRIC_DEVICE) {
  2803. if (fcport->flags & FCF_FCP2_DEVICE)
  2804. ha->isp_ops->fabric_logout(vha,
  2805. fcport->loop_id,
  2806. fcport->d_id.b.domain,
  2807. fcport->d_id.b.area,
  2808. fcport->d_id.b.al_pa);
  2809. if (fcport->loop_id == FC_NO_LOOP_ID) {
  2810. fcport->loop_id = next_loopid =
  2811. ha->min_external_loopid;
  2812. status = qla2x00_find_new_loop_id(
  2813. vha, fcport);
  2814. if (status != QLA_SUCCESS) {
  2815. /* Ran out of IDs to use */
  2816. break;
  2817. }
  2818. }
  2819. if (IS_ALOGIO_CAPABLE(ha)) {
  2820. fcport->flags |= FCF_ASYNC_SENT;
  2821. data[0] = 0;
  2822. data[1] = QLA_LOGIO_LOGIN_RETRIED;
  2823. status = qla2x00_post_async_login_work(
  2824. vha, fcport, data);
  2825. if (status == QLA_SUCCESS)
  2826. continue;
  2827. /* Attempt a retry. */
  2828. status = 1;
  2829. } else
  2830. status = qla2x00_fabric_login(vha,
  2831. fcport, &next_loopid);
  2832. } else
  2833. status = qla2x00_local_device_login(vha,
  2834. fcport);
  2835. if (status == QLA_SUCCESS) {
  2836. fcport->old_loop_id = fcport->loop_id;
  2837. DEBUG(printk("scsi(%ld): port login OK: logged "
  2838. "in ID 0x%x\n", vha->host_no, fcport->loop_id));
  2839. qla2x00_update_fcport(vha, fcport);
  2840. } else if (status == 1) {
  2841. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  2842. /* retry the login again */
  2843. DEBUG(printk("scsi(%ld): Retrying"
  2844. " %d login again loop_id 0x%x\n",
  2845. vha->host_no, fcport->login_retry,
  2846. fcport->loop_id));
  2847. } else {
  2848. fcport->login_retry = 0;
  2849. }
  2850. if (fcport->login_retry == 0 && status != QLA_SUCCESS)
  2851. fcport->loop_id = FC_NO_LOOP_ID;
  2852. }
  2853. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2854. break;
  2855. }
  2856. }
  2857. /**************************************************************************
  2858. * qla2x00_do_dpc
  2859. * This kernel thread is a task that is schedule by the interrupt handler
  2860. * to perform the background processing for interrupts.
  2861. *
  2862. * Notes:
  2863. * This task always run in the context of a kernel thread. It
  2864. * is kick-off by the driver's detect code and starts up
  2865. * up one per adapter. It immediately goes to sleep and waits for
  2866. * some fibre event. When either the interrupt handler or
  2867. * the timer routine detects a event it will one of the task
  2868. * bits then wake us up.
  2869. **************************************************************************/
  2870. static int
  2871. qla2x00_do_dpc(void *data)
  2872. {
  2873. int rval;
  2874. scsi_qla_host_t *base_vha;
  2875. struct qla_hw_data *ha;
  2876. ha = (struct qla_hw_data *)data;
  2877. base_vha = pci_get_drvdata(ha->pdev);
  2878. set_user_nice(current, -20);
  2879. set_current_state(TASK_INTERRUPTIBLE);
  2880. while (!kthread_should_stop()) {
  2881. DEBUG3(printk("qla2x00: DPC handler sleeping\n"));
  2882. schedule();
  2883. __set_current_state(TASK_RUNNING);
  2884. DEBUG3(printk("qla2x00: DPC handler waking up\n"));
  2885. /* Initialization not yet finished. Don't do anything yet. */
  2886. if (!base_vha->flags.init_done)
  2887. continue;
  2888. if (ha->flags.eeh_busy) {
  2889. DEBUG17(qla_printk(KERN_WARNING, ha,
  2890. "qla2x00_do_dpc: dpc_flags: %lx\n",
  2891. base_vha->dpc_flags));
  2892. continue;
  2893. }
  2894. DEBUG3(printk("scsi(%ld): DPC handler\n", base_vha->host_no));
  2895. ha->dpc_active = 1;
  2896. if (ha->flags.mbox_busy) {
  2897. ha->dpc_active = 0;
  2898. continue;
  2899. }
  2900. qla2x00_do_work(base_vha);
  2901. if (IS_QLA82XX(ha)) {
  2902. if (test_and_clear_bit(ISP_UNRECOVERABLE,
  2903. &base_vha->dpc_flags)) {
  2904. qla82xx_idc_lock(ha);
  2905. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  2906. QLA82XX_DEV_FAILED);
  2907. qla82xx_idc_unlock(ha);
  2908. qla_printk(KERN_INFO, ha,
  2909. "HW State: FAILED\n");
  2910. qla82xx_device_state_handler(base_vha);
  2911. continue;
  2912. }
  2913. if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
  2914. &base_vha->dpc_flags)) {
  2915. DEBUG(printk(KERN_INFO
  2916. "scsi(%ld): dpc: sched "
  2917. "qla82xx_fcoe_ctx_reset ha = %p\n",
  2918. base_vha->host_no, ha));
  2919. if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
  2920. &base_vha->dpc_flags))) {
  2921. if (qla82xx_fcoe_ctx_reset(base_vha)) {
  2922. /* FCoE-ctx reset failed.
  2923. * Escalate to chip-reset
  2924. */
  2925. set_bit(ISP_ABORT_NEEDED,
  2926. &base_vha->dpc_flags);
  2927. }
  2928. clear_bit(ABORT_ISP_ACTIVE,
  2929. &base_vha->dpc_flags);
  2930. }
  2931. DEBUG(printk("scsi(%ld): dpc:"
  2932. " qla82xx_fcoe_ctx_reset end\n",
  2933. base_vha->host_no));
  2934. }
  2935. }
  2936. if (test_and_clear_bit(ISP_ABORT_NEEDED,
  2937. &base_vha->dpc_flags)) {
  2938. DEBUG(printk("scsi(%ld): dpc: sched "
  2939. "qla2x00_abort_isp ha = %p\n",
  2940. base_vha->host_no, ha));
  2941. if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
  2942. &base_vha->dpc_flags))) {
  2943. if (ha->isp_ops->abort_isp(base_vha)) {
  2944. /* failed. retry later */
  2945. set_bit(ISP_ABORT_NEEDED,
  2946. &base_vha->dpc_flags);
  2947. }
  2948. clear_bit(ABORT_ISP_ACTIVE,
  2949. &base_vha->dpc_flags);
  2950. }
  2951. DEBUG(printk("scsi(%ld): dpc: qla2x00_abort_isp end\n",
  2952. base_vha->host_no));
  2953. }
  2954. if (test_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags)) {
  2955. qla2x00_update_fcports(base_vha);
  2956. clear_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
  2957. }
  2958. if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
  2959. DEBUG(printk(KERN_INFO "scsi(%ld): dpc: sched "
  2960. "qla2x00_quiesce_needed ha = %p\n",
  2961. base_vha->host_no, ha));
  2962. qla82xx_device_state_handler(base_vha);
  2963. clear_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags);
  2964. if (!ha->flags.quiesce_owner) {
  2965. qla2x00_perform_loop_resync(base_vha);
  2966. qla82xx_idc_lock(ha);
  2967. qla82xx_clear_qsnt_ready(base_vha);
  2968. qla82xx_idc_unlock(ha);
  2969. }
  2970. }
  2971. if (test_and_clear_bit(RESET_MARKER_NEEDED,
  2972. &base_vha->dpc_flags) &&
  2973. (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
  2974. DEBUG(printk("scsi(%ld): qla2x00_reset_marker()\n",
  2975. base_vha->host_no));
  2976. qla2x00_rst_aen(base_vha);
  2977. clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
  2978. }
  2979. /* Retry each device up to login retry count */
  2980. if ((test_and_clear_bit(RELOGIN_NEEDED,
  2981. &base_vha->dpc_flags)) &&
  2982. !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
  2983. atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
  2984. DEBUG(printk("scsi(%ld): qla2x00_port_login()\n",
  2985. base_vha->host_no));
  2986. qla2x00_relogin(base_vha);
  2987. DEBUG(printk("scsi(%ld): qla2x00_port_login - end\n",
  2988. base_vha->host_no));
  2989. }
  2990. if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
  2991. &base_vha->dpc_flags)) {
  2992. DEBUG(printk("scsi(%ld): qla2x00_loop_resync()\n",
  2993. base_vha->host_no));
  2994. if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
  2995. &base_vha->dpc_flags))) {
  2996. rval = qla2x00_loop_resync(base_vha);
  2997. clear_bit(LOOP_RESYNC_ACTIVE,
  2998. &base_vha->dpc_flags);
  2999. }
  3000. DEBUG(printk("scsi(%ld): qla2x00_loop_resync - end\n",
  3001. base_vha->host_no));
  3002. }
  3003. if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
  3004. atomic_read(&base_vha->loop_state) == LOOP_READY) {
  3005. clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
  3006. qla2xxx_flash_npiv_conf(base_vha);
  3007. }
  3008. if (!ha->interrupts_on)
  3009. ha->isp_ops->enable_intrs(ha);
  3010. if (test_and_clear_bit(BEACON_BLINK_NEEDED,
  3011. &base_vha->dpc_flags))
  3012. ha->isp_ops->beacon_blink(base_vha);
  3013. qla2x00_do_dpc_all_vps(base_vha);
  3014. ha->dpc_active = 0;
  3015. set_current_state(TASK_INTERRUPTIBLE);
  3016. } /* End of while(1) */
  3017. __set_current_state(TASK_RUNNING);
  3018. DEBUG(printk("scsi(%ld): DPC handler exiting\n", base_vha->host_no));
  3019. /*
  3020. * Make sure that nobody tries to wake us up again.
  3021. */
  3022. ha->dpc_active = 0;
  3023. /* Cleanup any residual CTX SRBs. */
  3024. qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
  3025. return 0;
  3026. }
  3027. void
  3028. qla2xxx_wake_dpc(struct scsi_qla_host *vha)
  3029. {
  3030. struct qla_hw_data *ha = vha->hw;
  3031. struct task_struct *t = ha->dpc_thread;
  3032. if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
  3033. wake_up_process(t);
  3034. }
  3035. /*
  3036. * qla2x00_rst_aen
  3037. * Processes asynchronous reset.
  3038. *
  3039. * Input:
  3040. * ha = adapter block pointer.
  3041. */
  3042. static void
  3043. qla2x00_rst_aen(scsi_qla_host_t *vha)
  3044. {
  3045. if (vha->flags.online && !vha->flags.reset_active &&
  3046. !atomic_read(&vha->loop_down_timer) &&
  3047. !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
  3048. do {
  3049. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  3050. /*
  3051. * Issue marker command only when we are going to start
  3052. * the I/O.
  3053. */
  3054. vha->marker_needed = 1;
  3055. } while (!atomic_read(&vha->loop_down_timer) &&
  3056. (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
  3057. }
  3058. }
  3059. static void
  3060. qla2x00_sp_free_dma(srb_t *sp)
  3061. {
  3062. struct scsi_cmnd *cmd = sp->cmd;
  3063. struct qla_hw_data *ha = sp->fcport->vha->hw;
  3064. if (sp->flags & SRB_DMA_VALID) {
  3065. scsi_dma_unmap(cmd);
  3066. sp->flags &= ~SRB_DMA_VALID;
  3067. }
  3068. if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
  3069. dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
  3070. scsi_prot_sg_count(cmd), cmd->sc_data_direction);
  3071. sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
  3072. }
  3073. if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
  3074. /* List assured to be having elements */
  3075. qla2x00_clean_dsd_pool(ha, sp);
  3076. sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
  3077. }
  3078. if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
  3079. dma_pool_free(ha->dl_dma_pool, sp->ctx,
  3080. ((struct crc_context *)sp->ctx)->crc_ctx_dma);
  3081. sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
  3082. }
  3083. CMD_SP(cmd) = NULL;
  3084. }
  3085. static void
  3086. qla2x00_sp_final_compl(struct qla_hw_data *ha, srb_t *sp)
  3087. {
  3088. struct scsi_cmnd *cmd = sp->cmd;
  3089. qla2x00_sp_free_dma(sp);
  3090. if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
  3091. struct ct6_dsd *ctx = sp->ctx;
  3092. dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd,
  3093. ctx->fcp_cmnd_dma);
  3094. list_splice(&ctx->dsd_list, &ha->gbl_dsd_list);
  3095. ha->gbl_dsd_inuse -= ctx->dsd_use_cnt;
  3096. ha->gbl_dsd_avail += ctx->dsd_use_cnt;
  3097. mempool_free(sp->ctx, ha->ctx_mempool);
  3098. sp->ctx = NULL;
  3099. }
  3100. mempool_free(sp, ha->srb_mempool);
  3101. cmd->scsi_done(cmd);
  3102. }
  3103. void
  3104. qla2x00_sp_compl(struct qla_hw_data *ha, srb_t *sp)
  3105. {
  3106. if (atomic_read(&sp->ref_count) == 0) {
  3107. DEBUG2(qla_printk(KERN_WARNING, ha,
  3108. "SP reference-count to ZERO -- sp=%p\n", sp));
  3109. DEBUG2(BUG());
  3110. return;
  3111. }
  3112. if (!atomic_dec_and_test(&sp->ref_count))
  3113. return;
  3114. qla2x00_sp_final_compl(ha, sp);
  3115. }
  3116. /**************************************************************************
  3117. * qla2x00_timer
  3118. *
  3119. * Description:
  3120. * One second timer
  3121. *
  3122. * Context: Interrupt
  3123. ***************************************************************************/
  3124. void
  3125. qla2x00_timer(scsi_qla_host_t *vha)
  3126. {
  3127. unsigned long cpu_flags = 0;
  3128. int start_dpc = 0;
  3129. int index;
  3130. srb_t *sp;
  3131. uint16_t w;
  3132. struct qla_hw_data *ha = vha->hw;
  3133. struct req_que *req;
  3134. if (ha->flags.eeh_busy) {
  3135. qla2x00_restart_timer(vha, WATCH_INTERVAL);
  3136. return;
  3137. }
  3138. /* Hardware read to raise pending EEH errors during mailbox waits. */
  3139. if (!pci_channel_offline(ha->pdev))
  3140. pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
  3141. /* Make sure qla82xx_watchdog is run only for physical port */
  3142. if (!vha->vp_idx && IS_QLA82XX(ha)) {
  3143. if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
  3144. start_dpc++;
  3145. qla82xx_watchdog(vha);
  3146. }
  3147. /* Loop down handler. */
  3148. if (atomic_read(&vha->loop_down_timer) > 0 &&
  3149. !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
  3150. !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
  3151. && vha->flags.online) {
  3152. if (atomic_read(&vha->loop_down_timer) ==
  3153. vha->loop_down_abort_time) {
  3154. DEBUG(printk("scsi(%ld): Loop Down - aborting the "
  3155. "queues before time expire\n",
  3156. vha->host_no));
  3157. if (!IS_QLA2100(ha) && vha->link_down_timeout)
  3158. atomic_set(&vha->loop_state, LOOP_DEAD);
  3159. /*
  3160. * Schedule an ISP abort to return any FCP2-device
  3161. * commands.
  3162. */
  3163. /* NPIV - scan physical port only */
  3164. if (!vha->vp_idx) {
  3165. spin_lock_irqsave(&ha->hardware_lock,
  3166. cpu_flags);
  3167. req = ha->req_q_map[0];
  3168. for (index = 1;
  3169. index < MAX_OUTSTANDING_COMMANDS;
  3170. index++) {
  3171. fc_port_t *sfcp;
  3172. sp = req->outstanding_cmds[index];
  3173. if (!sp)
  3174. continue;
  3175. if (sp->ctx && !IS_PROT_IO(sp))
  3176. continue;
  3177. sfcp = sp->fcport;
  3178. if (!(sfcp->flags & FCF_FCP2_DEVICE))
  3179. continue;
  3180. if (IS_QLA82XX(ha))
  3181. set_bit(FCOE_CTX_RESET_NEEDED,
  3182. &vha->dpc_flags);
  3183. else
  3184. set_bit(ISP_ABORT_NEEDED,
  3185. &vha->dpc_flags);
  3186. break;
  3187. }
  3188. spin_unlock_irqrestore(&ha->hardware_lock,
  3189. cpu_flags);
  3190. }
  3191. start_dpc++;
  3192. }
  3193. /* if the loop has been down for 4 minutes, reinit adapter */
  3194. if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
  3195. if (!(vha->device_flags & DFLG_NO_CABLE)) {
  3196. DEBUG(printk("scsi(%ld): Loop down - "
  3197. "aborting ISP.\n",
  3198. vha->host_no));
  3199. qla_printk(KERN_WARNING, ha,
  3200. "Loop down - aborting ISP.\n");
  3201. if (IS_QLA82XX(ha))
  3202. set_bit(FCOE_CTX_RESET_NEEDED,
  3203. &vha->dpc_flags);
  3204. else
  3205. set_bit(ISP_ABORT_NEEDED,
  3206. &vha->dpc_flags);
  3207. }
  3208. }
  3209. DEBUG3(printk("scsi(%ld): Loop Down - seconds remaining %d\n",
  3210. vha->host_no,
  3211. atomic_read(&vha->loop_down_timer)));
  3212. }
  3213. /* Check if beacon LED needs to be blinked for physical host only */
  3214. if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
  3215. set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
  3216. start_dpc++;
  3217. }
  3218. /* Process any deferred work. */
  3219. if (!list_empty(&vha->work_list))
  3220. start_dpc++;
  3221. /* Schedule the DPC routine if needed */
  3222. if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
  3223. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
  3224. test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
  3225. start_dpc ||
  3226. test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
  3227. test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
  3228. test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
  3229. test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
  3230. test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
  3231. test_bit(RELOGIN_NEEDED, &vha->dpc_flags)))
  3232. qla2xxx_wake_dpc(vha);
  3233. qla2x00_restart_timer(vha, WATCH_INTERVAL);
  3234. }
  3235. /* Firmware interface routines. */
  3236. #define FW_BLOBS 8
  3237. #define FW_ISP21XX 0
  3238. #define FW_ISP22XX 1
  3239. #define FW_ISP2300 2
  3240. #define FW_ISP2322 3
  3241. #define FW_ISP24XX 4
  3242. #define FW_ISP25XX 5
  3243. #define FW_ISP81XX 6
  3244. #define FW_ISP82XX 7
  3245. #define FW_FILE_ISP21XX "ql2100_fw.bin"
  3246. #define FW_FILE_ISP22XX "ql2200_fw.bin"
  3247. #define FW_FILE_ISP2300 "ql2300_fw.bin"
  3248. #define FW_FILE_ISP2322 "ql2322_fw.bin"
  3249. #define FW_FILE_ISP24XX "ql2400_fw.bin"
  3250. #define FW_FILE_ISP25XX "ql2500_fw.bin"
  3251. #define FW_FILE_ISP81XX "ql8100_fw.bin"
  3252. #define FW_FILE_ISP82XX "ql8200_fw.bin"
  3253. static DEFINE_MUTEX(qla_fw_lock);
  3254. static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
  3255. { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
  3256. { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
  3257. { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
  3258. { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
  3259. { .name = FW_FILE_ISP24XX, },
  3260. { .name = FW_FILE_ISP25XX, },
  3261. { .name = FW_FILE_ISP81XX, },
  3262. { .name = FW_FILE_ISP82XX, },
  3263. };
  3264. struct fw_blob *
  3265. qla2x00_request_firmware(scsi_qla_host_t *vha)
  3266. {
  3267. struct qla_hw_data *ha = vha->hw;
  3268. struct fw_blob *blob;
  3269. blob = NULL;
  3270. if (IS_QLA2100(ha)) {
  3271. blob = &qla_fw_blobs[FW_ISP21XX];
  3272. } else if (IS_QLA2200(ha)) {
  3273. blob = &qla_fw_blobs[FW_ISP22XX];
  3274. } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  3275. blob = &qla_fw_blobs[FW_ISP2300];
  3276. } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
  3277. blob = &qla_fw_blobs[FW_ISP2322];
  3278. } else if (IS_QLA24XX_TYPE(ha)) {
  3279. blob = &qla_fw_blobs[FW_ISP24XX];
  3280. } else if (IS_QLA25XX(ha)) {
  3281. blob = &qla_fw_blobs[FW_ISP25XX];
  3282. } else if (IS_QLA81XX(ha)) {
  3283. blob = &qla_fw_blobs[FW_ISP81XX];
  3284. } else if (IS_QLA82XX(ha)) {
  3285. blob = &qla_fw_blobs[FW_ISP82XX];
  3286. }
  3287. mutex_lock(&qla_fw_lock);
  3288. if (blob->fw)
  3289. goto out;
  3290. if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
  3291. DEBUG2(printk("scsi(%ld): Failed to load firmware image "
  3292. "(%s).\n", vha->host_no, blob->name));
  3293. blob->fw = NULL;
  3294. blob = NULL;
  3295. goto out;
  3296. }
  3297. out:
  3298. mutex_unlock(&qla_fw_lock);
  3299. return blob;
  3300. }
  3301. static void
  3302. qla2x00_release_firmware(void)
  3303. {
  3304. int idx;
  3305. mutex_lock(&qla_fw_lock);
  3306. for (idx = 0; idx < FW_BLOBS; idx++)
  3307. if (qla_fw_blobs[idx].fw)
  3308. release_firmware(qla_fw_blobs[idx].fw);
  3309. mutex_unlock(&qla_fw_lock);
  3310. }
  3311. static pci_ers_result_t
  3312. qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
  3313. {
  3314. scsi_qla_host_t *vha = pci_get_drvdata(pdev);
  3315. struct qla_hw_data *ha = vha->hw;
  3316. DEBUG2(qla_printk(KERN_WARNING, ha, "error_detected:state %x\n",
  3317. state));
  3318. switch (state) {
  3319. case pci_channel_io_normal:
  3320. ha->flags.eeh_busy = 0;
  3321. return PCI_ERS_RESULT_CAN_RECOVER;
  3322. case pci_channel_io_frozen:
  3323. ha->flags.eeh_busy = 1;
  3324. /* For ISP82XX complete any pending mailbox cmd */
  3325. if (IS_QLA82XX(ha)) {
  3326. ha->flags.isp82xx_fw_hung = 1;
  3327. if (ha->flags.mbox_busy) {
  3328. ha->flags.mbox_int = 1;
  3329. DEBUG2(qla_printk(KERN_ERR, ha,
  3330. "Due to pci channel io frozen, doing premature "
  3331. "completion of mbx command\n"));
  3332. complete(&ha->mbx_intr_comp);
  3333. }
  3334. }
  3335. qla2x00_free_irqs(vha);
  3336. pci_disable_device(pdev);
  3337. /* Return back all IOs */
  3338. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  3339. return PCI_ERS_RESULT_NEED_RESET;
  3340. case pci_channel_io_perm_failure:
  3341. ha->flags.pci_channel_io_perm_failure = 1;
  3342. qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
  3343. return PCI_ERS_RESULT_DISCONNECT;
  3344. }
  3345. return PCI_ERS_RESULT_NEED_RESET;
  3346. }
  3347. static pci_ers_result_t
  3348. qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
  3349. {
  3350. int risc_paused = 0;
  3351. uint32_t stat;
  3352. unsigned long flags;
  3353. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  3354. struct qla_hw_data *ha = base_vha->hw;
  3355. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  3356. struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
  3357. if (IS_QLA82XX(ha))
  3358. return PCI_ERS_RESULT_RECOVERED;
  3359. spin_lock_irqsave(&ha->hardware_lock, flags);
  3360. if (IS_QLA2100(ha) || IS_QLA2200(ha)){
  3361. stat = RD_REG_DWORD(&reg->hccr);
  3362. if (stat & HCCR_RISC_PAUSE)
  3363. risc_paused = 1;
  3364. } else if (IS_QLA23XX(ha)) {
  3365. stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
  3366. if (stat & HSR_RISC_PAUSED)
  3367. risc_paused = 1;
  3368. } else if (IS_FWI2_CAPABLE(ha)) {
  3369. stat = RD_REG_DWORD(&reg24->host_status);
  3370. if (stat & HSRX_RISC_PAUSED)
  3371. risc_paused = 1;
  3372. }
  3373. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3374. if (risc_paused) {
  3375. qla_printk(KERN_INFO, ha, "RISC paused -- mmio_enabled, "
  3376. "Dumping firmware!\n");
  3377. ha->isp_ops->fw_dump(base_vha, 0);
  3378. return PCI_ERS_RESULT_NEED_RESET;
  3379. } else
  3380. return PCI_ERS_RESULT_RECOVERED;
  3381. }
  3382. uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha)
  3383. {
  3384. uint32_t rval = QLA_FUNCTION_FAILED;
  3385. uint32_t drv_active = 0;
  3386. struct qla_hw_data *ha = base_vha->hw;
  3387. int fn;
  3388. struct pci_dev *other_pdev = NULL;
  3389. DEBUG17(qla_printk(KERN_INFO, ha,
  3390. "scsi(%ld): In qla82xx_error_recovery\n", base_vha->host_no));
  3391. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3392. if (base_vha->flags.online) {
  3393. /* Abort all outstanding commands,
  3394. * so as to be requeued later */
  3395. qla2x00_abort_isp_cleanup(base_vha);
  3396. }
  3397. fn = PCI_FUNC(ha->pdev->devfn);
  3398. while (fn > 0) {
  3399. fn--;
  3400. DEBUG17(qla_printk(KERN_INFO, ha,
  3401. "Finding pci device at function = 0x%x\n", fn));
  3402. other_pdev =
  3403. pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
  3404. ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
  3405. fn));
  3406. if (!other_pdev)
  3407. continue;
  3408. if (atomic_read(&other_pdev->enable_cnt)) {
  3409. DEBUG17(qla_printk(KERN_INFO, ha,
  3410. "Found PCI func available and enabled at 0x%x\n",
  3411. fn));
  3412. pci_dev_put(other_pdev);
  3413. break;
  3414. }
  3415. pci_dev_put(other_pdev);
  3416. }
  3417. if (!fn) {
  3418. /* Reset owner */
  3419. DEBUG17(qla_printk(KERN_INFO, ha,
  3420. "This devfn is reset owner = 0x%x\n", ha->pdev->devfn));
  3421. qla82xx_idc_lock(ha);
  3422. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  3423. QLA82XX_DEV_INITIALIZING);
  3424. qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
  3425. QLA82XX_IDC_VERSION);
  3426. drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
  3427. DEBUG17(qla_printk(KERN_INFO, ha,
  3428. "drv_active = 0x%x\n", drv_active));
  3429. qla82xx_idc_unlock(ha);
  3430. /* Reset if device is not already reset
  3431. * drv_active would be 0 if a reset has already been done
  3432. */
  3433. if (drv_active)
  3434. rval = qla82xx_start_firmware(base_vha);
  3435. else
  3436. rval = QLA_SUCCESS;
  3437. qla82xx_idc_lock(ha);
  3438. if (rval != QLA_SUCCESS) {
  3439. qla_printk(KERN_INFO, ha, "HW State: FAILED\n");
  3440. qla82xx_clear_drv_active(ha);
  3441. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  3442. QLA82XX_DEV_FAILED);
  3443. } else {
  3444. qla_printk(KERN_INFO, ha, "HW State: READY\n");
  3445. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  3446. QLA82XX_DEV_READY);
  3447. qla82xx_idc_unlock(ha);
  3448. ha->flags.isp82xx_fw_hung = 0;
  3449. rval = qla82xx_restart_isp(base_vha);
  3450. qla82xx_idc_lock(ha);
  3451. /* Clear driver state register */
  3452. qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
  3453. qla82xx_set_drv_active(base_vha);
  3454. }
  3455. qla82xx_idc_unlock(ha);
  3456. } else {
  3457. DEBUG17(qla_printk(KERN_INFO, ha,
  3458. "This devfn is not reset owner = 0x%x\n", ha->pdev->devfn));
  3459. if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
  3460. QLA82XX_DEV_READY)) {
  3461. ha->flags.isp82xx_fw_hung = 0;
  3462. rval = qla82xx_restart_isp(base_vha);
  3463. qla82xx_idc_lock(ha);
  3464. qla82xx_set_drv_active(base_vha);
  3465. qla82xx_idc_unlock(ha);
  3466. }
  3467. }
  3468. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3469. return rval;
  3470. }
  3471. static pci_ers_result_t
  3472. qla2xxx_pci_slot_reset(struct pci_dev *pdev)
  3473. {
  3474. pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
  3475. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  3476. struct qla_hw_data *ha = base_vha->hw;
  3477. struct rsp_que *rsp;
  3478. int rc, retries = 10;
  3479. DEBUG17(qla_printk(KERN_WARNING, ha, "slot_reset\n"));
  3480. /* Workaround: qla2xxx driver which access hardware earlier
  3481. * needs error state to be pci_channel_io_online.
  3482. * Otherwise mailbox command timesout.
  3483. */
  3484. pdev->error_state = pci_channel_io_normal;
  3485. pci_restore_state(pdev);
  3486. /* pci_restore_state() clears the saved_state flag of the device
  3487. * save restored state which resets saved_state flag
  3488. */
  3489. pci_save_state(pdev);
  3490. if (ha->mem_only)
  3491. rc = pci_enable_device_mem(pdev);
  3492. else
  3493. rc = pci_enable_device(pdev);
  3494. if (rc) {
  3495. qla_printk(KERN_WARNING, ha,
  3496. "Can't re-enable PCI device after reset.\n");
  3497. goto exit_slot_reset;
  3498. }
  3499. rsp = ha->rsp_q_map[0];
  3500. if (qla2x00_request_irqs(ha, rsp))
  3501. goto exit_slot_reset;
  3502. if (ha->isp_ops->pci_config(base_vha))
  3503. goto exit_slot_reset;
  3504. if (IS_QLA82XX(ha)) {
  3505. if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
  3506. ret = PCI_ERS_RESULT_RECOVERED;
  3507. goto exit_slot_reset;
  3508. } else
  3509. goto exit_slot_reset;
  3510. }
  3511. while (ha->flags.mbox_busy && retries--)
  3512. msleep(1000);
  3513. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3514. if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
  3515. ret = PCI_ERS_RESULT_RECOVERED;
  3516. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3517. exit_slot_reset:
  3518. DEBUG17(qla_printk(KERN_WARNING, ha,
  3519. "slot_reset-return:ret=%x\n", ret));
  3520. return ret;
  3521. }
  3522. static void
  3523. qla2xxx_pci_resume(struct pci_dev *pdev)
  3524. {
  3525. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  3526. struct qla_hw_data *ha = base_vha->hw;
  3527. int ret;
  3528. DEBUG17(qla_printk(KERN_WARNING, ha, "pci_resume\n"));
  3529. ret = qla2x00_wait_for_hba_online(base_vha);
  3530. if (ret != QLA_SUCCESS) {
  3531. qla_printk(KERN_ERR, ha,
  3532. "the device failed to resume I/O "
  3533. "from slot/link_reset");
  3534. }
  3535. pci_cleanup_aer_uncorrect_error_status(pdev);
  3536. ha->flags.eeh_busy = 0;
  3537. }
  3538. static struct pci_error_handlers qla2xxx_err_handler = {
  3539. .error_detected = qla2xxx_pci_error_detected,
  3540. .mmio_enabled = qla2xxx_pci_mmio_enabled,
  3541. .slot_reset = qla2xxx_pci_slot_reset,
  3542. .resume = qla2xxx_pci_resume,
  3543. };
  3544. static struct pci_device_id qla2xxx_pci_tbl[] = {
  3545. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
  3546. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
  3547. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
  3548. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
  3549. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
  3550. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
  3551. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
  3552. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
  3553. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
  3554. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
  3555. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
  3556. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
  3557. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
  3558. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
  3559. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
  3560. { 0 },
  3561. };
  3562. MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
  3563. static struct pci_driver qla2xxx_pci_driver = {
  3564. .name = QLA2XXX_DRIVER_NAME,
  3565. .driver = {
  3566. .owner = THIS_MODULE,
  3567. },
  3568. .id_table = qla2xxx_pci_tbl,
  3569. .probe = qla2x00_probe_one,
  3570. .remove = qla2x00_remove_one,
  3571. .shutdown = qla2x00_shutdown,
  3572. .err_handler = &qla2xxx_err_handler,
  3573. };
  3574. static struct file_operations apidev_fops = {
  3575. .owner = THIS_MODULE,
  3576. .llseek = noop_llseek,
  3577. };
  3578. /**
  3579. * qla2x00_module_init - Module initialization.
  3580. **/
  3581. static int __init
  3582. qla2x00_module_init(void)
  3583. {
  3584. int ret = 0;
  3585. /* Allocate cache for SRBs. */
  3586. srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
  3587. SLAB_HWCACHE_ALIGN, NULL);
  3588. if (srb_cachep == NULL) {
  3589. printk(KERN_ERR
  3590. "qla2xxx: Unable to allocate SRB cache...Failing load!\n");
  3591. return -ENOMEM;
  3592. }
  3593. /* Derive version string. */
  3594. strcpy(qla2x00_version_str, QLA2XXX_VERSION);
  3595. if (ql2xextended_error_logging)
  3596. strcat(qla2x00_version_str, "-debug");
  3597. qla2xxx_transport_template =
  3598. fc_attach_transport(&qla2xxx_transport_functions);
  3599. if (!qla2xxx_transport_template) {
  3600. kmem_cache_destroy(srb_cachep);
  3601. return -ENODEV;
  3602. }
  3603. apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
  3604. if (apidev_major < 0) {
  3605. printk(KERN_WARNING "qla2xxx: Unable to register char device "
  3606. "%s\n", QLA2XXX_APIDEV);
  3607. }
  3608. qla2xxx_transport_vport_template =
  3609. fc_attach_transport(&qla2xxx_transport_vport_functions);
  3610. if (!qla2xxx_transport_vport_template) {
  3611. kmem_cache_destroy(srb_cachep);
  3612. fc_release_transport(qla2xxx_transport_template);
  3613. return -ENODEV;
  3614. }
  3615. printk(KERN_INFO "QLogic Fibre Channel HBA Driver: %s\n",
  3616. qla2x00_version_str);
  3617. ret = pci_register_driver(&qla2xxx_pci_driver);
  3618. if (ret) {
  3619. kmem_cache_destroy(srb_cachep);
  3620. fc_release_transport(qla2xxx_transport_template);
  3621. fc_release_transport(qla2xxx_transport_vport_template);
  3622. }
  3623. return ret;
  3624. }
  3625. /**
  3626. * qla2x00_module_exit - Module cleanup.
  3627. **/
  3628. static void __exit
  3629. qla2x00_module_exit(void)
  3630. {
  3631. unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
  3632. pci_unregister_driver(&qla2xxx_pci_driver);
  3633. qla2x00_release_firmware();
  3634. kmem_cache_destroy(srb_cachep);
  3635. if (ctx_cachep)
  3636. kmem_cache_destroy(ctx_cachep);
  3637. fc_release_transport(qla2xxx_transport_template);
  3638. fc_release_transport(qla2xxx_transport_vport_template);
  3639. }
  3640. module_init(qla2x00_module_init);
  3641. module_exit(qla2x00_module_exit);
  3642. MODULE_AUTHOR("QLogic Corporation");
  3643. MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
  3644. MODULE_LICENSE("GPL");
  3645. MODULE_VERSION(QLA2XXX_VERSION);
  3646. MODULE_FIRMWARE(FW_FILE_ISP21XX);
  3647. MODULE_FIRMWARE(FW_FILE_ISP22XX);
  3648. MODULE_FIRMWARE(FW_FILE_ISP2300);
  3649. MODULE_FIRMWARE(FW_FILE_ISP2322);
  3650. MODULE_FIRMWARE(FW_FILE_ISP24XX);
  3651. MODULE_FIRMWARE(FW_FILE_ISP25XX);