twl4030.c 48 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl4030.h>
  29. #include <sound/core.h>
  30. #include <sound/pcm.h>
  31. #include <sound/pcm_params.h>
  32. #include <sound/soc.h>
  33. #include <sound/soc-dapm.h>
  34. #include <sound/initval.h>
  35. #include <sound/tlv.h>
  36. #include "twl4030.h"
  37. /*
  38. * twl4030 register cache & default register settings
  39. */
  40. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  41. 0x00, /* this register not used */
  42. 0x91, /* REG_CODEC_MODE (0x1) */
  43. 0xc3, /* REG_OPTION (0x2) */
  44. 0x00, /* REG_UNKNOWN (0x3) */
  45. 0x00, /* REG_MICBIAS_CTL (0x4) */
  46. 0x20, /* REG_ANAMICL (0x5) */
  47. 0x00, /* REG_ANAMICR (0x6) */
  48. 0x00, /* REG_AVADC_CTL (0x7) */
  49. 0x00, /* REG_ADCMICSEL (0x8) */
  50. 0x00, /* REG_DIGMIXING (0x9) */
  51. 0x0c, /* REG_ATXL1PGA (0xA) */
  52. 0x0c, /* REG_ATXR1PGA (0xB) */
  53. 0x00, /* REG_AVTXL2PGA (0xC) */
  54. 0x00, /* REG_AVTXR2PGA (0xD) */
  55. 0x01, /* REG_AUDIO_IF (0xE) */
  56. 0x00, /* REG_VOICE_IF (0xF) */
  57. 0x00, /* REG_ARXR1PGA (0x10) */
  58. 0x00, /* REG_ARXL1PGA (0x11) */
  59. 0x6c, /* REG_ARXR2PGA (0x12) */
  60. 0x6c, /* REG_ARXL2PGA (0x13) */
  61. 0x00, /* REG_VRXPGA (0x14) */
  62. 0x00, /* REG_VSTPGA (0x15) */
  63. 0x00, /* REG_VRX2ARXPGA (0x16) */
  64. 0x0c, /* REG_AVDAC_CTL (0x17) */
  65. 0x00, /* REG_ARX2VTXPGA (0x18) */
  66. 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
  67. 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
  68. 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
  69. 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
  70. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  71. 0x00, /* REG_BT_IF (0x1E) */
  72. 0x00, /* REG_BTPGA (0x1F) */
  73. 0x00, /* REG_BTSTPGA (0x20) */
  74. 0x00, /* REG_EAR_CTL (0x21) */
  75. 0x24, /* REG_HS_SEL (0x22) */
  76. 0x0a, /* REG_HS_GAIN_SET (0x23) */
  77. 0x00, /* REG_HS_POPN_SET (0x24) */
  78. 0x00, /* REG_PREDL_CTL (0x25) */
  79. 0x00, /* REG_PREDR_CTL (0x26) */
  80. 0x00, /* REG_PRECKL_CTL (0x27) */
  81. 0x00, /* REG_PRECKR_CTL (0x28) */
  82. 0x00, /* REG_HFL_CTL (0x29) */
  83. 0x00, /* REG_HFR_CTL (0x2A) */
  84. 0x00, /* REG_ALC_CTL (0x2B) */
  85. 0x00, /* REG_ALC_SET1 (0x2C) */
  86. 0x00, /* REG_ALC_SET2 (0x2D) */
  87. 0x00, /* REG_BOOST_CTL (0x2E) */
  88. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  89. 0x00, /* REG_DTMF_FREQSEL (0x30) */
  90. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  91. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  92. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  93. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  94. 0x00, /* REG_DTMF_TONOFF (0x35) */
  95. 0x00, /* REG_DTMF_WANONOFF (0x36) */
  96. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  99. 0x16, /* REG_APLL_CTL (0x3A) */
  100. 0x00, /* REG_DTMF_CTL (0x3B) */
  101. 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
  102. 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
  103. 0x00, /* REG_MISC_SET_1 (0x3E) */
  104. 0x00, /* REG_PCMBTMUX (0x3F) */
  105. 0x00, /* not used (0x40) */
  106. 0x00, /* not used (0x41) */
  107. 0x00, /* not used (0x42) */
  108. 0x00, /* REG_RX_PATH_SEL (0x43) */
  109. 0x00, /* REG_VDL_APGA_CTL (0x44) */
  110. 0x00, /* REG_VIBRA_CTL (0x45) */
  111. 0x00, /* REG_VIBRA_SET (0x46) */
  112. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  113. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  114. 0x00, /* REG_MISC_SET_2 (0x49) */
  115. };
  116. /* codec private data */
  117. struct twl4030_priv {
  118. unsigned int bypass_state;
  119. unsigned int codec_powered;
  120. unsigned int codec_muted;
  121. struct snd_pcm_substream *master_substream;
  122. struct snd_pcm_substream *slave_substream;
  123. };
  124. /*
  125. * read twl4030 register cache
  126. */
  127. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  128. unsigned int reg)
  129. {
  130. u8 *cache = codec->reg_cache;
  131. if (reg >= TWL4030_CACHEREGNUM)
  132. return -EIO;
  133. return cache[reg];
  134. }
  135. /*
  136. * write twl4030 register cache
  137. */
  138. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  139. u8 reg, u8 value)
  140. {
  141. u8 *cache = codec->reg_cache;
  142. if (reg >= TWL4030_CACHEREGNUM)
  143. return;
  144. cache[reg] = value;
  145. }
  146. /*
  147. * write to the twl4030 register space
  148. */
  149. static int twl4030_write(struct snd_soc_codec *codec,
  150. unsigned int reg, unsigned int value)
  151. {
  152. twl4030_write_reg_cache(codec, reg, value);
  153. return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
  154. }
  155. static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
  156. {
  157. struct twl4030_priv *twl4030 = codec->private_data;
  158. u8 mode;
  159. if (enable == twl4030->codec_powered)
  160. return;
  161. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  162. if (enable)
  163. mode |= TWL4030_CODECPDZ;
  164. else
  165. mode &= ~TWL4030_CODECPDZ;
  166. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  167. twl4030->codec_powered = enable;
  168. /* REVISIT: this delay is present in TI sample drivers */
  169. /* but there seems to be no TRM requirement for it */
  170. udelay(10);
  171. }
  172. static void twl4030_init_chip(struct snd_soc_codec *codec)
  173. {
  174. int i;
  175. /* clear CODECPDZ prior to setting register defaults */
  176. twl4030_codec_enable(codec, 0);
  177. /* set all audio section registers to reasonable defaults */
  178. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  179. twl4030_write(codec, i, twl4030_reg[i]);
  180. }
  181. static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
  182. {
  183. struct twl4030_priv *twl4030 = codec->private_data;
  184. u8 reg_val;
  185. if (mute == twl4030->codec_muted)
  186. return;
  187. if (mute) {
  188. /* Bypass the reg_cache and mute the volumes
  189. * Headset mute is done in it's own event handler
  190. * Things to mute: Earpiece, PreDrivL/R, CarkitL/R
  191. */
  192. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL);
  193. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  194. reg_val & (~TWL4030_EAR_GAIN),
  195. TWL4030_REG_EAR_CTL);
  196. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL);
  197. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  198. reg_val & (~TWL4030_PREDL_GAIN),
  199. TWL4030_REG_PREDL_CTL);
  200. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL);
  201. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  202. reg_val & (~TWL4030_PREDR_GAIN),
  203. TWL4030_REG_PREDL_CTL);
  204. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL);
  205. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  206. reg_val & (~TWL4030_PRECKL_GAIN),
  207. TWL4030_REG_PRECKL_CTL);
  208. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
  209. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  210. reg_val & (~TWL4030_PRECKL_GAIN),
  211. TWL4030_REG_PRECKR_CTL);
  212. /* Disable PLL */
  213. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  214. reg_val &= ~TWL4030_APLL_EN;
  215. twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
  216. } else {
  217. /* Restore the volumes
  218. * Headset mute is done in it's own event handler
  219. * Things to restore: Earpiece, PreDrivL/R, CarkitL/R
  220. */
  221. twl4030_write(codec, TWL4030_REG_EAR_CTL,
  222. twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL));
  223. twl4030_write(codec, TWL4030_REG_PREDL_CTL,
  224. twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL));
  225. twl4030_write(codec, TWL4030_REG_PREDR_CTL,
  226. twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL));
  227. twl4030_write(codec, TWL4030_REG_PRECKL_CTL,
  228. twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL));
  229. twl4030_write(codec, TWL4030_REG_PRECKR_CTL,
  230. twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL));
  231. /* Enable PLL */
  232. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  233. reg_val |= TWL4030_APLL_EN;
  234. twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
  235. }
  236. twl4030->codec_muted = mute;
  237. }
  238. static void twl4030_power_up(struct snd_soc_codec *codec)
  239. {
  240. struct twl4030_priv *twl4030 = codec->private_data;
  241. u8 anamicl, regmisc1, byte;
  242. int i = 0;
  243. if (twl4030->codec_powered)
  244. return;
  245. /* set CODECPDZ to turn on codec */
  246. twl4030_codec_enable(codec, 1);
  247. /* initiate offset cancellation */
  248. anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  249. twl4030_write(codec, TWL4030_REG_ANAMICL,
  250. anamicl | TWL4030_CNCL_OFFSET_START);
  251. /* wait for offset cancellation to complete */
  252. do {
  253. /* this takes a little while, so don't slam i2c */
  254. udelay(2000);
  255. twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  256. TWL4030_REG_ANAMICL);
  257. } while ((i++ < 100) &&
  258. ((byte & TWL4030_CNCL_OFFSET_START) ==
  259. TWL4030_CNCL_OFFSET_START));
  260. /* Make sure that the reg_cache has the same value as the HW */
  261. twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
  262. /* anti-pop when changing analog gain */
  263. regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  264. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  265. regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
  266. /* toggle CODECPDZ as per TRM */
  267. twl4030_codec_enable(codec, 0);
  268. twl4030_codec_enable(codec, 1);
  269. }
  270. /*
  271. * Unconditional power down
  272. */
  273. static void twl4030_power_down(struct snd_soc_codec *codec)
  274. {
  275. /* power down */
  276. twl4030_codec_enable(codec, 0);
  277. }
  278. /* Earpiece */
  279. static const char *twl4030_earpiece_texts[] =
  280. {"Off", "DACL1", "DACL2", "DACR1"};
  281. static const unsigned int twl4030_earpiece_values[] =
  282. {0x0, 0x1, 0x2, 0x4};
  283. static const struct soc_enum twl4030_earpiece_enum =
  284. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1, 0x7,
  285. ARRAY_SIZE(twl4030_earpiece_texts),
  286. twl4030_earpiece_texts,
  287. twl4030_earpiece_values);
  288. static const struct snd_kcontrol_new twl4030_dapm_earpiece_control =
  289. SOC_DAPM_VALUE_ENUM("Route", twl4030_earpiece_enum);
  290. /* PreDrive Left */
  291. static const char *twl4030_predrivel_texts[] =
  292. {"Off", "DACL1", "DACL2", "DACR2"};
  293. static const unsigned int twl4030_predrivel_values[] =
  294. {0x0, 0x1, 0x2, 0x4};
  295. static const struct soc_enum twl4030_predrivel_enum =
  296. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1, 0x7,
  297. ARRAY_SIZE(twl4030_predrivel_texts),
  298. twl4030_predrivel_texts,
  299. twl4030_predrivel_values);
  300. static const struct snd_kcontrol_new twl4030_dapm_predrivel_control =
  301. SOC_DAPM_VALUE_ENUM("Route", twl4030_predrivel_enum);
  302. /* PreDrive Right */
  303. static const char *twl4030_predriver_texts[] =
  304. {"Off", "DACR1", "DACR2", "DACL2"};
  305. static const unsigned int twl4030_predriver_values[] =
  306. {0x0, 0x1, 0x2, 0x4};
  307. static const struct soc_enum twl4030_predriver_enum =
  308. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1, 0x7,
  309. ARRAY_SIZE(twl4030_predriver_texts),
  310. twl4030_predriver_texts,
  311. twl4030_predriver_values);
  312. static const struct snd_kcontrol_new twl4030_dapm_predriver_control =
  313. SOC_DAPM_VALUE_ENUM("Route", twl4030_predriver_enum);
  314. /* Headset Left */
  315. static const char *twl4030_hsol_texts[] =
  316. {"Off", "DACL1", "DACL2"};
  317. static const struct soc_enum twl4030_hsol_enum =
  318. SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 1,
  319. ARRAY_SIZE(twl4030_hsol_texts),
  320. twl4030_hsol_texts);
  321. static const struct snd_kcontrol_new twl4030_dapm_hsol_control =
  322. SOC_DAPM_ENUM("Route", twl4030_hsol_enum);
  323. /* Headset Right */
  324. static const char *twl4030_hsor_texts[] =
  325. {"Off", "DACR1", "DACR2"};
  326. static const struct soc_enum twl4030_hsor_enum =
  327. SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 4,
  328. ARRAY_SIZE(twl4030_hsor_texts),
  329. twl4030_hsor_texts);
  330. static const struct snd_kcontrol_new twl4030_dapm_hsor_control =
  331. SOC_DAPM_ENUM("Route", twl4030_hsor_enum);
  332. /* Carkit Left */
  333. static const char *twl4030_carkitl_texts[] =
  334. {"Off", "DACL1", "DACL2"};
  335. static const struct soc_enum twl4030_carkitl_enum =
  336. SOC_ENUM_SINGLE(TWL4030_REG_PRECKL_CTL, 1,
  337. ARRAY_SIZE(twl4030_carkitl_texts),
  338. twl4030_carkitl_texts);
  339. static const struct snd_kcontrol_new twl4030_dapm_carkitl_control =
  340. SOC_DAPM_ENUM("Route", twl4030_carkitl_enum);
  341. /* Carkit Right */
  342. static const char *twl4030_carkitr_texts[] =
  343. {"Off", "DACR1", "DACR2"};
  344. static const struct soc_enum twl4030_carkitr_enum =
  345. SOC_ENUM_SINGLE(TWL4030_REG_PRECKR_CTL, 1,
  346. ARRAY_SIZE(twl4030_carkitr_texts),
  347. twl4030_carkitr_texts);
  348. static const struct snd_kcontrol_new twl4030_dapm_carkitr_control =
  349. SOC_DAPM_ENUM("Route", twl4030_carkitr_enum);
  350. /* Handsfree Left */
  351. static const char *twl4030_handsfreel_texts[] =
  352. {"Voice", "DACL1", "DACL2", "DACR2"};
  353. static const struct soc_enum twl4030_handsfreel_enum =
  354. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  355. ARRAY_SIZE(twl4030_handsfreel_texts),
  356. twl4030_handsfreel_texts);
  357. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  358. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  359. /* Handsfree Right */
  360. static const char *twl4030_handsfreer_texts[] =
  361. {"Voice", "DACR1", "DACR2", "DACL2"};
  362. static const struct soc_enum twl4030_handsfreer_enum =
  363. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  364. ARRAY_SIZE(twl4030_handsfreer_texts),
  365. twl4030_handsfreer_texts);
  366. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  367. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  368. /* Left analog microphone selection */
  369. static const char *twl4030_analoglmic_texts[] =
  370. {"Off", "Main mic", "Headset mic", "AUXL", "Carkit mic"};
  371. static const unsigned int twl4030_analoglmic_values[] =
  372. {0x0, 0x1, 0x2, 0x4, 0x8};
  373. static const struct soc_enum twl4030_analoglmic_enum =
  374. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0, 0xf,
  375. ARRAY_SIZE(twl4030_analoglmic_texts),
  376. twl4030_analoglmic_texts,
  377. twl4030_analoglmic_values);
  378. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_control =
  379. SOC_DAPM_VALUE_ENUM("Route", twl4030_analoglmic_enum);
  380. /* Right analog microphone selection */
  381. static const char *twl4030_analogrmic_texts[] =
  382. {"Off", "Sub mic", "AUXR"};
  383. static const unsigned int twl4030_analogrmic_values[] =
  384. {0x0, 0x1, 0x4};
  385. static const struct soc_enum twl4030_analogrmic_enum =
  386. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0, 0x5,
  387. ARRAY_SIZE(twl4030_analogrmic_texts),
  388. twl4030_analogrmic_texts,
  389. twl4030_analogrmic_values);
  390. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_control =
  391. SOC_DAPM_VALUE_ENUM("Route", twl4030_analogrmic_enum);
  392. /* TX1 L/R Analog/Digital microphone selection */
  393. static const char *twl4030_micpathtx1_texts[] =
  394. {"Analog", "Digimic0"};
  395. static const struct soc_enum twl4030_micpathtx1_enum =
  396. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  397. ARRAY_SIZE(twl4030_micpathtx1_texts),
  398. twl4030_micpathtx1_texts);
  399. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  400. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  401. /* TX2 L/R Analog/Digital microphone selection */
  402. static const char *twl4030_micpathtx2_texts[] =
  403. {"Analog", "Digimic1"};
  404. static const struct soc_enum twl4030_micpathtx2_enum =
  405. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  406. ARRAY_SIZE(twl4030_micpathtx2_texts),
  407. twl4030_micpathtx2_texts);
  408. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  409. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  410. /* Analog bypass for AudioR1 */
  411. static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
  412. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
  413. /* Analog bypass for AudioL1 */
  414. static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
  415. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
  416. /* Analog bypass for AudioR2 */
  417. static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
  418. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
  419. /* Analog bypass for AudioL2 */
  420. static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
  421. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
  422. /* Digital bypass gain, 0 mutes the bypass */
  423. static const unsigned int twl4030_dapm_dbypass_tlv[] = {
  424. TLV_DB_RANGE_HEAD(2),
  425. 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
  426. 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
  427. };
  428. /* Digital bypass left (TX1L -> RX2L) */
  429. static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
  430. SOC_DAPM_SINGLE_TLV("Volume",
  431. TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
  432. twl4030_dapm_dbypass_tlv);
  433. /* Digital bypass right (TX1R -> RX2R) */
  434. static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
  435. SOC_DAPM_SINGLE_TLV("Volume",
  436. TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
  437. twl4030_dapm_dbypass_tlv);
  438. static int micpath_event(struct snd_soc_dapm_widget *w,
  439. struct snd_kcontrol *kcontrol, int event)
  440. {
  441. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  442. unsigned char adcmicsel, micbias_ctl;
  443. adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
  444. micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
  445. /* Prepare the bits for the given TX path:
  446. * shift_l == 0: TX1 microphone path
  447. * shift_l == 2: TX2 microphone path */
  448. if (e->shift_l) {
  449. /* TX2 microphone path */
  450. if (adcmicsel & TWL4030_TX2IN_SEL)
  451. micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
  452. else
  453. micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
  454. } else {
  455. /* TX1 microphone path */
  456. if (adcmicsel & TWL4030_TX1IN_SEL)
  457. micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
  458. else
  459. micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
  460. }
  461. twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
  462. return 0;
  463. }
  464. static int handsfree_event(struct snd_soc_dapm_widget *w,
  465. struct snd_kcontrol *kcontrol, int event)
  466. {
  467. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  468. unsigned char hs_ctl;
  469. hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
  470. if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
  471. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  472. twl4030_write(w->codec, e->reg, hs_ctl);
  473. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  474. twl4030_write(w->codec, e->reg, hs_ctl);
  475. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  476. twl4030_write(w->codec, e->reg, hs_ctl);
  477. } else {
  478. hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
  479. | TWL4030_HF_CTL_HB_EN);
  480. twl4030_write(w->codec, e->reg, hs_ctl);
  481. }
  482. return 0;
  483. }
  484. static int headsetl_event(struct snd_soc_dapm_widget *w,
  485. struct snd_kcontrol *kcontrol, int event)
  486. {
  487. unsigned char hs_gain, hs_pop;
  488. /* Save the current volume */
  489. hs_gain = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_GAIN_SET);
  490. hs_pop = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_POPN_SET);
  491. switch (event) {
  492. case SND_SOC_DAPM_POST_PMU:
  493. /* Do the anti-pop/bias ramp enable according to the TRM */
  494. hs_pop |= TWL4030_VMID_EN;
  495. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  496. /* Is this needed? Can we just use whatever gain here? */
  497. twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET,
  498. (hs_gain & (~0x0f)) | 0x0a);
  499. hs_pop |= TWL4030_RAMP_EN;
  500. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  501. /* Restore the original volume */
  502. twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
  503. break;
  504. case SND_SOC_DAPM_POST_PMD:
  505. /* Do the anti-pop/bias ramp disable according to the TRM */
  506. hs_pop &= ~TWL4030_RAMP_EN;
  507. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  508. /* Bypass the reg_cache to mute the headset */
  509. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  510. hs_gain & (~0x0f),
  511. TWL4030_REG_HS_GAIN_SET);
  512. hs_pop &= ~TWL4030_VMID_EN;
  513. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  514. break;
  515. }
  516. return 0;
  517. }
  518. static int bypass_event(struct snd_soc_dapm_widget *w,
  519. struct snd_kcontrol *kcontrol, int event)
  520. {
  521. struct soc_mixer_control *m =
  522. (struct soc_mixer_control *)w->kcontrols->private_value;
  523. struct twl4030_priv *twl4030 = w->codec->private_data;
  524. unsigned char reg;
  525. reg = twl4030_read_reg_cache(w->codec, m->reg);
  526. if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
  527. /* Analog bypass */
  528. if (reg & (1 << m->shift))
  529. twl4030->bypass_state |=
  530. (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
  531. else
  532. twl4030->bypass_state &=
  533. ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
  534. } else {
  535. /* Digital bypass */
  536. if (reg & (0x7 << m->shift))
  537. twl4030->bypass_state |= (1 << (m->shift ? 5 : 4));
  538. else
  539. twl4030->bypass_state &= ~(1 << (m->shift ? 5 : 4));
  540. }
  541. if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
  542. if (twl4030->bypass_state)
  543. twl4030_codec_mute(w->codec, 0);
  544. else
  545. twl4030_codec_mute(w->codec, 1);
  546. }
  547. return 0;
  548. }
  549. /*
  550. * Some of the gain controls in TWL (mostly those which are associated with
  551. * the outputs) are implemented in an interesting way:
  552. * 0x0 : Power down (mute)
  553. * 0x1 : 6dB
  554. * 0x2 : 0 dB
  555. * 0x3 : -6 dB
  556. * Inverting not going to help with these.
  557. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  558. */
  559. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  560. xinvert, tlv_array) \
  561. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  562. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  563. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  564. .tlv.p = (tlv_array), \
  565. .info = snd_soc_info_volsw, \
  566. .get = snd_soc_get_volsw_twl4030, \
  567. .put = snd_soc_put_volsw_twl4030, \
  568. .private_value = (unsigned long)&(struct soc_mixer_control) \
  569. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  570. .max = xmax, .invert = xinvert} }
  571. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  572. xinvert, tlv_array) \
  573. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  574. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  575. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  576. .tlv.p = (tlv_array), \
  577. .info = snd_soc_info_volsw_2r, \
  578. .get = snd_soc_get_volsw_r2_twl4030,\
  579. .put = snd_soc_put_volsw_r2_twl4030, \
  580. .private_value = (unsigned long)&(struct soc_mixer_control) \
  581. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  582. .rshift = xshift, .max = xmax, .invert = xinvert} }
  583. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  584. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  585. xinvert, tlv_array)
  586. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  587. struct snd_ctl_elem_value *ucontrol)
  588. {
  589. struct soc_mixer_control *mc =
  590. (struct soc_mixer_control *)kcontrol->private_value;
  591. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  592. unsigned int reg = mc->reg;
  593. unsigned int shift = mc->shift;
  594. unsigned int rshift = mc->rshift;
  595. int max = mc->max;
  596. int mask = (1 << fls(max)) - 1;
  597. ucontrol->value.integer.value[0] =
  598. (snd_soc_read(codec, reg) >> shift) & mask;
  599. if (ucontrol->value.integer.value[0])
  600. ucontrol->value.integer.value[0] =
  601. max + 1 - ucontrol->value.integer.value[0];
  602. if (shift != rshift) {
  603. ucontrol->value.integer.value[1] =
  604. (snd_soc_read(codec, reg) >> rshift) & mask;
  605. if (ucontrol->value.integer.value[1])
  606. ucontrol->value.integer.value[1] =
  607. max + 1 - ucontrol->value.integer.value[1];
  608. }
  609. return 0;
  610. }
  611. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  612. struct snd_ctl_elem_value *ucontrol)
  613. {
  614. struct soc_mixer_control *mc =
  615. (struct soc_mixer_control *)kcontrol->private_value;
  616. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  617. unsigned int reg = mc->reg;
  618. unsigned int shift = mc->shift;
  619. unsigned int rshift = mc->rshift;
  620. int max = mc->max;
  621. int mask = (1 << fls(max)) - 1;
  622. unsigned short val, val2, val_mask;
  623. val = (ucontrol->value.integer.value[0] & mask);
  624. val_mask = mask << shift;
  625. if (val)
  626. val = max + 1 - val;
  627. val = val << shift;
  628. if (shift != rshift) {
  629. val2 = (ucontrol->value.integer.value[1] & mask);
  630. val_mask |= mask << rshift;
  631. if (val2)
  632. val2 = max + 1 - val2;
  633. val |= val2 << rshift;
  634. }
  635. return snd_soc_update_bits(codec, reg, val_mask, val);
  636. }
  637. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  638. struct snd_ctl_elem_value *ucontrol)
  639. {
  640. struct soc_mixer_control *mc =
  641. (struct soc_mixer_control *)kcontrol->private_value;
  642. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  643. unsigned int reg = mc->reg;
  644. unsigned int reg2 = mc->rreg;
  645. unsigned int shift = mc->shift;
  646. int max = mc->max;
  647. int mask = (1<<fls(max))-1;
  648. ucontrol->value.integer.value[0] =
  649. (snd_soc_read(codec, reg) >> shift) & mask;
  650. ucontrol->value.integer.value[1] =
  651. (snd_soc_read(codec, reg2) >> shift) & mask;
  652. if (ucontrol->value.integer.value[0])
  653. ucontrol->value.integer.value[0] =
  654. max + 1 - ucontrol->value.integer.value[0];
  655. if (ucontrol->value.integer.value[1])
  656. ucontrol->value.integer.value[1] =
  657. max + 1 - ucontrol->value.integer.value[1];
  658. return 0;
  659. }
  660. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  661. struct snd_ctl_elem_value *ucontrol)
  662. {
  663. struct soc_mixer_control *mc =
  664. (struct soc_mixer_control *)kcontrol->private_value;
  665. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  666. unsigned int reg = mc->reg;
  667. unsigned int reg2 = mc->rreg;
  668. unsigned int shift = mc->shift;
  669. int max = mc->max;
  670. int mask = (1 << fls(max)) - 1;
  671. int err;
  672. unsigned short val, val2, val_mask;
  673. val_mask = mask << shift;
  674. val = (ucontrol->value.integer.value[0] & mask);
  675. val2 = (ucontrol->value.integer.value[1] & mask);
  676. if (val)
  677. val = max + 1 - val;
  678. if (val2)
  679. val2 = max + 1 - val2;
  680. val = val << shift;
  681. val2 = val2 << shift;
  682. err = snd_soc_update_bits(codec, reg, val_mask, val);
  683. if (err < 0)
  684. return err;
  685. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  686. return err;
  687. }
  688. /*
  689. * FGAIN volume control:
  690. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  691. */
  692. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  693. /*
  694. * CGAIN volume control:
  695. * 0 dB to 12 dB in 6 dB steps
  696. * value 2 and 3 means 12 dB
  697. */
  698. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  699. /*
  700. * Analog playback gain
  701. * -24 dB to 12 dB in 2 dB steps
  702. */
  703. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  704. /*
  705. * Gain controls tied to outputs
  706. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  707. */
  708. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  709. /*
  710. * Capture gain after the ADCs
  711. * from 0 dB to 31 dB in 1 dB steps
  712. */
  713. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  714. /*
  715. * Gain control for input amplifiers
  716. * 0 dB to 30 dB in 6 dB steps
  717. */
  718. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  719. static const char *twl4030_rampdelay_texts[] = {
  720. "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
  721. "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
  722. "3495/2581/1748 ms"
  723. };
  724. static const struct soc_enum twl4030_rampdelay_enum =
  725. SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
  726. ARRAY_SIZE(twl4030_rampdelay_texts),
  727. twl4030_rampdelay_texts);
  728. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  729. /* Common playback gain controls */
  730. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  731. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  732. 0, 0x3f, 0, digital_fine_tlv),
  733. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  734. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  735. 0, 0x3f, 0, digital_fine_tlv),
  736. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  737. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  738. 6, 0x2, 0, digital_coarse_tlv),
  739. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  740. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  741. 6, 0x2, 0, digital_coarse_tlv),
  742. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  743. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  744. 3, 0x12, 1, analog_tlv),
  745. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  746. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  747. 3, 0x12, 1, analog_tlv),
  748. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  749. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  750. 1, 1, 0),
  751. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  752. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  753. 1, 1, 0),
  754. /* Separate output gain controls */
  755. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  756. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  757. 4, 3, 0, output_tvl),
  758. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  759. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  760. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  761. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  762. 4, 3, 0, output_tvl),
  763. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  764. TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl),
  765. /* Common capture gain controls */
  766. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  767. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  768. 0, 0x1f, 0, digital_capture_tlv),
  769. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  770. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  771. 0, 0x1f, 0, digital_capture_tlv),
  772. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  773. 0, 3, 5, 0, input_gain_tlv),
  774. SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
  775. };
  776. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  777. /* Left channel inputs */
  778. SND_SOC_DAPM_INPUT("MAINMIC"),
  779. SND_SOC_DAPM_INPUT("HSMIC"),
  780. SND_SOC_DAPM_INPUT("AUXL"),
  781. SND_SOC_DAPM_INPUT("CARKITMIC"),
  782. /* Right channel inputs */
  783. SND_SOC_DAPM_INPUT("SUBMIC"),
  784. SND_SOC_DAPM_INPUT("AUXR"),
  785. /* Digital microphones (Stereo) */
  786. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  787. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  788. /* Outputs */
  789. SND_SOC_DAPM_OUTPUT("OUTL"),
  790. SND_SOC_DAPM_OUTPUT("OUTR"),
  791. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  792. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  793. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  794. SND_SOC_DAPM_OUTPUT("HSOL"),
  795. SND_SOC_DAPM_OUTPUT("HSOR"),
  796. SND_SOC_DAPM_OUTPUT("CARKITL"),
  797. SND_SOC_DAPM_OUTPUT("CARKITR"),
  798. SND_SOC_DAPM_OUTPUT("HFL"),
  799. SND_SOC_DAPM_OUTPUT("HFR"),
  800. /* DACs */
  801. SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
  802. SND_SOC_NOPM, 0, 0),
  803. SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
  804. SND_SOC_NOPM, 0, 0),
  805. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
  806. SND_SOC_NOPM, 0, 0),
  807. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
  808. SND_SOC_NOPM, 0, 0),
  809. /* Analog PGAs */
  810. SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
  811. 0, 0, NULL, 0),
  812. SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
  813. 0, 0, NULL, 0),
  814. SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
  815. 0, 0, NULL, 0),
  816. SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
  817. 0, 0, NULL, 0),
  818. /* Analog bypasses */
  819. SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  820. &twl4030_dapm_abypassr1_control, bypass_event,
  821. SND_SOC_DAPM_POST_REG),
  822. SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  823. &twl4030_dapm_abypassl1_control,
  824. bypass_event, SND_SOC_DAPM_POST_REG),
  825. SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  826. &twl4030_dapm_abypassr2_control,
  827. bypass_event, SND_SOC_DAPM_POST_REG),
  828. SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  829. &twl4030_dapm_abypassl2_control,
  830. bypass_event, SND_SOC_DAPM_POST_REG),
  831. /* Digital bypasses */
  832. SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
  833. &twl4030_dapm_dbypassl_control, bypass_event,
  834. SND_SOC_DAPM_POST_REG),
  835. SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
  836. &twl4030_dapm_dbypassr_control, bypass_event,
  837. SND_SOC_DAPM_POST_REG),
  838. SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  839. 0, 0, NULL, 0),
  840. SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  841. 1, 0, NULL, 0),
  842. SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  843. 2, 0, NULL, 0),
  844. SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  845. 3, 0, NULL, 0),
  846. /* Output MUX controls */
  847. /* Earpiece */
  848. SND_SOC_DAPM_VALUE_MUX("Earpiece Mux", SND_SOC_NOPM, 0, 0,
  849. &twl4030_dapm_earpiece_control),
  850. /* PreDrivL/R */
  851. SND_SOC_DAPM_VALUE_MUX("PredriveL Mux", SND_SOC_NOPM, 0, 0,
  852. &twl4030_dapm_predrivel_control),
  853. SND_SOC_DAPM_VALUE_MUX("PredriveR Mux", SND_SOC_NOPM, 0, 0,
  854. &twl4030_dapm_predriver_control),
  855. /* HeadsetL/R */
  856. SND_SOC_DAPM_MUX_E("HeadsetL Mux", SND_SOC_NOPM, 0, 0,
  857. &twl4030_dapm_hsol_control, headsetl_event,
  858. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  859. SND_SOC_DAPM_MUX("HeadsetR Mux", SND_SOC_NOPM, 0, 0,
  860. &twl4030_dapm_hsor_control),
  861. /* CarkitL/R */
  862. SND_SOC_DAPM_MUX("CarkitL Mux", SND_SOC_NOPM, 0, 0,
  863. &twl4030_dapm_carkitl_control),
  864. SND_SOC_DAPM_MUX("CarkitR Mux", SND_SOC_NOPM, 0, 0,
  865. &twl4030_dapm_carkitr_control),
  866. /* HandsfreeL/R */
  867. SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
  868. &twl4030_dapm_handsfreel_control, handsfree_event,
  869. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  870. SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
  871. &twl4030_dapm_handsfreer_control, handsfree_event,
  872. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  873. /* Introducing four virtual ADC, since TWL4030 have four channel for
  874. capture */
  875. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  876. SND_SOC_NOPM, 0, 0),
  877. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  878. SND_SOC_NOPM, 0, 0),
  879. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  880. SND_SOC_NOPM, 0, 0),
  881. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  882. SND_SOC_NOPM, 0, 0),
  883. /* Analog/Digital mic path selection.
  884. TX1 Left/Right: either analog Left/Right or Digimic0
  885. TX2 Left/Right: either analog Left/Right or Digimic1 */
  886. SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  887. &twl4030_dapm_micpathtx1_control, micpath_event,
  888. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  889. SND_SOC_DAPM_POST_REG),
  890. SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  891. &twl4030_dapm_micpathtx2_control, micpath_event,
  892. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  893. SND_SOC_DAPM_POST_REG),
  894. /* Analog input muxes with switch for the capture amplifiers */
  895. SND_SOC_DAPM_VALUE_MUX("Analog Left Capture Route",
  896. TWL4030_REG_ANAMICL, 4, 0, &twl4030_dapm_analoglmic_control),
  897. SND_SOC_DAPM_VALUE_MUX("Analog Right Capture Route",
  898. TWL4030_REG_ANAMICR, 4, 0, &twl4030_dapm_analogrmic_control),
  899. SND_SOC_DAPM_PGA("ADC Physical Left",
  900. TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
  901. SND_SOC_DAPM_PGA("ADC Physical Right",
  902. TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
  903. SND_SOC_DAPM_PGA("Digimic0 Enable",
  904. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
  905. SND_SOC_DAPM_PGA("Digimic1 Enable",
  906. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
  907. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  908. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  909. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  910. };
  911. static const struct snd_soc_dapm_route intercon[] = {
  912. {"Analog L1 Playback Mixer", NULL, "DAC Left1"},
  913. {"Analog R1 Playback Mixer", NULL, "DAC Right1"},
  914. {"Analog L2 Playback Mixer", NULL, "DAC Left2"},
  915. {"Analog R2 Playback Mixer", NULL, "DAC Right2"},
  916. {"ARXL1_APGA", NULL, "Analog L1 Playback Mixer"},
  917. {"ARXR1_APGA", NULL, "Analog R1 Playback Mixer"},
  918. {"ARXL2_APGA", NULL, "Analog L2 Playback Mixer"},
  919. {"ARXR2_APGA", NULL, "Analog R2 Playback Mixer"},
  920. /* Internal playback routings */
  921. /* Earpiece */
  922. {"Earpiece Mux", "DACL1", "ARXL1_APGA"},
  923. {"Earpiece Mux", "DACL2", "ARXL2_APGA"},
  924. {"Earpiece Mux", "DACR1", "ARXR1_APGA"},
  925. /* PreDrivL */
  926. {"PredriveL Mux", "DACL1", "ARXL1_APGA"},
  927. {"PredriveL Mux", "DACL2", "ARXL2_APGA"},
  928. {"PredriveL Mux", "DACR2", "ARXR2_APGA"},
  929. /* PreDrivR */
  930. {"PredriveR Mux", "DACR1", "ARXR1_APGA"},
  931. {"PredriveR Mux", "DACR2", "ARXR2_APGA"},
  932. {"PredriveR Mux", "DACL2", "ARXL2_APGA"},
  933. /* HeadsetL */
  934. {"HeadsetL Mux", "DACL1", "ARXL1_APGA"},
  935. {"HeadsetL Mux", "DACL2", "ARXL2_APGA"},
  936. /* HeadsetR */
  937. {"HeadsetR Mux", "DACR1", "ARXR1_APGA"},
  938. {"HeadsetR Mux", "DACR2", "ARXR2_APGA"},
  939. /* CarkitL */
  940. {"CarkitL Mux", "DACL1", "ARXL1_APGA"},
  941. {"CarkitL Mux", "DACL2", "ARXL2_APGA"},
  942. /* CarkitR */
  943. {"CarkitR Mux", "DACR1", "ARXR1_APGA"},
  944. {"CarkitR Mux", "DACR2", "ARXR2_APGA"},
  945. /* HandsfreeL */
  946. {"HandsfreeL Mux", "DACL1", "ARXL1_APGA"},
  947. {"HandsfreeL Mux", "DACL2", "ARXL2_APGA"},
  948. {"HandsfreeL Mux", "DACR2", "ARXR2_APGA"},
  949. /* HandsfreeR */
  950. {"HandsfreeR Mux", "DACR1", "ARXR1_APGA"},
  951. {"HandsfreeR Mux", "DACR2", "ARXR2_APGA"},
  952. {"HandsfreeR Mux", "DACL2", "ARXL2_APGA"},
  953. /* outputs */
  954. {"OUTL", NULL, "ARXL2_APGA"},
  955. {"OUTR", NULL, "ARXR2_APGA"},
  956. {"EARPIECE", NULL, "Earpiece Mux"},
  957. {"PREDRIVEL", NULL, "PredriveL Mux"},
  958. {"PREDRIVER", NULL, "PredriveR Mux"},
  959. {"HSOL", NULL, "HeadsetL Mux"},
  960. {"HSOR", NULL, "HeadsetR Mux"},
  961. {"CARKITL", NULL, "CarkitL Mux"},
  962. {"CARKITR", NULL, "CarkitR Mux"},
  963. {"HFL", NULL, "HandsfreeL Mux"},
  964. {"HFR", NULL, "HandsfreeR Mux"},
  965. /* Capture path */
  966. {"Analog Left Capture Route", "Main mic", "MAINMIC"},
  967. {"Analog Left Capture Route", "Headset mic", "HSMIC"},
  968. {"Analog Left Capture Route", "AUXL", "AUXL"},
  969. {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
  970. {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
  971. {"Analog Right Capture Route", "AUXR", "AUXR"},
  972. {"ADC Physical Left", NULL, "Analog Left Capture Route"},
  973. {"ADC Physical Right", NULL, "Analog Right Capture Route"},
  974. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  975. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  976. /* TX1 Left capture path */
  977. {"TX1 Capture Route", "Analog", "ADC Physical Left"},
  978. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  979. /* TX1 Right capture path */
  980. {"TX1 Capture Route", "Analog", "ADC Physical Right"},
  981. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  982. /* TX2 Left capture path */
  983. {"TX2 Capture Route", "Analog", "ADC Physical Left"},
  984. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  985. /* TX2 Right capture path */
  986. {"TX2 Capture Route", "Analog", "ADC Physical Right"},
  987. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  988. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  989. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  990. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  991. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  992. /* Analog bypass routes */
  993. {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
  994. {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
  995. {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
  996. {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
  997. {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
  998. {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
  999. {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
  1000. {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
  1001. /* Digital bypass routes */
  1002. {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
  1003. {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
  1004. {"Analog R2 Playback Mixer", NULL, "Right Digital Loopback"},
  1005. {"Analog L2 Playback Mixer", NULL, "Left Digital Loopback"},
  1006. };
  1007. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  1008. {
  1009. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  1010. ARRAY_SIZE(twl4030_dapm_widgets));
  1011. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  1012. snd_soc_dapm_new_widgets(codec);
  1013. return 0;
  1014. }
  1015. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  1016. enum snd_soc_bias_level level)
  1017. {
  1018. struct twl4030_priv *twl4030 = codec->private_data;
  1019. switch (level) {
  1020. case SND_SOC_BIAS_ON:
  1021. twl4030_codec_mute(codec, 0);
  1022. break;
  1023. case SND_SOC_BIAS_PREPARE:
  1024. twl4030_power_up(codec);
  1025. if (twl4030->bypass_state)
  1026. twl4030_codec_mute(codec, 0);
  1027. else
  1028. twl4030_codec_mute(codec, 1);
  1029. break;
  1030. case SND_SOC_BIAS_STANDBY:
  1031. twl4030_power_up(codec);
  1032. if (twl4030->bypass_state)
  1033. twl4030_codec_mute(codec, 0);
  1034. else
  1035. twl4030_codec_mute(codec, 1);
  1036. break;
  1037. case SND_SOC_BIAS_OFF:
  1038. twl4030_power_down(codec);
  1039. break;
  1040. }
  1041. codec->bias_level = level;
  1042. return 0;
  1043. }
  1044. static int twl4030_startup(struct snd_pcm_substream *substream)
  1045. {
  1046. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1047. struct snd_soc_device *socdev = rtd->socdev;
  1048. struct snd_soc_codec *codec = socdev->codec;
  1049. struct twl4030_priv *twl4030 = codec->private_data;
  1050. /* If we already have a playback or capture going then constrain
  1051. * this substream to match it.
  1052. */
  1053. if (twl4030->master_substream) {
  1054. struct snd_pcm_runtime *master_runtime;
  1055. master_runtime = twl4030->master_substream->runtime;
  1056. snd_pcm_hw_constraint_minmax(substream->runtime,
  1057. SNDRV_PCM_HW_PARAM_RATE,
  1058. master_runtime->rate,
  1059. master_runtime->rate);
  1060. snd_pcm_hw_constraint_minmax(substream->runtime,
  1061. SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
  1062. master_runtime->sample_bits,
  1063. master_runtime->sample_bits);
  1064. twl4030->slave_substream = substream;
  1065. } else
  1066. twl4030->master_substream = substream;
  1067. return 0;
  1068. }
  1069. static void twl4030_shutdown(struct snd_pcm_substream *substream)
  1070. {
  1071. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1072. struct snd_soc_device *socdev = rtd->socdev;
  1073. struct snd_soc_codec *codec = socdev->codec;
  1074. struct twl4030_priv *twl4030 = codec->private_data;
  1075. if (twl4030->master_substream == substream)
  1076. twl4030->master_substream = twl4030->slave_substream;
  1077. twl4030->slave_substream = NULL;
  1078. }
  1079. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  1080. struct snd_pcm_hw_params *params,
  1081. struct snd_soc_dai *dai)
  1082. {
  1083. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1084. struct snd_soc_device *socdev = rtd->socdev;
  1085. struct snd_soc_codec *codec = socdev->card->codec;
  1086. struct twl4030_priv *twl4030 = codec->private_data;
  1087. u8 mode, old_mode, format, old_format;
  1088. if (substream == twl4030->slave_substream)
  1089. /* Ignoring hw_params for slave substream */
  1090. return 0;
  1091. /* bit rate */
  1092. old_mode = twl4030_read_reg_cache(codec,
  1093. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  1094. mode = old_mode & ~TWL4030_APLL_RATE;
  1095. switch (params_rate(params)) {
  1096. case 8000:
  1097. mode |= TWL4030_APLL_RATE_8000;
  1098. break;
  1099. case 11025:
  1100. mode |= TWL4030_APLL_RATE_11025;
  1101. break;
  1102. case 12000:
  1103. mode |= TWL4030_APLL_RATE_12000;
  1104. break;
  1105. case 16000:
  1106. mode |= TWL4030_APLL_RATE_16000;
  1107. break;
  1108. case 22050:
  1109. mode |= TWL4030_APLL_RATE_22050;
  1110. break;
  1111. case 24000:
  1112. mode |= TWL4030_APLL_RATE_24000;
  1113. break;
  1114. case 32000:
  1115. mode |= TWL4030_APLL_RATE_32000;
  1116. break;
  1117. case 44100:
  1118. mode |= TWL4030_APLL_RATE_44100;
  1119. break;
  1120. case 48000:
  1121. mode |= TWL4030_APLL_RATE_48000;
  1122. break;
  1123. case 96000:
  1124. mode |= TWL4030_APLL_RATE_96000;
  1125. break;
  1126. default:
  1127. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  1128. params_rate(params));
  1129. return -EINVAL;
  1130. }
  1131. if (mode != old_mode) {
  1132. /* change rate and set CODECPDZ */
  1133. twl4030_codec_enable(codec, 0);
  1134. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1135. twl4030_codec_enable(codec, 1);
  1136. }
  1137. /* sample size */
  1138. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1139. format = old_format;
  1140. format &= ~TWL4030_DATA_WIDTH;
  1141. switch (params_format(params)) {
  1142. case SNDRV_PCM_FORMAT_S16_LE:
  1143. format |= TWL4030_DATA_WIDTH_16S_16W;
  1144. break;
  1145. case SNDRV_PCM_FORMAT_S24_LE:
  1146. format |= TWL4030_DATA_WIDTH_32S_24W;
  1147. break;
  1148. default:
  1149. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  1150. params_format(params));
  1151. return -EINVAL;
  1152. }
  1153. if (format != old_format) {
  1154. /* clear CODECPDZ before changing format (codec requirement) */
  1155. twl4030_codec_enable(codec, 0);
  1156. /* change format */
  1157. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1158. /* set CODECPDZ afterwards */
  1159. twl4030_codec_enable(codec, 1);
  1160. }
  1161. return 0;
  1162. }
  1163. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1164. int clk_id, unsigned int freq, int dir)
  1165. {
  1166. struct snd_soc_codec *codec = codec_dai->codec;
  1167. u8 infreq;
  1168. switch (freq) {
  1169. case 19200000:
  1170. infreq = TWL4030_APLL_INFREQ_19200KHZ;
  1171. break;
  1172. case 26000000:
  1173. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  1174. break;
  1175. case 38400000:
  1176. infreq = TWL4030_APLL_INFREQ_38400KHZ;
  1177. break;
  1178. default:
  1179. printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
  1180. freq);
  1181. return -EINVAL;
  1182. }
  1183. infreq |= TWL4030_APLL_EN;
  1184. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  1185. return 0;
  1186. }
  1187. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1188. unsigned int fmt)
  1189. {
  1190. struct snd_soc_codec *codec = codec_dai->codec;
  1191. u8 old_format, format;
  1192. /* get format */
  1193. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1194. format = old_format;
  1195. /* set master/slave audio interface */
  1196. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1197. case SND_SOC_DAIFMT_CBM_CFM:
  1198. format &= ~(TWL4030_AIF_SLAVE_EN);
  1199. format &= ~(TWL4030_CLK256FS_EN);
  1200. break;
  1201. case SND_SOC_DAIFMT_CBS_CFS:
  1202. format |= TWL4030_AIF_SLAVE_EN;
  1203. format |= TWL4030_CLK256FS_EN;
  1204. break;
  1205. default:
  1206. return -EINVAL;
  1207. }
  1208. /* interface format */
  1209. format &= ~TWL4030_AIF_FORMAT;
  1210. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1211. case SND_SOC_DAIFMT_I2S:
  1212. format |= TWL4030_AIF_FORMAT_CODEC;
  1213. break;
  1214. default:
  1215. return -EINVAL;
  1216. }
  1217. if (format != old_format) {
  1218. /* clear CODECPDZ before changing format (codec requirement) */
  1219. twl4030_codec_enable(codec, 0);
  1220. /* change format */
  1221. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1222. /* set CODECPDZ afterwards */
  1223. twl4030_codec_enable(codec, 1);
  1224. }
  1225. return 0;
  1226. }
  1227. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  1228. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  1229. static struct snd_soc_dai_ops twl4030_dai_ops = {
  1230. .startup = twl4030_startup,
  1231. .shutdown = twl4030_shutdown,
  1232. .hw_params = twl4030_hw_params,
  1233. .set_sysclk = twl4030_set_dai_sysclk,
  1234. .set_fmt = twl4030_set_dai_fmt,
  1235. };
  1236. struct snd_soc_dai twl4030_dai = {
  1237. .name = "twl4030",
  1238. .playback = {
  1239. .stream_name = "Playback",
  1240. .channels_min = 2,
  1241. .channels_max = 2,
  1242. .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
  1243. .formats = TWL4030_FORMATS,},
  1244. .capture = {
  1245. .stream_name = "Capture",
  1246. .channels_min = 2,
  1247. .channels_max = 2,
  1248. .rates = TWL4030_RATES,
  1249. .formats = TWL4030_FORMATS,},
  1250. .ops = &twl4030_dai_ops,
  1251. };
  1252. EXPORT_SYMBOL_GPL(twl4030_dai);
  1253. static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
  1254. {
  1255. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1256. struct snd_soc_codec *codec = socdev->card->codec;
  1257. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1258. return 0;
  1259. }
  1260. static int twl4030_resume(struct platform_device *pdev)
  1261. {
  1262. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1263. struct snd_soc_codec *codec = socdev->card->codec;
  1264. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1265. twl4030_set_bias_level(codec, codec->suspend_bias_level);
  1266. return 0;
  1267. }
  1268. /*
  1269. * initialize the driver
  1270. * register the mixer and dsp interfaces with the kernel
  1271. */
  1272. static int twl4030_init(struct snd_soc_device *socdev)
  1273. {
  1274. struct snd_soc_codec *codec = socdev->card->codec;
  1275. int ret = 0;
  1276. printk(KERN_INFO "TWL4030 Audio Codec init \n");
  1277. codec->name = "twl4030";
  1278. codec->owner = THIS_MODULE;
  1279. codec->read = twl4030_read_reg_cache;
  1280. codec->write = twl4030_write;
  1281. codec->set_bias_level = twl4030_set_bias_level;
  1282. codec->dai = &twl4030_dai;
  1283. codec->num_dai = 1;
  1284. codec->reg_cache_size = sizeof(twl4030_reg);
  1285. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  1286. GFP_KERNEL);
  1287. if (codec->reg_cache == NULL)
  1288. return -ENOMEM;
  1289. /* register pcms */
  1290. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1291. if (ret < 0) {
  1292. printk(KERN_ERR "twl4030: failed to create pcms\n");
  1293. goto pcm_err;
  1294. }
  1295. twl4030_init_chip(codec);
  1296. /* power on device */
  1297. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1298. snd_soc_add_controls(codec, twl4030_snd_controls,
  1299. ARRAY_SIZE(twl4030_snd_controls));
  1300. twl4030_add_widgets(codec);
  1301. ret = snd_soc_init_card(socdev);
  1302. if (ret < 0) {
  1303. printk(KERN_ERR "twl4030: failed to register card\n");
  1304. goto card_err;
  1305. }
  1306. return ret;
  1307. card_err:
  1308. snd_soc_free_pcms(socdev);
  1309. snd_soc_dapm_free(socdev);
  1310. pcm_err:
  1311. kfree(codec->reg_cache);
  1312. return ret;
  1313. }
  1314. static struct snd_soc_device *twl4030_socdev;
  1315. static int twl4030_probe(struct platform_device *pdev)
  1316. {
  1317. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1318. struct snd_soc_codec *codec;
  1319. struct twl4030_priv *twl4030;
  1320. codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
  1321. if (codec == NULL)
  1322. return -ENOMEM;
  1323. twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
  1324. if (twl4030 == NULL) {
  1325. kfree(codec);
  1326. return -ENOMEM;
  1327. }
  1328. codec->private_data = twl4030;
  1329. socdev->card->codec = codec;
  1330. mutex_init(&codec->mutex);
  1331. INIT_LIST_HEAD(&codec->dapm_widgets);
  1332. INIT_LIST_HEAD(&codec->dapm_paths);
  1333. twl4030_socdev = socdev;
  1334. twl4030_init(socdev);
  1335. return 0;
  1336. }
  1337. static int twl4030_remove(struct platform_device *pdev)
  1338. {
  1339. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1340. struct snd_soc_codec *codec = socdev->card->codec;
  1341. printk(KERN_INFO "TWL4030 Audio Codec remove\n");
  1342. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1343. snd_soc_free_pcms(socdev);
  1344. snd_soc_dapm_free(socdev);
  1345. kfree(codec->private_data);
  1346. kfree(codec);
  1347. return 0;
  1348. }
  1349. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  1350. .probe = twl4030_probe,
  1351. .remove = twl4030_remove,
  1352. .suspend = twl4030_suspend,
  1353. .resume = twl4030_resume,
  1354. };
  1355. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  1356. static int __init twl4030_modinit(void)
  1357. {
  1358. return snd_soc_register_dai(&twl4030_dai);
  1359. }
  1360. module_init(twl4030_modinit);
  1361. static void __exit twl4030_exit(void)
  1362. {
  1363. snd_soc_unregister_dai(&twl4030_dai);
  1364. }
  1365. module_exit(twl4030_exit);
  1366. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  1367. MODULE_AUTHOR("Steve Sakoman");
  1368. MODULE_LICENSE("GPL");