fimc-core.c 37 KB

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  1. /*
  2. * S5P camera interface (video postprocessor) driver
  3. *
  4. * Copyright (c) 2010 Samsung Electronics
  5. *
  6. * Sylwester Nawrocki, <s.nawrocki@samsung.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published
  10. * by the Free Software Foundation, either version 2 of the License,
  11. * or (at your option) any later version.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/version.h>
  16. #include <linux/types.h>
  17. #include <linux/errno.h>
  18. #include <linux/bug.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/device.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/list.h>
  23. #include <linux/io.h>
  24. #include <linux/slab.h>
  25. #include <linux/clk.h>
  26. #include <media/v4l2-ioctl.h>
  27. #include <media/videobuf-dma-contig.h>
  28. #include "fimc-core.h"
  29. static char *fimc_clock_name[NUM_FIMC_CLOCKS] = { "sclk_fimc", "fimc" };
  30. static struct fimc_fmt fimc_formats[] = {
  31. {
  32. .name = "RGB565",
  33. .fourcc = V4L2_PIX_FMT_RGB565X,
  34. .depth = 16,
  35. .color = S5P_FIMC_RGB565,
  36. .buff_cnt = 1,
  37. .planes_cnt = 1
  38. }, {
  39. .name = "BGR666",
  40. .fourcc = V4L2_PIX_FMT_BGR666,
  41. .depth = 32,
  42. .color = S5P_FIMC_RGB666,
  43. .buff_cnt = 1,
  44. .planes_cnt = 1
  45. }, {
  46. .name = "XRGB-8-8-8-8, 24 bpp",
  47. .fourcc = V4L2_PIX_FMT_RGB24,
  48. .depth = 32,
  49. .color = S5P_FIMC_RGB888,
  50. .buff_cnt = 1,
  51. .planes_cnt = 1
  52. }, {
  53. .name = "YUV 4:2:2 packed, YCbYCr",
  54. .fourcc = V4L2_PIX_FMT_YUYV,
  55. .depth = 16,
  56. .color = S5P_FIMC_YCBYCR422,
  57. .buff_cnt = 1,
  58. .planes_cnt = 1
  59. }, {
  60. .name = "YUV 4:2:2 packed, CbYCrY",
  61. .fourcc = V4L2_PIX_FMT_UYVY,
  62. .depth = 16,
  63. .color = S5P_FIMC_CBYCRY422,
  64. .buff_cnt = 1,
  65. .planes_cnt = 1
  66. }, {
  67. .name = "YUV 4:2:2 packed, CrYCbY",
  68. .fourcc = V4L2_PIX_FMT_VYUY,
  69. .depth = 16,
  70. .color = S5P_FIMC_CRYCBY422,
  71. .buff_cnt = 1,
  72. .planes_cnt = 1
  73. }, {
  74. .name = "YUV 4:2:2 packed, YCrYCb",
  75. .fourcc = V4L2_PIX_FMT_YVYU,
  76. .depth = 16,
  77. .color = S5P_FIMC_YCRYCB422,
  78. .buff_cnt = 1,
  79. .planes_cnt = 1
  80. }, {
  81. .name = "YUV 4:2:2 planar, Y/Cb/Cr",
  82. .fourcc = V4L2_PIX_FMT_YUV422P,
  83. .depth = 12,
  84. .color = S5P_FIMC_YCBCR422,
  85. .buff_cnt = 1,
  86. .planes_cnt = 3
  87. }, {
  88. .name = "YUV 4:2:2 planar, Y/CbCr",
  89. .fourcc = V4L2_PIX_FMT_NV16,
  90. .depth = 16,
  91. .color = S5P_FIMC_YCBCR422,
  92. .buff_cnt = 1,
  93. .planes_cnt = 2
  94. }, {
  95. .name = "YUV 4:2:2 planar, Y/CrCb",
  96. .fourcc = V4L2_PIX_FMT_NV61,
  97. .depth = 16,
  98. .color = S5P_FIMC_RGB565,
  99. .buff_cnt = 1,
  100. .planes_cnt = 2
  101. }, {
  102. .name = "YUV 4:2:0 planar, YCbCr",
  103. .fourcc = V4L2_PIX_FMT_YUV420,
  104. .depth = 12,
  105. .color = S5P_FIMC_YCBCR420,
  106. .buff_cnt = 1,
  107. .planes_cnt = 3
  108. }, {
  109. .name = "YUV 4:2:0 planar, Y/CbCr",
  110. .fourcc = V4L2_PIX_FMT_NV12,
  111. .depth = 12,
  112. .color = S5P_FIMC_YCBCR420,
  113. .buff_cnt = 1,
  114. .planes_cnt = 2
  115. }
  116. };
  117. static struct v4l2_queryctrl fimc_ctrls[] = {
  118. {
  119. .id = V4L2_CID_HFLIP,
  120. .type = V4L2_CTRL_TYPE_BOOLEAN,
  121. .name = "Horizontal flip",
  122. .minimum = 0,
  123. .maximum = 1,
  124. .default_value = 0,
  125. },
  126. {
  127. .id = V4L2_CID_VFLIP,
  128. .type = V4L2_CTRL_TYPE_BOOLEAN,
  129. .name = "Vertical flip",
  130. .minimum = 0,
  131. .maximum = 1,
  132. .default_value = 0,
  133. },
  134. {
  135. .id = V4L2_CID_ROTATE,
  136. .type = V4L2_CTRL_TYPE_INTEGER,
  137. .name = "Rotation (CCW)",
  138. .minimum = 0,
  139. .maximum = 270,
  140. .step = 90,
  141. .default_value = 0,
  142. },
  143. };
  144. static struct v4l2_queryctrl *get_ctrl(int id)
  145. {
  146. int i;
  147. for (i = 0; i < ARRAY_SIZE(fimc_ctrls); ++i)
  148. if (id == fimc_ctrls[i].id)
  149. return &fimc_ctrls[i];
  150. return NULL;
  151. }
  152. static int fimc_check_scaler_ratio(struct v4l2_rect *r, struct fimc_frame *f)
  153. {
  154. if (r->width > f->width) {
  155. if (f->width > (r->width * SCALER_MAX_HRATIO))
  156. return -EINVAL;
  157. } else {
  158. if ((f->width * SCALER_MAX_HRATIO) < r->width)
  159. return -EINVAL;
  160. }
  161. if (r->height > f->height) {
  162. if (f->height > (r->height * SCALER_MAX_VRATIO))
  163. return -EINVAL;
  164. } else {
  165. if ((f->height * SCALER_MAX_VRATIO) < r->height)
  166. return -EINVAL;
  167. }
  168. return 0;
  169. }
  170. static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
  171. {
  172. if (src >= tar * 64) {
  173. return -EINVAL;
  174. } else if (src >= tar * 32) {
  175. *ratio = 32;
  176. *shift = 5;
  177. } else if (src >= tar * 16) {
  178. *ratio = 16;
  179. *shift = 4;
  180. } else if (src >= tar * 8) {
  181. *ratio = 8;
  182. *shift = 3;
  183. } else if (src >= tar * 4) {
  184. *ratio = 4;
  185. *shift = 2;
  186. } else if (src >= tar * 2) {
  187. *ratio = 2;
  188. *shift = 1;
  189. } else {
  190. *ratio = 1;
  191. *shift = 0;
  192. }
  193. return 0;
  194. }
  195. static int fimc_set_scaler_info(struct fimc_ctx *ctx)
  196. {
  197. struct fimc_scaler *sc = &ctx->scaler;
  198. struct fimc_frame *s_frame = &ctx->s_frame;
  199. struct fimc_frame *d_frame = &ctx->d_frame;
  200. int tx, ty, sx, sy;
  201. int ret;
  202. tx = d_frame->width;
  203. ty = d_frame->height;
  204. if (tx <= 0 || ty <= 0) {
  205. v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
  206. "invalid target size: %d x %d", tx, ty);
  207. return -EINVAL;
  208. }
  209. sx = s_frame->width;
  210. sy = s_frame->height;
  211. if (sx <= 0 || sy <= 0) {
  212. err("invalid source size: %d x %d", sx, sy);
  213. return -EINVAL;
  214. }
  215. sc->real_width = sx;
  216. sc->real_height = sy;
  217. dbg("sx= %d, sy= %d, tx= %d, ty= %d", sx, sy, tx, ty);
  218. ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
  219. if (ret)
  220. return ret;
  221. ret = fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor);
  222. if (ret)
  223. return ret;
  224. sc->pre_dst_width = sx / sc->pre_hratio;
  225. sc->pre_dst_height = sy / sc->pre_vratio;
  226. sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
  227. sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
  228. sc->scaleup_h = (tx >= sx) ? 1 : 0;
  229. sc->scaleup_v = (ty >= sy) ? 1 : 0;
  230. /* check to see if input and output size/format differ */
  231. if (s_frame->fmt->color == d_frame->fmt->color
  232. && s_frame->width == d_frame->width
  233. && s_frame->height == d_frame->height)
  234. sc->copy_mode = 1;
  235. else
  236. sc->copy_mode = 0;
  237. return 0;
  238. }
  239. static irqreturn_t fimc_isr(int irq, void *priv)
  240. {
  241. struct fimc_vid_buffer *src_buf, *dst_buf;
  242. struct fimc_dev *fimc = (struct fimc_dev *)priv;
  243. struct fimc_ctx *ctx;
  244. BUG_ON(!fimc);
  245. fimc_hw_clear_irq(fimc);
  246. spin_lock(&fimc->slock);
  247. if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
  248. ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
  249. if (!ctx || !ctx->m2m_ctx)
  250. goto isr_unlock;
  251. src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
  252. dst_buf = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
  253. if (src_buf && dst_buf) {
  254. spin_lock(&fimc->irqlock);
  255. src_buf->vb.state = dst_buf->vb.state = VIDEOBUF_DONE;
  256. wake_up(&src_buf->vb.done);
  257. wake_up(&dst_buf->vb.done);
  258. spin_unlock(&fimc->irqlock);
  259. v4l2_m2m_job_finish(fimc->m2m.m2m_dev, ctx->m2m_ctx);
  260. }
  261. }
  262. isr_unlock:
  263. spin_unlock(&fimc->slock);
  264. return IRQ_HANDLED;
  265. }
  266. /* The color format (planes_cnt, buff_cnt) must be already configured. */
  267. static int fimc_prepare_addr(struct fimc_ctx *ctx,
  268. struct fimc_vid_buffer *buf, enum v4l2_buf_type type)
  269. {
  270. struct fimc_frame *frame;
  271. struct fimc_addr *paddr;
  272. u32 pix_size;
  273. int ret = 0;
  274. frame = ctx_m2m_get_frame(ctx, type);
  275. if (IS_ERR(frame))
  276. return PTR_ERR(frame);
  277. paddr = &frame->paddr;
  278. if (!buf)
  279. return -EINVAL;
  280. pix_size = frame->width * frame->height;
  281. dbg("buff_cnt= %d, planes_cnt= %d, frame->size= %d, pix_size= %d",
  282. frame->fmt->buff_cnt, frame->fmt->planes_cnt,
  283. frame->size, pix_size);
  284. if (frame->fmt->buff_cnt == 1) {
  285. paddr->y = videobuf_to_dma_contig(&buf->vb);
  286. switch (frame->fmt->planes_cnt) {
  287. case 1:
  288. paddr->cb = 0;
  289. paddr->cr = 0;
  290. break;
  291. case 2:
  292. /* decompose Y into Y/Cb */
  293. paddr->cb = (u32)(paddr->y + pix_size);
  294. paddr->cr = 0;
  295. break;
  296. case 3:
  297. paddr->cb = (u32)(paddr->y + pix_size);
  298. /* decompose Y into Y/Cb/Cr */
  299. if (S5P_FIMC_YCBCR420 == frame->fmt->color)
  300. paddr->cr = (u32)(paddr->cb
  301. + (pix_size >> 2));
  302. else /* 422 */
  303. paddr->cr = (u32)(paddr->cb
  304. + (pix_size >> 1));
  305. break;
  306. default:
  307. return -EINVAL;
  308. }
  309. }
  310. dbg("PHYS_ADDR: type= %d, y= 0x%X cb= 0x%X cr= 0x%X ret= %d",
  311. type, paddr->y, paddr->cb, paddr->cr, ret);
  312. return ret;
  313. }
  314. /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
  315. static void fimc_set_yuv_order(struct fimc_ctx *ctx)
  316. {
  317. /* The one only mode supported in SoC. */
  318. ctx->in_order_2p = S5P_FIMC_LSB_CRCB;
  319. ctx->out_order_2p = S5P_FIMC_LSB_CRCB;
  320. /* Set order for 1 plane input formats. */
  321. switch (ctx->s_frame.fmt->color) {
  322. case S5P_FIMC_YCRYCB422:
  323. ctx->in_order_1p = S5P_FIMC_IN_YCRYCB;
  324. break;
  325. case S5P_FIMC_CBYCRY422:
  326. ctx->in_order_1p = S5P_FIMC_IN_CBYCRY;
  327. break;
  328. case S5P_FIMC_CRYCBY422:
  329. ctx->in_order_1p = S5P_FIMC_IN_CRYCBY;
  330. break;
  331. case S5P_FIMC_YCBYCR422:
  332. default:
  333. ctx->in_order_1p = S5P_FIMC_IN_YCBYCR;
  334. break;
  335. }
  336. dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
  337. switch (ctx->d_frame.fmt->color) {
  338. case S5P_FIMC_YCRYCB422:
  339. ctx->out_order_1p = S5P_FIMC_OUT_YCRYCB;
  340. break;
  341. case S5P_FIMC_CBYCRY422:
  342. ctx->out_order_1p = S5P_FIMC_OUT_CBYCRY;
  343. break;
  344. case S5P_FIMC_CRYCBY422:
  345. ctx->out_order_1p = S5P_FIMC_OUT_CRYCBY;
  346. break;
  347. case S5P_FIMC_YCBYCR422:
  348. default:
  349. ctx->out_order_1p = S5P_FIMC_OUT_YCBYCR;
  350. break;
  351. }
  352. dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
  353. }
  354. /**
  355. * fimc_prepare_config - check dimensions, operation and color mode
  356. * and pre-calculate offset and the scaling coefficients.
  357. *
  358. * @ctx: hardware context information
  359. * @flags: flags indicating which parameters to check/update
  360. *
  361. * Return: 0 if dimensions are valid or non zero otherwise.
  362. */
  363. static int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags)
  364. {
  365. struct fimc_frame *s_frame, *d_frame;
  366. struct fimc_vid_buffer *buf = NULL;
  367. struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
  368. int ret = 0;
  369. s_frame = &ctx->s_frame;
  370. d_frame = &ctx->d_frame;
  371. if (flags & FIMC_PARAMS) {
  372. if ((ctx->out_path == FIMC_DMA) &&
  373. (ctx->rotation == 90 || ctx->rotation == 270)) {
  374. swap(d_frame->f_width, d_frame->f_height);
  375. swap(d_frame->width, d_frame->height);
  376. }
  377. /* Prepare the output offset ratios for scaler. */
  378. d_frame->dma_offset.y_h = d_frame->offs_h;
  379. if (!variant->pix_hoff)
  380. d_frame->dma_offset.y_h *= (d_frame->fmt->depth >> 3);
  381. d_frame->dma_offset.y_v = d_frame->offs_v;
  382. d_frame->dma_offset.cb_h = d_frame->offs_h;
  383. d_frame->dma_offset.cb_v = d_frame->offs_v;
  384. d_frame->dma_offset.cr_h = d_frame->offs_h;
  385. d_frame->dma_offset.cr_v = d_frame->offs_v;
  386. if (!variant->pix_hoff && d_frame->fmt->planes_cnt == 3) {
  387. d_frame->dma_offset.cb_h >>= 1;
  388. d_frame->dma_offset.cb_v >>= 1;
  389. d_frame->dma_offset.cr_h >>= 1;
  390. d_frame->dma_offset.cr_v >>= 1;
  391. }
  392. dbg("out offset: color= %d, y_h= %d, y_v= %d",
  393. d_frame->fmt->color,
  394. d_frame->dma_offset.y_h, d_frame->dma_offset.y_v);
  395. /* Prepare the input offset ratios for scaler. */
  396. s_frame->dma_offset.y_h = s_frame->offs_h;
  397. if (!variant->pix_hoff)
  398. s_frame->dma_offset.y_h *= (s_frame->fmt->depth >> 3);
  399. s_frame->dma_offset.y_v = s_frame->offs_v;
  400. s_frame->dma_offset.cb_h = s_frame->offs_h;
  401. s_frame->dma_offset.cb_v = s_frame->offs_v;
  402. s_frame->dma_offset.cr_h = s_frame->offs_h;
  403. s_frame->dma_offset.cr_v = s_frame->offs_v;
  404. if (!variant->pix_hoff && s_frame->fmt->planes_cnt == 3) {
  405. s_frame->dma_offset.cb_h >>= 1;
  406. s_frame->dma_offset.cb_v >>= 1;
  407. s_frame->dma_offset.cr_h >>= 1;
  408. s_frame->dma_offset.cr_v >>= 1;
  409. }
  410. dbg("in offset: color= %d, y_h= %d, y_v= %d",
  411. s_frame->fmt->color, s_frame->dma_offset.y_h,
  412. s_frame->dma_offset.y_v);
  413. fimc_set_yuv_order(ctx);
  414. /* Check against the scaler ratio. */
  415. if (s_frame->height > (SCALER_MAX_VRATIO * d_frame->height) ||
  416. s_frame->width > (SCALER_MAX_HRATIO * d_frame->width)) {
  417. err("out of scaler range");
  418. return -EINVAL;
  419. }
  420. }
  421. /* Input DMA mode is not allowed when the scaler is disabled. */
  422. ctx->scaler.enabled = 1;
  423. if (flags & FIMC_SRC_ADDR) {
  424. buf = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
  425. ret = fimc_prepare_addr(ctx, buf,
  426. V4L2_BUF_TYPE_VIDEO_OUTPUT);
  427. if (ret)
  428. return ret;
  429. }
  430. if (flags & FIMC_DST_ADDR) {
  431. buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
  432. ret = fimc_prepare_addr(ctx, buf,
  433. V4L2_BUF_TYPE_VIDEO_CAPTURE);
  434. }
  435. return ret;
  436. }
  437. static void fimc_dma_run(void *priv)
  438. {
  439. struct fimc_ctx *ctx = priv;
  440. struct fimc_dev *fimc;
  441. unsigned long flags;
  442. u32 ret;
  443. if (WARN(!ctx, "null hardware context"))
  444. return;
  445. fimc = ctx->fimc_dev;
  446. spin_lock_irqsave(&ctx->slock, flags);
  447. set_bit(ST_M2M_PEND, &fimc->state);
  448. ctx->state |= (FIMC_SRC_ADDR | FIMC_DST_ADDR);
  449. ret = fimc_prepare_config(ctx, ctx->state);
  450. if (ret) {
  451. err("general configuration error");
  452. goto dma_unlock;
  453. }
  454. if (fimc->m2m.ctx != ctx)
  455. ctx->state |= FIMC_PARAMS;
  456. fimc_hw_set_input_addr(fimc, &ctx->s_frame.paddr);
  457. if (ctx->state & FIMC_PARAMS) {
  458. fimc_hw_set_input_path(ctx);
  459. fimc_hw_set_in_dma(ctx);
  460. if (fimc_set_scaler_info(ctx)) {
  461. err("scaler configuration error");
  462. goto dma_unlock;
  463. }
  464. fimc_hw_set_prescaler(ctx);
  465. fimc_hw_set_scaler(ctx);
  466. fimc_hw_set_target_format(ctx);
  467. fimc_hw_set_rotation(ctx);
  468. fimc_hw_set_effect(ctx);
  469. }
  470. fimc_hw_set_output_path(ctx);
  471. if (ctx->state & (FIMC_DST_ADDR | FIMC_PARAMS))
  472. fimc_hw_set_output_addr(fimc, &ctx->d_frame.paddr);
  473. if (ctx->state & FIMC_PARAMS)
  474. fimc_hw_set_out_dma(ctx);
  475. if (ctx->scaler.enabled)
  476. fimc_hw_start_scaler(fimc);
  477. fimc_hw_en_capture(ctx);
  478. ctx->state = 0;
  479. fimc_hw_start_in_dma(fimc);
  480. fimc->m2m.ctx = ctx;
  481. dma_unlock:
  482. spin_unlock_irqrestore(&ctx->slock, flags);
  483. }
  484. static void fimc_job_abort(void *priv)
  485. {
  486. /* Nothing done in job_abort. */
  487. }
  488. static void fimc_buf_release(struct videobuf_queue *vq,
  489. struct videobuf_buffer *vb)
  490. {
  491. videobuf_dma_contig_free(vq, vb);
  492. vb->state = VIDEOBUF_NEEDS_INIT;
  493. }
  494. static int fimc_buf_setup(struct videobuf_queue *vq, unsigned int *count,
  495. unsigned int *size)
  496. {
  497. struct fimc_ctx *ctx = vq->priv_data;
  498. struct fimc_frame *frame;
  499. frame = ctx_m2m_get_frame(ctx, vq->type);
  500. if (IS_ERR(frame))
  501. return PTR_ERR(frame);
  502. *size = (frame->width * frame->height * frame->fmt->depth) >> 3;
  503. if (0 == *count)
  504. *count = 1;
  505. return 0;
  506. }
  507. static int fimc_buf_prepare(struct videobuf_queue *vq,
  508. struct videobuf_buffer *vb, enum v4l2_field field)
  509. {
  510. struct fimc_ctx *ctx = vq->priv_data;
  511. struct v4l2_device *v4l2_dev = &ctx->fimc_dev->m2m.v4l2_dev;
  512. struct fimc_frame *frame;
  513. int ret;
  514. frame = ctx_m2m_get_frame(ctx, vq->type);
  515. if (IS_ERR(frame))
  516. return PTR_ERR(frame);
  517. if (vb->baddr) {
  518. if (vb->bsize < frame->size) {
  519. v4l2_err(v4l2_dev,
  520. "User-provided buffer too small (%d < %d)\n",
  521. vb->bsize, frame->size);
  522. WARN_ON(1);
  523. return -EINVAL;
  524. }
  525. } else if (vb->state != VIDEOBUF_NEEDS_INIT
  526. && vb->bsize < frame->size) {
  527. return -EINVAL;
  528. }
  529. vb->width = frame->width;
  530. vb->height = frame->height;
  531. vb->bytesperline = (frame->width * frame->fmt->depth) >> 3;
  532. vb->size = frame->size;
  533. vb->field = field;
  534. if (VIDEOBUF_NEEDS_INIT == vb->state) {
  535. ret = videobuf_iolock(vq, vb, NULL);
  536. if (ret) {
  537. v4l2_err(v4l2_dev, "Iolock failed\n");
  538. fimc_buf_release(vq, vb);
  539. return ret;
  540. }
  541. }
  542. vb->state = VIDEOBUF_PREPARED;
  543. return 0;
  544. }
  545. static void fimc_buf_queue(struct videobuf_queue *vq,
  546. struct videobuf_buffer *vb)
  547. {
  548. struct fimc_ctx *ctx = vq->priv_data;
  549. v4l2_m2m_buf_queue(ctx->m2m_ctx, vq, vb);
  550. }
  551. static struct videobuf_queue_ops fimc_qops = {
  552. .buf_setup = fimc_buf_setup,
  553. .buf_prepare = fimc_buf_prepare,
  554. .buf_queue = fimc_buf_queue,
  555. .buf_release = fimc_buf_release,
  556. };
  557. static int fimc_m2m_querycap(struct file *file, void *priv,
  558. struct v4l2_capability *cap)
  559. {
  560. struct fimc_ctx *ctx = file->private_data;
  561. struct fimc_dev *fimc = ctx->fimc_dev;
  562. strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1);
  563. strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1);
  564. cap->bus_info[0] = 0;
  565. cap->version = KERNEL_VERSION(1, 0, 0);
  566. cap->capabilities = V4L2_CAP_STREAMING |
  567. V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT;
  568. return 0;
  569. }
  570. static int fimc_m2m_enum_fmt(struct file *file, void *priv,
  571. struct v4l2_fmtdesc *f)
  572. {
  573. struct fimc_fmt *fmt;
  574. if (f->index >= ARRAY_SIZE(fimc_formats))
  575. return -EINVAL;
  576. fmt = &fimc_formats[f->index];
  577. strncpy(f->description, fmt->name, sizeof(f->description) - 1);
  578. f->pixelformat = fmt->fourcc;
  579. return 0;
  580. }
  581. static int fimc_m2m_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
  582. {
  583. struct fimc_ctx *ctx = priv;
  584. struct fimc_frame *frame;
  585. frame = ctx_m2m_get_frame(ctx, f->type);
  586. if (IS_ERR(frame))
  587. return PTR_ERR(frame);
  588. f->fmt.pix.width = frame->width;
  589. f->fmt.pix.height = frame->height;
  590. f->fmt.pix.field = V4L2_FIELD_NONE;
  591. f->fmt.pix.pixelformat = frame->fmt->fourcc;
  592. return 0;
  593. }
  594. static struct fimc_fmt *find_format(struct v4l2_format *f)
  595. {
  596. struct fimc_fmt *fmt;
  597. unsigned int i;
  598. for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
  599. fmt = &fimc_formats[i];
  600. if (fmt->fourcc == f->fmt.pix.pixelformat)
  601. break;
  602. }
  603. if (i == ARRAY_SIZE(fimc_formats))
  604. return NULL;
  605. return fmt;
  606. }
  607. static int fimc_m2m_try_fmt(struct file *file, void *priv,
  608. struct v4l2_format *f)
  609. {
  610. struct fimc_fmt *fmt;
  611. u32 max_width, max_height, mod_x, mod_y;
  612. struct fimc_ctx *ctx = priv;
  613. struct fimc_dev *fimc = ctx->fimc_dev;
  614. struct v4l2_pix_format *pix = &f->fmt.pix;
  615. struct samsung_fimc_variant *variant = fimc->variant;
  616. fmt = find_format(f);
  617. if (!fmt) {
  618. v4l2_err(&fimc->m2m.v4l2_dev,
  619. "Fourcc format (0x%X) invalid.\n", pix->pixelformat);
  620. return -EINVAL;
  621. }
  622. if (pix->field == V4L2_FIELD_ANY)
  623. pix->field = V4L2_FIELD_NONE;
  624. else if (V4L2_FIELD_NONE != pix->field)
  625. return -EINVAL;
  626. if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
  627. max_width = variant->scaler_dis_w;
  628. max_height = variant->scaler_dis_w;
  629. mod_x = variant->min_inp_pixsize;
  630. mod_y = variant->min_inp_pixsize;
  631. } else if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
  632. max_width = variant->out_rot_dis_w;
  633. max_height = variant->out_rot_dis_w;
  634. mod_x = variant->min_out_pixsize;
  635. mod_y = variant->min_out_pixsize;
  636. } else {
  637. err("Wrong stream type (%d)", f->type);
  638. return -EINVAL;
  639. }
  640. dbg("max_w= %d, max_h= %d", max_width, max_height);
  641. if (pix->height > max_height)
  642. pix->height = max_height;
  643. if (pix->width > max_width)
  644. pix->width = max_width;
  645. if (tiled_fmt(fmt)) {
  646. mod_x = 64; /* 64x32 tile */
  647. mod_y = 32;
  648. }
  649. dbg("mod_x= 0x%X, mod_y= 0x%X", mod_x, mod_y);
  650. pix->width = (pix->width == 0) ? mod_x : ALIGN(pix->width, mod_x);
  651. pix->height = (pix->height == 0) ? mod_y : ALIGN(pix->height, mod_y);
  652. if (pix->bytesperline == 0 ||
  653. pix->bytesperline * 8 / fmt->depth > pix->width)
  654. pix->bytesperline = (pix->width * fmt->depth) >> 3;
  655. if (pix->sizeimage == 0)
  656. pix->sizeimage = pix->height * pix->bytesperline;
  657. dbg("pix->bytesperline= %d, fmt->depth= %d",
  658. pix->bytesperline, fmt->depth);
  659. return 0;
  660. }
  661. static int fimc_m2m_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
  662. {
  663. struct fimc_ctx *ctx = priv;
  664. struct v4l2_device *v4l2_dev = &ctx->fimc_dev->m2m.v4l2_dev;
  665. struct videobuf_queue *src_vq, *dst_vq;
  666. struct fimc_frame *frame;
  667. struct v4l2_pix_format *pix;
  668. unsigned long flags;
  669. int ret = 0;
  670. BUG_ON(!ctx);
  671. ret = fimc_m2m_try_fmt(file, priv, f);
  672. if (ret)
  673. return ret;
  674. mutex_lock(&ctx->fimc_dev->lock);
  675. src_vq = v4l2_m2m_get_src_vq(ctx->m2m_ctx);
  676. dst_vq = v4l2_m2m_get_dst_vq(ctx->m2m_ctx);
  677. mutex_lock(&src_vq->vb_lock);
  678. mutex_lock(&dst_vq->vb_lock);
  679. if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
  680. if (videobuf_queue_is_busy(src_vq)) {
  681. v4l2_err(v4l2_dev, "%s queue busy\n", __func__);
  682. ret = -EBUSY;
  683. goto s_fmt_out;
  684. }
  685. frame = &ctx->s_frame;
  686. spin_lock_irqsave(&ctx->slock, flags);
  687. ctx->state |= FIMC_SRC_FMT;
  688. spin_unlock_irqrestore(&ctx->slock, flags);
  689. } else if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
  690. if (videobuf_queue_is_busy(dst_vq)) {
  691. v4l2_err(v4l2_dev, "%s queue busy\n", __func__);
  692. ret = -EBUSY;
  693. goto s_fmt_out;
  694. }
  695. frame = &ctx->d_frame;
  696. spin_lock_irqsave(&ctx->slock, flags);
  697. ctx->state |= FIMC_DST_FMT;
  698. spin_unlock_irqrestore(&ctx->slock, flags);
  699. } else {
  700. v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
  701. "Wrong buffer/video queue type (%d)\n", f->type);
  702. ret = -EINVAL;
  703. goto s_fmt_out;
  704. }
  705. pix = &f->fmt.pix;
  706. frame->fmt = find_format(f);
  707. if (!frame->fmt) {
  708. ret = -EINVAL;
  709. goto s_fmt_out;
  710. }
  711. frame->f_width = pix->bytesperline * 8 / frame->fmt->depth;
  712. frame->f_height = pix->sizeimage/pix->bytesperline;
  713. frame->width = pix->width;
  714. frame->height = pix->height;
  715. frame->o_width = pix->width;
  716. frame->o_height = pix->height;
  717. frame->offs_h = 0;
  718. frame->offs_v = 0;
  719. frame->size = (pix->width * pix->height * frame->fmt->depth) >> 3;
  720. src_vq->field = dst_vq->field = pix->field;
  721. spin_lock_irqsave(&ctx->slock, flags);
  722. ctx->state |= FIMC_PARAMS;
  723. spin_unlock_irqrestore(&ctx->slock, flags);
  724. dbg("f_width= %d, f_height= %d", frame->f_width, frame->f_height);
  725. s_fmt_out:
  726. mutex_unlock(&dst_vq->vb_lock);
  727. mutex_unlock(&src_vq->vb_lock);
  728. mutex_unlock(&ctx->fimc_dev->lock);
  729. return ret;
  730. }
  731. static int fimc_m2m_reqbufs(struct file *file, void *priv,
  732. struct v4l2_requestbuffers *reqbufs)
  733. {
  734. struct fimc_ctx *ctx = priv;
  735. return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
  736. }
  737. static int fimc_m2m_querybuf(struct file *file, void *priv,
  738. struct v4l2_buffer *buf)
  739. {
  740. struct fimc_ctx *ctx = priv;
  741. return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
  742. }
  743. static int fimc_m2m_qbuf(struct file *file, void *priv,
  744. struct v4l2_buffer *buf)
  745. {
  746. struct fimc_ctx *ctx = priv;
  747. return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
  748. }
  749. static int fimc_m2m_dqbuf(struct file *file, void *priv,
  750. struct v4l2_buffer *buf)
  751. {
  752. struct fimc_ctx *ctx = priv;
  753. return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
  754. }
  755. static int fimc_m2m_streamon(struct file *file, void *priv,
  756. enum v4l2_buf_type type)
  757. {
  758. struct fimc_ctx *ctx = priv;
  759. return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
  760. }
  761. static int fimc_m2m_streamoff(struct file *file, void *priv,
  762. enum v4l2_buf_type type)
  763. {
  764. struct fimc_ctx *ctx = priv;
  765. return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
  766. }
  767. int fimc_m2m_queryctrl(struct file *file, void *priv,
  768. struct v4l2_queryctrl *qc)
  769. {
  770. struct v4l2_queryctrl *c;
  771. c = get_ctrl(qc->id);
  772. if (!c)
  773. return -EINVAL;
  774. *qc = *c;
  775. return 0;
  776. }
  777. int fimc_m2m_g_ctrl(struct file *file, void *priv,
  778. struct v4l2_control *ctrl)
  779. {
  780. struct fimc_ctx *ctx = priv;
  781. switch (ctrl->id) {
  782. case V4L2_CID_HFLIP:
  783. ctrl->value = (FLIP_X_AXIS & ctx->flip) ? 1 : 0;
  784. break;
  785. case V4L2_CID_VFLIP:
  786. ctrl->value = (FLIP_Y_AXIS & ctx->flip) ? 1 : 0;
  787. break;
  788. case V4L2_CID_ROTATE:
  789. ctrl->value = ctx->rotation;
  790. break;
  791. default:
  792. v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev, "Invalid control\n");
  793. return -EINVAL;
  794. }
  795. dbg("ctrl->value= %d", ctrl->value);
  796. return 0;
  797. }
  798. static int check_ctrl_val(struct fimc_ctx *ctx,
  799. struct v4l2_control *ctrl)
  800. {
  801. struct v4l2_queryctrl *c;
  802. c = get_ctrl(ctrl->id);
  803. if (!c)
  804. return -EINVAL;
  805. if (ctrl->value < c->minimum || ctrl->value > c->maximum
  806. || (c->step != 0 && ctrl->value % c->step != 0)) {
  807. v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
  808. "Invalid control value\n");
  809. return -ERANGE;
  810. }
  811. return 0;
  812. }
  813. int fimc_m2m_s_ctrl(struct file *file, void *priv,
  814. struct v4l2_control *ctrl)
  815. {
  816. struct fimc_ctx *ctx = priv;
  817. struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
  818. unsigned long flags;
  819. int ret = 0;
  820. ret = check_ctrl_val(ctx, ctrl);
  821. if (ret)
  822. return ret;
  823. switch (ctrl->id) {
  824. case V4L2_CID_HFLIP:
  825. if (ctx->rotation != 0)
  826. return 0;
  827. if (ctrl->value)
  828. ctx->flip |= FLIP_X_AXIS;
  829. else
  830. ctx->flip &= ~FLIP_X_AXIS;
  831. break;
  832. case V4L2_CID_VFLIP:
  833. if (ctx->rotation != 0)
  834. return 0;
  835. if (ctrl->value)
  836. ctx->flip |= FLIP_Y_AXIS;
  837. else
  838. ctx->flip &= ~FLIP_Y_AXIS;
  839. break;
  840. case V4L2_CID_ROTATE:
  841. if (ctrl->value == 90 || ctrl->value == 270) {
  842. if (ctx->out_path == FIMC_LCDFIFO &&
  843. !variant->has_inp_rot) {
  844. return -EINVAL;
  845. } else if (ctx->in_path == FIMC_DMA &&
  846. !variant->has_out_rot) {
  847. return -EINVAL;
  848. }
  849. }
  850. ctx->rotation = ctrl->value;
  851. if (ctrl->value == 180)
  852. ctx->flip = FLIP_XY_AXIS;
  853. break;
  854. default:
  855. v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev, "Invalid control\n");
  856. return -EINVAL;
  857. }
  858. spin_lock_irqsave(&ctx->slock, flags);
  859. ctx->state |= FIMC_PARAMS;
  860. spin_unlock_irqrestore(&ctx->slock, flags);
  861. return 0;
  862. }
  863. static int fimc_m2m_cropcap(struct file *file, void *fh,
  864. struct v4l2_cropcap *cr)
  865. {
  866. struct fimc_frame *frame;
  867. struct fimc_ctx *ctx = fh;
  868. frame = ctx_m2m_get_frame(ctx, cr->type);
  869. if (IS_ERR(frame))
  870. return PTR_ERR(frame);
  871. cr->bounds.left = 0;
  872. cr->bounds.top = 0;
  873. cr->bounds.width = frame->f_width;
  874. cr->bounds.height = frame->f_height;
  875. cr->defrect.left = frame->offs_h;
  876. cr->defrect.top = frame->offs_v;
  877. cr->defrect.width = frame->o_width;
  878. cr->defrect.height = frame->o_height;
  879. return 0;
  880. }
  881. static int fimc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
  882. {
  883. struct fimc_frame *frame;
  884. struct fimc_ctx *ctx = file->private_data;
  885. frame = ctx_m2m_get_frame(ctx, cr->type);
  886. if (IS_ERR(frame))
  887. return PTR_ERR(frame);
  888. cr->c.left = frame->offs_h;
  889. cr->c.top = frame->offs_v;
  890. cr->c.width = frame->width;
  891. cr->c.height = frame->height;
  892. return 0;
  893. }
  894. static int fimc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
  895. {
  896. struct fimc_ctx *ctx = file->private_data;
  897. struct fimc_dev *fimc = ctx->fimc_dev;
  898. unsigned long flags;
  899. struct fimc_frame *f;
  900. u32 min_size;
  901. int ret = 0;
  902. if (cr->c.top < 0 || cr->c.left < 0) {
  903. v4l2_err(&fimc->m2m.v4l2_dev,
  904. "doesn't support negative values for top & left\n");
  905. return -EINVAL;
  906. }
  907. if (cr->c.width <= 0 || cr->c.height <= 0) {
  908. v4l2_err(&fimc->m2m.v4l2_dev,
  909. "crop width and height must be greater than 0\n");
  910. return -EINVAL;
  911. }
  912. f = ctx_m2m_get_frame(ctx, cr->type);
  913. if (IS_ERR(f))
  914. return PTR_ERR(f);
  915. /* Adjust to required pixel boundary. */
  916. min_size = (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) ?
  917. fimc->variant->min_inp_pixsize : fimc->variant->min_out_pixsize;
  918. cr->c.width = round_down(cr->c.width, min_size);
  919. cr->c.height = round_down(cr->c.height, min_size);
  920. cr->c.left = round_down(cr->c.left + 1, min_size);
  921. cr->c.top = round_down(cr->c.top + 1, min_size);
  922. if ((cr->c.left + cr->c.width > f->o_width)
  923. || (cr->c.top + cr->c.height > f->o_height)) {
  924. v4l2_err(&fimc->m2m.v4l2_dev, "Error in S_CROP params\n");
  925. return -EINVAL;
  926. }
  927. spin_lock_irqsave(&ctx->slock, flags);
  928. if ((ctx->state & FIMC_SRC_FMT) && (ctx->state & FIMC_DST_FMT)) {
  929. /* Check for the pixel scaling ratio when cropping input img. */
  930. if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
  931. ret = fimc_check_scaler_ratio(&cr->c, &ctx->d_frame);
  932. else if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
  933. ret = fimc_check_scaler_ratio(&cr->c, &ctx->s_frame);
  934. if (ret) {
  935. spin_unlock_irqrestore(&ctx->slock, flags);
  936. v4l2_err(&fimc->m2m.v4l2_dev, "Out of scaler range");
  937. return -EINVAL;
  938. }
  939. }
  940. ctx->state |= FIMC_PARAMS;
  941. spin_unlock_irqrestore(&ctx->slock, flags);
  942. f->offs_h = cr->c.left;
  943. f->offs_v = cr->c.top;
  944. f->width = cr->c.width;
  945. f->height = cr->c.height;
  946. return 0;
  947. }
  948. static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops = {
  949. .vidioc_querycap = fimc_m2m_querycap,
  950. .vidioc_enum_fmt_vid_cap = fimc_m2m_enum_fmt,
  951. .vidioc_enum_fmt_vid_out = fimc_m2m_enum_fmt,
  952. .vidioc_g_fmt_vid_cap = fimc_m2m_g_fmt,
  953. .vidioc_g_fmt_vid_out = fimc_m2m_g_fmt,
  954. .vidioc_try_fmt_vid_cap = fimc_m2m_try_fmt,
  955. .vidioc_try_fmt_vid_out = fimc_m2m_try_fmt,
  956. .vidioc_s_fmt_vid_cap = fimc_m2m_s_fmt,
  957. .vidioc_s_fmt_vid_out = fimc_m2m_s_fmt,
  958. .vidioc_reqbufs = fimc_m2m_reqbufs,
  959. .vidioc_querybuf = fimc_m2m_querybuf,
  960. .vidioc_qbuf = fimc_m2m_qbuf,
  961. .vidioc_dqbuf = fimc_m2m_dqbuf,
  962. .vidioc_streamon = fimc_m2m_streamon,
  963. .vidioc_streamoff = fimc_m2m_streamoff,
  964. .vidioc_queryctrl = fimc_m2m_queryctrl,
  965. .vidioc_g_ctrl = fimc_m2m_g_ctrl,
  966. .vidioc_s_ctrl = fimc_m2m_s_ctrl,
  967. .vidioc_g_crop = fimc_m2m_g_crop,
  968. .vidioc_s_crop = fimc_m2m_s_crop,
  969. .vidioc_cropcap = fimc_m2m_cropcap
  970. };
  971. static void queue_init(void *priv, struct videobuf_queue *vq,
  972. enum v4l2_buf_type type)
  973. {
  974. struct fimc_ctx *ctx = priv;
  975. struct fimc_dev *fimc = ctx->fimc_dev;
  976. videobuf_queue_dma_contig_init(vq, &fimc_qops,
  977. fimc->m2m.v4l2_dev.dev,
  978. &fimc->irqlock, type, V4L2_FIELD_NONE,
  979. sizeof(struct fimc_vid_buffer), priv);
  980. }
  981. static int fimc_m2m_open(struct file *file)
  982. {
  983. struct fimc_dev *fimc = video_drvdata(file);
  984. struct fimc_ctx *ctx = NULL;
  985. int err = 0;
  986. mutex_lock(&fimc->lock);
  987. fimc->m2m.refcnt++;
  988. set_bit(ST_OUTDMA_RUN, &fimc->state);
  989. mutex_unlock(&fimc->lock);
  990. ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
  991. if (!ctx)
  992. return -ENOMEM;
  993. file->private_data = ctx;
  994. ctx->fimc_dev = fimc;
  995. /* default format */
  996. ctx->s_frame.fmt = &fimc_formats[0];
  997. ctx->d_frame.fmt = &fimc_formats[0];
  998. /* per user process device context initialization */
  999. ctx->state = 0;
  1000. ctx->flags = 0;
  1001. ctx->effect.type = S5P_FIMC_EFFECT_ORIGINAL;
  1002. ctx->in_path = FIMC_DMA;
  1003. ctx->out_path = FIMC_DMA;
  1004. spin_lock_init(&ctx->slock);
  1005. ctx->m2m_ctx = v4l2_m2m_ctx_init(ctx, fimc->m2m.m2m_dev, queue_init);
  1006. if (IS_ERR(ctx->m2m_ctx)) {
  1007. err = PTR_ERR(ctx->m2m_ctx);
  1008. kfree(ctx);
  1009. }
  1010. return err;
  1011. }
  1012. static int fimc_m2m_release(struct file *file)
  1013. {
  1014. struct fimc_ctx *ctx = file->private_data;
  1015. struct fimc_dev *fimc = ctx->fimc_dev;
  1016. v4l2_m2m_ctx_release(ctx->m2m_ctx);
  1017. kfree(ctx);
  1018. mutex_lock(&fimc->lock);
  1019. if (--fimc->m2m.refcnt <= 0)
  1020. clear_bit(ST_OUTDMA_RUN, &fimc->state);
  1021. mutex_unlock(&fimc->lock);
  1022. return 0;
  1023. }
  1024. static unsigned int fimc_m2m_poll(struct file *file,
  1025. struct poll_table_struct *wait)
  1026. {
  1027. struct fimc_ctx *ctx = file->private_data;
  1028. return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
  1029. }
  1030. static int fimc_m2m_mmap(struct file *file, struct vm_area_struct *vma)
  1031. {
  1032. struct fimc_ctx *ctx = file->private_data;
  1033. return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
  1034. }
  1035. static const struct v4l2_file_operations fimc_m2m_fops = {
  1036. .owner = THIS_MODULE,
  1037. .open = fimc_m2m_open,
  1038. .release = fimc_m2m_release,
  1039. .poll = fimc_m2m_poll,
  1040. .ioctl = video_ioctl2,
  1041. .mmap = fimc_m2m_mmap,
  1042. };
  1043. static struct v4l2_m2m_ops m2m_ops = {
  1044. .device_run = fimc_dma_run,
  1045. .job_abort = fimc_job_abort,
  1046. };
  1047. static int fimc_register_m2m_device(struct fimc_dev *fimc)
  1048. {
  1049. struct video_device *vfd;
  1050. struct platform_device *pdev;
  1051. struct v4l2_device *v4l2_dev;
  1052. int ret = 0;
  1053. if (!fimc)
  1054. return -ENODEV;
  1055. pdev = fimc->pdev;
  1056. v4l2_dev = &fimc->m2m.v4l2_dev;
  1057. /* set name if it is empty */
  1058. if (!v4l2_dev->name[0])
  1059. snprintf(v4l2_dev->name, sizeof(v4l2_dev->name),
  1060. "%s.m2m", dev_name(&pdev->dev));
  1061. ret = v4l2_device_register(&pdev->dev, v4l2_dev);
  1062. if (ret)
  1063. return ret;;
  1064. vfd = video_device_alloc();
  1065. if (!vfd) {
  1066. v4l2_err(v4l2_dev, "Failed to allocate video device\n");
  1067. goto err_m2m_r1;
  1068. }
  1069. vfd->fops = &fimc_m2m_fops;
  1070. vfd->ioctl_ops = &fimc_m2m_ioctl_ops;
  1071. vfd->minor = -1;
  1072. vfd->release = video_device_release;
  1073. snprintf(vfd->name, sizeof(vfd->name), "%s:m2m", dev_name(&pdev->dev));
  1074. video_set_drvdata(vfd, fimc);
  1075. platform_set_drvdata(pdev, fimc);
  1076. fimc->m2m.vfd = vfd;
  1077. fimc->m2m.m2m_dev = v4l2_m2m_init(&m2m_ops);
  1078. if (IS_ERR(fimc->m2m.m2m_dev)) {
  1079. v4l2_err(v4l2_dev, "failed to initialize v4l2-m2m device\n");
  1080. ret = PTR_ERR(fimc->m2m.m2m_dev);
  1081. goto err_m2m_r2;
  1082. }
  1083. ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
  1084. if (ret) {
  1085. v4l2_err(v4l2_dev,
  1086. "%s(): failed to register video device\n", __func__);
  1087. goto err_m2m_r3;
  1088. }
  1089. v4l2_info(v4l2_dev,
  1090. "FIMC m2m driver registered as /dev/video%d\n", vfd->num);
  1091. return 0;
  1092. err_m2m_r3:
  1093. v4l2_m2m_release(fimc->m2m.m2m_dev);
  1094. err_m2m_r2:
  1095. video_device_release(fimc->m2m.vfd);
  1096. err_m2m_r1:
  1097. v4l2_device_unregister(v4l2_dev);
  1098. return ret;
  1099. }
  1100. static void fimc_unregister_m2m_device(struct fimc_dev *fimc)
  1101. {
  1102. if (fimc) {
  1103. v4l2_m2m_release(fimc->m2m.m2m_dev);
  1104. video_unregister_device(fimc->m2m.vfd);
  1105. video_device_release(fimc->m2m.vfd);
  1106. v4l2_device_unregister(&fimc->m2m.v4l2_dev);
  1107. }
  1108. }
  1109. static void fimc_clk_release(struct fimc_dev *fimc)
  1110. {
  1111. int i;
  1112. for (i = 0; i < NUM_FIMC_CLOCKS; i++) {
  1113. if (fimc->clock[i]) {
  1114. clk_disable(fimc->clock[i]);
  1115. clk_put(fimc->clock[i]);
  1116. }
  1117. }
  1118. }
  1119. static int fimc_clk_get(struct fimc_dev *fimc)
  1120. {
  1121. int i;
  1122. for (i = 0; i < NUM_FIMC_CLOCKS; i++) {
  1123. fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clock_name[i]);
  1124. if (IS_ERR(fimc->clock[i])) {
  1125. dev_err(&fimc->pdev->dev,
  1126. "failed to get fimc clock: %s\n",
  1127. fimc_clock_name[i]);
  1128. return -ENXIO;
  1129. }
  1130. clk_enable(fimc->clock[i]);
  1131. }
  1132. return 0;
  1133. }
  1134. static int fimc_probe(struct platform_device *pdev)
  1135. {
  1136. struct fimc_dev *fimc;
  1137. struct resource *res;
  1138. struct samsung_fimc_driverdata *drv_data;
  1139. int ret = 0;
  1140. dev_dbg(&pdev->dev, "%s():\n", __func__);
  1141. drv_data = (struct samsung_fimc_driverdata *)
  1142. platform_get_device_id(pdev)->driver_data;
  1143. if (pdev->id >= drv_data->devs_cnt) {
  1144. dev_err(&pdev->dev, "Invalid platform device id: %d\n",
  1145. pdev->id);
  1146. return -EINVAL;
  1147. }
  1148. fimc = kzalloc(sizeof(struct fimc_dev), GFP_KERNEL);
  1149. if (!fimc)
  1150. return -ENOMEM;
  1151. fimc->id = pdev->id;
  1152. fimc->variant = drv_data->variant[fimc->id];
  1153. fimc->pdev = pdev;
  1154. fimc->state = ST_IDLE;
  1155. spin_lock_init(&fimc->irqlock);
  1156. spin_lock_init(&fimc->slock);
  1157. mutex_init(&fimc->lock);
  1158. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1159. if (!res) {
  1160. dev_err(&pdev->dev, "failed to find the registers\n");
  1161. ret = -ENOENT;
  1162. goto err_info;
  1163. }
  1164. fimc->regs_res = request_mem_region(res->start, resource_size(res),
  1165. dev_name(&pdev->dev));
  1166. if (!fimc->regs_res) {
  1167. dev_err(&pdev->dev, "failed to obtain register region\n");
  1168. ret = -ENOENT;
  1169. goto err_info;
  1170. }
  1171. fimc->regs = ioremap(res->start, resource_size(res));
  1172. if (!fimc->regs) {
  1173. dev_err(&pdev->dev, "failed to map registers\n");
  1174. ret = -ENXIO;
  1175. goto err_req_region;
  1176. }
  1177. ret = fimc_clk_get(fimc);
  1178. if (ret)
  1179. goto err_regs_unmap;
  1180. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1181. if (!res) {
  1182. dev_err(&pdev->dev, "failed to get IRQ resource\n");
  1183. ret = -ENXIO;
  1184. goto err_clk;
  1185. }
  1186. fimc->irq = res->start;
  1187. fimc_hw_reset(fimc);
  1188. ret = request_irq(fimc->irq, fimc_isr, 0, pdev->name, fimc);
  1189. if (ret) {
  1190. dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
  1191. goto err_clk;
  1192. }
  1193. fimc->work_queue = create_workqueue(dev_name(&fimc->pdev->dev));
  1194. if (!fimc->work_queue) {
  1195. ret = -ENOMEM;
  1196. goto err_irq;
  1197. }
  1198. ret = fimc_register_m2m_device(fimc);
  1199. if (ret)
  1200. goto err_wq;
  1201. fimc_hw_en_lastirq(fimc, true);
  1202. dev_dbg(&pdev->dev, "%s(): fimc-%d registered successfully\n",
  1203. __func__, fimc->id);
  1204. return 0;
  1205. err_wq:
  1206. destroy_workqueue(fimc->work_queue);
  1207. err_irq:
  1208. free_irq(fimc->irq, fimc);
  1209. err_clk:
  1210. fimc_clk_release(fimc);
  1211. err_regs_unmap:
  1212. iounmap(fimc->regs);
  1213. err_req_region:
  1214. release_resource(fimc->regs_res);
  1215. kfree(fimc->regs_res);
  1216. err_info:
  1217. kfree(fimc);
  1218. dev_err(&pdev->dev, "failed to install\n");
  1219. return ret;
  1220. }
  1221. static int __devexit fimc_remove(struct platform_device *pdev)
  1222. {
  1223. struct fimc_dev *fimc =
  1224. (struct fimc_dev *)platform_get_drvdata(pdev);
  1225. v4l2_info(&fimc->m2m.v4l2_dev, "Removing %s\n", pdev->name);
  1226. free_irq(fimc->irq, fimc);
  1227. fimc_hw_reset(fimc);
  1228. fimc_unregister_m2m_device(fimc);
  1229. fimc_clk_release(fimc);
  1230. iounmap(fimc->regs);
  1231. release_resource(fimc->regs_res);
  1232. kfree(fimc->regs_res);
  1233. kfree(fimc);
  1234. return 0;
  1235. }
  1236. static struct samsung_fimc_variant fimc01_variant_s5p = {
  1237. .has_inp_rot = 1,
  1238. .has_out_rot = 1,
  1239. .min_inp_pixsize = 16,
  1240. .min_out_pixsize = 16,
  1241. .scaler_en_w = 3264,
  1242. .scaler_dis_w = 8192,
  1243. .in_rot_en_h = 1920,
  1244. .in_rot_dis_w = 8192,
  1245. .out_rot_en_w = 1920,
  1246. .out_rot_dis_w = 4224,
  1247. };
  1248. static struct samsung_fimc_variant fimc2_variant_s5p = {
  1249. .min_inp_pixsize = 16,
  1250. .min_out_pixsize = 16,
  1251. .scaler_en_w = 4224,
  1252. .scaler_dis_w = 8192,
  1253. .in_rot_en_h = 1920,
  1254. .in_rot_dis_w = 8192,
  1255. .out_rot_en_w = 1920,
  1256. .out_rot_dis_w = 4224,
  1257. };
  1258. static struct samsung_fimc_variant fimc01_variant_s5pv210 = {
  1259. .has_inp_rot = 1,
  1260. .has_out_rot = 1,
  1261. .min_inp_pixsize = 16,
  1262. .min_out_pixsize = 32,
  1263. .scaler_en_w = 4224,
  1264. .scaler_dis_w = 8192,
  1265. .in_rot_en_h = 1920,
  1266. .in_rot_dis_w = 8192,
  1267. .out_rot_en_w = 1920,
  1268. .out_rot_dis_w = 4224,
  1269. };
  1270. static struct samsung_fimc_variant fimc2_variant_s5pv210 = {
  1271. .min_inp_pixsize = 16,
  1272. .min_out_pixsize = 32,
  1273. .scaler_en_w = 1920,
  1274. .scaler_dis_w = 8192,
  1275. .in_rot_en_h = 1280,
  1276. .in_rot_dis_w = 8192,
  1277. .out_rot_en_w = 1280,
  1278. .out_rot_dis_w = 1920,
  1279. };
  1280. static struct samsung_fimc_driverdata fimc_drvdata_s5p = {
  1281. .variant = {
  1282. [0] = &fimc01_variant_s5p,
  1283. [1] = &fimc01_variant_s5p,
  1284. [2] = &fimc2_variant_s5p,
  1285. },
  1286. .devs_cnt = 3
  1287. };
  1288. static struct samsung_fimc_driverdata fimc_drvdata_s5pv210 = {
  1289. .variant = {
  1290. [0] = &fimc01_variant_s5pv210,
  1291. [1] = &fimc01_variant_s5pv210,
  1292. [2] = &fimc2_variant_s5pv210,
  1293. },
  1294. .devs_cnt = 3
  1295. };
  1296. static struct platform_device_id fimc_driver_ids[] = {
  1297. {
  1298. .name = "s5p-fimc",
  1299. .driver_data = (unsigned long)&fimc_drvdata_s5p,
  1300. }, {
  1301. .name = "s5pv210-fimc",
  1302. .driver_data = (unsigned long)&fimc_drvdata_s5pv210,
  1303. },
  1304. {},
  1305. };
  1306. MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
  1307. static struct platform_driver fimc_driver = {
  1308. .probe = fimc_probe,
  1309. .remove = __devexit_p(fimc_remove),
  1310. .id_table = fimc_driver_ids,
  1311. .driver = {
  1312. .name = MODULE_NAME,
  1313. .owner = THIS_MODULE,
  1314. }
  1315. };
  1316. static char banner[] __initdata = KERN_INFO
  1317. "S5PC Camera Interface V4L2 Driver, (c) 2010 Samsung Electronics\n";
  1318. static int __init fimc_init(void)
  1319. {
  1320. u32 ret;
  1321. printk(banner);
  1322. ret = platform_driver_register(&fimc_driver);
  1323. if (ret) {
  1324. printk(KERN_ERR "FIMC platform driver register failed\n");
  1325. return -1;
  1326. }
  1327. return 0;
  1328. }
  1329. static void __exit fimc_exit(void)
  1330. {
  1331. platform_driver_unregister(&fimc_driver);
  1332. }
  1333. module_init(fimc_init);
  1334. module_exit(fimc_exit);
  1335. MODULE_AUTHOR("Sylwester Nawrocki, s.nawrocki@samsung.com");
  1336. MODULE_DESCRIPTION("S3C/S5P FIMC (video postprocessor) driver");
  1337. MODULE_LICENSE("GPL");