intel_display.c 299 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/dmi.h>
  27. #include <linux/module.h>
  28. #include <linux/input.h>
  29. #include <linux/i2c.h>
  30. #include <linux/kernel.h>
  31. #include <linux/slab.h>
  32. #include <linux/vgaarb.h>
  33. #include <drm/drm_edid.h>
  34. #include <drm/drmP.h>
  35. #include "intel_drv.h"
  36. #include <drm/i915_drm.h>
  37. #include "i915_drv.h"
  38. #include "i915_trace.h"
  39. #include <drm/drm_dp_helper.h>
  40. #include <drm/drm_crtc_helper.h>
  41. #include <linux/dma_remapping.h>
  42. bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  43. static void intel_increase_pllclock(struct drm_crtc *crtc);
  44. static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  45. static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  46. struct intel_crtc_config *pipe_config);
  47. static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  48. struct intel_crtc_config *pipe_config);
  49. static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  50. int x, int y, struct drm_framebuffer *old_fb);
  51. typedef struct {
  52. int min, max;
  53. } intel_range_t;
  54. typedef struct {
  55. int dot_limit;
  56. int p2_slow, p2_fast;
  57. } intel_p2_t;
  58. typedef struct intel_limit intel_limit_t;
  59. struct intel_limit {
  60. intel_range_t dot, vco, n, m, m1, m2, p, p1;
  61. intel_p2_t p2;
  62. };
  63. int
  64. intel_pch_rawclk(struct drm_device *dev)
  65. {
  66. struct drm_i915_private *dev_priv = dev->dev_private;
  67. WARN_ON(!HAS_PCH_SPLIT(dev));
  68. return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  69. }
  70. static inline u32 /* units of 100MHz */
  71. intel_fdi_link_freq(struct drm_device *dev)
  72. {
  73. if (IS_GEN5(dev)) {
  74. struct drm_i915_private *dev_priv = dev->dev_private;
  75. return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  76. } else
  77. return 27;
  78. }
  79. static const intel_limit_t intel_limits_i8xx_dac = {
  80. .dot = { .min = 25000, .max = 350000 },
  81. .vco = { .min = 930000, .max = 1400000 },
  82. .n = { .min = 3, .max = 16 },
  83. .m = { .min = 96, .max = 140 },
  84. .m1 = { .min = 18, .max = 26 },
  85. .m2 = { .min = 6, .max = 16 },
  86. .p = { .min = 4, .max = 128 },
  87. .p1 = { .min = 2, .max = 33 },
  88. .p2 = { .dot_limit = 165000,
  89. .p2_slow = 4, .p2_fast = 2 },
  90. };
  91. static const intel_limit_t intel_limits_i8xx_dvo = {
  92. .dot = { .min = 25000, .max = 350000 },
  93. .vco = { .min = 930000, .max = 1400000 },
  94. .n = { .min = 3, .max = 16 },
  95. .m = { .min = 96, .max = 140 },
  96. .m1 = { .min = 18, .max = 26 },
  97. .m2 = { .min = 6, .max = 16 },
  98. .p = { .min = 4, .max = 128 },
  99. .p1 = { .min = 2, .max = 33 },
  100. .p2 = { .dot_limit = 165000,
  101. .p2_slow = 4, .p2_fast = 4 },
  102. };
  103. static const intel_limit_t intel_limits_i8xx_lvds = {
  104. .dot = { .min = 25000, .max = 350000 },
  105. .vco = { .min = 930000, .max = 1400000 },
  106. .n = { .min = 3, .max = 16 },
  107. .m = { .min = 96, .max = 140 },
  108. .m1 = { .min = 18, .max = 26 },
  109. .m2 = { .min = 6, .max = 16 },
  110. .p = { .min = 4, .max = 128 },
  111. .p1 = { .min = 1, .max = 6 },
  112. .p2 = { .dot_limit = 165000,
  113. .p2_slow = 14, .p2_fast = 7 },
  114. };
  115. static const intel_limit_t intel_limits_i9xx_sdvo = {
  116. .dot = { .min = 20000, .max = 400000 },
  117. .vco = { .min = 1400000, .max = 2800000 },
  118. .n = { .min = 1, .max = 6 },
  119. .m = { .min = 70, .max = 120 },
  120. .m1 = { .min = 8, .max = 18 },
  121. .m2 = { .min = 3, .max = 7 },
  122. .p = { .min = 5, .max = 80 },
  123. .p1 = { .min = 1, .max = 8 },
  124. .p2 = { .dot_limit = 200000,
  125. .p2_slow = 10, .p2_fast = 5 },
  126. };
  127. static const intel_limit_t intel_limits_i9xx_lvds = {
  128. .dot = { .min = 20000, .max = 400000 },
  129. .vco = { .min = 1400000, .max = 2800000 },
  130. .n = { .min = 1, .max = 6 },
  131. .m = { .min = 70, .max = 120 },
  132. .m1 = { .min = 8, .max = 18 },
  133. .m2 = { .min = 3, .max = 7 },
  134. .p = { .min = 7, .max = 98 },
  135. .p1 = { .min = 1, .max = 8 },
  136. .p2 = { .dot_limit = 112000,
  137. .p2_slow = 14, .p2_fast = 7 },
  138. };
  139. static const intel_limit_t intel_limits_g4x_sdvo = {
  140. .dot = { .min = 25000, .max = 270000 },
  141. .vco = { .min = 1750000, .max = 3500000},
  142. .n = { .min = 1, .max = 4 },
  143. .m = { .min = 104, .max = 138 },
  144. .m1 = { .min = 17, .max = 23 },
  145. .m2 = { .min = 5, .max = 11 },
  146. .p = { .min = 10, .max = 30 },
  147. .p1 = { .min = 1, .max = 3},
  148. .p2 = { .dot_limit = 270000,
  149. .p2_slow = 10,
  150. .p2_fast = 10
  151. },
  152. };
  153. static const intel_limit_t intel_limits_g4x_hdmi = {
  154. .dot = { .min = 22000, .max = 400000 },
  155. .vco = { .min = 1750000, .max = 3500000},
  156. .n = { .min = 1, .max = 4 },
  157. .m = { .min = 104, .max = 138 },
  158. .m1 = { .min = 16, .max = 23 },
  159. .m2 = { .min = 5, .max = 11 },
  160. .p = { .min = 5, .max = 80 },
  161. .p1 = { .min = 1, .max = 8},
  162. .p2 = { .dot_limit = 165000,
  163. .p2_slow = 10, .p2_fast = 5 },
  164. };
  165. static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
  166. .dot = { .min = 20000, .max = 115000 },
  167. .vco = { .min = 1750000, .max = 3500000 },
  168. .n = { .min = 1, .max = 3 },
  169. .m = { .min = 104, .max = 138 },
  170. .m1 = { .min = 17, .max = 23 },
  171. .m2 = { .min = 5, .max = 11 },
  172. .p = { .min = 28, .max = 112 },
  173. .p1 = { .min = 2, .max = 8 },
  174. .p2 = { .dot_limit = 0,
  175. .p2_slow = 14, .p2_fast = 14
  176. },
  177. };
  178. static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
  179. .dot = { .min = 80000, .max = 224000 },
  180. .vco = { .min = 1750000, .max = 3500000 },
  181. .n = { .min = 1, .max = 3 },
  182. .m = { .min = 104, .max = 138 },
  183. .m1 = { .min = 17, .max = 23 },
  184. .m2 = { .min = 5, .max = 11 },
  185. .p = { .min = 14, .max = 42 },
  186. .p1 = { .min = 2, .max = 6 },
  187. .p2 = { .dot_limit = 0,
  188. .p2_slow = 7, .p2_fast = 7
  189. },
  190. };
  191. static const intel_limit_t intel_limits_pineview_sdvo = {
  192. .dot = { .min = 20000, .max = 400000},
  193. .vco = { .min = 1700000, .max = 3500000 },
  194. /* Pineview's Ncounter is a ring counter */
  195. .n = { .min = 3, .max = 6 },
  196. .m = { .min = 2, .max = 256 },
  197. /* Pineview only has one combined m divider, which we treat as m2. */
  198. .m1 = { .min = 0, .max = 0 },
  199. .m2 = { .min = 0, .max = 254 },
  200. .p = { .min = 5, .max = 80 },
  201. .p1 = { .min = 1, .max = 8 },
  202. .p2 = { .dot_limit = 200000,
  203. .p2_slow = 10, .p2_fast = 5 },
  204. };
  205. static const intel_limit_t intel_limits_pineview_lvds = {
  206. .dot = { .min = 20000, .max = 400000 },
  207. .vco = { .min = 1700000, .max = 3500000 },
  208. .n = { .min = 3, .max = 6 },
  209. .m = { .min = 2, .max = 256 },
  210. .m1 = { .min = 0, .max = 0 },
  211. .m2 = { .min = 0, .max = 254 },
  212. .p = { .min = 7, .max = 112 },
  213. .p1 = { .min = 1, .max = 8 },
  214. .p2 = { .dot_limit = 112000,
  215. .p2_slow = 14, .p2_fast = 14 },
  216. };
  217. /* Ironlake / Sandybridge
  218. *
  219. * We calculate clock using (register_value + 2) for N/M1/M2, so here
  220. * the range value for them is (actual_value - 2).
  221. */
  222. static const intel_limit_t intel_limits_ironlake_dac = {
  223. .dot = { .min = 25000, .max = 350000 },
  224. .vco = { .min = 1760000, .max = 3510000 },
  225. .n = { .min = 1, .max = 5 },
  226. .m = { .min = 79, .max = 127 },
  227. .m1 = { .min = 12, .max = 22 },
  228. .m2 = { .min = 5, .max = 9 },
  229. .p = { .min = 5, .max = 80 },
  230. .p1 = { .min = 1, .max = 8 },
  231. .p2 = { .dot_limit = 225000,
  232. .p2_slow = 10, .p2_fast = 5 },
  233. };
  234. static const intel_limit_t intel_limits_ironlake_single_lvds = {
  235. .dot = { .min = 25000, .max = 350000 },
  236. .vco = { .min = 1760000, .max = 3510000 },
  237. .n = { .min = 1, .max = 3 },
  238. .m = { .min = 79, .max = 118 },
  239. .m1 = { .min = 12, .max = 22 },
  240. .m2 = { .min = 5, .max = 9 },
  241. .p = { .min = 28, .max = 112 },
  242. .p1 = { .min = 2, .max = 8 },
  243. .p2 = { .dot_limit = 225000,
  244. .p2_slow = 14, .p2_fast = 14 },
  245. };
  246. static const intel_limit_t intel_limits_ironlake_dual_lvds = {
  247. .dot = { .min = 25000, .max = 350000 },
  248. .vco = { .min = 1760000, .max = 3510000 },
  249. .n = { .min = 1, .max = 3 },
  250. .m = { .min = 79, .max = 127 },
  251. .m1 = { .min = 12, .max = 22 },
  252. .m2 = { .min = 5, .max = 9 },
  253. .p = { .min = 14, .max = 56 },
  254. .p1 = { .min = 2, .max = 8 },
  255. .p2 = { .dot_limit = 225000,
  256. .p2_slow = 7, .p2_fast = 7 },
  257. };
  258. /* LVDS 100mhz refclk limits. */
  259. static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
  260. .dot = { .min = 25000, .max = 350000 },
  261. .vco = { .min = 1760000, .max = 3510000 },
  262. .n = { .min = 1, .max = 2 },
  263. .m = { .min = 79, .max = 126 },
  264. .m1 = { .min = 12, .max = 22 },
  265. .m2 = { .min = 5, .max = 9 },
  266. .p = { .min = 28, .max = 112 },
  267. .p1 = { .min = 2, .max = 8 },
  268. .p2 = { .dot_limit = 225000,
  269. .p2_slow = 14, .p2_fast = 14 },
  270. };
  271. static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
  272. .dot = { .min = 25000, .max = 350000 },
  273. .vco = { .min = 1760000, .max = 3510000 },
  274. .n = { .min = 1, .max = 3 },
  275. .m = { .min = 79, .max = 126 },
  276. .m1 = { .min = 12, .max = 22 },
  277. .m2 = { .min = 5, .max = 9 },
  278. .p = { .min = 14, .max = 42 },
  279. .p1 = { .min = 2, .max = 6 },
  280. .p2 = { .dot_limit = 225000,
  281. .p2_slow = 7, .p2_fast = 7 },
  282. };
  283. static const intel_limit_t intel_limits_vlv_dac = {
  284. .dot = { .min = 25000, .max = 270000 },
  285. .vco = { .min = 4000000, .max = 6000000 },
  286. .n = { .min = 1, .max = 7 },
  287. .m = { .min = 22, .max = 450 }, /* guess */
  288. .m1 = { .min = 2, .max = 3 },
  289. .m2 = { .min = 11, .max = 156 },
  290. .p = { .min = 10, .max = 30 },
  291. .p1 = { .min = 1, .max = 3 },
  292. .p2 = { .dot_limit = 270000,
  293. .p2_slow = 2, .p2_fast = 20 },
  294. };
  295. static const intel_limit_t intel_limits_vlv_hdmi = {
  296. .dot = { .min = 25000, .max = 270000 },
  297. .vco = { .min = 4000000, .max = 6000000 },
  298. .n = { .min = 1, .max = 7 },
  299. .m = { .min = 60, .max = 300 }, /* guess */
  300. .m1 = { .min = 2, .max = 3 },
  301. .m2 = { .min = 11, .max = 156 },
  302. .p = { .min = 10, .max = 30 },
  303. .p1 = { .min = 2, .max = 3 },
  304. .p2 = { .dot_limit = 270000,
  305. .p2_slow = 2, .p2_fast = 20 },
  306. };
  307. static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
  308. int refclk)
  309. {
  310. struct drm_device *dev = crtc->dev;
  311. const intel_limit_t *limit;
  312. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  313. if (intel_is_dual_link_lvds(dev)) {
  314. if (refclk == 100000)
  315. limit = &intel_limits_ironlake_dual_lvds_100m;
  316. else
  317. limit = &intel_limits_ironlake_dual_lvds;
  318. } else {
  319. if (refclk == 100000)
  320. limit = &intel_limits_ironlake_single_lvds_100m;
  321. else
  322. limit = &intel_limits_ironlake_single_lvds;
  323. }
  324. } else
  325. limit = &intel_limits_ironlake_dac;
  326. return limit;
  327. }
  328. static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
  329. {
  330. struct drm_device *dev = crtc->dev;
  331. const intel_limit_t *limit;
  332. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  333. if (intel_is_dual_link_lvds(dev))
  334. limit = &intel_limits_g4x_dual_channel_lvds;
  335. else
  336. limit = &intel_limits_g4x_single_channel_lvds;
  337. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
  338. intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  339. limit = &intel_limits_g4x_hdmi;
  340. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
  341. limit = &intel_limits_g4x_sdvo;
  342. } else /* The option is for other outputs */
  343. limit = &intel_limits_i9xx_sdvo;
  344. return limit;
  345. }
  346. static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
  347. {
  348. struct drm_device *dev = crtc->dev;
  349. const intel_limit_t *limit;
  350. if (HAS_PCH_SPLIT(dev))
  351. limit = intel_ironlake_limit(crtc, refclk);
  352. else if (IS_G4X(dev)) {
  353. limit = intel_g4x_limit(crtc);
  354. } else if (IS_PINEVIEW(dev)) {
  355. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  356. limit = &intel_limits_pineview_lvds;
  357. else
  358. limit = &intel_limits_pineview_sdvo;
  359. } else if (IS_VALLEYVIEW(dev)) {
  360. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
  361. limit = &intel_limits_vlv_dac;
  362. else
  363. limit = &intel_limits_vlv_hdmi;
  364. } else if (!IS_GEN2(dev)) {
  365. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  366. limit = &intel_limits_i9xx_lvds;
  367. else
  368. limit = &intel_limits_i9xx_sdvo;
  369. } else {
  370. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  371. limit = &intel_limits_i8xx_lvds;
  372. else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
  373. limit = &intel_limits_i8xx_dvo;
  374. else
  375. limit = &intel_limits_i8xx_dac;
  376. }
  377. return limit;
  378. }
  379. /* m1 is reserved as 0 in Pineview, n is a ring counter */
  380. static void pineview_clock(int refclk, intel_clock_t *clock)
  381. {
  382. clock->m = clock->m2 + 2;
  383. clock->p = clock->p1 * clock->p2;
  384. clock->vco = refclk * clock->m / clock->n;
  385. clock->dot = clock->vco / clock->p;
  386. }
  387. static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
  388. {
  389. return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
  390. }
  391. static void i9xx_clock(int refclk, intel_clock_t *clock)
  392. {
  393. clock->m = i9xx_dpll_compute_m(clock);
  394. clock->p = clock->p1 * clock->p2;
  395. clock->vco = refclk * clock->m / (clock->n + 2);
  396. clock->dot = clock->vco / clock->p;
  397. }
  398. /**
  399. * Returns whether any output on the specified pipe is of the specified type
  400. */
  401. bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
  402. {
  403. struct drm_device *dev = crtc->dev;
  404. struct intel_encoder *encoder;
  405. for_each_encoder_on_crtc(dev, crtc, encoder)
  406. if (encoder->type == type)
  407. return true;
  408. return false;
  409. }
  410. #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
  411. /**
  412. * Returns whether the given set of divisors are valid for a given refclk with
  413. * the given connectors.
  414. */
  415. static bool intel_PLL_is_valid(struct drm_device *dev,
  416. const intel_limit_t *limit,
  417. const intel_clock_t *clock)
  418. {
  419. if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
  420. INTELPllInvalid("p1 out of range\n");
  421. if (clock->p < limit->p.min || limit->p.max < clock->p)
  422. INTELPllInvalid("p out of range\n");
  423. if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
  424. INTELPllInvalid("m2 out of range\n");
  425. if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
  426. INTELPllInvalid("m1 out of range\n");
  427. if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
  428. INTELPllInvalid("m1 <= m2\n");
  429. if (clock->m < limit->m.min || limit->m.max < clock->m)
  430. INTELPllInvalid("m out of range\n");
  431. if (clock->n < limit->n.min || limit->n.max < clock->n)
  432. INTELPllInvalid("n out of range\n");
  433. if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
  434. INTELPllInvalid("vco out of range\n");
  435. /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
  436. * connector, etc., rather than just a single range.
  437. */
  438. if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
  439. INTELPllInvalid("dot out of range\n");
  440. return true;
  441. }
  442. static bool
  443. i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
  444. int target, int refclk, intel_clock_t *match_clock,
  445. intel_clock_t *best_clock)
  446. {
  447. struct drm_device *dev = crtc->dev;
  448. intel_clock_t clock;
  449. int err = target;
  450. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  451. /*
  452. * For LVDS just rely on its current settings for dual-channel.
  453. * We haven't figured out how to reliably set up different
  454. * single/dual channel state, if we even can.
  455. */
  456. if (intel_is_dual_link_lvds(dev))
  457. clock.p2 = limit->p2.p2_fast;
  458. else
  459. clock.p2 = limit->p2.p2_slow;
  460. } else {
  461. if (target < limit->p2.dot_limit)
  462. clock.p2 = limit->p2.p2_slow;
  463. else
  464. clock.p2 = limit->p2.p2_fast;
  465. }
  466. memset(best_clock, 0, sizeof(*best_clock));
  467. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  468. clock.m1++) {
  469. for (clock.m2 = limit->m2.min;
  470. clock.m2 <= limit->m2.max; clock.m2++) {
  471. if (clock.m2 >= clock.m1)
  472. break;
  473. for (clock.n = limit->n.min;
  474. clock.n <= limit->n.max; clock.n++) {
  475. for (clock.p1 = limit->p1.min;
  476. clock.p1 <= limit->p1.max; clock.p1++) {
  477. int this_err;
  478. i9xx_clock(refclk, &clock);
  479. if (!intel_PLL_is_valid(dev, limit,
  480. &clock))
  481. continue;
  482. if (match_clock &&
  483. clock.p != match_clock->p)
  484. continue;
  485. this_err = abs(clock.dot - target);
  486. if (this_err < err) {
  487. *best_clock = clock;
  488. err = this_err;
  489. }
  490. }
  491. }
  492. }
  493. }
  494. return (err != target);
  495. }
  496. static bool
  497. pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
  498. int target, int refclk, intel_clock_t *match_clock,
  499. intel_clock_t *best_clock)
  500. {
  501. struct drm_device *dev = crtc->dev;
  502. intel_clock_t clock;
  503. int err = target;
  504. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  505. /*
  506. * For LVDS just rely on its current settings for dual-channel.
  507. * We haven't figured out how to reliably set up different
  508. * single/dual channel state, if we even can.
  509. */
  510. if (intel_is_dual_link_lvds(dev))
  511. clock.p2 = limit->p2.p2_fast;
  512. else
  513. clock.p2 = limit->p2.p2_slow;
  514. } else {
  515. if (target < limit->p2.dot_limit)
  516. clock.p2 = limit->p2.p2_slow;
  517. else
  518. clock.p2 = limit->p2.p2_fast;
  519. }
  520. memset(best_clock, 0, sizeof(*best_clock));
  521. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  522. clock.m1++) {
  523. for (clock.m2 = limit->m2.min;
  524. clock.m2 <= limit->m2.max; clock.m2++) {
  525. for (clock.n = limit->n.min;
  526. clock.n <= limit->n.max; clock.n++) {
  527. for (clock.p1 = limit->p1.min;
  528. clock.p1 <= limit->p1.max; clock.p1++) {
  529. int this_err;
  530. pineview_clock(refclk, &clock);
  531. if (!intel_PLL_is_valid(dev, limit,
  532. &clock))
  533. continue;
  534. if (match_clock &&
  535. clock.p != match_clock->p)
  536. continue;
  537. this_err = abs(clock.dot - target);
  538. if (this_err < err) {
  539. *best_clock = clock;
  540. err = this_err;
  541. }
  542. }
  543. }
  544. }
  545. }
  546. return (err != target);
  547. }
  548. static bool
  549. g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
  550. int target, int refclk, intel_clock_t *match_clock,
  551. intel_clock_t *best_clock)
  552. {
  553. struct drm_device *dev = crtc->dev;
  554. intel_clock_t clock;
  555. int max_n;
  556. bool found;
  557. /* approximately equals target * 0.00585 */
  558. int err_most = (target >> 8) + (target >> 9);
  559. found = false;
  560. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  561. if (intel_is_dual_link_lvds(dev))
  562. clock.p2 = limit->p2.p2_fast;
  563. else
  564. clock.p2 = limit->p2.p2_slow;
  565. } else {
  566. if (target < limit->p2.dot_limit)
  567. clock.p2 = limit->p2.p2_slow;
  568. else
  569. clock.p2 = limit->p2.p2_fast;
  570. }
  571. memset(best_clock, 0, sizeof(*best_clock));
  572. max_n = limit->n.max;
  573. /* based on hardware requirement, prefer smaller n to precision */
  574. for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  575. /* based on hardware requirement, prefere larger m1,m2 */
  576. for (clock.m1 = limit->m1.max;
  577. clock.m1 >= limit->m1.min; clock.m1--) {
  578. for (clock.m2 = limit->m2.max;
  579. clock.m2 >= limit->m2.min; clock.m2--) {
  580. for (clock.p1 = limit->p1.max;
  581. clock.p1 >= limit->p1.min; clock.p1--) {
  582. int this_err;
  583. i9xx_clock(refclk, &clock);
  584. if (!intel_PLL_is_valid(dev, limit,
  585. &clock))
  586. continue;
  587. this_err = abs(clock.dot - target);
  588. if (this_err < err_most) {
  589. *best_clock = clock;
  590. err_most = this_err;
  591. max_n = clock.n;
  592. found = true;
  593. }
  594. }
  595. }
  596. }
  597. }
  598. return found;
  599. }
  600. static bool
  601. vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
  602. int target, int refclk, intel_clock_t *match_clock,
  603. intel_clock_t *best_clock)
  604. {
  605. u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
  606. u32 m, n, fastclk;
  607. u32 updrate, minupdate, p;
  608. unsigned long bestppm, ppm, absppm;
  609. int dotclk, flag;
  610. flag = 0;
  611. dotclk = target * 1000;
  612. bestppm = 1000000;
  613. ppm = absppm = 0;
  614. fastclk = dotclk / (2*100);
  615. updrate = 0;
  616. minupdate = 19200;
  617. n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
  618. bestm1 = bestm2 = bestp1 = bestp2 = 0;
  619. /* based on hardware requirement, prefer smaller n to precision */
  620. for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
  621. updrate = refclk / n;
  622. for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
  623. for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
  624. if (p2 > 10)
  625. p2 = p2 - 1;
  626. p = p1 * p2;
  627. /* based on hardware requirement, prefer bigger m1,m2 values */
  628. for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
  629. m2 = (((2*(fastclk * p * n / m1 )) +
  630. refclk) / (2*refclk));
  631. m = m1 * m2;
  632. vco = updrate * m;
  633. if (vco >= limit->vco.min && vco < limit->vco.max) {
  634. ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
  635. absppm = (ppm > 0) ? ppm : (-ppm);
  636. if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
  637. bestppm = 0;
  638. flag = 1;
  639. }
  640. if (absppm < bestppm - 10) {
  641. bestppm = absppm;
  642. flag = 1;
  643. }
  644. if (flag) {
  645. bestn = n;
  646. bestm1 = m1;
  647. bestm2 = m2;
  648. bestp1 = p1;
  649. bestp2 = p2;
  650. flag = 0;
  651. }
  652. }
  653. }
  654. }
  655. }
  656. }
  657. best_clock->n = bestn;
  658. best_clock->m1 = bestm1;
  659. best_clock->m2 = bestm2;
  660. best_clock->p1 = bestp1;
  661. best_clock->p2 = bestp2;
  662. return true;
  663. }
  664. bool intel_crtc_active(struct drm_crtc *crtc)
  665. {
  666. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  667. /* Be paranoid as we can arrive here with only partial
  668. * state retrieved from the hardware during setup.
  669. *
  670. * We can ditch the adjusted_mode.clock check as soon
  671. * as Haswell has gained clock readout/fastboot support.
  672. *
  673. * We can ditch the crtc->fb check as soon as we can
  674. * properly reconstruct framebuffers.
  675. */
  676. return intel_crtc->active && crtc->fb &&
  677. intel_crtc->config.adjusted_mode.clock;
  678. }
  679. enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
  680. enum pipe pipe)
  681. {
  682. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  683. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  684. return intel_crtc->config.cpu_transcoder;
  685. }
  686. static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
  687. {
  688. struct drm_i915_private *dev_priv = dev->dev_private;
  689. u32 frame, frame_reg = PIPEFRAME(pipe);
  690. frame = I915_READ(frame_reg);
  691. if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
  692. DRM_DEBUG_KMS("vblank wait timed out\n");
  693. }
  694. /**
  695. * intel_wait_for_vblank - wait for vblank on a given pipe
  696. * @dev: drm device
  697. * @pipe: pipe to wait for
  698. *
  699. * Wait for vblank to occur on a given pipe. Needed for various bits of
  700. * mode setting code.
  701. */
  702. void intel_wait_for_vblank(struct drm_device *dev, int pipe)
  703. {
  704. struct drm_i915_private *dev_priv = dev->dev_private;
  705. int pipestat_reg = PIPESTAT(pipe);
  706. if (INTEL_INFO(dev)->gen >= 5) {
  707. ironlake_wait_for_vblank(dev, pipe);
  708. return;
  709. }
  710. /* Clear existing vblank status. Note this will clear any other
  711. * sticky status fields as well.
  712. *
  713. * This races with i915_driver_irq_handler() with the result
  714. * that either function could miss a vblank event. Here it is not
  715. * fatal, as we will either wait upon the next vblank interrupt or
  716. * timeout. Generally speaking intel_wait_for_vblank() is only
  717. * called during modeset at which time the GPU should be idle and
  718. * should *not* be performing page flips and thus not waiting on
  719. * vblanks...
  720. * Currently, the result of us stealing a vblank from the irq
  721. * handler is that a single frame will be skipped during swapbuffers.
  722. */
  723. I915_WRITE(pipestat_reg,
  724. I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
  725. /* Wait for vblank interrupt bit to set */
  726. if (wait_for(I915_READ(pipestat_reg) &
  727. PIPE_VBLANK_INTERRUPT_STATUS,
  728. 50))
  729. DRM_DEBUG_KMS("vblank wait timed out\n");
  730. }
  731. /*
  732. * intel_wait_for_pipe_off - wait for pipe to turn off
  733. * @dev: drm device
  734. * @pipe: pipe to wait for
  735. *
  736. * After disabling a pipe, we can't wait for vblank in the usual way,
  737. * spinning on the vblank interrupt status bit, since we won't actually
  738. * see an interrupt when the pipe is disabled.
  739. *
  740. * On Gen4 and above:
  741. * wait for the pipe register state bit to turn off
  742. *
  743. * Otherwise:
  744. * wait for the display line value to settle (it usually
  745. * ends up stopping at the start of the next frame).
  746. *
  747. */
  748. void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
  749. {
  750. struct drm_i915_private *dev_priv = dev->dev_private;
  751. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  752. pipe);
  753. if (INTEL_INFO(dev)->gen >= 4) {
  754. int reg = PIPECONF(cpu_transcoder);
  755. /* Wait for the Pipe State to go off */
  756. if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
  757. 100))
  758. WARN(1, "pipe_off wait timed out\n");
  759. } else {
  760. u32 last_line, line_mask;
  761. int reg = PIPEDSL(pipe);
  762. unsigned long timeout = jiffies + msecs_to_jiffies(100);
  763. if (IS_GEN2(dev))
  764. line_mask = DSL_LINEMASK_GEN2;
  765. else
  766. line_mask = DSL_LINEMASK_GEN3;
  767. /* Wait for the display line to settle */
  768. do {
  769. last_line = I915_READ(reg) & line_mask;
  770. mdelay(5);
  771. } while (((I915_READ(reg) & line_mask) != last_line) &&
  772. time_after(timeout, jiffies));
  773. if (time_after(jiffies, timeout))
  774. WARN(1, "pipe_off wait timed out\n");
  775. }
  776. }
  777. /*
  778. * ibx_digital_port_connected - is the specified port connected?
  779. * @dev_priv: i915 private structure
  780. * @port: the port to test
  781. *
  782. * Returns true if @port is connected, false otherwise.
  783. */
  784. bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
  785. struct intel_digital_port *port)
  786. {
  787. u32 bit;
  788. if (HAS_PCH_IBX(dev_priv->dev)) {
  789. switch(port->port) {
  790. case PORT_B:
  791. bit = SDE_PORTB_HOTPLUG;
  792. break;
  793. case PORT_C:
  794. bit = SDE_PORTC_HOTPLUG;
  795. break;
  796. case PORT_D:
  797. bit = SDE_PORTD_HOTPLUG;
  798. break;
  799. default:
  800. return true;
  801. }
  802. } else {
  803. switch(port->port) {
  804. case PORT_B:
  805. bit = SDE_PORTB_HOTPLUG_CPT;
  806. break;
  807. case PORT_C:
  808. bit = SDE_PORTC_HOTPLUG_CPT;
  809. break;
  810. case PORT_D:
  811. bit = SDE_PORTD_HOTPLUG_CPT;
  812. break;
  813. default:
  814. return true;
  815. }
  816. }
  817. return I915_READ(SDEISR) & bit;
  818. }
  819. static const char *state_string(bool enabled)
  820. {
  821. return enabled ? "on" : "off";
  822. }
  823. /* Only for pre-ILK configs */
  824. void assert_pll(struct drm_i915_private *dev_priv,
  825. enum pipe pipe, bool state)
  826. {
  827. int reg;
  828. u32 val;
  829. bool cur_state;
  830. reg = DPLL(pipe);
  831. val = I915_READ(reg);
  832. cur_state = !!(val & DPLL_VCO_ENABLE);
  833. WARN(cur_state != state,
  834. "PLL state assertion failure (expected %s, current %s)\n",
  835. state_string(state), state_string(cur_state));
  836. }
  837. /* XXX: the dsi pll is shared between MIPI DSI ports */
  838. static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
  839. {
  840. u32 val;
  841. bool cur_state;
  842. mutex_lock(&dev_priv->dpio_lock);
  843. val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
  844. mutex_unlock(&dev_priv->dpio_lock);
  845. cur_state = val & DSI_PLL_VCO_EN;
  846. WARN(cur_state != state,
  847. "DSI PLL state assertion failure (expected %s, current %s)\n",
  848. state_string(state), state_string(cur_state));
  849. }
  850. #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
  851. #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
  852. struct intel_shared_dpll *
  853. intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
  854. {
  855. struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  856. if (crtc->config.shared_dpll < 0)
  857. return NULL;
  858. return &dev_priv->shared_dplls[crtc->config.shared_dpll];
  859. }
  860. /* For ILK+ */
  861. void assert_shared_dpll(struct drm_i915_private *dev_priv,
  862. struct intel_shared_dpll *pll,
  863. bool state)
  864. {
  865. bool cur_state;
  866. struct intel_dpll_hw_state hw_state;
  867. if (HAS_PCH_LPT(dev_priv->dev)) {
  868. DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
  869. return;
  870. }
  871. if (WARN (!pll,
  872. "asserting DPLL %s with no DPLL\n", state_string(state)))
  873. return;
  874. cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
  875. WARN(cur_state != state,
  876. "%s assertion failure (expected %s, current %s)\n",
  877. pll->name, state_string(state), state_string(cur_state));
  878. }
  879. static void assert_fdi_tx(struct drm_i915_private *dev_priv,
  880. enum pipe pipe, bool state)
  881. {
  882. int reg;
  883. u32 val;
  884. bool cur_state;
  885. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  886. pipe);
  887. if (HAS_DDI(dev_priv->dev)) {
  888. /* DDI does not have a specific FDI_TX register */
  889. reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
  890. val = I915_READ(reg);
  891. cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
  892. } else {
  893. reg = FDI_TX_CTL(pipe);
  894. val = I915_READ(reg);
  895. cur_state = !!(val & FDI_TX_ENABLE);
  896. }
  897. WARN(cur_state != state,
  898. "FDI TX state assertion failure (expected %s, current %s)\n",
  899. state_string(state), state_string(cur_state));
  900. }
  901. #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
  902. #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
  903. static void assert_fdi_rx(struct drm_i915_private *dev_priv,
  904. enum pipe pipe, bool state)
  905. {
  906. int reg;
  907. u32 val;
  908. bool cur_state;
  909. reg = FDI_RX_CTL(pipe);
  910. val = I915_READ(reg);
  911. cur_state = !!(val & FDI_RX_ENABLE);
  912. WARN(cur_state != state,
  913. "FDI RX state assertion failure (expected %s, current %s)\n",
  914. state_string(state), state_string(cur_state));
  915. }
  916. #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
  917. #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
  918. static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
  919. enum pipe pipe)
  920. {
  921. int reg;
  922. u32 val;
  923. /* ILK FDI PLL is always enabled */
  924. if (dev_priv->info->gen == 5)
  925. return;
  926. /* On Haswell, DDI ports are responsible for the FDI PLL setup */
  927. if (HAS_DDI(dev_priv->dev))
  928. return;
  929. reg = FDI_TX_CTL(pipe);
  930. val = I915_READ(reg);
  931. WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
  932. }
  933. void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
  934. enum pipe pipe, bool state)
  935. {
  936. int reg;
  937. u32 val;
  938. bool cur_state;
  939. reg = FDI_RX_CTL(pipe);
  940. val = I915_READ(reg);
  941. cur_state = !!(val & FDI_RX_PLL_ENABLE);
  942. WARN(cur_state != state,
  943. "FDI RX PLL assertion failure (expected %s, current %s)\n",
  944. state_string(state), state_string(cur_state));
  945. }
  946. static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
  947. enum pipe pipe)
  948. {
  949. int pp_reg, lvds_reg;
  950. u32 val;
  951. enum pipe panel_pipe = PIPE_A;
  952. bool locked = true;
  953. if (HAS_PCH_SPLIT(dev_priv->dev)) {
  954. pp_reg = PCH_PP_CONTROL;
  955. lvds_reg = PCH_LVDS;
  956. } else {
  957. pp_reg = PP_CONTROL;
  958. lvds_reg = LVDS;
  959. }
  960. val = I915_READ(pp_reg);
  961. if (!(val & PANEL_POWER_ON) ||
  962. ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
  963. locked = false;
  964. if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
  965. panel_pipe = PIPE_B;
  966. WARN(panel_pipe == pipe && locked,
  967. "panel assertion failure, pipe %c regs locked\n",
  968. pipe_name(pipe));
  969. }
  970. static void assert_cursor(struct drm_i915_private *dev_priv,
  971. enum pipe pipe, bool state)
  972. {
  973. struct drm_device *dev = dev_priv->dev;
  974. bool cur_state;
  975. if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
  976. cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
  977. else if (IS_845G(dev) || IS_I865G(dev))
  978. cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
  979. else
  980. cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
  981. WARN(cur_state != state,
  982. "cursor on pipe %c assertion failure (expected %s, current %s)\n",
  983. pipe_name(pipe), state_string(state), state_string(cur_state));
  984. }
  985. #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
  986. #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
  987. void assert_pipe(struct drm_i915_private *dev_priv,
  988. enum pipe pipe, bool state)
  989. {
  990. int reg;
  991. u32 val;
  992. bool cur_state;
  993. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  994. pipe);
  995. /* if we need the pipe A quirk it must be always on */
  996. if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
  997. state = true;
  998. if (!intel_display_power_enabled(dev_priv->dev,
  999. POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
  1000. cur_state = false;
  1001. } else {
  1002. reg = PIPECONF(cpu_transcoder);
  1003. val = I915_READ(reg);
  1004. cur_state = !!(val & PIPECONF_ENABLE);
  1005. }
  1006. WARN(cur_state != state,
  1007. "pipe %c assertion failure (expected %s, current %s)\n",
  1008. pipe_name(pipe), state_string(state), state_string(cur_state));
  1009. }
  1010. static void assert_plane(struct drm_i915_private *dev_priv,
  1011. enum plane plane, bool state)
  1012. {
  1013. int reg;
  1014. u32 val;
  1015. bool cur_state;
  1016. reg = DSPCNTR(plane);
  1017. val = I915_READ(reg);
  1018. cur_state = !!(val & DISPLAY_PLANE_ENABLE);
  1019. WARN(cur_state != state,
  1020. "plane %c assertion failure (expected %s, current %s)\n",
  1021. plane_name(plane), state_string(state), state_string(cur_state));
  1022. }
  1023. #define assert_plane_enabled(d, p) assert_plane(d, p, true)
  1024. #define assert_plane_disabled(d, p) assert_plane(d, p, false)
  1025. static void assert_planes_disabled(struct drm_i915_private *dev_priv,
  1026. enum pipe pipe)
  1027. {
  1028. struct drm_device *dev = dev_priv->dev;
  1029. int reg, i;
  1030. u32 val;
  1031. int cur_pipe;
  1032. /* Primary planes are fixed to pipes on gen4+ */
  1033. if (INTEL_INFO(dev)->gen >= 4) {
  1034. reg = DSPCNTR(pipe);
  1035. val = I915_READ(reg);
  1036. WARN((val & DISPLAY_PLANE_ENABLE),
  1037. "plane %c assertion failure, should be disabled but not\n",
  1038. plane_name(pipe));
  1039. return;
  1040. }
  1041. /* Need to check both planes against the pipe */
  1042. for_each_pipe(i) {
  1043. reg = DSPCNTR(i);
  1044. val = I915_READ(reg);
  1045. cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
  1046. DISPPLANE_SEL_PIPE_SHIFT;
  1047. WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
  1048. "plane %c assertion failure, should be off on pipe %c but is still active\n",
  1049. plane_name(i), pipe_name(pipe));
  1050. }
  1051. }
  1052. static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
  1053. enum pipe pipe)
  1054. {
  1055. struct drm_device *dev = dev_priv->dev;
  1056. int reg, i;
  1057. u32 val;
  1058. if (IS_VALLEYVIEW(dev)) {
  1059. for (i = 0; i < dev_priv->num_plane; i++) {
  1060. reg = SPCNTR(pipe, i);
  1061. val = I915_READ(reg);
  1062. WARN((val & SP_ENABLE),
  1063. "sprite %c assertion failure, should be off on pipe %c but is still active\n",
  1064. sprite_name(pipe, i), pipe_name(pipe));
  1065. }
  1066. } else if (INTEL_INFO(dev)->gen >= 7) {
  1067. reg = SPRCTL(pipe);
  1068. val = I915_READ(reg);
  1069. WARN((val & SPRITE_ENABLE),
  1070. "sprite %c assertion failure, should be off on pipe %c but is still active\n",
  1071. plane_name(pipe), pipe_name(pipe));
  1072. } else if (INTEL_INFO(dev)->gen >= 5) {
  1073. reg = DVSCNTR(pipe);
  1074. val = I915_READ(reg);
  1075. WARN((val & DVS_ENABLE),
  1076. "sprite %c assertion failure, should be off on pipe %c but is still active\n",
  1077. plane_name(pipe), pipe_name(pipe));
  1078. }
  1079. }
  1080. static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
  1081. {
  1082. u32 val;
  1083. bool enabled;
  1084. if (HAS_PCH_LPT(dev_priv->dev)) {
  1085. DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
  1086. return;
  1087. }
  1088. val = I915_READ(PCH_DREF_CONTROL);
  1089. enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
  1090. DREF_SUPERSPREAD_SOURCE_MASK));
  1091. WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
  1092. }
  1093. static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
  1094. enum pipe pipe)
  1095. {
  1096. int reg;
  1097. u32 val;
  1098. bool enabled;
  1099. reg = PCH_TRANSCONF(pipe);
  1100. val = I915_READ(reg);
  1101. enabled = !!(val & TRANS_ENABLE);
  1102. WARN(enabled,
  1103. "transcoder assertion failed, should be off on pipe %c but is still active\n",
  1104. pipe_name(pipe));
  1105. }
  1106. static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
  1107. enum pipe pipe, u32 port_sel, u32 val)
  1108. {
  1109. if ((val & DP_PORT_EN) == 0)
  1110. return false;
  1111. if (HAS_PCH_CPT(dev_priv->dev)) {
  1112. u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
  1113. u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
  1114. if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
  1115. return false;
  1116. } else {
  1117. if ((val & DP_PIPE_MASK) != (pipe << 30))
  1118. return false;
  1119. }
  1120. return true;
  1121. }
  1122. static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
  1123. enum pipe pipe, u32 val)
  1124. {
  1125. if ((val & SDVO_ENABLE) == 0)
  1126. return false;
  1127. if (HAS_PCH_CPT(dev_priv->dev)) {
  1128. if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
  1129. return false;
  1130. } else {
  1131. if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
  1132. return false;
  1133. }
  1134. return true;
  1135. }
  1136. static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
  1137. enum pipe pipe, u32 val)
  1138. {
  1139. if ((val & LVDS_PORT_EN) == 0)
  1140. return false;
  1141. if (HAS_PCH_CPT(dev_priv->dev)) {
  1142. if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1143. return false;
  1144. } else {
  1145. if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
  1146. return false;
  1147. }
  1148. return true;
  1149. }
  1150. static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
  1151. enum pipe pipe, u32 val)
  1152. {
  1153. if ((val & ADPA_DAC_ENABLE) == 0)
  1154. return false;
  1155. if (HAS_PCH_CPT(dev_priv->dev)) {
  1156. if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1157. return false;
  1158. } else {
  1159. if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
  1160. return false;
  1161. }
  1162. return true;
  1163. }
  1164. static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
  1165. enum pipe pipe, int reg, u32 port_sel)
  1166. {
  1167. u32 val = I915_READ(reg);
  1168. WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
  1169. "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
  1170. reg, pipe_name(pipe));
  1171. WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
  1172. && (val & DP_PIPEB_SELECT),
  1173. "IBX PCH dp port still using transcoder B\n");
  1174. }
  1175. static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
  1176. enum pipe pipe, int reg)
  1177. {
  1178. u32 val = I915_READ(reg);
  1179. WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
  1180. "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
  1181. reg, pipe_name(pipe));
  1182. WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
  1183. && (val & SDVO_PIPE_B_SELECT),
  1184. "IBX PCH hdmi port still using transcoder B\n");
  1185. }
  1186. static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
  1187. enum pipe pipe)
  1188. {
  1189. int reg;
  1190. u32 val;
  1191. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
  1192. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
  1193. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
  1194. reg = PCH_ADPA;
  1195. val = I915_READ(reg);
  1196. WARN(adpa_pipe_enabled(dev_priv, pipe, val),
  1197. "PCH VGA enabled on transcoder %c, should be disabled\n",
  1198. pipe_name(pipe));
  1199. reg = PCH_LVDS;
  1200. val = I915_READ(reg);
  1201. WARN(lvds_pipe_enabled(dev_priv, pipe, val),
  1202. "PCH LVDS enabled on transcoder %c, should be disabled\n",
  1203. pipe_name(pipe));
  1204. assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
  1205. assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
  1206. assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
  1207. }
  1208. static void vlv_enable_pll(struct intel_crtc *crtc)
  1209. {
  1210. struct drm_device *dev = crtc->base.dev;
  1211. struct drm_i915_private *dev_priv = dev->dev_private;
  1212. int reg = DPLL(crtc->pipe);
  1213. u32 dpll = crtc->config.dpll_hw_state.dpll;
  1214. assert_pipe_disabled(dev_priv, crtc->pipe);
  1215. /* No really, not for ILK+ */
  1216. BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
  1217. /* PLL is protected by panel, make sure we can write it */
  1218. if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
  1219. assert_panel_unlocked(dev_priv, crtc->pipe);
  1220. I915_WRITE(reg, dpll);
  1221. POSTING_READ(reg);
  1222. udelay(150);
  1223. if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
  1224. DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
  1225. I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
  1226. POSTING_READ(DPLL_MD(crtc->pipe));
  1227. /* We do this three times for luck */
  1228. I915_WRITE(reg, dpll);
  1229. POSTING_READ(reg);
  1230. udelay(150); /* wait for warmup */
  1231. I915_WRITE(reg, dpll);
  1232. POSTING_READ(reg);
  1233. udelay(150); /* wait for warmup */
  1234. I915_WRITE(reg, dpll);
  1235. POSTING_READ(reg);
  1236. udelay(150); /* wait for warmup */
  1237. }
  1238. static void i9xx_enable_pll(struct intel_crtc *crtc)
  1239. {
  1240. struct drm_device *dev = crtc->base.dev;
  1241. struct drm_i915_private *dev_priv = dev->dev_private;
  1242. int reg = DPLL(crtc->pipe);
  1243. u32 dpll = crtc->config.dpll_hw_state.dpll;
  1244. assert_pipe_disabled(dev_priv, crtc->pipe);
  1245. /* No really, not for ILK+ */
  1246. BUG_ON(dev_priv->info->gen >= 5);
  1247. /* PLL is protected by panel, make sure we can write it */
  1248. if (IS_MOBILE(dev) && !IS_I830(dev))
  1249. assert_panel_unlocked(dev_priv, crtc->pipe);
  1250. I915_WRITE(reg, dpll);
  1251. /* Wait for the clocks to stabilize. */
  1252. POSTING_READ(reg);
  1253. udelay(150);
  1254. if (INTEL_INFO(dev)->gen >= 4) {
  1255. I915_WRITE(DPLL_MD(crtc->pipe),
  1256. crtc->config.dpll_hw_state.dpll_md);
  1257. } else {
  1258. /* The pixel multiplier can only be updated once the
  1259. * DPLL is enabled and the clocks are stable.
  1260. *
  1261. * So write it again.
  1262. */
  1263. I915_WRITE(reg, dpll);
  1264. }
  1265. /* We do this three times for luck */
  1266. I915_WRITE(reg, dpll);
  1267. POSTING_READ(reg);
  1268. udelay(150); /* wait for warmup */
  1269. I915_WRITE(reg, dpll);
  1270. POSTING_READ(reg);
  1271. udelay(150); /* wait for warmup */
  1272. I915_WRITE(reg, dpll);
  1273. POSTING_READ(reg);
  1274. udelay(150); /* wait for warmup */
  1275. }
  1276. /**
  1277. * i9xx_disable_pll - disable a PLL
  1278. * @dev_priv: i915 private structure
  1279. * @pipe: pipe PLL to disable
  1280. *
  1281. * Disable the PLL for @pipe, making sure the pipe is off first.
  1282. *
  1283. * Note! This is for pre-ILK only.
  1284. */
  1285. static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
  1286. {
  1287. /* Don't disable pipe A or pipe A PLLs if needed */
  1288. if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  1289. return;
  1290. /* Make sure the pipe isn't still relying on us */
  1291. assert_pipe_disabled(dev_priv, pipe);
  1292. I915_WRITE(DPLL(pipe), 0);
  1293. POSTING_READ(DPLL(pipe));
  1294. }
  1295. void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
  1296. {
  1297. u32 port_mask;
  1298. if (!port)
  1299. port_mask = DPLL_PORTB_READY_MASK;
  1300. else
  1301. port_mask = DPLL_PORTC_READY_MASK;
  1302. if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
  1303. WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
  1304. 'B' + port, I915_READ(DPLL(0)));
  1305. }
  1306. /**
  1307. * ironlake_enable_shared_dpll - enable PCH PLL
  1308. * @dev_priv: i915 private structure
  1309. * @pipe: pipe PLL to enable
  1310. *
  1311. * The PCH PLL needs to be enabled before the PCH transcoder, since it
  1312. * drives the transcoder clock.
  1313. */
  1314. static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
  1315. {
  1316. struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  1317. struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
  1318. /* PCH PLLs only available on ILK, SNB and IVB */
  1319. BUG_ON(dev_priv->info->gen < 5);
  1320. if (WARN_ON(pll == NULL))
  1321. return;
  1322. if (WARN_ON(pll->refcount == 0))
  1323. return;
  1324. DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
  1325. pll->name, pll->active, pll->on,
  1326. crtc->base.base.id);
  1327. if (pll->active++) {
  1328. WARN_ON(!pll->on);
  1329. assert_shared_dpll_enabled(dev_priv, pll);
  1330. return;
  1331. }
  1332. WARN_ON(pll->on);
  1333. DRM_DEBUG_KMS("enabling %s\n", pll->name);
  1334. pll->enable(dev_priv, pll);
  1335. pll->on = true;
  1336. }
  1337. static void intel_disable_shared_dpll(struct intel_crtc *crtc)
  1338. {
  1339. struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  1340. struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
  1341. /* PCH only available on ILK+ */
  1342. BUG_ON(dev_priv->info->gen < 5);
  1343. if (WARN_ON(pll == NULL))
  1344. return;
  1345. if (WARN_ON(pll->refcount == 0))
  1346. return;
  1347. DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
  1348. pll->name, pll->active, pll->on,
  1349. crtc->base.base.id);
  1350. if (WARN_ON(pll->active == 0)) {
  1351. assert_shared_dpll_disabled(dev_priv, pll);
  1352. return;
  1353. }
  1354. assert_shared_dpll_enabled(dev_priv, pll);
  1355. WARN_ON(!pll->on);
  1356. if (--pll->active)
  1357. return;
  1358. DRM_DEBUG_KMS("disabling %s\n", pll->name);
  1359. pll->disable(dev_priv, pll);
  1360. pll->on = false;
  1361. }
  1362. static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
  1363. enum pipe pipe)
  1364. {
  1365. struct drm_device *dev = dev_priv->dev;
  1366. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  1367. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1368. uint32_t reg, val, pipeconf_val;
  1369. /* PCH only available on ILK+ */
  1370. BUG_ON(dev_priv->info->gen < 5);
  1371. /* Make sure PCH DPLL is enabled */
  1372. assert_shared_dpll_enabled(dev_priv,
  1373. intel_crtc_to_shared_dpll(intel_crtc));
  1374. /* FDI must be feeding us bits for PCH ports */
  1375. assert_fdi_tx_enabled(dev_priv, pipe);
  1376. assert_fdi_rx_enabled(dev_priv, pipe);
  1377. if (HAS_PCH_CPT(dev)) {
  1378. /* Workaround: Set the timing override bit before enabling the
  1379. * pch transcoder. */
  1380. reg = TRANS_CHICKEN2(pipe);
  1381. val = I915_READ(reg);
  1382. val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
  1383. I915_WRITE(reg, val);
  1384. }
  1385. reg = PCH_TRANSCONF(pipe);
  1386. val = I915_READ(reg);
  1387. pipeconf_val = I915_READ(PIPECONF(pipe));
  1388. if (HAS_PCH_IBX(dev_priv->dev)) {
  1389. /*
  1390. * make the BPC in transcoder be consistent with
  1391. * that in pipeconf reg.
  1392. */
  1393. val &= ~PIPECONF_BPC_MASK;
  1394. val |= pipeconf_val & PIPECONF_BPC_MASK;
  1395. }
  1396. val &= ~TRANS_INTERLACE_MASK;
  1397. if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
  1398. if (HAS_PCH_IBX(dev_priv->dev) &&
  1399. intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
  1400. val |= TRANS_LEGACY_INTERLACED_ILK;
  1401. else
  1402. val |= TRANS_INTERLACED;
  1403. else
  1404. val |= TRANS_PROGRESSIVE;
  1405. I915_WRITE(reg, val | TRANS_ENABLE);
  1406. if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
  1407. DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
  1408. }
  1409. static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
  1410. enum transcoder cpu_transcoder)
  1411. {
  1412. u32 val, pipeconf_val;
  1413. /* PCH only available on ILK+ */
  1414. BUG_ON(dev_priv->info->gen < 5);
  1415. /* FDI must be feeding us bits for PCH ports */
  1416. assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
  1417. assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
  1418. /* Workaround: set timing override bit. */
  1419. val = I915_READ(_TRANSA_CHICKEN2);
  1420. val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
  1421. I915_WRITE(_TRANSA_CHICKEN2, val);
  1422. val = TRANS_ENABLE;
  1423. pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
  1424. if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
  1425. PIPECONF_INTERLACED_ILK)
  1426. val |= TRANS_INTERLACED;
  1427. else
  1428. val |= TRANS_PROGRESSIVE;
  1429. I915_WRITE(LPT_TRANSCONF, val);
  1430. if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
  1431. DRM_ERROR("Failed to enable PCH transcoder\n");
  1432. }
  1433. static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
  1434. enum pipe pipe)
  1435. {
  1436. struct drm_device *dev = dev_priv->dev;
  1437. uint32_t reg, val;
  1438. /* FDI relies on the transcoder */
  1439. assert_fdi_tx_disabled(dev_priv, pipe);
  1440. assert_fdi_rx_disabled(dev_priv, pipe);
  1441. /* Ports must be off as well */
  1442. assert_pch_ports_disabled(dev_priv, pipe);
  1443. reg = PCH_TRANSCONF(pipe);
  1444. val = I915_READ(reg);
  1445. val &= ~TRANS_ENABLE;
  1446. I915_WRITE(reg, val);
  1447. /* wait for PCH transcoder off, transcoder state */
  1448. if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
  1449. DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
  1450. if (!HAS_PCH_IBX(dev)) {
  1451. /* Workaround: Clear the timing override chicken bit again. */
  1452. reg = TRANS_CHICKEN2(pipe);
  1453. val = I915_READ(reg);
  1454. val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
  1455. I915_WRITE(reg, val);
  1456. }
  1457. }
  1458. static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
  1459. {
  1460. u32 val;
  1461. val = I915_READ(LPT_TRANSCONF);
  1462. val &= ~TRANS_ENABLE;
  1463. I915_WRITE(LPT_TRANSCONF, val);
  1464. /* wait for PCH transcoder off, transcoder state */
  1465. if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
  1466. DRM_ERROR("Failed to disable PCH transcoder\n");
  1467. /* Workaround: clear timing override bit. */
  1468. val = I915_READ(_TRANSA_CHICKEN2);
  1469. val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
  1470. I915_WRITE(_TRANSA_CHICKEN2, val);
  1471. }
  1472. /**
  1473. * intel_enable_pipe - enable a pipe, asserting requirements
  1474. * @dev_priv: i915 private structure
  1475. * @pipe: pipe to enable
  1476. * @pch_port: on ILK+, is this pipe driving a PCH port or not
  1477. *
  1478. * Enable @pipe, making sure that various hardware specific requirements
  1479. * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
  1480. *
  1481. * @pipe should be %PIPE_A or %PIPE_B.
  1482. *
  1483. * Will wait until the pipe is actually running (i.e. first vblank) before
  1484. * returning.
  1485. */
  1486. static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
  1487. bool pch_port, bool dsi)
  1488. {
  1489. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  1490. pipe);
  1491. enum pipe pch_transcoder;
  1492. int reg;
  1493. u32 val;
  1494. assert_planes_disabled(dev_priv, pipe);
  1495. assert_cursor_disabled(dev_priv, pipe);
  1496. assert_sprites_disabled(dev_priv, pipe);
  1497. if (HAS_PCH_LPT(dev_priv->dev))
  1498. pch_transcoder = TRANSCODER_A;
  1499. else
  1500. pch_transcoder = pipe;
  1501. /*
  1502. * A pipe without a PLL won't actually be able to drive bits from
  1503. * a plane. On ILK+ the pipe PLLs are integrated, so we don't
  1504. * need the check.
  1505. */
  1506. if (!HAS_PCH_SPLIT(dev_priv->dev))
  1507. if (dsi)
  1508. assert_dsi_pll_enabled(dev_priv);
  1509. else
  1510. assert_pll_enabled(dev_priv, pipe);
  1511. else {
  1512. if (pch_port) {
  1513. /* if driving the PCH, we need FDI enabled */
  1514. assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
  1515. assert_fdi_tx_pll_enabled(dev_priv,
  1516. (enum pipe) cpu_transcoder);
  1517. }
  1518. /* FIXME: assert CPU port conditions for SNB+ */
  1519. }
  1520. reg = PIPECONF(cpu_transcoder);
  1521. val = I915_READ(reg);
  1522. if (val & PIPECONF_ENABLE)
  1523. return;
  1524. I915_WRITE(reg, val | PIPECONF_ENABLE);
  1525. intel_wait_for_vblank(dev_priv->dev, pipe);
  1526. }
  1527. /**
  1528. * intel_disable_pipe - disable a pipe, asserting requirements
  1529. * @dev_priv: i915 private structure
  1530. * @pipe: pipe to disable
  1531. *
  1532. * Disable @pipe, making sure that various hardware specific requirements
  1533. * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
  1534. *
  1535. * @pipe should be %PIPE_A or %PIPE_B.
  1536. *
  1537. * Will wait until the pipe has shut down before returning.
  1538. */
  1539. static void intel_disable_pipe(struct drm_i915_private *dev_priv,
  1540. enum pipe pipe)
  1541. {
  1542. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  1543. pipe);
  1544. int reg;
  1545. u32 val;
  1546. /*
  1547. * Make sure planes won't keep trying to pump pixels to us,
  1548. * or we might hang the display.
  1549. */
  1550. assert_planes_disabled(dev_priv, pipe);
  1551. assert_cursor_disabled(dev_priv, pipe);
  1552. assert_sprites_disabled(dev_priv, pipe);
  1553. /* Don't disable pipe A or pipe A PLLs if needed */
  1554. if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  1555. return;
  1556. reg = PIPECONF(cpu_transcoder);
  1557. val = I915_READ(reg);
  1558. if ((val & PIPECONF_ENABLE) == 0)
  1559. return;
  1560. I915_WRITE(reg, val & ~PIPECONF_ENABLE);
  1561. intel_wait_for_pipe_off(dev_priv->dev, pipe);
  1562. }
  1563. /*
  1564. * Plane regs are double buffered, going from enabled->disabled needs a
  1565. * trigger in order to latch. The display address reg provides this.
  1566. */
  1567. void intel_flush_display_plane(struct drm_i915_private *dev_priv,
  1568. enum plane plane)
  1569. {
  1570. if (dev_priv->info->gen >= 4)
  1571. I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
  1572. else
  1573. I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
  1574. }
  1575. /**
  1576. * intel_enable_plane - enable a display plane on a given pipe
  1577. * @dev_priv: i915 private structure
  1578. * @plane: plane to enable
  1579. * @pipe: pipe being fed
  1580. *
  1581. * Enable @plane on @pipe, making sure that @pipe is running first.
  1582. */
  1583. static void intel_enable_plane(struct drm_i915_private *dev_priv,
  1584. enum plane plane, enum pipe pipe)
  1585. {
  1586. int reg;
  1587. u32 val;
  1588. /* If the pipe isn't enabled, we can't pump pixels and may hang */
  1589. assert_pipe_enabled(dev_priv, pipe);
  1590. reg = DSPCNTR(plane);
  1591. val = I915_READ(reg);
  1592. if (val & DISPLAY_PLANE_ENABLE)
  1593. return;
  1594. I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
  1595. intel_flush_display_plane(dev_priv, plane);
  1596. intel_wait_for_vblank(dev_priv->dev, pipe);
  1597. }
  1598. /**
  1599. * intel_disable_plane - disable a display plane
  1600. * @dev_priv: i915 private structure
  1601. * @plane: plane to disable
  1602. * @pipe: pipe consuming the data
  1603. *
  1604. * Disable @plane; should be an independent operation.
  1605. */
  1606. static void intel_disable_plane(struct drm_i915_private *dev_priv,
  1607. enum plane plane, enum pipe pipe)
  1608. {
  1609. int reg;
  1610. u32 val;
  1611. reg = DSPCNTR(plane);
  1612. val = I915_READ(reg);
  1613. if ((val & DISPLAY_PLANE_ENABLE) == 0)
  1614. return;
  1615. I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
  1616. intel_flush_display_plane(dev_priv, plane);
  1617. intel_wait_for_vblank(dev_priv->dev, pipe);
  1618. }
  1619. static bool need_vtd_wa(struct drm_device *dev)
  1620. {
  1621. #ifdef CONFIG_INTEL_IOMMU
  1622. if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
  1623. return true;
  1624. #endif
  1625. return false;
  1626. }
  1627. int
  1628. intel_pin_and_fence_fb_obj(struct drm_device *dev,
  1629. struct drm_i915_gem_object *obj,
  1630. struct intel_ring_buffer *pipelined)
  1631. {
  1632. struct drm_i915_private *dev_priv = dev->dev_private;
  1633. u32 alignment;
  1634. int ret;
  1635. switch (obj->tiling_mode) {
  1636. case I915_TILING_NONE:
  1637. if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
  1638. alignment = 128 * 1024;
  1639. else if (INTEL_INFO(dev)->gen >= 4)
  1640. alignment = 4 * 1024;
  1641. else
  1642. alignment = 64 * 1024;
  1643. break;
  1644. case I915_TILING_X:
  1645. /* pin() will align the object as required by fence */
  1646. alignment = 0;
  1647. break;
  1648. case I915_TILING_Y:
  1649. /* Despite that we check this in framebuffer_init userspace can
  1650. * screw us over and change the tiling after the fact. Only
  1651. * pinned buffers can't change their tiling. */
  1652. DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
  1653. return -EINVAL;
  1654. default:
  1655. BUG();
  1656. }
  1657. /* Note that the w/a also requires 64 PTE of padding following the
  1658. * bo. We currently fill all unused PTE with the shadow page and so
  1659. * we should always have valid PTE following the scanout preventing
  1660. * the VT-d warning.
  1661. */
  1662. if (need_vtd_wa(dev) && alignment < 256 * 1024)
  1663. alignment = 256 * 1024;
  1664. dev_priv->mm.interruptible = false;
  1665. ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
  1666. if (ret)
  1667. goto err_interruptible;
  1668. /* Install a fence for tiled scan-out. Pre-i965 always needs a
  1669. * fence, whereas 965+ only requires a fence if using
  1670. * framebuffer compression. For simplicity, we always install
  1671. * a fence as the cost is not that onerous.
  1672. */
  1673. ret = i915_gem_object_get_fence(obj);
  1674. if (ret)
  1675. goto err_unpin;
  1676. i915_gem_object_pin_fence(obj);
  1677. dev_priv->mm.interruptible = true;
  1678. return 0;
  1679. err_unpin:
  1680. i915_gem_object_unpin_from_display_plane(obj);
  1681. err_interruptible:
  1682. dev_priv->mm.interruptible = true;
  1683. return ret;
  1684. }
  1685. void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
  1686. {
  1687. i915_gem_object_unpin_fence(obj);
  1688. i915_gem_object_unpin_from_display_plane(obj);
  1689. }
  1690. /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
  1691. * is assumed to be a power-of-two. */
  1692. unsigned long intel_gen4_compute_page_offset(int *x, int *y,
  1693. unsigned int tiling_mode,
  1694. unsigned int cpp,
  1695. unsigned int pitch)
  1696. {
  1697. if (tiling_mode != I915_TILING_NONE) {
  1698. unsigned int tile_rows, tiles;
  1699. tile_rows = *y / 8;
  1700. *y %= 8;
  1701. tiles = *x / (512/cpp);
  1702. *x %= 512/cpp;
  1703. return tile_rows * pitch * 8 + tiles * 4096;
  1704. } else {
  1705. unsigned int offset;
  1706. offset = *y * pitch + *x * cpp;
  1707. *y = 0;
  1708. *x = (offset & 4095) / cpp;
  1709. return offset & -4096;
  1710. }
  1711. }
  1712. static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  1713. int x, int y)
  1714. {
  1715. struct drm_device *dev = crtc->dev;
  1716. struct drm_i915_private *dev_priv = dev->dev_private;
  1717. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1718. struct intel_framebuffer *intel_fb;
  1719. struct drm_i915_gem_object *obj;
  1720. int plane = intel_crtc->plane;
  1721. unsigned long linear_offset;
  1722. u32 dspcntr;
  1723. u32 reg;
  1724. switch (plane) {
  1725. case 0:
  1726. case 1:
  1727. break;
  1728. default:
  1729. DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
  1730. return -EINVAL;
  1731. }
  1732. intel_fb = to_intel_framebuffer(fb);
  1733. obj = intel_fb->obj;
  1734. reg = DSPCNTR(plane);
  1735. dspcntr = I915_READ(reg);
  1736. /* Mask out pixel format bits in case we change it */
  1737. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1738. switch (fb->pixel_format) {
  1739. case DRM_FORMAT_C8:
  1740. dspcntr |= DISPPLANE_8BPP;
  1741. break;
  1742. case DRM_FORMAT_XRGB1555:
  1743. case DRM_FORMAT_ARGB1555:
  1744. dspcntr |= DISPPLANE_BGRX555;
  1745. break;
  1746. case DRM_FORMAT_RGB565:
  1747. dspcntr |= DISPPLANE_BGRX565;
  1748. break;
  1749. case DRM_FORMAT_XRGB8888:
  1750. case DRM_FORMAT_ARGB8888:
  1751. dspcntr |= DISPPLANE_BGRX888;
  1752. break;
  1753. case DRM_FORMAT_XBGR8888:
  1754. case DRM_FORMAT_ABGR8888:
  1755. dspcntr |= DISPPLANE_RGBX888;
  1756. break;
  1757. case DRM_FORMAT_XRGB2101010:
  1758. case DRM_FORMAT_ARGB2101010:
  1759. dspcntr |= DISPPLANE_BGRX101010;
  1760. break;
  1761. case DRM_FORMAT_XBGR2101010:
  1762. case DRM_FORMAT_ABGR2101010:
  1763. dspcntr |= DISPPLANE_RGBX101010;
  1764. break;
  1765. default:
  1766. BUG();
  1767. }
  1768. if (INTEL_INFO(dev)->gen >= 4) {
  1769. if (obj->tiling_mode != I915_TILING_NONE)
  1770. dspcntr |= DISPPLANE_TILED;
  1771. else
  1772. dspcntr &= ~DISPPLANE_TILED;
  1773. }
  1774. if (IS_G4X(dev))
  1775. dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  1776. I915_WRITE(reg, dspcntr);
  1777. linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
  1778. if (INTEL_INFO(dev)->gen >= 4) {
  1779. intel_crtc->dspaddr_offset =
  1780. intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
  1781. fb->bits_per_pixel / 8,
  1782. fb->pitches[0]);
  1783. linear_offset -= intel_crtc->dspaddr_offset;
  1784. } else {
  1785. intel_crtc->dspaddr_offset = linear_offset;
  1786. }
  1787. DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
  1788. i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
  1789. fb->pitches[0]);
  1790. I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
  1791. if (INTEL_INFO(dev)->gen >= 4) {
  1792. I915_MODIFY_DISPBASE(DSPSURF(plane),
  1793. i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  1794. I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  1795. I915_WRITE(DSPLINOFF(plane), linear_offset);
  1796. } else
  1797. I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
  1798. POSTING_READ(reg);
  1799. return 0;
  1800. }
  1801. static int ironlake_update_plane(struct drm_crtc *crtc,
  1802. struct drm_framebuffer *fb, int x, int y)
  1803. {
  1804. struct drm_device *dev = crtc->dev;
  1805. struct drm_i915_private *dev_priv = dev->dev_private;
  1806. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1807. struct intel_framebuffer *intel_fb;
  1808. struct drm_i915_gem_object *obj;
  1809. int plane = intel_crtc->plane;
  1810. unsigned long linear_offset;
  1811. u32 dspcntr;
  1812. u32 reg;
  1813. switch (plane) {
  1814. case 0:
  1815. case 1:
  1816. case 2:
  1817. break;
  1818. default:
  1819. DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
  1820. return -EINVAL;
  1821. }
  1822. intel_fb = to_intel_framebuffer(fb);
  1823. obj = intel_fb->obj;
  1824. reg = DSPCNTR(plane);
  1825. dspcntr = I915_READ(reg);
  1826. /* Mask out pixel format bits in case we change it */
  1827. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1828. switch (fb->pixel_format) {
  1829. case DRM_FORMAT_C8:
  1830. dspcntr |= DISPPLANE_8BPP;
  1831. break;
  1832. case DRM_FORMAT_RGB565:
  1833. dspcntr |= DISPPLANE_BGRX565;
  1834. break;
  1835. case DRM_FORMAT_XRGB8888:
  1836. case DRM_FORMAT_ARGB8888:
  1837. dspcntr |= DISPPLANE_BGRX888;
  1838. break;
  1839. case DRM_FORMAT_XBGR8888:
  1840. case DRM_FORMAT_ABGR8888:
  1841. dspcntr |= DISPPLANE_RGBX888;
  1842. break;
  1843. case DRM_FORMAT_XRGB2101010:
  1844. case DRM_FORMAT_ARGB2101010:
  1845. dspcntr |= DISPPLANE_BGRX101010;
  1846. break;
  1847. case DRM_FORMAT_XBGR2101010:
  1848. case DRM_FORMAT_ABGR2101010:
  1849. dspcntr |= DISPPLANE_RGBX101010;
  1850. break;
  1851. default:
  1852. BUG();
  1853. }
  1854. if (obj->tiling_mode != I915_TILING_NONE)
  1855. dspcntr |= DISPPLANE_TILED;
  1856. else
  1857. dspcntr &= ~DISPPLANE_TILED;
  1858. if (IS_HASWELL(dev))
  1859. dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
  1860. else
  1861. dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  1862. I915_WRITE(reg, dspcntr);
  1863. linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
  1864. intel_crtc->dspaddr_offset =
  1865. intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
  1866. fb->bits_per_pixel / 8,
  1867. fb->pitches[0]);
  1868. linear_offset -= intel_crtc->dspaddr_offset;
  1869. DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
  1870. i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
  1871. fb->pitches[0]);
  1872. I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
  1873. I915_MODIFY_DISPBASE(DSPSURF(plane),
  1874. i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  1875. if (IS_HASWELL(dev)) {
  1876. I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
  1877. } else {
  1878. I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  1879. I915_WRITE(DSPLINOFF(plane), linear_offset);
  1880. }
  1881. POSTING_READ(reg);
  1882. return 0;
  1883. }
  1884. /* Assume fb object is pinned & idle & fenced and just update base pointers */
  1885. static int
  1886. intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  1887. int x, int y, enum mode_set_atomic state)
  1888. {
  1889. struct drm_device *dev = crtc->dev;
  1890. struct drm_i915_private *dev_priv = dev->dev_private;
  1891. if (dev_priv->display.disable_fbc)
  1892. dev_priv->display.disable_fbc(dev);
  1893. intel_increase_pllclock(crtc);
  1894. return dev_priv->display.update_plane(crtc, fb, x, y);
  1895. }
  1896. void intel_display_handle_reset(struct drm_device *dev)
  1897. {
  1898. struct drm_i915_private *dev_priv = dev->dev_private;
  1899. struct drm_crtc *crtc;
  1900. /*
  1901. * Flips in the rings have been nuked by the reset,
  1902. * so complete all pending flips so that user space
  1903. * will get its events and not get stuck.
  1904. *
  1905. * Also update the base address of all primary
  1906. * planes to the the last fb to make sure we're
  1907. * showing the correct fb after a reset.
  1908. *
  1909. * Need to make two loops over the crtcs so that we
  1910. * don't try to grab a crtc mutex before the
  1911. * pending_flip_queue really got woken up.
  1912. */
  1913. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1914. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1915. enum plane plane = intel_crtc->plane;
  1916. intel_prepare_page_flip(dev, plane);
  1917. intel_finish_page_flip_plane(dev, plane);
  1918. }
  1919. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1920. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1921. mutex_lock(&crtc->mutex);
  1922. if (intel_crtc->active)
  1923. dev_priv->display.update_plane(crtc, crtc->fb,
  1924. crtc->x, crtc->y);
  1925. mutex_unlock(&crtc->mutex);
  1926. }
  1927. }
  1928. static int
  1929. intel_finish_fb(struct drm_framebuffer *old_fb)
  1930. {
  1931. struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
  1932. struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  1933. bool was_interruptible = dev_priv->mm.interruptible;
  1934. int ret;
  1935. /* Big Hammer, we also need to ensure that any pending
  1936. * MI_WAIT_FOR_EVENT inside a user batch buffer on the
  1937. * current scanout is retired before unpinning the old
  1938. * framebuffer.
  1939. *
  1940. * This should only fail upon a hung GPU, in which case we
  1941. * can safely continue.
  1942. */
  1943. dev_priv->mm.interruptible = false;
  1944. ret = i915_gem_object_finish_gpu(obj);
  1945. dev_priv->mm.interruptible = was_interruptible;
  1946. return ret;
  1947. }
  1948. static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
  1949. {
  1950. struct drm_device *dev = crtc->dev;
  1951. struct drm_i915_master_private *master_priv;
  1952. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1953. if (!dev->primary->master)
  1954. return;
  1955. master_priv = dev->primary->master->driver_priv;
  1956. if (!master_priv->sarea_priv)
  1957. return;
  1958. switch (intel_crtc->pipe) {
  1959. case 0:
  1960. master_priv->sarea_priv->pipeA_x = x;
  1961. master_priv->sarea_priv->pipeA_y = y;
  1962. break;
  1963. case 1:
  1964. master_priv->sarea_priv->pipeB_x = x;
  1965. master_priv->sarea_priv->pipeB_y = y;
  1966. break;
  1967. default:
  1968. break;
  1969. }
  1970. }
  1971. static int
  1972. intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
  1973. struct drm_framebuffer *fb)
  1974. {
  1975. struct drm_device *dev = crtc->dev;
  1976. struct drm_i915_private *dev_priv = dev->dev_private;
  1977. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1978. struct drm_framebuffer *old_fb;
  1979. int ret;
  1980. /* no fb bound */
  1981. if (!fb) {
  1982. DRM_ERROR("No FB bound\n");
  1983. return 0;
  1984. }
  1985. if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
  1986. DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
  1987. plane_name(intel_crtc->plane),
  1988. INTEL_INFO(dev)->num_pipes);
  1989. return -EINVAL;
  1990. }
  1991. mutex_lock(&dev->struct_mutex);
  1992. ret = intel_pin_and_fence_fb_obj(dev,
  1993. to_intel_framebuffer(fb)->obj,
  1994. NULL);
  1995. if (ret != 0) {
  1996. mutex_unlock(&dev->struct_mutex);
  1997. DRM_ERROR("pin & fence failed\n");
  1998. return ret;
  1999. }
  2000. /* Update pipe size and adjust fitter if needed */
  2001. if (i915_fastboot) {
  2002. I915_WRITE(PIPESRC(intel_crtc->pipe),
  2003. ((crtc->mode.hdisplay - 1) << 16) |
  2004. (crtc->mode.vdisplay - 1));
  2005. if (!intel_crtc->config.pch_pfit.size &&
  2006. (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
  2007. intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
  2008. I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
  2009. I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
  2010. I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
  2011. }
  2012. }
  2013. ret = dev_priv->display.update_plane(crtc, fb, x, y);
  2014. if (ret) {
  2015. intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
  2016. mutex_unlock(&dev->struct_mutex);
  2017. DRM_ERROR("failed to update base address\n");
  2018. return ret;
  2019. }
  2020. old_fb = crtc->fb;
  2021. crtc->fb = fb;
  2022. crtc->x = x;
  2023. crtc->y = y;
  2024. if (old_fb) {
  2025. if (intel_crtc->active && old_fb != fb)
  2026. intel_wait_for_vblank(dev, intel_crtc->pipe);
  2027. intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
  2028. }
  2029. intel_update_fbc(dev);
  2030. intel_edp_psr_update(dev);
  2031. mutex_unlock(&dev->struct_mutex);
  2032. intel_crtc_update_sarea_pos(crtc, x, y);
  2033. return 0;
  2034. }
  2035. static void intel_fdi_normal_train(struct drm_crtc *crtc)
  2036. {
  2037. struct drm_device *dev = crtc->dev;
  2038. struct drm_i915_private *dev_priv = dev->dev_private;
  2039. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2040. int pipe = intel_crtc->pipe;
  2041. u32 reg, temp;
  2042. /* enable normal train */
  2043. reg = FDI_TX_CTL(pipe);
  2044. temp = I915_READ(reg);
  2045. if (IS_IVYBRIDGE(dev)) {
  2046. temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  2047. temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
  2048. } else {
  2049. temp &= ~FDI_LINK_TRAIN_NONE;
  2050. temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
  2051. }
  2052. I915_WRITE(reg, temp);
  2053. reg = FDI_RX_CTL(pipe);
  2054. temp = I915_READ(reg);
  2055. if (HAS_PCH_CPT(dev)) {
  2056. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2057. temp |= FDI_LINK_TRAIN_NORMAL_CPT;
  2058. } else {
  2059. temp &= ~FDI_LINK_TRAIN_NONE;
  2060. temp |= FDI_LINK_TRAIN_NONE;
  2061. }
  2062. I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
  2063. /* wait one idle pattern time */
  2064. POSTING_READ(reg);
  2065. udelay(1000);
  2066. /* IVB wants error correction enabled */
  2067. if (IS_IVYBRIDGE(dev))
  2068. I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
  2069. FDI_FE_ERRC_ENABLE);
  2070. }
  2071. static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
  2072. {
  2073. return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
  2074. }
  2075. static void ivb_modeset_global_resources(struct drm_device *dev)
  2076. {
  2077. struct drm_i915_private *dev_priv = dev->dev_private;
  2078. struct intel_crtc *pipe_B_crtc =
  2079. to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
  2080. struct intel_crtc *pipe_C_crtc =
  2081. to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
  2082. uint32_t temp;
  2083. /*
  2084. * When everything is off disable fdi C so that we could enable fdi B
  2085. * with all lanes. Note that we don't care about enabled pipes without
  2086. * an enabled pch encoder.
  2087. */
  2088. if (!pipe_has_enabled_pch(pipe_B_crtc) &&
  2089. !pipe_has_enabled_pch(pipe_C_crtc)) {
  2090. WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
  2091. WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
  2092. temp = I915_READ(SOUTH_CHICKEN1);
  2093. temp &= ~FDI_BC_BIFURCATION_SELECT;
  2094. DRM_DEBUG_KMS("disabling fdi C rx\n");
  2095. I915_WRITE(SOUTH_CHICKEN1, temp);
  2096. }
  2097. }
  2098. /* The FDI link training functions for ILK/Ibexpeak. */
  2099. static void ironlake_fdi_link_train(struct drm_crtc *crtc)
  2100. {
  2101. struct drm_device *dev = crtc->dev;
  2102. struct drm_i915_private *dev_priv = dev->dev_private;
  2103. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2104. int pipe = intel_crtc->pipe;
  2105. int plane = intel_crtc->plane;
  2106. u32 reg, temp, tries;
  2107. /* FDI needs bits from pipe & plane first */
  2108. assert_pipe_enabled(dev_priv, pipe);
  2109. assert_plane_enabled(dev_priv, plane);
  2110. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2111. for train result */
  2112. reg = FDI_RX_IMR(pipe);
  2113. temp = I915_READ(reg);
  2114. temp &= ~FDI_RX_SYMBOL_LOCK;
  2115. temp &= ~FDI_RX_BIT_LOCK;
  2116. I915_WRITE(reg, temp);
  2117. I915_READ(reg);
  2118. udelay(150);
  2119. /* enable CPU FDI TX and PCH FDI RX */
  2120. reg = FDI_TX_CTL(pipe);
  2121. temp = I915_READ(reg);
  2122. temp &= ~FDI_DP_PORT_WIDTH_MASK;
  2123. temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
  2124. temp &= ~FDI_LINK_TRAIN_NONE;
  2125. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2126. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2127. reg = FDI_RX_CTL(pipe);
  2128. temp = I915_READ(reg);
  2129. temp &= ~FDI_LINK_TRAIN_NONE;
  2130. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2131. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2132. POSTING_READ(reg);
  2133. udelay(150);
  2134. /* Ironlake workaround, enable clock pointer after FDI enable*/
  2135. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  2136. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
  2137. FDI_RX_PHASE_SYNC_POINTER_EN);
  2138. reg = FDI_RX_IIR(pipe);
  2139. for (tries = 0; tries < 5; tries++) {
  2140. temp = I915_READ(reg);
  2141. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2142. if ((temp & FDI_RX_BIT_LOCK)) {
  2143. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2144. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2145. break;
  2146. }
  2147. }
  2148. if (tries == 5)
  2149. DRM_ERROR("FDI train 1 fail!\n");
  2150. /* Train 2 */
  2151. reg = FDI_TX_CTL(pipe);
  2152. temp = I915_READ(reg);
  2153. temp &= ~FDI_LINK_TRAIN_NONE;
  2154. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2155. I915_WRITE(reg, temp);
  2156. reg = FDI_RX_CTL(pipe);
  2157. temp = I915_READ(reg);
  2158. temp &= ~FDI_LINK_TRAIN_NONE;
  2159. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2160. I915_WRITE(reg, temp);
  2161. POSTING_READ(reg);
  2162. udelay(150);
  2163. reg = FDI_RX_IIR(pipe);
  2164. for (tries = 0; tries < 5; tries++) {
  2165. temp = I915_READ(reg);
  2166. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2167. if (temp & FDI_RX_SYMBOL_LOCK) {
  2168. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2169. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2170. break;
  2171. }
  2172. }
  2173. if (tries == 5)
  2174. DRM_ERROR("FDI train 2 fail!\n");
  2175. DRM_DEBUG_KMS("FDI train done\n");
  2176. }
  2177. static const int snb_b_fdi_train_param[] = {
  2178. FDI_LINK_TRAIN_400MV_0DB_SNB_B,
  2179. FDI_LINK_TRAIN_400MV_6DB_SNB_B,
  2180. FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
  2181. FDI_LINK_TRAIN_800MV_0DB_SNB_B,
  2182. };
  2183. /* The FDI link training functions for SNB/Cougarpoint. */
  2184. static void gen6_fdi_link_train(struct drm_crtc *crtc)
  2185. {
  2186. struct drm_device *dev = crtc->dev;
  2187. struct drm_i915_private *dev_priv = dev->dev_private;
  2188. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2189. int pipe = intel_crtc->pipe;
  2190. u32 reg, temp, i, retry;
  2191. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2192. for train result */
  2193. reg = FDI_RX_IMR(pipe);
  2194. temp = I915_READ(reg);
  2195. temp &= ~FDI_RX_SYMBOL_LOCK;
  2196. temp &= ~FDI_RX_BIT_LOCK;
  2197. I915_WRITE(reg, temp);
  2198. POSTING_READ(reg);
  2199. udelay(150);
  2200. /* enable CPU FDI TX and PCH FDI RX */
  2201. reg = FDI_TX_CTL(pipe);
  2202. temp = I915_READ(reg);
  2203. temp &= ~FDI_DP_PORT_WIDTH_MASK;
  2204. temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
  2205. temp &= ~FDI_LINK_TRAIN_NONE;
  2206. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2207. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2208. /* SNB-B */
  2209. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2210. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2211. I915_WRITE(FDI_RX_MISC(pipe),
  2212. FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
  2213. reg = FDI_RX_CTL(pipe);
  2214. temp = I915_READ(reg);
  2215. if (HAS_PCH_CPT(dev)) {
  2216. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2217. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2218. } else {
  2219. temp &= ~FDI_LINK_TRAIN_NONE;
  2220. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2221. }
  2222. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2223. POSTING_READ(reg);
  2224. udelay(150);
  2225. for (i = 0; i < 4; i++) {
  2226. reg = FDI_TX_CTL(pipe);
  2227. temp = I915_READ(reg);
  2228. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2229. temp |= snb_b_fdi_train_param[i];
  2230. I915_WRITE(reg, temp);
  2231. POSTING_READ(reg);
  2232. udelay(500);
  2233. for (retry = 0; retry < 5; retry++) {
  2234. reg = FDI_RX_IIR(pipe);
  2235. temp = I915_READ(reg);
  2236. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2237. if (temp & FDI_RX_BIT_LOCK) {
  2238. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2239. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2240. break;
  2241. }
  2242. udelay(50);
  2243. }
  2244. if (retry < 5)
  2245. break;
  2246. }
  2247. if (i == 4)
  2248. DRM_ERROR("FDI train 1 fail!\n");
  2249. /* Train 2 */
  2250. reg = FDI_TX_CTL(pipe);
  2251. temp = I915_READ(reg);
  2252. temp &= ~FDI_LINK_TRAIN_NONE;
  2253. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2254. if (IS_GEN6(dev)) {
  2255. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2256. /* SNB-B */
  2257. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2258. }
  2259. I915_WRITE(reg, temp);
  2260. reg = FDI_RX_CTL(pipe);
  2261. temp = I915_READ(reg);
  2262. if (HAS_PCH_CPT(dev)) {
  2263. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2264. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  2265. } else {
  2266. temp &= ~FDI_LINK_TRAIN_NONE;
  2267. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2268. }
  2269. I915_WRITE(reg, temp);
  2270. POSTING_READ(reg);
  2271. udelay(150);
  2272. for (i = 0; i < 4; i++) {
  2273. reg = FDI_TX_CTL(pipe);
  2274. temp = I915_READ(reg);
  2275. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2276. temp |= snb_b_fdi_train_param[i];
  2277. I915_WRITE(reg, temp);
  2278. POSTING_READ(reg);
  2279. udelay(500);
  2280. for (retry = 0; retry < 5; retry++) {
  2281. reg = FDI_RX_IIR(pipe);
  2282. temp = I915_READ(reg);
  2283. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2284. if (temp & FDI_RX_SYMBOL_LOCK) {
  2285. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2286. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2287. break;
  2288. }
  2289. udelay(50);
  2290. }
  2291. if (retry < 5)
  2292. break;
  2293. }
  2294. if (i == 4)
  2295. DRM_ERROR("FDI train 2 fail!\n");
  2296. DRM_DEBUG_KMS("FDI train done.\n");
  2297. }
  2298. /* Manual link training for Ivy Bridge A0 parts */
  2299. static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
  2300. {
  2301. struct drm_device *dev = crtc->dev;
  2302. struct drm_i915_private *dev_priv = dev->dev_private;
  2303. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2304. int pipe = intel_crtc->pipe;
  2305. u32 reg, temp, i, j;
  2306. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2307. for train result */
  2308. reg = FDI_RX_IMR(pipe);
  2309. temp = I915_READ(reg);
  2310. temp &= ~FDI_RX_SYMBOL_LOCK;
  2311. temp &= ~FDI_RX_BIT_LOCK;
  2312. I915_WRITE(reg, temp);
  2313. POSTING_READ(reg);
  2314. udelay(150);
  2315. DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
  2316. I915_READ(FDI_RX_IIR(pipe)));
  2317. /* Try each vswing and preemphasis setting twice before moving on */
  2318. for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
  2319. /* disable first in case we need to retry */
  2320. reg = FDI_TX_CTL(pipe);
  2321. temp = I915_READ(reg);
  2322. temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
  2323. temp &= ~FDI_TX_ENABLE;
  2324. I915_WRITE(reg, temp);
  2325. reg = FDI_RX_CTL(pipe);
  2326. temp = I915_READ(reg);
  2327. temp &= ~FDI_LINK_TRAIN_AUTO;
  2328. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2329. temp &= ~FDI_RX_ENABLE;
  2330. I915_WRITE(reg, temp);
  2331. /* enable CPU FDI TX and PCH FDI RX */
  2332. reg = FDI_TX_CTL(pipe);
  2333. temp = I915_READ(reg);
  2334. temp &= ~FDI_DP_PORT_WIDTH_MASK;
  2335. temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
  2336. temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
  2337. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2338. temp |= snb_b_fdi_train_param[j/2];
  2339. temp |= FDI_COMPOSITE_SYNC;
  2340. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2341. I915_WRITE(FDI_RX_MISC(pipe),
  2342. FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
  2343. reg = FDI_RX_CTL(pipe);
  2344. temp = I915_READ(reg);
  2345. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2346. temp |= FDI_COMPOSITE_SYNC;
  2347. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2348. POSTING_READ(reg);
  2349. udelay(1); /* should be 0.5us */
  2350. for (i = 0; i < 4; i++) {
  2351. reg = FDI_RX_IIR(pipe);
  2352. temp = I915_READ(reg);
  2353. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2354. if (temp & FDI_RX_BIT_LOCK ||
  2355. (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
  2356. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2357. DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
  2358. i);
  2359. break;
  2360. }
  2361. udelay(1); /* should be 0.5us */
  2362. }
  2363. if (i == 4) {
  2364. DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
  2365. continue;
  2366. }
  2367. /* Train 2 */
  2368. reg = FDI_TX_CTL(pipe);
  2369. temp = I915_READ(reg);
  2370. temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  2371. temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
  2372. I915_WRITE(reg, temp);
  2373. reg = FDI_RX_CTL(pipe);
  2374. temp = I915_READ(reg);
  2375. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2376. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  2377. I915_WRITE(reg, temp);
  2378. POSTING_READ(reg);
  2379. udelay(2); /* should be 1.5us */
  2380. for (i = 0; i < 4; i++) {
  2381. reg = FDI_RX_IIR(pipe);
  2382. temp = I915_READ(reg);
  2383. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2384. if (temp & FDI_RX_SYMBOL_LOCK ||
  2385. (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
  2386. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2387. DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
  2388. i);
  2389. goto train_done;
  2390. }
  2391. udelay(2); /* should be 1.5us */
  2392. }
  2393. if (i == 4)
  2394. DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
  2395. }
  2396. train_done:
  2397. DRM_DEBUG_KMS("FDI train done.\n");
  2398. }
  2399. static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
  2400. {
  2401. struct drm_device *dev = intel_crtc->base.dev;
  2402. struct drm_i915_private *dev_priv = dev->dev_private;
  2403. int pipe = intel_crtc->pipe;
  2404. u32 reg, temp;
  2405. /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
  2406. reg = FDI_RX_CTL(pipe);
  2407. temp = I915_READ(reg);
  2408. temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
  2409. temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
  2410. temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  2411. I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
  2412. POSTING_READ(reg);
  2413. udelay(200);
  2414. /* Switch from Rawclk to PCDclk */
  2415. temp = I915_READ(reg);
  2416. I915_WRITE(reg, temp | FDI_PCDCLK);
  2417. POSTING_READ(reg);
  2418. udelay(200);
  2419. /* Enable CPU FDI TX PLL, always on for Ironlake */
  2420. reg = FDI_TX_CTL(pipe);
  2421. temp = I915_READ(reg);
  2422. if ((temp & FDI_TX_PLL_ENABLE) == 0) {
  2423. I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
  2424. POSTING_READ(reg);
  2425. udelay(100);
  2426. }
  2427. }
  2428. static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
  2429. {
  2430. struct drm_device *dev = intel_crtc->base.dev;
  2431. struct drm_i915_private *dev_priv = dev->dev_private;
  2432. int pipe = intel_crtc->pipe;
  2433. u32 reg, temp;
  2434. /* Switch from PCDclk to Rawclk */
  2435. reg = FDI_RX_CTL(pipe);
  2436. temp = I915_READ(reg);
  2437. I915_WRITE(reg, temp & ~FDI_PCDCLK);
  2438. /* Disable CPU FDI TX PLL */
  2439. reg = FDI_TX_CTL(pipe);
  2440. temp = I915_READ(reg);
  2441. I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
  2442. POSTING_READ(reg);
  2443. udelay(100);
  2444. reg = FDI_RX_CTL(pipe);
  2445. temp = I915_READ(reg);
  2446. I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
  2447. /* Wait for the clocks to turn off. */
  2448. POSTING_READ(reg);
  2449. udelay(100);
  2450. }
  2451. static void ironlake_fdi_disable(struct drm_crtc *crtc)
  2452. {
  2453. struct drm_device *dev = crtc->dev;
  2454. struct drm_i915_private *dev_priv = dev->dev_private;
  2455. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2456. int pipe = intel_crtc->pipe;
  2457. u32 reg, temp;
  2458. /* disable CPU FDI tx and PCH FDI rx */
  2459. reg = FDI_TX_CTL(pipe);
  2460. temp = I915_READ(reg);
  2461. I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
  2462. POSTING_READ(reg);
  2463. reg = FDI_RX_CTL(pipe);
  2464. temp = I915_READ(reg);
  2465. temp &= ~(0x7 << 16);
  2466. temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  2467. I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
  2468. POSTING_READ(reg);
  2469. udelay(100);
  2470. /* Ironlake workaround, disable clock pointer after downing FDI */
  2471. if (HAS_PCH_IBX(dev)) {
  2472. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  2473. }
  2474. /* still set train pattern 1 */
  2475. reg = FDI_TX_CTL(pipe);
  2476. temp = I915_READ(reg);
  2477. temp &= ~FDI_LINK_TRAIN_NONE;
  2478. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2479. I915_WRITE(reg, temp);
  2480. reg = FDI_RX_CTL(pipe);
  2481. temp = I915_READ(reg);
  2482. if (HAS_PCH_CPT(dev)) {
  2483. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2484. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2485. } else {
  2486. temp &= ~FDI_LINK_TRAIN_NONE;
  2487. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2488. }
  2489. /* BPC in FDI rx is consistent with that in PIPECONF */
  2490. temp &= ~(0x07 << 16);
  2491. temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  2492. I915_WRITE(reg, temp);
  2493. POSTING_READ(reg);
  2494. udelay(100);
  2495. }
  2496. static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
  2497. {
  2498. struct drm_device *dev = crtc->dev;
  2499. struct drm_i915_private *dev_priv = dev->dev_private;
  2500. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2501. unsigned long flags;
  2502. bool pending;
  2503. if (i915_reset_in_progress(&dev_priv->gpu_error) ||
  2504. intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
  2505. return false;
  2506. spin_lock_irqsave(&dev->event_lock, flags);
  2507. pending = to_intel_crtc(crtc)->unpin_work != NULL;
  2508. spin_unlock_irqrestore(&dev->event_lock, flags);
  2509. return pending;
  2510. }
  2511. static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
  2512. {
  2513. struct drm_device *dev = crtc->dev;
  2514. struct drm_i915_private *dev_priv = dev->dev_private;
  2515. if (crtc->fb == NULL)
  2516. return;
  2517. WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
  2518. wait_event(dev_priv->pending_flip_queue,
  2519. !intel_crtc_has_pending_flip(crtc));
  2520. mutex_lock(&dev->struct_mutex);
  2521. intel_finish_fb(crtc->fb);
  2522. mutex_unlock(&dev->struct_mutex);
  2523. }
  2524. /* Program iCLKIP clock to the desired frequency */
  2525. static void lpt_program_iclkip(struct drm_crtc *crtc)
  2526. {
  2527. struct drm_device *dev = crtc->dev;
  2528. struct drm_i915_private *dev_priv = dev->dev_private;
  2529. int clock = to_intel_crtc(crtc)->config.adjusted_mode.clock;
  2530. u32 divsel, phaseinc, auxdiv, phasedir = 0;
  2531. u32 temp;
  2532. mutex_lock(&dev_priv->dpio_lock);
  2533. /* It is necessary to ungate the pixclk gate prior to programming
  2534. * the divisors, and gate it back when it is done.
  2535. */
  2536. I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
  2537. /* Disable SSCCTL */
  2538. intel_sbi_write(dev_priv, SBI_SSCCTL6,
  2539. intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
  2540. SBI_SSCCTL_DISABLE,
  2541. SBI_ICLK);
  2542. /* 20MHz is a corner case which is out of range for the 7-bit divisor */
  2543. if (clock == 20000) {
  2544. auxdiv = 1;
  2545. divsel = 0x41;
  2546. phaseinc = 0x20;
  2547. } else {
  2548. /* The iCLK virtual clock root frequency is in MHz,
  2549. * but the adjusted_mode->clock in in KHz. To get the divisors,
  2550. * it is necessary to divide one by another, so we
  2551. * convert the virtual clock precision to KHz here for higher
  2552. * precision.
  2553. */
  2554. u32 iclk_virtual_root_freq = 172800 * 1000;
  2555. u32 iclk_pi_range = 64;
  2556. u32 desired_divisor, msb_divisor_value, pi_value;
  2557. desired_divisor = (iclk_virtual_root_freq / clock);
  2558. msb_divisor_value = desired_divisor / iclk_pi_range;
  2559. pi_value = desired_divisor % iclk_pi_range;
  2560. auxdiv = 0;
  2561. divsel = msb_divisor_value - 2;
  2562. phaseinc = pi_value;
  2563. }
  2564. /* This should not happen with any sane values */
  2565. WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
  2566. ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
  2567. WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
  2568. ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
  2569. DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
  2570. clock,
  2571. auxdiv,
  2572. divsel,
  2573. phasedir,
  2574. phaseinc);
  2575. /* Program SSCDIVINTPHASE6 */
  2576. temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
  2577. temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
  2578. temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
  2579. temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
  2580. temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
  2581. temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
  2582. temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
  2583. intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
  2584. /* Program SSCAUXDIV */
  2585. temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
  2586. temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
  2587. temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
  2588. intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
  2589. /* Enable modulator and associated divider */
  2590. temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
  2591. temp &= ~SBI_SSCCTL_DISABLE;
  2592. intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
  2593. /* Wait for initialization time */
  2594. udelay(24);
  2595. I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
  2596. mutex_unlock(&dev_priv->dpio_lock);
  2597. }
  2598. static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
  2599. enum pipe pch_transcoder)
  2600. {
  2601. struct drm_device *dev = crtc->base.dev;
  2602. struct drm_i915_private *dev_priv = dev->dev_private;
  2603. enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
  2604. I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
  2605. I915_READ(HTOTAL(cpu_transcoder)));
  2606. I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
  2607. I915_READ(HBLANK(cpu_transcoder)));
  2608. I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
  2609. I915_READ(HSYNC(cpu_transcoder)));
  2610. I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
  2611. I915_READ(VTOTAL(cpu_transcoder)));
  2612. I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
  2613. I915_READ(VBLANK(cpu_transcoder)));
  2614. I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
  2615. I915_READ(VSYNC(cpu_transcoder)));
  2616. I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
  2617. I915_READ(VSYNCSHIFT(cpu_transcoder)));
  2618. }
  2619. /*
  2620. * Enable PCH resources required for PCH ports:
  2621. * - PCH PLLs
  2622. * - FDI training & RX/TX
  2623. * - update transcoder timings
  2624. * - DP transcoding bits
  2625. * - transcoder
  2626. */
  2627. static void ironlake_pch_enable(struct drm_crtc *crtc)
  2628. {
  2629. struct drm_device *dev = crtc->dev;
  2630. struct drm_i915_private *dev_priv = dev->dev_private;
  2631. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2632. int pipe = intel_crtc->pipe;
  2633. u32 reg, temp;
  2634. assert_pch_transcoder_disabled(dev_priv, pipe);
  2635. /* Write the TU size bits before fdi link training, so that error
  2636. * detection works. */
  2637. I915_WRITE(FDI_RX_TUSIZE1(pipe),
  2638. I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
  2639. /* For PCH output, training FDI link */
  2640. dev_priv->display.fdi_link_train(crtc);
  2641. /* We need to program the right clock selection before writing the pixel
  2642. * mutliplier into the DPLL. */
  2643. if (HAS_PCH_CPT(dev)) {
  2644. u32 sel;
  2645. temp = I915_READ(PCH_DPLL_SEL);
  2646. temp |= TRANS_DPLL_ENABLE(pipe);
  2647. sel = TRANS_DPLLB_SEL(pipe);
  2648. if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
  2649. temp |= sel;
  2650. else
  2651. temp &= ~sel;
  2652. I915_WRITE(PCH_DPLL_SEL, temp);
  2653. }
  2654. /* XXX: pch pll's can be enabled any time before we enable the PCH
  2655. * transcoder, and we actually should do this to not upset any PCH
  2656. * transcoder that already use the clock when we share it.
  2657. *
  2658. * Note that enable_shared_dpll tries to do the right thing, but
  2659. * get_shared_dpll unconditionally resets the pll - we need that to have
  2660. * the right LVDS enable sequence. */
  2661. ironlake_enable_shared_dpll(intel_crtc);
  2662. /* set transcoder timing, panel must allow it */
  2663. assert_panel_unlocked(dev_priv, pipe);
  2664. ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
  2665. intel_fdi_normal_train(crtc);
  2666. /* For PCH DP, enable TRANS_DP_CTL */
  2667. if (HAS_PCH_CPT(dev) &&
  2668. (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
  2669. intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
  2670. u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
  2671. reg = TRANS_DP_CTL(pipe);
  2672. temp = I915_READ(reg);
  2673. temp &= ~(TRANS_DP_PORT_SEL_MASK |
  2674. TRANS_DP_SYNC_MASK |
  2675. TRANS_DP_BPC_MASK);
  2676. temp |= (TRANS_DP_OUTPUT_ENABLE |
  2677. TRANS_DP_ENH_FRAMING);
  2678. temp |= bpc << 9; /* same format but at 11:9 */
  2679. if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
  2680. temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
  2681. if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
  2682. temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
  2683. switch (intel_trans_dp_port_sel(crtc)) {
  2684. case PCH_DP_B:
  2685. temp |= TRANS_DP_PORT_SEL_B;
  2686. break;
  2687. case PCH_DP_C:
  2688. temp |= TRANS_DP_PORT_SEL_C;
  2689. break;
  2690. case PCH_DP_D:
  2691. temp |= TRANS_DP_PORT_SEL_D;
  2692. break;
  2693. default:
  2694. BUG();
  2695. }
  2696. I915_WRITE(reg, temp);
  2697. }
  2698. ironlake_enable_pch_transcoder(dev_priv, pipe);
  2699. }
  2700. static void lpt_pch_enable(struct drm_crtc *crtc)
  2701. {
  2702. struct drm_device *dev = crtc->dev;
  2703. struct drm_i915_private *dev_priv = dev->dev_private;
  2704. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2705. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  2706. assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
  2707. lpt_program_iclkip(crtc);
  2708. /* Set transcoder timing. */
  2709. ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
  2710. lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
  2711. }
  2712. static void intel_put_shared_dpll(struct intel_crtc *crtc)
  2713. {
  2714. struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
  2715. if (pll == NULL)
  2716. return;
  2717. if (pll->refcount == 0) {
  2718. WARN(1, "bad %s refcount\n", pll->name);
  2719. return;
  2720. }
  2721. if (--pll->refcount == 0) {
  2722. WARN_ON(pll->on);
  2723. WARN_ON(pll->active);
  2724. }
  2725. crtc->config.shared_dpll = DPLL_ID_PRIVATE;
  2726. }
  2727. static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
  2728. {
  2729. struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  2730. struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
  2731. enum intel_dpll_id i;
  2732. if (pll) {
  2733. DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
  2734. crtc->base.base.id, pll->name);
  2735. intel_put_shared_dpll(crtc);
  2736. }
  2737. if (HAS_PCH_IBX(dev_priv->dev)) {
  2738. /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
  2739. i = (enum intel_dpll_id) crtc->pipe;
  2740. pll = &dev_priv->shared_dplls[i];
  2741. DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
  2742. crtc->base.base.id, pll->name);
  2743. goto found;
  2744. }
  2745. for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  2746. pll = &dev_priv->shared_dplls[i];
  2747. /* Only want to check enabled timings first */
  2748. if (pll->refcount == 0)
  2749. continue;
  2750. if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
  2751. sizeof(pll->hw_state)) == 0) {
  2752. DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
  2753. crtc->base.base.id,
  2754. pll->name, pll->refcount, pll->active);
  2755. goto found;
  2756. }
  2757. }
  2758. /* Ok no matching timings, maybe there's a free one? */
  2759. for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  2760. pll = &dev_priv->shared_dplls[i];
  2761. if (pll->refcount == 0) {
  2762. DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
  2763. crtc->base.base.id, pll->name);
  2764. goto found;
  2765. }
  2766. }
  2767. return NULL;
  2768. found:
  2769. crtc->config.shared_dpll = i;
  2770. DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
  2771. pipe_name(crtc->pipe));
  2772. if (pll->active == 0) {
  2773. memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
  2774. sizeof(pll->hw_state));
  2775. DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
  2776. WARN_ON(pll->on);
  2777. assert_shared_dpll_disabled(dev_priv, pll);
  2778. pll->mode_set(dev_priv, pll);
  2779. }
  2780. pll->refcount++;
  2781. return pll;
  2782. }
  2783. static void cpt_verify_modeset(struct drm_device *dev, int pipe)
  2784. {
  2785. struct drm_i915_private *dev_priv = dev->dev_private;
  2786. int dslreg = PIPEDSL(pipe);
  2787. u32 temp;
  2788. temp = I915_READ(dslreg);
  2789. udelay(500);
  2790. if (wait_for(I915_READ(dslreg) != temp, 5)) {
  2791. if (wait_for(I915_READ(dslreg) != temp, 5))
  2792. DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
  2793. }
  2794. }
  2795. static void ironlake_pfit_enable(struct intel_crtc *crtc)
  2796. {
  2797. struct drm_device *dev = crtc->base.dev;
  2798. struct drm_i915_private *dev_priv = dev->dev_private;
  2799. int pipe = crtc->pipe;
  2800. if (crtc->config.pch_pfit.size) {
  2801. /* Force use of hard-coded filter coefficients
  2802. * as some pre-programmed values are broken,
  2803. * e.g. x201.
  2804. */
  2805. if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
  2806. I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
  2807. PF_PIPE_SEL_IVB(pipe));
  2808. else
  2809. I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
  2810. I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
  2811. I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
  2812. }
  2813. }
  2814. static void intel_enable_planes(struct drm_crtc *crtc)
  2815. {
  2816. struct drm_device *dev = crtc->dev;
  2817. enum pipe pipe = to_intel_crtc(crtc)->pipe;
  2818. struct intel_plane *intel_plane;
  2819. list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
  2820. if (intel_plane->pipe == pipe)
  2821. intel_plane_restore(&intel_plane->base);
  2822. }
  2823. static void intel_disable_planes(struct drm_crtc *crtc)
  2824. {
  2825. struct drm_device *dev = crtc->dev;
  2826. enum pipe pipe = to_intel_crtc(crtc)->pipe;
  2827. struct intel_plane *intel_plane;
  2828. list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
  2829. if (intel_plane->pipe == pipe)
  2830. intel_plane_disable(&intel_plane->base);
  2831. }
  2832. static void ironlake_crtc_enable(struct drm_crtc *crtc)
  2833. {
  2834. struct drm_device *dev = crtc->dev;
  2835. struct drm_i915_private *dev_priv = dev->dev_private;
  2836. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2837. struct intel_encoder *encoder;
  2838. int pipe = intel_crtc->pipe;
  2839. int plane = intel_crtc->plane;
  2840. WARN_ON(!crtc->enabled);
  2841. if (intel_crtc->active)
  2842. return;
  2843. intel_crtc->active = true;
  2844. intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
  2845. intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
  2846. for_each_encoder_on_crtc(dev, crtc, encoder)
  2847. if (encoder->pre_enable)
  2848. encoder->pre_enable(encoder);
  2849. if (intel_crtc->config.has_pch_encoder) {
  2850. /* Note: FDI PLL enabling _must_ be done before we enable the
  2851. * cpu pipes, hence this is separate from all the other fdi/pch
  2852. * enabling. */
  2853. ironlake_fdi_pll_enable(intel_crtc);
  2854. } else {
  2855. assert_fdi_tx_disabled(dev_priv, pipe);
  2856. assert_fdi_rx_disabled(dev_priv, pipe);
  2857. }
  2858. ironlake_pfit_enable(intel_crtc);
  2859. /*
  2860. * On ILK+ LUT must be loaded before the pipe is running but with
  2861. * clocks enabled
  2862. */
  2863. intel_crtc_load_lut(crtc);
  2864. intel_update_watermarks(crtc);
  2865. intel_enable_pipe(dev_priv, pipe,
  2866. intel_crtc->config.has_pch_encoder, false);
  2867. intel_enable_plane(dev_priv, plane, pipe);
  2868. intel_enable_planes(crtc);
  2869. intel_crtc_update_cursor(crtc, true);
  2870. if (intel_crtc->config.has_pch_encoder)
  2871. ironlake_pch_enable(crtc);
  2872. mutex_lock(&dev->struct_mutex);
  2873. intel_update_fbc(dev);
  2874. mutex_unlock(&dev->struct_mutex);
  2875. for_each_encoder_on_crtc(dev, crtc, encoder)
  2876. encoder->enable(encoder);
  2877. if (HAS_PCH_CPT(dev))
  2878. cpt_verify_modeset(dev, intel_crtc->pipe);
  2879. /*
  2880. * There seems to be a race in PCH platform hw (at least on some
  2881. * outputs) where an enabled pipe still completes any pageflip right
  2882. * away (as if the pipe is off) instead of waiting for vblank. As soon
  2883. * as the first vblank happend, everything works as expected. Hence just
  2884. * wait for one vblank before returning to avoid strange things
  2885. * happening.
  2886. */
  2887. intel_wait_for_vblank(dev, intel_crtc->pipe);
  2888. }
  2889. /* IPS only exists on ULT machines and is tied to pipe A. */
  2890. static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
  2891. {
  2892. return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
  2893. }
  2894. static void hsw_enable_ips(struct intel_crtc *crtc)
  2895. {
  2896. struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  2897. if (!crtc->config.ips_enabled)
  2898. return;
  2899. /* We can only enable IPS after we enable a plane and wait for a vblank.
  2900. * We guarantee that the plane is enabled by calling intel_enable_ips
  2901. * only after intel_enable_plane. And intel_enable_plane already waits
  2902. * for a vblank, so all we need to do here is to enable the IPS bit. */
  2903. assert_plane_enabled(dev_priv, crtc->plane);
  2904. I915_WRITE(IPS_CTL, IPS_ENABLE);
  2905. }
  2906. static void hsw_disable_ips(struct intel_crtc *crtc)
  2907. {
  2908. struct drm_device *dev = crtc->base.dev;
  2909. struct drm_i915_private *dev_priv = dev->dev_private;
  2910. if (!crtc->config.ips_enabled)
  2911. return;
  2912. assert_plane_enabled(dev_priv, crtc->plane);
  2913. I915_WRITE(IPS_CTL, 0);
  2914. POSTING_READ(IPS_CTL);
  2915. /* We need to wait for a vblank before we can disable the plane. */
  2916. intel_wait_for_vblank(dev, crtc->pipe);
  2917. }
  2918. static void haswell_crtc_enable(struct drm_crtc *crtc)
  2919. {
  2920. struct drm_device *dev = crtc->dev;
  2921. struct drm_i915_private *dev_priv = dev->dev_private;
  2922. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2923. struct intel_encoder *encoder;
  2924. int pipe = intel_crtc->pipe;
  2925. int plane = intel_crtc->plane;
  2926. WARN_ON(!crtc->enabled);
  2927. if (intel_crtc->active)
  2928. return;
  2929. intel_crtc->active = true;
  2930. intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
  2931. if (intel_crtc->config.has_pch_encoder)
  2932. intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
  2933. if (intel_crtc->config.has_pch_encoder)
  2934. dev_priv->display.fdi_link_train(crtc);
  2935. for_each_encoder_on_crtc(dev, crtc, encoder)
  2936. if (encoder->pre_enable)
  2937. encoder->pre_enable(encoder);
  2938. intel_ddi_enable_pipe_clock(intel_crtc);
  2939. ironlake_pfit_enable(intel_crtc);
  2940. /*
  2941. * On ILK+ LUT must be loaded before the pipe is running but with
  2942. * clocks enabled
  2943. */
  2944. intel_crtc_load_lut(crtc);
  2945. intel_ddi_set_pipe_settings(crtc);
  2946. intel_ddi_enable_transcoder_func(crtc);
  2947. intel_update_watermarks(crtc);
  2948. intel_enable_pipe(dev_priv, pipe,
  2949. intel_crtc->config.has_pch_encoder, false);
  2950. intel_enable_plane(dev_priv, plane, pipe);
  2951. intel_enable_planes(crtc);
  2952. intel_crtc_update_cursor(crtc, true);
  2953. hsw_enable_ips(intel_crtc);
  2954. if (intel_crtc->config.has_pch_encoder)
  2955. lpt_pch_enable(crtc);
  2956. mutex_lock(&dev->struct_mutex);
  2957. intel_update_fbc(dev);
  2958. mutex_unlock(&dev->struct_mutex);
  2959. for_each_encoder_on_crtc(dev, crtc, encoder) {
  2960. encoder->enable(encoder);
  2961. intel_opregion_notify_encoder(encoder, true);
  2962. }
  2963. /*
  2964. * There seems to be a race in PCH platform hw (at least on some
  2965. * outputs) where an enabled pipe still completes any pageflip right
  2966. * away (as if the pipe is off) instead of waiting for vblank. As soon
  2967. * as the first vblank happend, everything works as expected. Hence just
  2968. * wait for one vblank before returning to avoid strange things
  2969. * happening.
  2970. */
  2971. intel_wait_for_vblank(dev, intel_crtc->pipe);
  2972. }
  2973. static void ironlake_pfit_disable(struct intel_crtc *crtc)
  2974. {
  2975. struct drm_device *dev = crtc->base.dev;
  2976. struct drm_i915_private *dev_priv = dev->dev_private;
  2977. int pipe = crtc->pipe;
  2978. /* To avoid upsetting the power well on haswell only disable the pfit if
  2979. * it's in use. The hw state code will make sure we get this right. */
  2980. if (crtc->config.pch_pfit.size) {
  2981. I915_WRITE(PF_CTL(pipe), 0);
  2982. I915_WRITE(PF_WIN_POS(pipe), 0);
  2983. I915_WRITE(PF_WIN_SZ(pipe), 0);
  2984. }
  2985. }
  2986. static void ironlake_crtc_disable(struct drm_crtc *crtc)
  2987. {
  2988. struct drm_device *dev = crtc->dev;
  2989. struct drm_i915_private *dev_priv = dev->dev_private;
  2990. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2991. struct intel_encoder *encoder;
  2992. int pipe = intel_crtc->pipe;
  2993. int plane = intel_crtc->plane;
  2994. u32 reg, temp;
  2995. if (!intel_crtc->active)
  2996. return;
  2997. for_each_encoder_on_crtc(dev, crtc, encoder)
  2998. encoder->disable(encoder);
  2999. intel_crtc_wait_for_pending_flips(crtc);
  3000. drm_vblank_off(dev, pipe);
  3001. if (dev_priv->fbc.plane == plane)
  3002. intel_disable_fbc(dev);
  3003. intel_crtc_update_cursor(crtc, false);
  3004. intel_disable_planes(crtc);
  3005. intel_disable_plane(dev_priv, plane, pipe);
  3006. if (intel_crtc->config.has_pch_encoder)
  3007. intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
  3008. intel_disable_pipe(dev_priv, pipe);
  3009. ironlake_pfit_disable(intel_crtc);
  3010. for_each_encoder_on_crtc(dev, crtc, encoder)
  3011. if (encoder->post_disable)
  3012. encoder->post_disable(encoder);
  3013. if (intel_crtc->config.has_pch_encoder) {
  3014. ironlake_fdi_disable(crtc);
  3015. ironlake_disable_pch_transcoder(dev_priv, pipe);
  3016. intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
  3017. if (HAS_PCH_CPT(dev)) {
  3018. /* disable TRANS_DP_CTL */
  3019. reg = TRANS_DP_CTL(pipe);
  3020. temp = I915_READ(reg);
  3021. temp &= ~(TRANS_DP_OUTPUT_ENABLE |
  3022. TRANS_DP_PORT_SEL_MASK);
  3023. temp |= TRANS_DP_PORT_SEL_NONE;
  3024. I915_WRITE(reg, temp);
  3025. /* disable DPLL_SEL */
  3026. temp = I915_READ(PCH_DPLL_SEL);
  3027. temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
  3028. I915_WRITE(PCH_DPLL_SEL, temp);
  3029. }
  3030. /* disable PCH DPLL */
  3031. intel_disable_shared_dpll(intel_crtc);
  3032. ironlake_fdi_pll_disable(intel_crtc);
  3033. }
  3034. intel_crtc->active = false;
  3035. intel_update_watermarks(crtc);
  3036. mutex_lock(&dev->struct_mutex);
  3037. intel_update_fbc(dev);
  3038. mutex_unlock(&dev->struct_mutex);
  3039. }
  3040. static void haswell_crtc_disable(struct drm_crtc *crtc)
  3041. {
  3042. struct drm_device *dev = crtc->dev;
  3043. struct drm_i915_private *dev_priv = dev->dev_private;
  3044. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3045. struct intel_encoder *encoder;
  3046. int pipe = intel_crtc->pipe;
  3047. int plane = intel_crtc->plane;
  3048. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  3049. if (!intel_crtc->active)
  3050. return;
  3051. for_each_encoder_on_crtc(dev, crtc, encoder) {
  3052. intel_opregion_notify_encoder(encoder, false);
  3053. encoder->disable(encoder);
  3054. }
  3055. intel_crtc_wait_for_pending_flips(crtc);
  3056. drm_vblank_off(dev, pipe);
  3057. /* FBC must be disabled before disabling the plane on HSW. */
  3058. if (dev_priv->fbc.plane == plane)
  3059. intel_disable_fbc(dev);
  3060. hsw_disable_ips(intel_crtc);
  3061. intel_crtc_update_cursor(crtc, false);
  3062. intel_disable_planes(crtc);
  3063. intel_disable_plane(dev_priv, plane, pipe);
  3064. if (intel_crtc->config.has_pch_encoder)
  3065. intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
  3066. intel_disable_pipe(dev_priv, pipe);
  3067. intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
  3068. ironlake_pfit_disable(intel_crtc);
  3069. intel_ddi_disable_pipe_clock(intel_crtc);
  3070. for_each_encoder_on_crtc(dev, crtc, encoder)
  3071. if (encoder->post_disable)
  3072. encoder->post_disable(encoder);
  3073. if (intel_crtc->config.has_pch_encoder) {
  3074. lpt_disable_pch_transcoder(dev_priv);
  3075. intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
  3076. intel_ddi_fdi_disable(crtc);
  3077. }
  3078. intel_crtc->active = false;
  3079. intel_update_watermarks(crtc);
  3080. mutex_lock(&dev->struct_mutex);
  3081. intel_update_fbc(dev);
  3082. mutex_unlock(&dev->struct_mutex);
  3083. }
  3084. static void ironlake_crtc_off(struct drm_crtc *crtc)
  3085. {
  3086. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3087. intel_put_shared_dpll(intel_crtc);
  3088. }
  3089. static void haswell_crtc_off(struct drm_crtc *crtc)
  3090. {
  3091. intel_ddi_put_crtc_pll(crtc);
  3092. }
  3093. static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
  3094. {
  3095. if (!enable && intel_crtc->overlay) {
  3096. struct drm_device *dev = intel_crtc->base.dev;
  3097. struct drm_i915_private *dev_priv = dev->dev_private;
  3098. mutex_lock(&dev->struct_mutex);
  3099. dev_priv->mm.interruptible = false;
  3100. (void) intel_overlay_switch_off(intel_crtc->overlay);
  3101. dev_priv->mm.interruptible = true;
  3102. mutex_unlock(&dev->struct_mutex);
  3103. }
  3104. /* Let userspace switch the overlay on again. In most cases userspace
  3105. * has to recompute where to put it anyway.
  3106. */
  3107. }
  3108. /**
  3109. * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
  3110. * cursor plane briefly if not already running after enabling the display
  3111. * plane.
  3112. * This workaround avoids occasional blank screens when self refresh is
  3113. * enabled.
  3114. */
  3115. static void
  3116. g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
  3117. {
  3118. u32 cntl = I915_READ(CURCNTR(pipe));
  3119. if ((cntl & CURSOR_MODE) == 0) {
  3120. u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
  3121. I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
  3122. I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
  3123. intel_wait_for_vblank(dev_priv->dev, pipe);
  3124. I915_WRITE(CURCNTR(pipe), cntl);
  3125. I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
  3126. I915_WRITE(FW_BLC_SELF, fw_bcl_self);
  3127. }
  3128. }
  3129. static void i9xx_pfit_enable(struct intel_crtc *crtc)
  3130. {
  3131. struct drm_device *dev = crtc->base.dev;
  3132. struct drm_i915_private *dev_priv = dev->dev_private;
  3133. struct intel_crtc_config *pipe_config = &crtc->config;
  3134. if (!crtc->config.gmch_pfit.control)
  3135. return;
  3136. /*
  3137. * The panel fitter should only be adjusted whilst the pipe is disabled,
  3138. * according to register description and PRM.
  3139. */
  3140. WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
  3141. assert_pipe_disabled(dev_priv, crtc->pipe);
  3142. I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
  3143. I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
  3144. /* Border color in case we don't scale up to the full screen. Black by
  3145. * default, change to something else for debugging. */
  3146. I915_WRITE(BCLRPAT(crtc->pipe), 0);
  3147. }
  3148. static void valleyview_crtc_enable(struct drm_crtc *crtc)
  3149. {
  3150. struct drm_device *dev = crtc->dev;
  3151. struct drm_i915_private *dev_priv = dev->dev_private;
  3152. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3153. struct intel_encoder *encoder;
  3154. int pipe = intel_crtc->pipe;
  3155. int plane = intel_crtc->plane;
  3156. bool is_dsi;
  3157. WARN_ON(!crtc->enabled);
  3158. if (intel_crtc->active)
  3159. return;
  3160. intel_crtc->active = true;
  3161. for_each_encoder_on_crtc(dev, crtc, encoder)
  3162. if (encoder->pre_pll_enable)
  3163. encoder->pre_pll_enable(encoder);
  3164. is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
  3165. if (!is_dsi)
  3166. vlv_enable_pll(intel_crtc);
  3167. for_each_encoder_on_crtc(dev, crtc, encoder)
  3168. if (encoder->pre_enable)
  3169. encoder->pre_enable(encoder);
  3170. i9xx_pfit_enable(intel_crtc);
  3171. intel_crtc_load_lut(crtc);
  3172. intel_update_watermarks(crtc);
  3173. intel_enable_pipe(dev_priv, pipe, false, is_dsi);
  3174. intel_enable_plane(dev_priv, plane, pipe);
  3175. intel_enable_planes(crtc);
  3176. intel_crtc_update_cursor(crtc, true);
  3177. intel_update_fbc(dev);
  3178. for_each_encoder_on_crtc(dev, crtc, encoder)
  3179. encoder->enable(encoder);
  3180. }
  3181. static void i9xx_crtc_enable(struct drm_crtc *crtc)
  3182. {
  3183. struct drm_device *dev = crtc->dev;
  3184. struct drm_i915_private *dev_priv = dev->dev_private;
  3185. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3186. struct intel_encoder *encoder;
  3187. int pipe = intel_crtc->pipe;
  3188. int plane = intel_crtc->plane;
  3189. WARN_ON(!crtc->enabled);
  3190. if (intel_crtc->active)
  3191. return;
  3192. intel_crtc->active = true;
  3193. for_each_encoder_on_crtc(dev, crtc, encoder)
  3194. if (encoder->pre_enable)
  3195. encoder->pre_enable(encoder);
  3196. i9xx_enable_pll(intel_crtc);
  3197. i9xx_pfit_enable(intel_crtc);
  3198. intel_crtc_load_lut(crtc);
  3199. intel_update_watermarks(crtc);
  3200. intel_enable_pipe(dev_priv, pipe, false, false);
  3201. intel_enable_plane(dev_priv, plane, pipe);
  3202. intel_enable_planes(crtc);
  3203. /* The fixup needs to happen before cursor is enabled */
  3204. if (IS_G4X(dev))
  3205. g4x_fixup_plane(dev_priv, pipe);
  3206. intel_crtc_update_cursor(crtc, true);
  3207. /* Give the overlay scaler a chance to enable if it's on this pipe */
  3208. intel_crtc_dpms_overlay(intel_crtc, true);
  3209. intel_update_fbc(dev);
  3210. for_each_encoder_on_crtc(dev, crtc, encoder)
  3211. encoder->enable(encoder);
  3212. }
  3213. static void i9xx_pfit_disable(struct intel_crtc *crtc)
  3214. {
  3215. struct drm_device *dev = crtc->base.dev;
  3216. struct drm_i915_private *dev_priv = dev->dev_private;
  3217. if (!crtc->config.gmch_pfit.control)
  3218. return;
  3219. assert_pipe_disabled(dev_priv, crtc->pipe);
  3220. DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
  3221. I915_READ(PFIT_CONTROL));
  3222. I915_WRITE(PFIT_CONTROL, 0);
  3223. }
  3224. static void i9xx_crtc_disable(struct drm_crtc *crtc)
  3225. {
  3226. struct drm_device *dev = crtc->dev;
  3227. struct drm_i915_private *dev_priv = dev->dev_private;
  3228. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3229. struct intel_encoder *encoder;
  3230. int pipe = intel_crtc->pipe;
  3231. int plane = intel_crtc->plane;
  3232. if (!intel_crtc->active)
  3233. return;
  3234. for_each_encoder_on_crtc(dev, crtc, encoder)
  3235. encoder->disable(encoder);
  3236. /* Give the overlay scaler a chance to disable if it's on this pipe */
  3237. intel_crtc_wait_for_pending_flips(crtc);
  3238. drm_vblank_off(dev, pipe);
  3239. if (dev_priv->fbc.plane == plane)
  3240. intel_disable_fbc(dev);
  3241. intel_crtc_dpms_overlay(intel_crtc, false);
  3242. intel_crtc_update_cursor(crtc, false);
  3243. intel_disable_planes(crtc);
  3244. intel_disable_plane(dev_priv, plane, pipe);
  3245. intel_disable_pipe(dev_priv, pipe);
  3246. i9xx_pfit_disable(intel_crtc);
  3247. for_each_encoder_on_crtc(dev, crtc, encoder)
  3248. if (encoder->post_disable)
  3249. encoder->post_disable(encoder);
  3250. if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
  3251. i9xx_disable_pll(dev_priv, pipe);
  3252. intel_crtc->active = false;
  3253. intel_update_watermarks(crtc);
  3254. intel_update_fbc(dev);
  3255. }
  3256. static void i9xx_crtc_off(struct drm_crtc *crtc)
  3257. {
  3258. }
  3259. static void intel_crtc_update_sarea(struct drm_crtc *crtc,
  3260. bool enabled)
  3261. {
  3262. struct drm_device *dev = crtc->dev;
  3263. struct drm_i915_master_private *master_priv;
  3264. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3265. int pipe = intel_crtc->pipe;
  3266. if (!dev->primary->master)
  3267. return;
  3268. master_priv = dev->primary->master->driver_priv;
  3269. if (!master_priv->sarea_priv)
  3270. return;
  3271. switch (pipe) {
  3272. case 0:
  3273. master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
  3274. master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
  3275. break;
  3276. case 1:
  3277. master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
  3278. master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
  3279. break;
  3280. default:
  3281. DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
  3282. break;
  3283. }
  3284. }
  3285. /**
  3286. * Sets the power management mode of the pipe and plane.
  3287. */
  3288. void intel_crtc_update_dpms(struct drm_crtc *crtc)
  3289. {
  3290. struct drm_device *dev = crtc->dev;
  3291. struct drm_i915_private *dev_priv = dev->dev_private;
  3292. struct intel_encoder *intel_encoder;
  3293. bool enable = false;
  3294. for_each_encoder_on_crtc(dev, crtc, intel_encoder)
  3295. enable |= intel_encoder->connectors_active;
  3296. if (enable)
  3297. dev_priv->display.crtc_enable(crtc);
  3298. else
  3299. dev_priv->display.crtc_disable(crtc);
  3300. intel_crtc_update_sarea(crtc, enable);
  3301. }
  3302. static void intel_crtc_disable(struct drm_crtc *crtc)
  3303. {
  3304. struct drm_device *dev = crtc->dev;
  3305. struct drm_connector *connector;
  3306. struct drm_i915_private *dev_priv = dev->dev_private;
  3307. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3308. /* crtc should still be enabled when we disable it. */
  3309. WARN_ON(!crtc->enabled);
  3310. dev_priv->display.crtc_disable(crtc);
  3311. intel_crtc->eld_vld = false;
  3312. intel_crtc_update_sarea(crtc, false);
  3313. dev_priv->display.off(crtc);
  3314. assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
  3315. assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
  3316. assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
  3317. if (crtc->fb) {
  3318. mutex_lock(&dev->struct_mutex);
  3319. intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
  3320. mutex_unlock(&dev->struct_mutex);
  3321. crtc->fb = NULL;
  3322. }
  3323. /* Update computed state. */
  3324. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  3325. if (!connector->encoder || !connector->encoder->crtc)
  3326. continue;
  3327. if (connector->encoder->crtc != crtc)
  3328. continue;
  3329. connector->dpms = DRM_MODE_DPMS_OFF;
  3330. to_intel_encoder(connector->encoder)->connectors_active = false;
  3331. }
  3332. }
  3333. void intel_encoder_destroy(struct drm_encoder *encoder)
  3334. {
  3335. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  3336. drm_encoder_cleanup(encoder);
  3337. kfree(intel_encoder);
  3338. }
  3339. /* Simple dpms helper for encoders with just one connector, no cloning and only
  3340. * one kind of off state. It clamps all !ON modes to fully OFF and changes the
  3341. * state of the entire output pipe. */
  3342. static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
  3343. {
  3344. if (mode == DRM_MODE_DPMS_ON) {
  3345. encoder->connectors_active = true;
  3346. intel_crtc_update_dpms(encoder->base.crtc);
  3347. } else {
  3348. encoder->connectors_active = false;
  3349. intel_crtc_update_dpms(encoder->base.crtc);
  3350. }
  3351. }
  3352. /* Cross check the actual hw state with our own modeset state tracking (and it's
  3353. * internal consistency). */
  3354. static void intel_connector_check_state(struct intel_connector *connector)
  3355. {
  3356. if (connector->get_hw_state(connector)) {
  3357. struct intel_encoder *encoder = connector->encoder;
  3358. struct drm_crtc *crtc;
  3359. bool encoder_enabled;
  3360. enum pipe pipe;
  3361. DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  3362. connector->base.base.id,
  3363. drm_get_connector_name(&connector->base));
  3364. WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
  3365. "wrong connector dpms state\n");
  3366. WARN(connector->base.encoder != &encoder->base,
  3367. "active connector not linked to encoder\n");
  3368. WARN(!encoder->connectors_active,
  3369. "encoder->connectors_active not set\n");
  3370. encoder_enabled = encoder->get_hw_state(encoder, &pipe);
  3371. WARN(!encoder_enabled, "encoder not enabled\n");
  3372. if (WARN_ON(!encoder->base.crtc))
  3373. return;
  3374. crtc = encoder->base.crtc;
  3375. WARN(!crtc->enabled, "crtc not enabled\n");
  3376. WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
  3377. WARN(pipe != to_intel_crtc(crtc)->pipe,
  3378. "encoder active on the wrong pipe\n");
  3379. }
  3380. }
  3381. /* Even simpler default implementation, if there's really no special case to
  3382. * consider. */
  3383. void intel_connector_dpms(struct drm_connector *connector, int mode)
  3384. {
  3385. struct intel_encoder *encoder = intel_attached_encoder(connector);
  3386. /* All the simple cases only support two dpms states. */
  3387. if (mode != DRM_MODE_DPMS_ON)
  3388. mode = DRM_MODE_DPMS_OFF;
  3389. if (mode == connector->dpms)
  3390. return;
  3391. connector->dpms = mode;
  3392. /* Only need to change hw state when actually enabled */
  3393. if (encoder->base.crtc)
  3394. intel_encoder_dpms(encoder, mode);
  3395. else
  3396. WARN_ON(encoder->connectors_active != false);
  3397. intel_modeset_check_state(connector->dev);
  3398. }
  3399. /* Simple connector->get_hw_state implementation for encoders that support only
  3400. * one connector and no cloning and hence the encoder state determines the state
  3401. * of the connector. */
  3402. bool intel_connector_get_hw_state(struct intel_connector *connector)
  3403. {
  3404. enum pipe pipe = 0;
  3405. struct intel_encoder *encoder = connector->encoder;
  3406. return encoder->get_hw_state(encoder, &pipe);
  3407. }
  3408. static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
  3409. struct intel_crtc_config *pipe_config)
  3410. {
  3411. struct drm_i915_private *dev_priv = dev->dev_private;
  3412. struct intel_crtc *pipe_B_crtc =
  3413. to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
  3414. DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
  3415. pipe_name(pipe), pipe_config->fdi_lanes);
  3416. if (pipe_config->fdi_lanes > 4) {
  3417. DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
  3418. pipe_name(pipe), pipe_config->fdi_lanes);
  3419. return false;
  3420. }
  3421. if (IS_HASWELL(dev)) {
  3422. if (pipe_config->fdi_lanes > 2) {
  3423. DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
  3424. pipe_config->fdi_lanes);
  3425. return false;
  3426. } else {
  3427. return true;
  3428. }
  3429. }
  3430. if (INTEL_INFO(dev)->num_pipes == 2)
  3431. return true;
  3432. /* Ivybridge 3 pipe is really complicated */
  3433. switch (pipe) {
  3434. case PIPE_A:
  3435. return true;
  3436. case PIPE_B:
  3437. if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
  3438. pipe_config->fdi_lanes > 2) {
  3439. DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
  3440. pipe_name(pipe), pipe_config->fdi_lanes);
  3441. return false;
  3442. }
  3443. return true;
  3444. case PIPE_C:
  3445. if (!pipe_has_enabled_pch(pipe_B_crtc) ||
  3446. pipe_B_crtc->config.fdi_lanes <= 2) {
  3447. if (pipe_config->fdi_lanes > 2) {
  3448. DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
  3449. pipe_name(pipe), pipe_config->fdi_lanes);
  3450. return false;
  3451. }
  3452. } else {
  3453. DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
  3454. return false;
  3455. }
  3456. return true;
  3457. default:
  3458. BUG();
  3459. }
  3460. }
  3461. #define RETRY 1
  3462. static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
  3463. struct intel_crtc_config *pipe_config)
  3464. {
  3465. struct drm_device *dev = intel_crtc->base.dev;
  3466. struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
  3467. int lane, link_bw, fdi_dotclock;
  3468. bool setup_ok, needs_recompute = false;
  3469. retry:
  3470. /* FDI is a binary signal running at ~2.7GHz, encoding
  3471. * each output octet as 10 bits. The actual frequency
  3472. * is stored as a divider into a 100MHz clock, and the
  3473. * mode pixel clock is stored in units of 1KHz.
  3474. * Hence the bw of each lane in terms of the mode signal
  3475. * is:
  3476. */
  3477. link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
  3478. fdi_dotclock = adjusted_mode->clock;
  3479. lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
  3480. pipe_config->pipe_bpp);
  3481. pipe_config->fdi_lanes = lane;
  3482. intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
  3483. link_bw, &pipe_config->fdi_m_n);
  3484. setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
  3485. intel_crtc->pipe, pipe_config);
  3486. if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
  3487. pipe_config->pipe_bpp -= 2*3;
  3488. DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
  3489. pipe_config->pipe_bpp);
  3490. needs_recompute = true;
  3491. pipe_config->bw_constrained = true;
  3492. goto retry;
  3493. }
  3494. if (needs_recompute)
  3495. return RETRY;
  3496. return setup_ok ? 0 : -EINVAL;
  3497. }
  3498. static void hsw_compute_ips_config(struct intel_crtc *crtc,
  3499. struct intel_crtc_config *pipe_config)
  3500. {
  3501. pipe_config->ips_enabled = i915_enable_ips &&
  3502. hsw_crtc_supports_ips(crtc) &&
  3503. pipe_config->pipe_bpp <= 24;
  3504. }
  3505. static int intel_crtc_compute_config(struct intel_crtc *crtc,
  3506. struct intel_crtc_config *pipe_config)
  3507. {
  3508. struct drm_device *dev = crtc->base.dev;
  3509. struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
  3510. /* FIXME should check pixel clock limits on all platforms */
  3511. if (INTEL_INFO(dev)->gen < 4) {
  3512. struct drm_i915_private *dev_priv = dev->dev_private;
  3513. int clock_limit =
  3514. dev_priv->display.get_display_clock_speed(dev);
  3515. /*
  3516. * Enable pixel doubling when the dot clock
  3517. * is > 90% of the (display) core speed.
  3518. *
  3519. * GDG double wide on either pipe,
  3520. * otherwise pipe A only.
  3521. */
  3522. if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
  3523. adjusted_mode->clock > clock_limit * 9 / 10) {
  3524. clock_limit *= 2;
  3525. pipe_config->double_wide = true;
  3526. }
  3527. if (adjusted_mode->clock > clock_limit * 9 / 10)
  3528. return -EINVAL;
  3529. }
  3530. /*
  3531. * Pipe horizontal size must be even in:
  3532. * - DVO ganged mode
  3533. * - LVDS dual channel mode
  3534. * - Double wide pipe
  3535. */
  3536. if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
  3537. intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
  3538. pipe_config->pipe_src_w &= ~1;
  3539. /* Cantiga+ cannot handle modes with a hsync front porch of 0.
  3540. * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
  3541. */
  3542. if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
  3543. adjusted_mode->hsync_start == adjusted_mode->hdisplay)
  3544. return -EINVAL;
  3545. if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
  3546. pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
  3547. } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
  3548. /* only a 8bpc pipe, with 6bpc dither through the panel fitter
  3549. * for lvds. */
  3550. pipe_config->pipe_bpp = 8*3;
  3551. }
  3552. if (HAS_IPS(dev))
  3553. hsw_compute_ips_config(crtc, pipe_config);
  3554. /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
  3555. * clock survives for now. */
  3556. if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  3557. pipe_config->shared_dpll = crtc->config.shared_dpll;
  3558. if (pipe_config->has_pch_encoder)
  3559. return ironlake_fdi_compute_config(crtc, pipe_config);
  3560. return 0;
  3561. }
  3562. static int valleyview_get_display_clock_speed(struct drm_device *dev)
  3563. {
  3564. return 400000; /* FIXME */
  3565. }
  3566. static int i945_get_display_clock_speed(struct drm_device *dev)
  3567. {
  3568. return 400000;
  3569. }
  3570. static int i915_get_display_clock_speed(struct drm_device *dev)
  3571. {
  3572. return 333000;
  3573. }
  3574. static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
  3575. {
  3576. return 200000;
  3577. }
  3578. static int pnv_get_display_clock_speed(struct drm_device *dev)
  3579. {
  3580. u16 gcfgc = 0;
  3581. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  3582. switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  3583. case GC_DISPLAY_CLOCK_267_MHZ_PNV:
  3584. return 267000;
  3585. case GC_DISPLAY_CLOCK_333_MHZ_PNV:
  3586. return 333000;
  3587. case GC_DISPLAY_CLOCK_444_MHZ_PNV:
  3588. return 444000;
  3589. case GC_DISPLAY_CLOCK_200_MHZ_PNV:
  3590. return 200000;
  3591. default:
  3592. DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
  3593. case GC_DISPLAY_CLOCK_133_MHZ_PNV:
  3594. return 133000;
  3595. case GC_DISPLAY_CLOCK_167_MHZ_PNV:
  3596. return 167000;
  3597. }
  3598. }
  3599. static int i915gm_get_display_clock_speed(struct drm_device *dev)
  3600. {
  3601. u16 gcfgc = 0;
  3602. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  3603. if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
  3604. return 133000;
  3605. else {
  3606. switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  3607. case GC_DISPLAY_CLOCK_333_MHZ:
  3608. return 333000;
  3609. default:
  3610. case GC_DISPLAY_CLOCK_190_200_MHZ:
  3611. return 190000;
  3612. }
  3613. }
  3614. }
  3615. static int i865_get_display_clock_speed(struct drm_device *dev)
  3616. {
  3617. return 266000;
  3618. }
  3619. static int i855_get_display_clock_speed(struct drm_device *dev)
  3620. {
  3621. u16 hpllcc = 0;
  3622. /* Assume that the hardware is in the high speed state. This
  3623. * should be the default.
  3624. */
  3625. switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
  3626. case GC_CLOCK_133_200:
  3627. case GC_CLOCK_100_200:
  3628. return 200000;
  3629. case GC_CLOCK_166_250:
  3630. return 250000;
  3631. case GC_CLOCK_100_133:
  3632. return 133000;
  3633. }
  3634. /* Shouldn't happen */
  3635. return 0;
  3636. }
  3637. static int i830_get_display_clock_speed(struct drm_device *dev)
  3638. {
  3639. return 133000;
  3640. }
  3641. static void
  3642. intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
  3643. {
  3644. while (*num > DATA_LINK_M_N_MASK ||
  3645. *den > DATA_LINK_M_N_MASK) {
  3646. *num >>= 1;
  3647. *den >>= 1;
  3648. }
  3649. }
  3650. static void compute_m_n(unsigned int m, unsigned int n,
  3651. uint32_t *ret_m, uint32_t *ret_n)
  3652. {
  3653. *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
  3654. *ret_m = div_u64((uint64_t) m * *ret_n, n);
  3655. intel_reduce_m_n_ratio(ret_m, ret_n);
  3656. }
  3657. void
  3658. intel_link_compute_m_n(int bits_per_pixel, int nlanes,
  3659. int pixel_clock, int link_clock,
  3660. struct intel_link_m_n *m_n)
  3661. {
  3662. m_n->tu = 64;
  3663. compute_m_n(bits_per_pixel * pixel_clock,
  3664. link_clock * nlanes * 8,
  3665. &m_n->gmch_m, &m_n->gmch_n);
  3666. compute_m_n(pixel_clock, link_clock,
  3667. &m_n->link_m, &m_n->link_n);
  3668. }
  3669. static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
  3670. {
  3671. if (i915_panel_use_ssc >= 0)
  3672. return i915_panel_use_ssc != 0;
  3673. return dev_priv->vbt.lvds_use_ssc
  3674. && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
  3675. }
  3676. static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
  3677. {
  3678. struct drm_device *dev = crtc->dev;
  3679. struct drm_i915_private *dev_priv = dev->dev_private;
  3680. int refclk;
  3681. if (IS_VALLEYVIEW(dev)) {
  3682. refclk = 100000;
  3683. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  3684. intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
  3685. refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
  3686. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  3687. refclk / 1000);
  3688. } else if (!IS_GEN2(dev)) {
  3689. refclk = 96000;
  3690. } else {
  3691. refclk = 48000;
  3692. }
  3693. return refclk;
  3694. }
  3695. static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
  3696. {
  3697. return (1 << dpll->n) << 16 | dpll->m2;
  3698. }
  3699. static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
  3700. {
  3701. return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
  3702. }
  3703. static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
  3704. intel_clock_t *reduced_clock)
  3705. {
  3706. struct drm_device *dev = crtc->base.dev;
  3707. struct drm_i915_private *dev_priv = dev->dev_private;
  3708. int pipe = crtc->pipe;
  3709. u32 fp, fp2 = 0;
  3710. if (IS_PINEVIEW(dev)) {
  3711. fp = pnv_dpll_compute_fp(&crtc->config.dpll);
  3712. if (reduced_clock)
  3713. fp2 = pnv_dpll_compute_fp(reduced_clock);
  3714. } else {
  3715. fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
  3716. if (reduced_clock)
  3717. fp2 = i9xx_dpll_compute_fp(reduced_clock);
  3718. }
  3719. I915_WRITE(FP0(pipe), fp);
  3720. crtc->config.dpll_hw_state.fp0 = fp;
  3721. crtc->lowfreq_avail = false;
  3722. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
  3723. reduced_clock && i915_powersave) {
  3724. I915_WRITE(FP1(pipe), fp2);
  3725. crtc->config.dpll_hw_state.fp1 = fp2;
  3726. crtc->lowfreq_avail = true;
  3727. } else {
  3728. I915_WRITE(FP1(pipe), fp);
  3729. crtc->config.dpll_hw_state.fp1 = fp;
  3730. }
  3731. }
  3732. static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
  3733. pipe)
  3734. {
  3735. u32 reg_val;
  3736. /*
  3737. * PLLB opamp always calibrates to max value of 0x3f, force enable it
  3738. * and set it to a reasonable value instead.
  3739. */
  3740. reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
  3741. reg_val &= 0xffffff00;
  3742. reg_val |= 0x00000030;
  3743. vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
  3744. reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
  3745. reg_val &= 0x8cffffff;
  3746. reg_val = 0x8c000000;
  3747. vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
  3748. reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
  3749. reg_val &= 0xffffff00;
  3750. vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
  3751. reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
  3752. reg_val &= 0x00ffffff;
  3753. reg_val |= 0xb0000000;
  3754. vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
  3755. }
  3756. static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
  3757. struct intel_link_m_n *m_n)
  3758. {
  3759. struct drm_device *dev = crtc->base.dev;
  3760. struct drm_i915_private *dev_priv = dev->dev_private;
  3761. int pipe = crtc->pipe;
  3762. I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
  3763. I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
  3764. I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
  3765. I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
  3766. }
  3767. static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  3768. struct intel_link_m_n *m_n)
  3769. {
  3770. struct drm_device *dev = crtc->base.dev;
  3771. struct drm_i915_private *dev_priv = dev->dev_private;
  3772. int pipe = crtc->pipe;
  3773. enum transcoder transcoder = crtc->config.cpu_transcoder;
  3774. if (INTEL_INFO(dev)->gen >= 5) {
  3775. I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
  3776. I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
  3777. I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
  3778. I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
  3779. } else {
  3780. I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
  3781. I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
  3782. I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
  3783. I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
  3784. }
  3785. }
  3786. static void intel_dp_set_m_n(struct intel_crtc *crtc)
  3787. {
  3788. if (crtc->config.has_pch_encoder)
  3789. intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
  3790. else
  3791. intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
  3792. }
  3793. static void vlv_update_pll(struct intel_crtc *crtc)
  3794. {
  3795. struct drm_device *dev = crtc->base.dev;
  3796. struct drm_i915_private *dev_priv = dev->dev_private;
  3797. int pipe = crtc->pipe;
  3798. u32 dpll, mdiv;
  3799. u32 bestn, bestm1, bestm2, bestp1, bestp2;
  3800. u32 coreclk, reg_val, dpll_md;
  3801. mutex_lock(&dev_priv->dpio_lock);
  3802. bestn = crtc->config.dpll.n;
  3803. bestm1 = crtc->config.dpll.m1;
  3804. bestm2 = crtc->config.dpll.m2;
  3805. bestp1 = crtc->config.dpll.p1;
  3806. bestp2 = crtc->config.dpll.p2;
  3807. /* See eDP HDMI DPIO driver vbios notes doc */
  3808. /* PLL B needs special handling */
  3809. if (pipe)
  3810. vlv_pllb_recal_opamp(dev_priv, pipe);
  3811. /* Set up Tx target for periodic Rcomp update */
  3812. vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
  3813. /* Disable target IRef on PLL */
  3814. reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
  3815. reg_val &= 0x00ffffff;
  3816. vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
  3817. /* Disable fast lock */
  3818. vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
  3819. /* Set idtafcrecal before PLL is enabled */
  3820. mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
  3821. mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
  3822. mdiv |= ((bestn << DPIO_N_SHIFT));
  3823. mdiv |= (1 << DPIO_K_SHIFT);
  3824. /*
  3825. * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
  3826. * but we don't support that).
  3827. * Note: don't use the DAC post divider as it seems unstable.
  3828. */
  3829. mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
  3830. vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
  3831. mdiv |= DPIO_ENABLE_CALIBRATION;
  3832. vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
  3833. /* Set HBR and RBR LPF coefficients */
  3834. if (crtc->config.port_clock == 162000 ||
  3835. intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
  3836. intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
  3837. vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
  3838. 0x009f0003);
  3839. else
  3840. vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
  3841. 0x00d0000f);
  3842. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
  3843. intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
  3844. /* Use SSC source */
  3845. if (!pipe)
  3846. vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
  3847. 0x0df40000);
  3848. else
  3849. vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
  3850. 0x0df70000);
  3851. } else { /* HDMI or VGA */
  3852. /* Use bend source */
  3853. if (!pipe)
  3854. vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
  3855. 0x0df70000);
  3856. else
  3857. vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
  3858. 0x0df40000);
  3859. }
  3860. coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
  3861. coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
  3862. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
  3863. intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
  3864. coreclk |= 0x01000000;
  3865. vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
  3866. vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
  3867. /* Enable DPIO clock input */
  3868. dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
  3869. DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
  3870. if (pipe)
  3871. dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
  3872. dpll |= DPLL_VCO_ENABLE;
  3873. crtc->config.dpll_hw_state.dpll = dpll;
  3874. dpll_md = (crtc->config.pixel_multiplier - 1)
  3875. << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  3876. crtc->config.dpll_hw_state.dpll_md = dpll_md;
  3877. if (crtc->config.has_dp_encoder)
  3878. intel_dp_set_m_n(crtc);
  3879. mutex_unlock(&dev_priv->dpio_lock);
  3880. }
  3881. static void i9xx_update_pll(struct intel_crtc *crtc,
  3882. intel_clock_t *reduced_clock,
  3883. int num_connectors)
  3884. {
  3885. struct drm_device *dev = crtc->base.dev;
  3886. struct drm_i915_private *dev_priv = dev->dev_private;
  3887. u32 dpll;
  3888. bool is_sdvo;
  3889. struct dpll *clock = &crtc->config.dpll;
  3890. i9xx_update_pll_dividers(crtc, reduced_clock);
  3891. is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
  3892. intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
  3893. dpll = DPLL_VGA_MODE_DIS;
  3894. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
  3895. dpll |= DPLLB_MODE_LVDS;
  3896. else
  3897. dpll |= DPLLB_MODE_DAC_SERIAL;
  3898. if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  3899. dpll |= (crtc->config.pixel_multiplier - 1)
  3900. << SDVO_MULTIPLIER_SHIFT_HIRES;
  3901. }
  3902. if (is_sdvo)
  3903. dpll |= DPLL_SDVO_HIGH_SPEED;
  3904. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
  3905. dpll |= DPLL_SDVO_HIGH_SPEED;
  3906. /* compute bitmask from p1 value */
  3907. if (IS_PINEVIEW(dev))
  3908. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
  3909. else {
  3910. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3911. if (IS_G4X(dev) && reduced_clock)
  3912. dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  3913. }
  3914. switch (clock->p2) {
  3915. case 5:
  3916. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  3917. break;
  3918. case 7:
  3919. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  3920. break;
  3921. case 10:
  3922. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  3923. break;
  3924. case 14:
  3925. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  3926. break;
  3927. }
  3928. if (INTEL_INFO(dev)->gen >= 4)
  3929. dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
  3930. if (crtc->config.sdvo_tv_clock)
  3931. dpll |= PLL_REF_INPUT_TVCLKINBC;
  3932. else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
  3933. intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  3934. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  3935. else
  3936. dpll |= PLL_REF_INPUT_DREFCLK;
  3937. dpll |= DPLL_VCO_ENABLE;
  3938. crtc->config.dpll_hw_state.dpll = dpll;
  3939. if (INTEL_INFO(dev)->gen >= 4) {
  3940. u32 dpll_md = (crtc->config.pixel_multiplier - 1)
  3941. << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  3942. crtc->config.dpll_hw_state.dpll_md = dpll_md;
  3943. }
  3944. if (crtc->config.has_dp_encoder)
  3945. intel_dp_set_m_n(crtc);
  3946. }
  3947. static void i8xx_update_pll(struct intel_crtc *crtc,
  3948. intel_clock_t *reduced_clock,
  3949. int num_connectors)
  3950. {
  3951. struct drm_device *dev = crtc->base.dev;
  3952. struct drm_i915_private *dev_priv = dev->dev_private;
  3953. u32 dpll;
  3954. struct dpll *clock = &crtc->config.dpll;
  3955. i9xx_update_pll_dividers(crtc, reduced_clock);
  3956. dpll = DPLL_VGA_MODE_DIS;
  3957. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
  3958. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3959. } else {
  3960. if (clock->p1 == 2)
  3961. dpll |= PLL_P1_DIVIDE_BY_TWO;
  3962. else
  3963. dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3964. if (clock->p2 == 4)
  3965. dpll |= PLL_P2_DIVIDE_BY_4;
  3966. }
  3967. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
  3968. dpll |= DPLL_DVO_2X_MODE;
  3969. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
  3970. intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  3971. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  3972. else
  3973. dpll |= PLL_REF_INPUT_DREFCLK;
  3974. dpll |= DPLL_VCO_ENABLE;
  3975. crtc->config.dpll_hw_state.dpll = dpll;
  3976. }
  3977. static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
  3978. {
  3979. struct drm_device *dev = intel_crtc->base.dev;
  3980. struct drm_i915_private *dev_priv = dev->dev_private;
  3981. enum pipe pipe = intel_crtc->pipe;
  3982. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  3983. struct drm_display_mode *adjusted_mode =
  3984. &intel_crtc->config.adjusted_mode;
  3985. uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
  3986. /* We need to be careful not to changed the adjusted mode, for otherwise
  3987. * the hw state checker will get angry at the mismatch. */
  3988. crtc_vtotal = adjusted_mode->crtc_vtotal;
  3989. crtc_vblank_end = adjusted_mode->crtc_vblank_end;
  3990. if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
  3991. /* the chip adds 2 halflines automatically */
  3992. crtc_vtotal -= 1;
  3993. crtc_vblank_end -= 1;
  3994. vsyncshift = adjusted_mode->crtc_hsync_start
  3995. - adjusted_mode->crtc_htotal / 2;
  3996. } else {
  3997. vsyncshift = 0;
  3998. }
  3999. if (INTEL_INFO(dev)->gen > 3)
  4000. I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
  4001. I915_WRITE(HTOTAL(cpu_transcoder),
  4002. (adjusted_mode->crtc_hdisplay - 1) |
  4003. ((adjusted_mode->crtc_htotal - 1) << 16));
  4004. I915_WRITE(HBLANK(cpu_transcoder),
  4005. (adjusted_mode->crtc_hblank_start - 1) |
  4006. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  4007. I915_WRITE(HSYNC(cpu_transcoder),
  4008. (adjusted_mode->crtc_hsync_start - 1) |
  4009. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  4010. I915_WRITE(VTOTAL(cpu_transcoder),
  4011. (adjusted_mode->crtc_vdisplay - 1) |
  4012. ((crtc_vtotal - 1) << 16));
  4013. I915_WRITE(VBLANK(cpu_transcoder),
  4014. (adjusted_mode->crtc_vblank_start - 1) |
  4015. ((crtc_vblank_end - 1) << 16));
  4016. I915_WRITE(VSYNC(cpu_transcoder),
  4017. (adjusted_mode->crtc_vsync_start - 1) |
  4018. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  4019. /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
  4020. * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
  4021. * documented on the DDI_FUNC_CTL register description, EDP Input Select
  4022. * bits. */
  4023. if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
  4024. (pipe == PIPE_B || pipe == PIPE_C))
  4025. I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
  4026. /* pipesrc controls the size that is scaled from, which should
  4027. * always be the user's requested size.
  4028. */
  4029. I915_WRITE(PIPESRC(pipe),
  4030. ((intel_crtc->config.pipe_src_w - 1) << 16) |
  4031. (intel_crtc->config.pipe_src_h - 1));
  4032. }
  4033. static void intel_get_pipe_timings(struct intel_crtc *crtc,
  4034. struct intel_crtc_config *pipe_config)
  4035. {
  4036. struct drm_device *dev = crtc->base.dev;
  4037. struct drm_i915_private *dev_priv = dev->dev_private;
  4038. enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
  4039. uint32_t tmp;
  4040. tmp = I915_READ(HTOTAL(cpu_transcoder));
  4041. pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
  4042. pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
  4043. tmp = I915_READ(HBLANK(cpu_transcoder));
  4044. pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
  4045. pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
  4046. tmp = I915_READ(HSYNC(cpu_transcoder));
  4047. pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
  4048. pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
  4049. tmp = I915_READ(VTOTAL(cpu_transcoder));
  4050. pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
  4051. pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
  4052. tmp = I915_READ(VBLANK(cpu_transcoder));
  4053. pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
  4054. pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
  4055. tmp = I915_READ(VSYNC(cpu_transcoder));
  4056. pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
  4057. pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
  4058. if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
  4059. pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
  4060. pipe_config->adjusted_mode.crtc_vtotal += 1;
  4061. pipe_config->adjusted_mode.crtc_vblank_end += 1;
  4062. }
  4063. tmp = I915_READ(PIPESRC(crtc->pipe));
  4064. pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
  4065. pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
  4066. pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
  4067. pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
  4068. }
  4069. static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
  4070. struct intel_crtc_config *pipe_config)
  4071. {
  4072. struct drm_crtc *crtc = &intel_crtc->base;
  4073. crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
  4074. crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
  4075. crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
  4076. crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
  4077. crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
  4078. crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
  4079. crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
  4080. crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
  4081. crtc->mode.flags = pipe_config->adjusted_mode.flags;
  4082. crtc->mode.clock = pipe_config->adjusted_mode.clock;
  4083. crtc->mode.flags |= pipe_config->adjusted_mode.flags;
  4084. }
  4085. static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
  4086. {
  4087. struct drm_device *dev = intel_crtc->base.dev;
  4088. struct drm_i915_private *dev_priv = dev->dev_private;
  4089. uint32_t pipeconf;
  4090. pipeconf = 0;
  4091. if (intel_crtc->config.double_wide)
  4092. pipeconf |= PIPECONF_DOUBLE_WIDE;
  4093. /* only g4x and later have fancy bpc/dither controls */
  4094. if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
  4095. /* Bspec claims that we can't use dithering for 30bpp pipes. */
  4096. if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
  4097. pipeconf |= PIPECONF_DITHER_EN |
  4098. PIPECONF_DITHER_TYPE_SP;
  4099. switch (intel_crtc->config.pipe_bpp) {
  4100. case 18:
  4101. pipeconf |= PIPECONF_6BPC;
  4102. break;
  4103. case 24:
  4104. pipeconf |= PIPECONF_8BPC;
  4105. break;
  4106. case 30:
  4107. pipeconf |= PIPECONF_10BPC;
  4108. break;
  4109. default:
  4110. /* Case prevented by intel_choose_pipe_bpp_dither. */
  4111. BUG();
  4112. }
  4113. }
  4114. if (HAS_PIPE_CXSR(dev)) {
  4115. if (intel_crtc->lowfreq_avail) {
  4116. DRM_DEBUG_KMS("enabling CxSR downclocking\n");
  4117. pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
  4118. } else {
  4119. DRM_DEBUG_KMS("disabling CxSR downclocking\n");
  4120. }
  4121. }
  4122. if (!IS_GEN2(dev) &&
  4123. intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
  4124. pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
  4125. else
  4126. pipeconf |= PIPECONF_PROGRESSIVE;
  4127. if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
  4128. pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
  4129. I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
  4130. POSTING_READ(PIPECONF(intel_crtc->pipe));
  4131. }
  4132. static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
  4133. int x, int y,
  4134. struct drm_framebuffer *fb)
  4135. {
  4136. struct drm_device *dev = crtc->dev;
  4137. struct drm_i915_private *dev_priv = dev->dev_private;
  4138. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4139. int pipe = intel_crtc->pipe;
  4140. int plane = intel_crtc->plane;
  4141. int refclk, num_connectors = 0;
  4142. intel_clock_t clock, reduced_clock;
  4143. u32 dspcntr;
  4144. bool ok, has_reduced_clock = false;
  4145. bool is_lvds = false, is_dsi = false;
  4146. struct intel_encoder *encoder;
  4147. const intel_limit_t *limit;
  4148. int ret;
  4149. for_each_encoder_on_crtc(dev, crtc, encoder) {
  4150. switch (encoder->type) {
  4151. case INTEL_OUTPUT_LVDS:
  4152. is_lvds = true;
  4153. break;
  4154. case INTEL_OUTPUT_DSI:
  4155. is_dsi = true;
  4156. break;
  4157. }
  4158. num_connectors++;
  4159. }
  4160. refclk = i9xx_get_refclk(crtc, num_connectors);
  4161. if (!is_dsi && !intel_crtc->config.clock_set) {
  4162. /*
  4163. * Returns a set of divisors for the desired target clock with
  4164. * the given refclk, or FALSE. The returned values represent
  4165. * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
  4166. * 2) / p1 / p2.
  4167. */
  4168. limit = intel_limit(crtc, refclk);
  4169. ok = dev_priv->display.find_dpll(limit, crtc,
  4170. intel_crtc->config.port_clock,
  4171. refclk, NULL, &clock);
  4172. if (!ok && !intel_crtc->config.clock_set) {
  4173. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  4174. return -EINVAL;
  4175. }
  4176. }
  4177. /* Ensure that the cursor is valid for the new mode before changing... */
  4178. intel_crtc_update_cursor(crtc, true);
  4179. if (!is_dsi && is_lvds && dev_priv->lvds_downclock_avail) {
  4180. /*
  4181. * Ensure we match the reduced clock's P to the target clock.
  4182. * If the clocks don't match, we can't switch the display clock
  4183. * by using the FP0/FP1. In such case we will disable the LVDS
  4184. * downclock feature.
  4185. */
  4186. limit = intel_limit(crtc, refclk);
  4187. has_reduced_clock =
  4188. dev_priv->display.find_dpll(limit, crtc,
  4189. dev_priv->lvds_downclock,
  4190. refclk, &clock,
  4191. &reduced_clock);
  4192. }
  4193. /* Compat-code for transition, will disappear. */
  4194. if (!intel_crtc->config.clock_set) {
  4195. intel_crtc->config.dpll.n = clock.n;
  4196. intel_crtc->config.dpll.m1 = clock.m1;
  4197. intel_crtc->config.dpll.m2 = clock.m2;
  4198. intel_crtc->config.dpll.p1 = clock.p1;
  4199. intel_crtc->config.dpll.p2 = clock.p2;
  4200. }
  4201. if (IS_GEN2(dev)) {
  4202. i8xx_update_pll(intel_crtc,
  4203. has_reduced_clock ? &reduced_clock : NULL,
  4204. num_connectors);
  4205. } else if (IS_VALLEYVIEW(dev)) {
  4206. if (!is_dsi)
  4207. vlv_update_pll(intel_crtc);
  4208. } else {
  4209. i9xx_update_pll(intel_crtc,
  4210. has_reduced_clock ? &reduced_clock : NULL,
  4211. num_connectors);
  4212. }
  4213. /* Set up the display plane register */
  4214. dspcntr = DISPPLANE_GAMMA_ENABLE;
  4215. if (!IS_VALLEYVIEW(dev)) {
  4216. if (pipe == 0)
  4217. dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
  4218. else
  4219. dspcntr |= DISPPLANE_SEL_PIPE_B;
  4220. }
  4221. intel_set_pipe_timings(intel_crtc);
  4222. /* pipesrc and dspsize control the size that is scaled from,
  4223. * which should always be the user's requested size.
  4224. */
  4225. I915_WRITE(DSPSIZE(plane),
  4226. ((intel_crtc->config.pipe_src_h - 1) << 16) |
  4227. (intel_crtc->config.pipe_src_w - 1));
  4228. I915_WRITE(DSPPOS(plane), 0);
  4229. i9xx_set_pipeconf(intel_crtc);
  4230. I915_WRITE(DSPCNTR(plane), dspcntr);
  4231. POSTING_READ(DSPCNTR(plane));
  4232. ret = intel_pipe_set_base(crtc, x, y, fb);
  4233. return ret;
  4234. }
  4235. static void i9xx_get_pfit_config(struct intel_crtc *crtc,
  4236. struct intel_crtc_config *pipe_config)
  4237. {
  4238. struct drm_device *dev = crtc->base.dev;
  4239. struct drm_i915_private *dev_priv = dev->dev_private;
  4240. uint32_t tmp;
  4241. tmp = I915_READ(PFIT_CONTROL);
  4242. if (!(tmp & PFIT_ENABLE))
  4243. return;
  4244. /* Check whether the pfit is attached to our pipe. */
  4245. if (INTEL_INFO(dev)->gen < 4) {
  4246. if (crtc->pipe != PIPE_B)
  4247. return;
  4248. } else {
  4249. if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
  4250. return;
  4251. }
  4252. pipe_config->gmch_pfit.control = tmp;
  4253. pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
  4254. if (INTEL_INFO(dev)->gen < 5)
  4255. pipe_config->gmch_pfit.lvds_border_bits =
  4256. I915_READ(LVDS) & LVDS_BORDER_ENABLE;
  4257. }
  4258. static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
  4259. struct intel_crtc_config *pipe_config)
  4260. {
  4261. struct drm_device *dev = crtc->base.dev;
  4262. struct drm_i915_private *dev_priv = dev->dev_private;
  4263. uint32_t tmp;
  4264. pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
  4265. pipe_config->shared_dpll = DPLL_ID_PRIVATE;
  4266. tmp = I915_READ(PIPECONF(crtc->pipe));
  4267. if (!(tmp & PIPECONF_ENABLE))
  4268. return false;
  4269. if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
  4270. switch (tmp & PIPECONF_BPC_MASK) {
  4271. case PIPECONF_6BPC:
  4272. pipe_config->pipe_bpp = 18;
  4273. break;
  4274. case PIPECONF_8BPC:
  4275. pipe_config->pipe_bpp = 24;
  4276. break;
  4277. case PIPECONF_10BPC:
  4278. pipe_config->pipe_bpp = 30;
  4279. break;
  4280. default:
  4281. break;
  4282. }
  4283. }
  4284. if (INTEL_INFO(dev)->gen < 4)
  4285. pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
  4286. intel_get_pipe_timings(crtc, pipe_config);
  4287. i9xx_get_pfit_config(crtc, pipe_config);
  4288. if (INTEL_INFO(dev)->gen >= 4) {
  4289. tmp = I915_READ(DPLL_MD(crtc->pipe));
  4290. pipe_config->pixel_multiplier =
  4291. ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
  4292. >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
  4293. pipe_config->dpll_hw_state.dpll_md = tmp;
  4294. } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  4295. tmp = I915_READ(DPLL(crtc->pipe));
  4296. pipe_config->pixel_multiplier =
  4297. ((tmp & SDVO_MULTIPLIER_MASK)
  4298. >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
  4299. } else {
  4300. /* Note that on i915G/GM the pixel multiplier is in the sdvo
  4301. * port and will be fixed up in the encoder->get_config
  4302. * function. */
  4303. pipe_config->pixel_multiplier = 1;
  4304. }
  4305. pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
  4306. if (!IS_VALLEYVIEW(dev)) {
  4307. pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
  4308. pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
  4309. } else {
  4310. /* Mask out read-only status bits. */
  4311. pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
  4312. DPLL_PORTC_READY_MASK |
  4313. DPLL_PORTB_READY_MASK);
  4314. }
  4315. i9xx_crtc_clock_get(crtc, pipe_config);
  4316. return true;
  4317. }
  4318. static void ironlake_init_pch_refclk(struct drm_device *dev)
  4319. {
  4320. struct drm_i915_private *dev_priv = dev->dev_private;
  4321. struct drm_mode_config *mode_config = &dev->mode_config;
  4322. struct intel_encoder *encoder;
  4323. u32 val, final;
  4324. bool has_lvds = false;
  4325. bool has_cpu_edp = false;
  4326. bool has_panel = false;
  4327. bool has_ck505 = false;
  4328. bool can_ssc = false;
  4329. /* We need to take the global config into account */
  4330. list_for_each_entry(encoder, &mode_config->encoder_list,
  4331. base.head) {
  4332. switch (encoder->type) {
  4333. case INTEL_OUTPUT_LVDS:
  4334. has_panel = true;
  4335. has_lvds = true;
  4336. break;
  4337. case INTEL_OUTPUT_EDP:
  4338. has_panel = true;
  4339. if (enc_to_dig_port(&encoder->base)->port == PORT_A)
  4340. has_cpu_edp = true;
  4341. break;
  4342. }
  4343. }
  4344. if (HAS_PCH_IBX(dev)) {
  4345. has_ck505 = dev_priv->vbt.display_clock_mode;
  4346. can_ssc = has_ck505;
  4347. } else {
  4348. has_ck505 = false;
  4349. can_ssc = true;
  4350. }
  4351. DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
  4352. has_panel, has_lvds, has_ck505);
  4353. /* Ironlake: try to setup display ref clock before DPLL
  4354. * enabling. This is only under driver's control after
  4355. * PCH B stepping, previous chipset stepping should be
  4356. * ignoring this setting.
  4357. */
  4358. val = I915_READ(PCH_DREF_CONTROL);
  4359. /* As we must carefully and slowly disable/enable each source in turn,
  4360. * compute the final state we want first and check if we need to
  4361. * make any changes at all.
  4362. */
  4363. final = val;
  4364. final &= ~DREF_NONSPREAD_SOURCE_MASK;
  4365. if (has_ck505)
  4366. final |= DREF_NONSPREAD_CK505_ENABLE;
  4367. else
  4368. final |= DREF_NONSPREAD_SOURCE_ENABLE;
  4369. final &= ~DREF_SSC_SOURCE_MASK;
  4370. final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  4371. final &= ~DREF_SSC1_ENABLE;
  4372. if (has_panel) {
  4373. final |= DREF_SSC_SOURCE_ENABLE;
  4374. if (intel_panel_use_ssc(dev_priv) && can_ssc)
  4375. final |= DREF_SSC1_ENABLE;
  4376. if (has_cpu_edp) {
  4377. if (intel_panel_use_ssc(dev_priv) && can_ssc)
  4378. final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  4379. else
  4380. final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  4381. } else
  4382. final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  4383. } else {
  4384. final |= DREF_SSC_SOURCE_DISABLE;
  4385. final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  4386. }
  4387. if (final == val)
  4388. return;
  4389. /* Always enable nonspread source */
  4390. val &= ~DREF_NONSPREAD_SOURCE_MASK;
  4391. if (has_ck505)
  4392. val |= DREF_NONSPREAD_CK505_ENABLE;
  4393. else
  4394. val |= DREF_NONSPREAD_SOURCE_ENABLE;
  4395. if (has_panel) {
  4396. val &= ~DREF_SSC_SOURCE_MASK;
  4397. val |= DREF_SSC_SOURCE_ENABLE;
  4398. /* SSC must be turned on before enabling the CPU output */
  4399. if (intel_panel_use_ssc(dev_priv) && can_ssc) {
  4400. DRM_DEBUG_KMS("Using SSC on panel\n");
  4401. val |= DREF_SSC1_ENABLE;
  4402. } else
  4403. val &= ~DREF_SSC1_ENABLE;
  4404. /* Get SSC going before enabling the outputs */
  4405. I915_WRITE(PCH_DREF_CONTROL, val);
  4406. POSTING_READ(PCH_DREF_CONTROL);
  4407. udelay(200);
  4408. val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  4409. /* Enable CPU source on CPU attached eDP */
  4410. if (has_cpu_edp) {
  4411. if (intel_panel_use_ssc(dev_priv) && can_ssc) {
  4412. DRM_DEBUG_KMS("Using SSC on eDP\n");
  4413. val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  4414. }
  4415. else
  4416. val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  4417. } else
  4418. val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  4419. I915_WRITE(PCH_DREF_CONTROL, val);
  4420. POSTING_READ(PCH_DREF_CONTROL);
  4421. udelay(200);
  4422. } else {
  4423. DRM_DEBUG_KMS("Disabling SSC entirely\n");
  4424. val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  4425. /* Turn off CPU output */
  4426. val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  4427. I915_WRITE(PCH_DREF_CONTROL, val);
  4428. POSTING_READ(PCH_DREF_CONTROL);
  4429. udelay(200);
  4430. /* Turn off the SSC source */
  4431. val &= ~DREF_SSC_SOURCE_MASK;
  4432. val |= DREF_SSC_SOURCE_DISABLE;
  4433. /* Turn off SSC1 */
  4434. val &= ~DREF_SSC1_ENABLE;
  4435. I915_WRITE(PCH_DREF_CONTROL, val);
  4436. POSTING_READ(PCH_DREF_CONTROL);
  4437. udelay(200);
  4438. }
  4439. BUG_ON(val != final);
  4440. }
  4441. static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
  4442. {
  4443. uint32_t tmp;
  4444. tmp = I915_READ(SOUTH_CHICKEN2);
  4445. tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
  4446. I915_WRITE(SOUTH_CHICKEN2, tmp);
  4447. if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
  4448. FDI_MPHY_IOSFSB_RESET_STATUS, 100))
  4449. DRM_ERROR("FDI mPHY reset assert timeout\n");
  4450. tmp = I915_READ(SOUTH_CHICKEN2);
  4451. tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
  4452. I915_WRITE(SOUTH_CHICKEN2, tmp);
  4453. if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
  4454. FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
  4455. DRM_ERROR("FDI mPHY reset de-assert timeout\n");
  4456. }
  4457. /* WaMPhyProgramming:hsw */
  4458. static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
  4459. {
  4460. uint32_t tmp;
  4461. tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
  4462. tmp &= ~(0xFF << 24);
  4463. tmp |= (0x12 << 24);
  4464. intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
  4465. tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
  4466. tmp |= (1 << 11);
  4467. intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
  4468. tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
  4469. tmp |= (1 << 11);
  4470. intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
  4471. tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
  4472. tmp |= (1 << 24) | (1 << 21) | (1 << 18);
  4473. intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
  4474. tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
  4475. tmp |= (1 << 24) | (1 << 21) | (1 << 18);
  4476. intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
  4477. tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
  4478. tmp &= ~(7 << 13);
  4479. tmp |= (5 << 13);
  4480. intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
  4481. tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
  4482. tmp &= ~(7 << 13);
  4483. tmp |= (5 << 13);
  4484. intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
  4485. tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
  4486. tmp &= ~0xFF;
  4487. tmp |= 0x1C;
  4488. intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
  4489. tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
  4490. tmp &= ~0xFF;
  4491. tmp |= 0x1C;
  4492. intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
  4493. tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
  4494. tmp &= ~(0xFF << 16);
  4495. tmp |= (0x1C << 16);
  4496. intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
  4497. tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
  4498. tmp &= ~(0xFF << 16);
  4499. tmp |= (0x1C << 16);
  4500. intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
  4501. tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
  4502. tmp |= (1 << 27);
  4503. intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
  4504. tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
  4505. tmp |= (1 << 27);
  4506. intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
  4507. tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
  4508. tmp &= ~(0xF << 28);
  4509. tmp |= (4 << 28);
  4510. intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
  4511. tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
  4512. tmp &= ~(0xF << 28);
  4513. tmp |= (4 << 28);
  4514. intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
  4515. }
  4516. /* Implements 3 different sequences from BSpec chapter "Display iCLK
  4517. * Programming" based on the parameters passed:
  4518. * - Sequence to enable CLKOUT_DP
  4519. * - Sequence to enable CLKOUT_DP without spread
  4520. * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
  4521. */
  4522. static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
  4523. bool with_fdi)
  4524. {
  4525. struct drm_i915_private *dev_priv = dev->dev_private;
  4526. uint32_t reg, tmp;
  4527. if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
  4528. with_spread = true;
  4529. if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
  4530. with_fdi, "LP PCH doesn't have FDI\n"))
  4531. with_fdi = false;
  4532. mutex_lock(&dev_priv->dpio_lock);
  4533. tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
  4534. tmp &= ~SBI_SSCCTL_DISABLE;
  4535. tmp |= SBI_SSCCTL_PATHALT;
  4536. intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  4537. udelay(24);
  4538. if (with_spread) {
  4539. tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
  4540. tmp &= ~SBI_SSCCTL_PATHALT;
  4541. intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  4542. if (with_fdi) {
  4543. lpt_reset_fdi_mphy(dev_priv);
  4544. lpt_program_fdi_mphy(dev_priv);
  4545. }
  4546. }
  4547. reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
  4548. SBI_GEN0 : SBI_DBUFF0;
  4549. tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
  4550. tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
  4551. intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
  4552. mutex_unlock(&dev_priv->dpio_lock);
  4553. }
  4554. /* Sequence to disable CLKOUT_DP */
  4555. static void lpt_disable_clkout_dp(struct drm_device *dev)
  4556. {
  4557. struct drm_i915_private *dev_priv = dev->dev_private;
  4558. uint32_t reg, tmp;
  4559. mutex_lock(&dev_priv->dpio_lock);
  4560. reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
  4561. SBI_GEN0 : SBI_DBUFF0;
  4562. tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
  4563. tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
  4564. intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
  4565. tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
  4566. if (!(tmp & SBI_SSCCTL_DISABLE)) {
  4567. if (!(tmp & SBI_SSCCTL_PATHALT)) {
  4568. tmp |= SBI_SSCCTL_PATHALT;
  4569. intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  4570. udelay(32);
  4571. }
  4572. tmp |= SBI_SSCCTL_DISABLE;
  4573. intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  4574. }
  4575. mutex_unlock(&dev_priv->dpio_lock);
  4576. }
  4577. static void lpt_init_pch_refclk(struct drm_device *dev)
  4578. {
  4579. struct drm_mode_config *mode_config = &dev->mode_config;
  4580. struct intel_encoder *encoder;
  4581. bool has_vga = false;
  4582. list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
  4583. switch (encoder->type) {
  4584. case INTEL_OUTPUT_ANALOG:
  4585. has_vga = true;
  4586. break;
  4587. }
  4588. }
  4589. if (has_vga)
  4590. lpt_enable_clkout_dp(dev, true, true);
  4591. else
  4592. lpt_disable_clkout_dp(dev);
  4593. }
  4594. /*
  4595. * Initialize reference clocks when the driver loads
  4596. */
  4597. void intel_init_pch_refclk(struct drm_device *dev)
  4598. {
  4599. if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  4600. ironlake_init_pch_refclk(dev);
  4601. else if (HAS_PCH_LPT(dev))
  4602. lpt_init_pch_refclk(dev);
  4603. }
  4604. static int ironlake_get_refclk(struct drm_crtc *crtc)
  4605. {
  4606. struct drm_device *dev = crtc->dev;
  4607. struct drm_i915_private *dev_priv = dev->dev_private;
  4608. struct intel_encoder *encoder;
  4609. int num_connectors = 0;
  4610. bool is_lvds = false;
  4611. for_each_encoder_on_crtc(dev, crtc, encoder) {
  4612. switch (encoder->type) {
  4613. case INTEL_OUTPUT_LVDS:
  4614. is_lvds = true;
  4615. break;
  4616. }
  4617. num_connectors++;
  4618. }
  4619. if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
  4620. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  4621. dev_priv->vbt.lvds_ssc_freq);
  4622. return dev_priv->vbt.lvds_ssc_freq * 1000;
  4623. }
  4624. return 120000;
  4625. }
  4626. static void ironlake_set_pipeconf(struct drm_crtc *crtc)
  4627. {
  4628. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  4629. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4630. int pipe = intel_crtc->pipe;
  4631. uint32_t val;
  4632. val = 0;
  4633. switch (intel_crtc->config.pipe_bpp) {
  4634. case 18:
  4635. val |= PIPECONF_6BPC;
  4636. break;
  4637. case 24:
  4638. val |= PIPECONF_8BPC;
  4639. break;
  4640. case 30:
  4641. val |= PIPECONF_10BPC;
  4642. break;
  4643. case 36:
  4644. val |= PIPECONF_12BPC;
  4645. break;
  4646. default:
  4647. /* Case prevented by intel_choose_pipe_bpp_dither. */
  4648. BUG();
  4649. }
  4650. if (intel_crtc->config.dither)
  4651. val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
  4652. if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
  4653. val |= PIPECONF_INTERLACED_ILK;
  4654. else
  4655. val |= PIPECONF_PROGRESSIVE;
  4656. if (intel_crtc->config.limited_color_range)
  4657. val |= PIPECONF_COLOR_RANGE_SELECT;
  4658. I915_WRITE(PIPECONF(pipe), val);
  4659. POSTING_READ(PIPECONF(pipe));
  4660. }
  4661. /*
  4662. * Set up the pipe CSC unit.
  4663. *
  4664. * Currently only full range RGB to limited range RGB conversion
  4665. * is supported, but eventually this should handle various
  4666. * RGB<->YCbCr scenarios as well.
  4667. */
  4668. static void intel_set_pipe_csc(struct drm_crtc *crtc)
  4669. {
  4670. struct drm_device *dev = crtc->dev;
  4671. struct drm_i915_private *dev_priv = dev->dev_private;
  4672. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4673. int pipe = intel_crtc->pipe;
  4674. uint16_t coeff = 0x7800; /* 1.0 */
  4675. /*
  4676. * TODO: Check what kind of values actually come out of the pipe
  4677. * with these coeff/postoff values and adjust to get the best
  4678. * accuracy. Perhaps we even need to take the bpc value into
  4679. * consideration.
  4680. */
  4681. if (intel_crtc->config.limited_color_range)
  4682. coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
  4683. /*
  4684. * GY/GU and RY/RU should be the other way around according
  4685. * to BSpec, but reality doesn't agree. Just set them up in
  4686. * a way that results in the correct picture.
  4687. */
  4688. I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
  4689. I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
  4690. I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
  4691. I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
  4692. I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
  4693. I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
  4694. I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
  4695. I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
  4696. I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
  4697. if (INTEL_INFO(dev)->gen > 6) {
  4698. uint16_t postoff = 0;
  4699. if (intel_crtc->config.limited_color_range)
  4700. postoff = (16 * (1 << 13) / 255) & 0x1fff;
  4701. I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
  4702. I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
  4703. I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
  4704. I915_WRITE(PIPE_CSC_MODE(pipe), 0);
  4705. } else {
  4706. uint32_t mode = CSC_MODE_YUV_TO_RGB;
  4707. if (intel_crtc->config.limited_color_range)
  4708. mode |= CSC_BLACK_SCREEN_OFFSET;
  4709. I915_WRITE(PIPE_CSC_MODE(pipe), mode);
  4710. }
  4711. }
  4712. static void haswell_set_pipeconf(struct drm_crtc *crtc)
  4713. {
  4714. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  4715. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4716. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  4717. uint32_t val;
  4718. val = 0;
  4719. if (intel_crtc->config.dither)
  4720. val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
  4721. if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
  4722. val |= PIPECONF_INTERLACED_ILK;
  4723. else
  4724. val |= PIPECONF_PROGRESSIVE;
  4725. I915_WRITE(PIPECONF(cpu_transcoder), val);
  4726. POSTING_READ(PIPECONF(cpu_transcoder));
  4727. I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
  4728. POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
  4729. }
  4730. static bool ironlake_compute_clocks(struct drm_crtc *crtc,
  4731. intel_clock_t *clock,
  4732. bool *has_reduced_clock,
  4733. intel_clock_t *reduced_clock)
  4734. {
  4735. struct drm_device *dev = crtc->dev;
  4736. struct drm_i915_private *dev_priv = dev->dev_private;
  4737. struct intel_encoder *intel_encoder;
  4738. int refclk;
  4739. const intel_limit_t *limit;
  4740. bool ret, is_lvds = false;
  4741. for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  4742. switch (intel_encoder->type) {
  4743. case INTEL_OUTPUT_LVDS:
  4744. is_lvds = true;
  4745. break;
  4746. }
  4747. }
  4748. refclk = ironlake_get_refclk(crtc);
  4749. /*
  4750. * Returns a set of divisors for the desired target clock with the given
  4751. * refclk, or FALSE. The returned values represent the clock equation:
  4752. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  4753. */
  4754. limit = intel_limit(crtc, refclk);
  4755. ret = dev_priv->display.find_dpll(limit, crtc,
  4756. to_intel_crtc(crtc)->config.port_clock,
  4757. refclk, NULL, clock);
  4758. if (!ret)
  4759. return false;
  4760. if (is_lvds && dev_priv->lvds_downclock_avail) {
  4761. /*
  4762. * Ensure we match the reduced clock's P to the target clock.
  4763. * If the clocks don't match, we can't switch the display clock
  4764. * by using the FP0/FP1. In such case we will disable the LVDS
  4765. * downclock feature.
  4766. */
  4767. *has_reduced_clock =
  4768. dev_priv->display.find_dpll(limit, crtc,
  4769. dev_priv->lvds_downclock,
  4770. refclk, clock,
  4771. reduced_clock);
  4772. }
  4773. return true;
  4774. }
  4775. static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
  4776. {
  4777. struct drm_i915_private *dev_priv = dev->dev_private;
  4778. uint32_t temp;
  4779. temp = I915_READ(SOUTH_CHICKEN1);
  4780. if (temp & FDI_BC_BIFURCATION_SELECT)
  4781. return;
  4782. WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
  4783. WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
  4784. temp |= FDI_BC_BIFURCATION_SELECT;
  4785. DRM_DEBUG_KMS("enabling fdi C rx\n");
  4786. I915_WRITE(SOUTH_CHICKEN1, temp);
  4787. POSTING_READ(SOUTH_CHICKEN1);
  4788. }
  4789. static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
  4790. {
  4791. struct drm_device *dev = intel_crtc->base.dev;
  4792. struct drm_i915_private *dev_priv = dev->dev_private;
  4793. switch (intel_crtc->pipe) {
  4794. case PIPE_A:
  4795. break;
  4796. case PIPE_B:
  4797. if (intel_crtc->config.fdi_lanes > 2)
  4798. WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
  4799. else
  4800. cpt_enable_fdi_bc_bifurcation(dev);
  4801. break;
  4802. case PIPE_C:
  4803. cpt_enable_fdi_bc_bifurcation(dev);
  4804. break;
  4805. default:
  4806. BUG();
  4807. }
  4808. }
  4809. int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
  4810. {
  4811. /*
  4812. * Account for spread spectrum to avoid
  4813. * oversubscribing the link. Max center spread
  4814. * is 2.5%; use 5% for safety's sake.
  4815. */
  4816. u32 bps = target_clock * bpp * 21 / 20;
  4817. return bps / (link_bw * 8) + 1;
  4818. }
  4819. static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
  4820. {
  4821. return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
  4822. }
  4823. static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
  4824. u32 *fp,
  4825. intel_clock_t *reduced_clock, u32 *fp2)
  4826. {
  4827. struct drm_crtc *crtc = &intel_crtc->base;
  4828. struct drm_device *dev = crtc->dev;
  4829. struct drm_i915_private *dev_priv = dev->dev_private;
  4830. struct intel_encoder *intel_encoder;
  4831. uint32_t dpll;
  4832. int factor, num_connectors = 0;
  4833. bool is_lvds = false, is_sdvo = false;
  4834. for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  4835. switch (intel_encoder->type) {
  4836. case INTEL_OUTPUT_LVDS:
  4837. is_lvds = true;
  4838. break;
  4839. case INTEL_OUTPUT_SDVO:
  4840. case INTEL_OUTPUT_HDMI:
  4841. is_sdvo = true;
  4842. break;
  4843. }
  4844. num_connectors++;
  4845. }
  4846. /* Enable autotuning of the PLL clock (if permissible) */
  4847. factor = 21;
  4848. if (is_lvds) {
  4849. if ((intel_panel_use_ssc(dev_priv) &&
  4850. dev_priv->vbt.lvds_ssc_freq == 100) ||
  4851. (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
  4852. factor = 25;
  4853. } else if (intel_crtc->config.sdvo_tv_clock)
  4854. factor = 20;
  4855. if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
  4856. *fp |= FP_CB_TUNE;
  4857. if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
  4858. *fp2 |= FP_CB_TUNE;
  4859. dpll = 0;
  4860. if (is_lvds)
  4861. dpll |= DPLLB_MODE_LVDS;
  4862. else
  4863. dpll |= DPLLB_MODE_DAC_SERIAL;
  4864. dpll |= (intel_crtc->config.pixel_multiplier - 1)
  4865. << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
  4866. if (is_sdvo)
  4867. dpll |= DPLL_SDVO_HIGH_SPEED;
  4868. if (intel_crtc->config.has_dp_encoder)
  4869. dpll |= DPLL_SDVO_HIGH_SPEED;
  4870. /* compute bitmask from p1 value */
  4871. dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  4872. /* also FPA1 */
  4873. dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  4874. switch (intel_crtc->config.dpll.p2) {
  4875. case 5:
  4876. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  4877. break;
  4878. case 7:
  4879. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  4880. break;
  4881. case 10:
  4882. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  4883. break;
  4884. case 14:
  4885. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  4886. break;
  4887. }
  4888. if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  4889. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  4890. else
  4891. dpll |= PLL_REF_INPUT_DREFCLK;
  4892. return dpll | DPLL_VCO_ENABLE;
  4893. }
  4894. static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
  4895. int x, int y,
  4896. struct drm_framebuffer *fb)
  4897. {
  4898. struct drm_device *dev = crtc->dev;
  4899. struct drm_i915_private *dev_priv = dev->dev_private;
  4900. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4901. int pipe = intel_crtc->pipe;
  4902. int plane = intel_crtc->plane;
  4903. int num_connectors = 0;
  4904. intel_clock_t clock, reduced_clock;
  4905. u32 dpll = 0, fp = 0, fp2 = 0;
  4906. bool ok, has_reduced_clock = false;
  4907. bool is_lvds = false;
  4908. struct intel_encoder *encoder;
  4909. struct intel_shared_dpll *pll;
  4910. int ret;
  4911. for_each_encoder_on_crtc(dev, crtc, encoder) {
  4912. switch (encoder->type) {
  4913. case INTEL_OUTPUT_LVDS:
  4914. is_lvds = true;
  4915. break;
  4916. }
  4917. num_connectors++;
  4918. }
  4919. WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
  4920. "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
  4921. ok = ironlake_compute_clocks(crtc, &clock,
  4922. &has_reduced_clock, &reduced_clock);
  4923. if (!ok && !intel_crtc->config.clock_set) {
  4924. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  4925. return -EINVAL;
  4926. }
  4927. /* Compat-code for transition, will disappear. */
  4928. if (!intel_crtc->config.clock_set) {
  4929. intel_crtc->config.dpll.n = clock.n;
  4930. intel_crtc->config.dpll.m1 = clock.m1;
  4931. intel_crtc->config.dpll.m2 = clock.m2;
  4932. intel_crtc->config.dpll.p1 = clock.p1;
  4933. intel_crtc->config.dpll.p2 = clock.p2;
  4934. }
  4935. /* Ensure that the cursor is valid for the new mode before changing... */
  4936. intel_crtc_update_cursor(crtc, true);
  4937. /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
  4938. if (intel_crtc->config.has_pch_encoder) {
  4939. fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
  4940. if (has_reduced_clock)
  4941. fp2 = i9xx_dpll_compute_fp(&reduced_clock);
  4942. dpll = ironlake_compute_dpll(intel_crtc,
  4943. &fp, &reduced_clock,
  4944. has_reduced_clock ? &fp2 : NULL);
  4945. intel_crtc->config.dpll_hw_state.dpll = dpll;
  4946. intel_crtc->config.dpll_hw_state.fp0 = fp;
  4947. if (has_reduced_clock)
  4948. intel_crtc->config.dpll_hw_state.fp1 = fp2;
  4949. else
  4950. intel_crtc->config.dpll_hw_state.fp1 = fp;
  4951. pll = intel_get_shared_dpll(intel_crtc);
  4952. if (pll == NULL) {
  4953. DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
  4954. pipe_name(pipe));
  4955. return -EINVAL;
  4956. }
  4957. } else
  4958. intel_put_shared_dpll(intel_crtc);
  4959. if (intel_crtc->config.has_dp_encoder)
  4960. intel_dp_set_m_n(intel_crtc);
  4961. if (is_lvds && has_reduced_clock && i915_powersave)
  4962. intel_crtc->lowfreq_avail = true;
  4963. else
  4964. intel_crtc->lowfreq_avail = false;
  4965. if (intel_crtc->config.has_pch_encoder) {
  4966. pll = intel_crtc_to_shared_dpll(intel_crtc);
  4967. }
  4968. intel_set_pipe_timings(intel_crtc);
  4969. if (intel_crtc->config.has_pch_encoder) {
  4970. intel_cpu_transcoder_set_m_n(intel_crtc,
  4971. &intel_crtc->config.fdi_m_n);
  4972. }
  4973. if (IS_IVYBRIDGE(dev))
  4974. ivybridge_update_fdi_bc_bifurcation(intel_crtc);
  4975. ironlake_set_pipeconf(crtc);
  4976. /* Set up the display plane register */
  4977. I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
  4978. POSTING_READ(DSPCNTR(plane));
  4979. ret = intel_pipe_set_base(crtc, x, y, fb);
  4980. return ret;
  4981. }
  4982. static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
  4983. struct intel_link_m_n *m_n)
  4984. {
  4985. struct drm_device *dev = crtc->base.dev;
  4986. struct drm_i915_private *dev_priv = dev->dev_private;
  4987. enum pipe pipe = crtc->pipe;
  4988. m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
  4989. m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
  4990. m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
  4991. & ~TU_SIZE_MASK;
  4992. m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
  4993. m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
  4994. & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
  4995. }
  4996. static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
  4997. enum transcoder transcoder,
  4998. struct intel_link_m_n *m_n)
  4999. {
  5000. struct drm_device *dev = crtc->base.dev;
  5001. struct drm_i915_private *dev_priv = dev->dev_private;
  5002. enum pipe pipe = crtc->pipe;
  5003. if (INTEL_INFO(dev)->gen >= 5) {
  5004. m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
  5005. m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
  5006. m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
  5007. & ~TU_SIZE_MASK;
  5008. m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
  5009. m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
  5010. & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
  5011. } else {
  5012. m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
  5013. m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
  5014. m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
  5015. & ~TU_SIZE_MASK;
  5016. m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
  5017. m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
  5018. & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
  5019. }
  5020. }
  5021. void intel_dp_get_m_n(struct intel_crtc *crtc,
  5022. struct intel_crtc_config *pipe_config)
  5023. {
  5024. if (crtc->config.has_pch_encoder)
  5025. intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
  5026. else
  5027. intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
  5028. &pipe_config->dp_m_n);
  5029. }
  5030. static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
  5031. struct intel_crtc_config *pipe_config)
  5032. {
  5033. intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
  5034. &pipe_config->fdi_m_n);
  5035. }
  5036. static void ironlake_get_pfit_config(struct intel_crtc *crtc,
  5037. struct intel_crtc_config *pipe_config)
  5038. {
  5039. struct drm_device *dev = crtc->base.dev;
  5040. struct drm_i915_private *dev_priv = dev->dev_private;
  5041. uint32_t tmp;
  5042. tmp = I915_READ(PF_CTL(crtc->pipe));
  5043. if (tmp & PF_ENABLE) {
  5044. pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
  5045. pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
  5046. /* We currently do not free assignements of panel fitters on
  5047. * ivb/hsw (since we don't use the higher upscaling modes which
  5048. * differentiates them) so just WARN about this case for now. */
  5049. if (IS_GEN7(dev)) {
  5050. WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
  5051. PF_PIPE_SEL_IVB(crtc->pipe));
  5052. }
  5053. }
  5054. }
  5055. static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
  5056. struct intel_crtc_config *pipe_config)
  5057. {
  5058. struct drm_device *dev = crtc->base.dev;
  5059. struct drm_i915_private *dev_priv = dev->dev_private;
  5060. uint32_t tmp;
  5061. pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
  5062. pipe_config->shared_dpll = DPLL_ID_PRIVATE;
  5063. tmp = I915_READ(PIPECONF(crtc->pipe));
  5064. if (!(tmp & PIPECONF_ENABLE))
  5065. return false;
  5066. switch (tmp & PIPECONF_BPC_MASK) {
  5067. case PIPECONF_6BPC:
  5068. pipe_config->pipe_bpp = 18;
  5069. break;
  5070. case PIPECONF_8BPC:
  5071. pipe_config->pipe_bpp = 24;
  5072. break;
  5073. case PIPECONF_10BPC:
  5074. pipe_config->pipe_bpp = 30;
  5075. break;
  5076. case PIPECONF_12BPC:
  5077. pipe_config->pipe_bpp = 36;
  5078. break;
  5079. default:
  5080. break;
  5081. }
  5082. if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
  5083. struct intel_shared_dpll *pll;
  5084. pipe_config->has_pch_encoder = true;
  5085. tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
  5086. pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
  5087. FDI_DP_PORT_WIDTH_SHIFT) + 1;
  5088. ironlake_get_fdi_m_n_config(crtc, pipe_config);
  5089. if (HAS_PCH_IBX(dev_priv->dev)) {
  5090. pipe_config->shared_dpll =
  5091. (enum intel_dpll_id) crtc->pipe;
  5092. } else {
  5093. tmp = I915_READ(PCH_DPLL_SEL);
  5094. if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
  5095. pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
  5096. else
  5097. pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
  5098. }
  5099. pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
  5100. WARN_ON(!pll->get_hw_state(dev_priv, pll,
  5101. &pipe_config->dpll_hw_state));
  5102. tmp = pipe_config->dpll_hw_state.dpll;
  5103. pipe_config->pixel_multiplier =
  5104. ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
  5105. >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
  5106. ironlake_pch_clock_get(crtc, pipe_config);
  5107. } else {
  5108. pipe_config->pixel_multiplier = 1;
  5109. }
  5110. intel_get_pipe_timings(crtc, pipe_config);
  5111. ironlake_get_pfit_config(crtc, pipe_config);
  5112. return true;
  5113. }
  5114. static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
  5115. {
  5116. struct drm_device *dev = dev_priv->dev;
  5117. struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
  5118. struct intel_crtc *crtc;
  5119. unsigned long irqflags;
  5120. uint32_t val;
  5121. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
  5122. WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
  5123. pipe_name(crtc->pipe));
  5124. WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
  5125. WARN(plls->spll_refcount, "SPLL enabled\n");
  5126. WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
  5127. WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
  5128. WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
  5129. WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
  5130. "CPU PWM1 enabled\n");
  5131. WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
  5132. "CPU PWM2 enabled\n");
  5133. WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
  5134. "PCH PWM1 enabled\n");
  5135. WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
  5136. "Utility pin enabled\n");
  5137. WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
  5138. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  5139. val = I915_READ(DEIMR);
  5140. WARN((val & ~DE_PCH_EVENT_IVB) != val,
  5141. "Unexpected DEIMR bits enabled: 0x%x\n", val);
  5142. val = I915_READ(SDEIMR);
  5143. WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
  5144. "Unexpected SDEIMR bits enabled: 0x%x\n", val);
  5145. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  5146. }
  5147. /*
  5148. * This function implements pieces of two sequences from BSpec:
  5149. * - Sequence for display software to disable LCPLL
  5150. * - Sequence for display software to allow package C8+
  5151. * The steps implemented here are just the steps that actually touch the LCPLL
  5152. * register. Callers should take care of disabling all the display engine
  5153. * functions, doing the mode unset, fixing interrupts, etc.
  5154. */
  5155. void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
  5156. bool switch_to_fclk, bool allow_power_down)
  5157. {
  5158. uint32_t val;
  5159. assert_can_disable_lcpll(dev_priv);
  5160. val = I915_READ(LCPLL_CTL);
  5161. if (switch_to_fclk) {
  5162. val |= LCPLL_CD_SOURCE_FCLK;
  5163. I915_WRITE(LCPLL_CTL, val);
  5164. if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
  5165. LCPLL_CD_SOURCE_FCLK_DONE, 1))
  5166. DRM_ERROR("Switching to FCLK failed\n");
  5167. val = I915_READ(LCPLL_CTL);
  5168. }
  5169. val |= LCPLL_PLL_DISABLE;
  5170. I915_WRITE(LCPLL_CTL, val);
  5171. POSTING_READ(LCPLL_CTL);
  5172. if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
  5173. DRM_ERROR("LCPLL still locked\n");
  5174. val = I915_READ(D_COMP);
  5175. val |= D_COMP_COMP_DISABLE;
  5176. mutex_lock(&dev_priv->rps.hw_lock);
  5177. if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
  5178. DRM_ERROR("Failed to disable D_COMP\n");
  5179. mutex_unlock(&dev_priv->rps.hw_lock);
  5180. POSTING_READ(D_COMP);
  5181. ndelay(100);
  5182. if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
  5183. DRM_ERROR("D_COMP RCOMP still in progress\n");
  5184. if (allow_power_down) {
  5185. val = I915_READ(LCPLL_CTL);
  5186. val |= LCPLL_POWER_DOWN_ALLOW;
  5187. I915_WRITE(LCPLL_CTL, val);
  5188. POSTING_READ(LCPLL_CTL);
  5189. }
  5190. }
  5191. /*
  5192. * Fully restores LCPLL, disallowing power down and switching back to LCPLL
  5193. * source.
  5194. */
  5195. void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
  5196. {
  5197. uint32_t val;
  5198. val = I915_READ(LCPLL_CTL);
  5199. if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
  5200. LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
  5201. return;
  5202. /* Make sure we're not on PC8 state before disabling PC8, otherwise
  5203. * we'll hang the machine! */
  5204. dev_priv->uncore.funcs.force_wake_get(dev_priv);
  5205. if (val & LCPLL_POWER_DOWN_ALLOW) {
  5206. val &= ~LCPLL_POWER_DOWN_ALLOW;
  5207. I915_WRITE(LCPLL_CTL, val);
  5208. POSTING_READ(LCPLL_CTL);
  5209. }
  5210. val = I915_READ(D_COMP);
  5211. val |= D_COMP_COMP_FORCE;
  5212. val &= ~D_COMP_COMP_DISABLE;
  5213. mutex_lock(&dev_priv->rps.hw_lock);
  5214. if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
  5215. DRM_ERROR("Failed to enable D_COMP\n");
  5216. mutex_unlock(&dev_priv->rps.hw_lock);
  5217. POSTING_READ(D_COMP);
  5218. val = I915_READ(LCPLL_CTL);
  5219. val &= ~LCPLL_PLL_DISABLE;
  5220. I915_WRITE(LCPLL_CTL, val);
  5221. if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
  5222. DRM_ERROR("LCPLL not locked yet\n");
  5223. if (val & LCPLL_CD_SOURCE_FCLK) {
  5224. val = I915_READ(LCPLL_CTL);
  5225. val &= ~LCPLL_CD_SOURCE_FCLK;
  5226. I915_WRITE(LCPLL_CTL, val);
  5227. if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
  5228. LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
  5229. DRM_ERROR("Switching back to LCPLL failed\n");
  5230. }
  5231. dev_priv->uncore.funcs.force_wake_put(dev_priv);
  5232. }
  5233. void hsw_enable_pc8_work(struct work_struct *__work)
  5234. {
  5235. struct drm_i915_private *dev_priv =
  5236. container_of(to_delayed_work(__work), struct drm_i915_private,
  5237. pc8.enable_work);
  5238. struct drm_device *dev = dev_priv->dev;
  5239. uint32_t val;
  5240. if (dev_priv->pc8.enabled)
  5241. return;
  5242. DRM_DEBUG_KMS("Enabling package C8+\n");
  5243. dev_priv->pc8.enabled = true;
  5244. if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
  5245. val = I915_READ(SOUTH_DSPCLK_GATE_D);
  5246. val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
  5247. I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
  5248. }
  5249. lpt_disable_clkout_dp(dev);
  5250. hsw_pc8_disable_interrupts(dev);
  5251. hsw_disable_lcpll(dev_priv, true, true);
  5252. }
  5253. static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
  5254. {
  5255. WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
  5256. WARN(dev_priv->pc8.disable_count < 1,
  5257. "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
  5258. dev_priv->pc8.disable_count--;
  5259. if (dev_priv->pc8.disable_count != 0)
  5260. return;
  5261. schedule_delayed_work(&dev_priv->pc8.enable_work,
  5262. msecs_to_jiffies(i915_pc8_timeout));
  5263. }
  5264. static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
  5265. {
  5266. struct drm_device *dev = dev_priv->dev;
  5267. uint32_t val;
  5268. WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
  5269. WARN(dev_priv->pc8.disable_count < 0,
  5270. "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
  5271. dev_priv->pc8.disable_count++;
  5272. if (dev_priv->pc8.disable_count != 1)
  5273. return;
  5274. cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
  5275. if (!dev_priv->pc8.enabled)
  5276. return;
  5277. DRM_DEBUG_KMS("Disabling package C8+\n");
  5278. hsw_restore_lcpll(dev_priv);
  5279. hsw_pc8_restore_interrupts(dev);
  5280. lpt_init_pch_refclk(dev);
  5281. if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
  5282. val = I915_READ(SOUTH_DSPCLK_GATE_D);
  5283. val |= PCH_LP_PARTITION_LEVEL_DISABLE;
  5284. I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
  5285. }
  5286. intel_prepare_ddi(dev);
  5287. i915_gem_init_swizzling(dev);
  5288. mutex_lock(&dev_priv->rps.hw_lock);
  5289. gen6_update_ring_freq(dev);
  5290. mutex_unlock(&dev_priv->rps.hw_lock);
  5291. dev_priv->pc8.enabled = false;
  5292. }
  5293. void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
  5294. {
  5295. mutex_lock(&dev_priv->pc8.lock);
  5296. __hsw_enable_package_c8(dev_priv);
  5297. mutex_unlock(&dev_priv->pc8.lock);
  5298. }
  5299. void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
  5300. {
  5301. mutex_lock(&dev_priv->pc8.lock);
  5302. __hsw_disable_package_c8(dev_priv);
  5303. mutex_unlock(&dev_priv->pc8.lock);
  5304. }
  5305. static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
  5306. {
  5307. struct drm_device *dev = dev_priv->dev;
  5308. struct intel_crtc *crtc;
  5309. uint32_t val;
  5310. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
  5311. if (crtc->base.enabled)
  5312. return false;
  5313. /* This case is still possible since we have the i915.disable_power_well
  5314. * parameter and also the KVMr or something else might be requesting the
  5315. * power well. */
  5316. val = I915_READ(HSW_PWR_WELL_DRIVER);
  5317. if (val != 0) {
  5318. DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
  5319. return false;
  5320. }
  5321. return true;
  5322. }
  5323. /* Since we're called from modeset_global_resources there's no way to
  5324. * symmetrically increase and decrease the refcount, so we use
  5325. * dev_priv->pc8.requirements_met to track whether we already have the refcount
  5326. * or not.
  5327. */
  5328. static void hsw_update_package_c8(struct drm_device *dev)
  5329. {
  5330. struct drm_i915_private *dev_priv = dev->dev_private;
  5331. bool allow;
  5332. if (!i915_enable_pc8)
  5333. return;
  5334. mutex_lock(&dev_priv->pc8.lock);
  5335. allow = hsw_can_enable_package_c8(dev_priv);
  5336. if (allow == dev_priv->pc8.requirements_met)
  5337. goto done;
  5338. dev_priv->pc8.requirements_met = allow;
  5339. if (allow)
  5340. __hsw_enable_package_c8(dev_priv);
  5341. else
  5342. __hsw_disable_package_c8(dev_priv);
  5343. done:
  5344. mutex_unlock(&dev_priv->pc8.lock);
  5345. }
  5346. static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
  5347. {
  5348. if (!dev_priv->pc8.gpu_idle) {
  5349. dev_priv->pc8.gpu_idle = true;
  5350. hsw_enable_package_c8(dev_priv);
  5351. }
  5352. }
  5353. static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
  5354. {
  5355. if (dev_priv->pc8.gpu_idle) {
  5356. dev_priv->pc8.gpu_idle = false;
  5357. hsw_disable_package_c8(dev_priv);
  5358. }
  5359. }
  5360. static void haswell_modeset_global_resources(struct drm_device *dev)
  5361. {
  5362. bool enable = false;
  5363. struct intel_crtc *crtc;
  5364. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
  5365. if (!crtc->base.enabled)
  5366. continue;
  5367. if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
  5368. crtc->config.cpu_transcoder != TRANSCODER_EDP)
  5369. enable = true;
  5370. }
  5371. intel_set_power_well(dev, enable);
  5372. hsw_update_package_c8(dev);
  5373. }
  5374. static int haswell_crtc_mode_set(struct drm_crtc *crtc,
  5375. int x, int y,
  5376. struct drm_framebuffer *fb)
  5377. {
  5378. struct drm_device *dev = crtc->dev;
  5379. struct drm_i915_private *dev_priv = dev->dev_private;
  5380. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5381. int plane = intel_crtc->plane;
  5382. int ret;
  5383. if (!intel_ddi_pll_mode_set(crtc))
  5384. return -EINVAL;
  5385. /* Ensure that the cursor is valid for the new mode before changing... */
  5386. intel_crtc_update_cursor(crtc, true);
  5387. if (intel_crtc->config.has_dp_encoder)
  5388. intel_dp_set_m_n(intel_crtc);
  5389. intel_crtc->lowfreq_avail = false;
  5390. intel_set_pipe_timings(intel_crtc);
  5391. if (intel_crtc->config.has_pch_encoder) {
  5392. intel_cpu_transcoder_set_m_n(intel_crtc,
  5393. &intel_crtc->config.fdi_m_n);
  5394. }
  5395. haswell_set_pipeconf(crtc);
  5396. intel_set_pipe_csc(crtc);
  5397. /* Set up the display plane register */
  5398. I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
  5399. POSTING_READ(DSPCNTR(plane));
  5400. ret = intel_pipe_set_base(crtc, x, y, fb);
  5401. return ret;
  5402. }
  5403. static bool haswell_get_pipe_config(struct intel_crtc *crtc,
  5404. struct intel_crtc_config *pipe_config)
  5405. {
  5406. struct drm_device *dev = crtc->base.dev;
  5407. struct drm_i915_private *dev_priv = dev->dev_private;
  5408. enum intel_display_power_domain pfit_domain;
  5409. uint32_t tmp;
  5410. pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
  5411. pipe_config->shared_dpll = DPLL_ID_PRIVATE;
  5412. tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
  5413. if (tmp & TRANS_DDI_FUNC_ENABLE) {
  5414. enum pipe trans_edp_pipe;
  5415. switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
  5416. default:
  5417. WARN(1, "unknown pipe linked to edp transcoder\n");
  5418. case TRANS_DDI_EDP_INPUT_A_ONOFF:
  5419. case TRANS_DDI_EDP_INPUT_A_ON:
  5420. trans_edp_pipe = PIPE_A;
  5421. break;
  5422. case TRANS_DDI_EDP_INPUT_B_ONOFF:
  5423. trans_edp_pipe = PIPE_B;
  5424. break;
  5425. case TRANS_DDI_EDP_INPUT_C_ONOFF:
  5426. trans_edp_pipe = PIPE_C;
  5427. break;
  5428. }
  5429. if (trans_edp_pipe == crtc->pipe)
  5430. pipe_config->cpu_transcoder = TRANSCODER_EDP;
  5431. }
  5432. if (!intel_display_power_enabled(dev,
  5433. POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
  5434. return false;
  5435. tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
  5436. if (!(tmp & PIPECONF_ENABLE))
  5437. return false;
  5438. /*
  5439. * Haswell has only FDI/PCH transcoder A. It is which is connected to
  5440. * DDI E. So just check whether this pipe is wired to DDI E and whether
  5441. * the PCH transcoder is on.
  5442. */
  5443. tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
  5444. if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
  5445. I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
  5446. pipe_config->has_pch_encoder = true;
  5447. tmp = I915_READ(FDI_RX_CTL(PIPE_A));
  5448. pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
  5449. FDI_DP_PORT_WIDTH_SHIFT) + 1;
  5450. ironlake_get_fdi_m_n_config(crtc, pipe_config);
  5451. }
  5452. intel_get_pipe_timings(crtc, pipe_config);
  5453. pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
  5454. if (intel_display_power_enabled(dev, pfit_domain))
  5455. ironlake_get_pfit_config(crtc, pipe_config);
  5456. pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
  5457. (I915_READ(IPS_CTL) & IPS_ENABLE);
  5458. pipe_config->pixel_multiplier = 1;
  5459. return true;
  5460. }
  5461. static int intel_crtc_mode_set(struct drm_crtc *crtc,
  5462. int x, int y,
  5463. struct drm_framebuffer *fb)
  5464. {
  5465. struct drm_device *dev = crtc->dev;
  5466. struct drm_i915_private *dev_priv = dev->dev_private;
  5467. struct intel_encoder *encoder;
  5468. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5469. struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
  5470. int pipe = intel_crtc->pipe;
  5471. int ret;
  5472. drm_vblank_pre_modeset(dev, pipe);
  5473. ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
  5474. drm_vblank_post_modeset(dev, pipe);
  5475. if (ret != 0)
  5476. return ret;
  5477. for_each_encoder_on_crtc(dev, crtc, encoder) {
  5478. DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
  5479. encoder->base.base.id,
  5480. drm_get_encoder_name(&encoder->base),
  5481. mode->base.id, mode->name);
  5482. encoder->mode_set(encoder);
  5483. }
  5484. return 0;
  5485. }
  5486. static bool intel_eld_uptodate(struct drm_connector *connector,
  5487. int reg_eldv, uint32_t bits_eldv,
  5488. int reg_elda, uint32_t bits_elda,
  5489. int reg_edid)
  5490. {
  5491. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  5492. uint8_t *eld = connector->eld;
  5493. uint32_t i;
  5494. i = I915_READ(reg_eldv);
  5495. i &= bits_eldv;
  5496. if (!eld[0])
  5497. return !i;
  5498. if (!i)
  5499. return false;
  5500. i = I915_READ(reg_elda);
  5501. i &= ~bits_elda;
  5502. I915_WRITE(reg_elda, i);
  5503. for (i = 0; i < eld[2]; i++)
  5504. if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
  5505. return false;
  5506. return true;
  5507. }
  5508. static void g4x_write_eld(struct drm_connector *connector,
  5509. struct drm_crtc *crtc)
  5510. {
  5511. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  5512. uint8_t *eld = connector->eld;
  5513. uint32_t eldv;
  5514. uint32_t len;
  5515. uint32_t i;
  5516. i = I915_READ(G4X_AUD_VID_DID);
  5517. if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
  5518. eldv = G4X_ELDV_DEVCL_DEVBLC;
  5519. else
  5520. eldv = G4X_ELDV_DEVCTG;
  5521. if (intel_eld_uptodate(connector,
  5522. G4X_AUD_CNTL_ST, eldv,
  5523. G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
  5524. G4X_HDMIW_HDMIEDID))
  5525. return;
  5526. i = I915_READ(G4X_AUD_CNTL_ST);
  5527. i &= ~(eldv | G4X_ELD_ADDR);
  5528. len = (i >> 9) & 0x1f; /* ELD buffer size */
  5529. I915_WRITE(G4X_AUD_CNTL_ST, i);
  5530. if (!eld[0])
  5531. return;
  5532. len = min_t(uint8_t, eld[2], len);
  5533. DRM_DEBUG_DRIVER("ELD size %d\n", len);
  5534. for (i = 0; i < len; i++)
  5535. I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
  5536. i = I915_READ(G4X_AUD_CNTL_ST);
  5537. i |= eldv;
  5538. I915_WRITE(G4X_AUD_CNTL_ST, i);
  5539. }
  5540. static void haswell_write_eld(struct drm_connector *connector,
  5541. struct drm_crtc *crtc)
  5542. {
  5543. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  5544. uint8_t *eld = connector->eld;
  5545. struct drm_device *dev = crtc->dev;
  5546. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5547. uint32_t eldv;
  5548. uint32_t i;
  5549. int len;
  5550. int pipe = to_intel_crtc(crtc)->pipe;
  5551. int tmp;
  5552. int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
  5553. int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
  5554. int aud_config = HSW_AUD_CFG(pipe);
  5555. int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
  5556. DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
  5557. /* Audio output enable */
  5558. DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
  5559. tmp = I915_READ(aud_cntrl_st2);
  5560. tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
  5561. I915_WRITE(aud_cntrl_st2, tmp);
  5562. /* Wait for 1 vertical blank */
  5563. intel_wait_for_vblank(dev, pipe);
  5564. /* Set ELD valid state */
  5565. tmp = I915_READ(aud_cntrl_st2);
  5566. DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
  5567. tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
  5568. I915_WRITE(aud_cntrl_st2, tmp);
  5569. tmp = I915_READ(aud_cntrl_st2);
  5570. DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
  5571. /* Enable HDMI mode */
  5572. tmp = I915_READ(aud_config);
  5573. DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
  5574. /* clear N_programing_enable and N_value_index */
  5575. tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
  5576. I915_WRITE(aud_config, tmp);
  5577. DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
  5578. eldv = AUDIO_ELD_VALID_A << (pipe * 4);
  5579. intel_crtc->eld_vld = true;
  5580. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  5581. DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
  5582. eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
  5583. I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
  5584. } else
  5585. I915_WRITE(aud_config, 0);
  5586. if (intel_eld_uptodate(connector,
  5587. aud_cntrl_st2, eldv,
  5588. aud_cntl_st, IBX_ELD_ADDRESS,
  5589. hdmiw_hdmiedid))
  5590. return;
  5591. i = I915_READ(aud_cntrl_st2);
  5592. i &= ~eldv;
  5593. I915_WRITE(aud_cntrl_st2, i);
  5594. if (!eld[0])
  5595. return;
  5596. i = I915_READ(aud_cntl_st);
  5597. i &= ~IBX_ELD_ADDRESS;
  5598. I915_WRITE(aud_cntl_st, i);
  5599. i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
  5600. DRM_DEBUG_DRIVER("port num:%d\n", i);
  5601. len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
  5602. DRM_DEBUG_DRIVER("ELD size %d\n", len);
  5603. for (i = 0; i < len; i++)
  5604. I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
  5605. i = I915_READ(aud_cntrl_st2);
  5606. i |= eldv;
  5607. I915_WRITE(aud_cntrl_st2, i);
  5608. }
  5609. static void ironlake_write_eld(struct drm_connector *connector,
  5610. struct drm_crtc *crtc)
  5611. {
  5612. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  5613. uint8_t *eld = connector->eld;
  5614. uint32_t eldv;
  5615. uint32_t i;
  5616. int len;
  5617. int hdmiw_hdmiedid;
  5618. int aud_config;
  5619. int aud_cntl_st;
  5620. int aud_cntrl_st2;
  5621. int pipe = to_intel_crtc(crtc)->pipe;
  5622. if (HAS_PCH_IBX(connector->dev)) {
  5623. hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
  5624. aud_config = IBX_AUD_CFG(pipe);
  5625. aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
  5626. aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
  5627. } else {
  5628. hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
  5629. aud_config = CPT_AUD_CFG(pipe);
  5630. aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
  5631. aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
  5632. }
  5633. DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
  5634. i = I915_READ(aud_cntl_st);
  5635. i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
  5636. if (!i) {
  5637. DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
  5638. /* operate blindly on all ports */
  5639. eldv = IBX_ELD_VALIDB;
  5640. eldv |= IBX_ELD_VALIDB << 4;
  5641. eldv |= IBX_ELD_VALIDB << 8;
  5642. } else {
  5643. DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
  5644. eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
  5645. }
  5646. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  5647. DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
  5648. eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
  5649. I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
  5650. } else
  5651. I915_WRITE(aud_config, 0);
  5652. if (intel_eld_uptodate(connector,
  5653. aud_cntrl_st2, eldv,
  5654. aud_cntl_st, IBX_ELD_ADDRESS,
  5655. hdmiw_hdmiedid))
  5656. return;
  5657. i = I915_READ(aud_cntrl_st2);
  5658. i &= ~eldv;
  5659. I915_WRITE(aud_cntrl_st2, i);
  5660. if (!eld[0])
  5661. return;
  5662. i = I915_READ(aud_cntl_st);
  5663. i &= ~IBX_ELD_ADDRESS;
  5664. I915_WRITE(aud_cntl_st, i);
  5665. len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
  5666. DRM_DEBUG_DRIVER("ELD size %d\n", len);
  5667. for (i = 0; i < len; i++)
  5668. I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
  5669. i = I915_READ(aud_cntrl_st2);
  5670. i |= eldv;
  5671. I915_WRITE(aud_cntrl_st2, i);
  5672. }
  5673. void intel_write_eld(struct drm_encoder *encoder,
  5674. struct drm_display_mode *mode)
  5675. {
  5676. struct drm_crtc *crtc = encoder->crtc;
  5677. struct drm_connector *connector;
  5678. struct drm_device *dev = encoder->dev;
  5679. struct drm_i915_private *dev_priv = dev->dev_private;
  5680. connector = drm_select_eld(encoder, mode);
  5681. if (!connector)
  5682. return;
  5683. DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  5684. connector->base.id,
  5685. drm_get_connector_name(connector),
  5686. connector->encoder->base.id,
  5687. drm_get_encoder_name(connector->encoder));
  5688. connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
  5689. if (dev_priv->display.write_eld)
  5690. dev_priv->display.write_eld(connector, crtc);
  5691. }
  5692. /** Loads the palette/gamma unit for the CRTC with the prepared values */
  5693. void intel_crtc_load_lut(struct drm_crtc *crtc)
  5694. {
  5695. struct drm_device *dev = crtc->dev;
  5696. struct drm_i915_private *dev_priv = dev->dev_private;
  5697. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5698. enum pipe pipe = intel_crtc->pipe;
  5699. int palreg = PALETTE(pipe);
  5700. int i;
  5701. bool reenable_ips = false;
  5702. /* The clocks have to be on to load the palette. */
  5703. if (!crtc->enabled || !intel_crtc->active)
  5704. return;
  5705. if (!HAS_PCH_SPLIT(dev_priv->dev)) {
  5706. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
  5707. assert_dsi_pll_enabled(dev_priv);
  5708. else
  5709. assert_pll_enabled(dev_priv, pipe);
  5710. }
  5711. /* use legacy palette for Ironlake */
  5712. if (HAS_PCH_SPLIT(dev))
  5713. palreg = LGC_PALETTE(pipe);
  5714. /* Workaround : Do not read or write the pipe palette/gamma data while
  5715. * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
  5716. */
  5717. if (intel_crtc->config.ips_enabled &&
  5718. ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
  5719. GAMMA_MODE_MODE_SPLIT)) {
  5720. hsw_disable_ips(intel_crtc);
  5721. reenable_ips = true;
  5722. }
  5723. for (i = 0; i < 256; i++) {
  5724. I915_WRITE(palreg + 4 * i,
  5725. (intel_crtc->lut_r[i] << 16) |
  5726. (intel_crtc->lut_g[i] << 8) |
  5727. intel_crtc->lut_b[i]);
  5728. }
  5729. if (reenable_ips)
  5730. hsw_enable_ips(intel_crtc);
  5731. }
  5732. static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
  5733. {
  5734. struct drm_device *dev = crtc->dev;
  5735. struct drm_i915_private *dev_priv = dev->dev_private;
  5736. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5737. bool visible = base != 0;
  5738. u32 cntl;
  5739. if (intel_crtc->cursor_visible == visible)
  5740. return;
  5741. cntl = I915_READ(_CURACNTR);
  5742. if (visible) {
  5743. /* On these chipsets we can only modify the base whilst
  5744. * the cursor is disabled.
  5745. */
  5746. I915_WRITE(_CURABASE, base);
  5747. cntl &= ~(CURSOR_FORMAT_MASK);
  5748. /* XXX width must be 64, stride 256 => 0x00 << 28 */
  5749. cntl |= CURSOR_ENABLE |
  5750. CURSOR_GAMMA_ENABLE |
  5751. CURSOR_FORMAT_ARGB;
  5752. } else
  5753. cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
  5754. I915_WRITE(_CURACNTR, cntl);
  5755. intel_crtc->cursor_visible = visible;
  5756. }
  5757. static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
  5758. {
  5759. struct drm_device *dev = crtc->dev;
  5760. struct drm_i915_private *dev_priv = dev->dev_private;
  5761. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5762. int pipe = intel_crtc->pipe;
  5763. bool visible = base != 0;
  5764. if (intel_crtc->cursor_visible != visible) {
  5765. uint32_t cntl = I915_READ(CURCNTR(pipe));
  5766. if (base) {
  5767. cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
  5768. cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  5769. cntl |= pipe << 28; /* Connect to correct pipe */
  5770. } else {
  5771. cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  5772. cntl |= CURSOR_MODE_DISABLE;
  5773. }
  5774. I915_WRITE(CURCNTR(pipe), cntl);
  5775. intel_crtc->cursor_visible = visible;
  5776. }
  5777. /* and commit changes on next vblank */
  5778. I915_WRITE(CURBASE(pipe), base);
  5779. }
  5780. static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
  5781. {
  5782. struct drm_device *dev = crtc->dev;
  5783. struct drm_i915_private *dev_priv = dev->dev_private;
  5784. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5785. int pipe = intel_crtc->pipe;
  5786. bool visible = base != 0;
  5787. if (intel_crtc->cursor_visible != visible) {
  5788. uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
  5789. if (base) {
  5790. cntl &= ~CURSOR_MODE;
  5791. cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  5792. } else {
  5793. cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  5794. cntl |= CURSOR_MODE_DISABLE;
  5795. }
  5796. if (IS_HASWELL(dev)) {
  5797. cntl |= CURSOR_PIPE_CSC_ENABLE;
  5798. cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
  5799. }
  5800. I915_WRITE(CURCNTR_IVB(pipe), cntl);
  5801. intel_crtc->cursor_visible = visible;
  5802. }
  5803. /* and commit changes on next vblank */
  5804. I915_WRITE(CURBASE_IVB(pipe), base);
  5805. }
  5806. /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
  5807. static void intel_crtc_update_cursor(struct drm_crtc *crtc,
  5808. bool on)
  5809. {
  5810. struct drm_device *dev = crtc->dev;
  5811. struct drm_i915_private *dev_priv = dev->dev_private;
  5812. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5813. int pipe = intel_crtc->pipe;
  5814. int x = intel_crtc->cursor_x;
  5815. int y = intel_crtc->cursor_y;
  5816. u32 base = 0, pos = 0;
  5817. bool visible;
  5818. if (on)
  5819. base = intel_crtc->cursor_addr;
  5820. if (x >= intel_crtc->config.pipe_src_w)
  5821. base = 0;
  5822. if (y >= intel_crtc->config.pipe_src_h)
  5823. base = 0;
  5824. if (x < 0) {
  5825. if (x + intel_crtc->cursor_width <= 0)
  5826. base = 0;
  5827. pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
  5828. x = -x;
  5829. }
  5830. pos |= x << CURSOR_X_SHIFT;
  5831. if (y < 0) {
  5832. if (y + intel_crtc->cursor_height <= 0)
  5833. base = 0;
  5834. pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
  5835. y = -y;
  5836. }
  5837. pos |= y << CURSOR_Y_SHIFT;
  5838. visible = base != 0;
  5839. if (!visible && !intel_crtc->cursor_visible)
  5840. return;
  5841. if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
  5842. I915_WRITE(CURPOS_IVB(pipe), pos);
  5843. ivb_update_cursor(crtc, base);
  5844. } else {
  5845. I915_WRITE(CURPOS(pipe), pos);
  5846. if (IS_845G(dev) || IS_I865G(dev))
  5847. i845_update_cursor(crtc, base);
  5848. else
  5849. i9xx_update_cursor(crtc, base);
  5850. }
  5851. }
  5852. static int intel_crtc_cursor_set(struct drm_crtc *crtc,
  5853. struct drm_file *file,
  5854. uint32_t handle,
  5855. uint32_t width, uint32_t height)
  5856. {
  5857. struct drm_device *dev = crtc->dev;
  5858. struct drm_i915_private *dev_priv = dev->dev_private;
  5859. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5860. struct drm_i915_gem_object *obj;
  5861. uint32_t addr;
  5862. int ret;
  5863. /* if we want to turn off the cursor ignore width and height */
  5864. if (!handle) {
  5865. DRM_DEBUG_KMS("cursor off\n");
  5866. addr = 0;
  5867. obj = NULL;
  5868. mutex_lock(&dev->struct_mutex);
  5869. goto finish;
  5870. }
  5871. /* Currently we only support 64x64 cursors */
  5872. if (width != 64 || height != 64) {
  5873. DRM_ERROR("we currently only support 64x64 cursors\n");
  5874. return -EINVAL;
  5875. }
  5876. obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
  5877. if (&obj->base == NULL)
  5878. return -ENOENT;
  5879. if (obj->base.size < width * height * 4) {
  5880. DRM_ERROR("buffer is to small\n");
  5881. ret = -ENOMEM;
  5882. goto fail;
  5883. }
  5884. /* we only need to pin inside GTT if cursor is non-phy */
  5885. mutex_lock(&dev->struct_mutex);
  5886. if (!dev_priv->info->cursor_needs_physical) {
  5887. unsigned alignment;
  5888. if (obj->tiling_mode) {
  5889. DRM_ERROR("cursor cannot be tiled\n");
  5890. ret = -EINVAL;
  5891. goto fail_locked;
  5892. }
  5893. /* Note that the w/a also requires 2 PTE of padding following
  5894. * the bo. We currently fill all unused PTE with the shadow
  5895. * page and so we should always have valid PTE following the
  5896. * cursor preventing the VT-d warning.
  5897. */
  5898. alignment = 0;
  5899. if (need_vtd_wa(dev))
  5900. alignment = 64*1024;
  5901. ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
  5902. if (ret) {
  5903. DRM_ERROR("failed to move cursor bo into the GTT\n");
  5904. goto fail_locked;
  5905. }
  5906. ret = i915_gem_object_put_fence(obj);
  5907. if (ret) {
  5908. DRM_ERROR("failed to release fence for cursor");
  5909. goto fail_unpin;
  5910. }
  5911. addr = i915_gem_obj_ggtt_offset(obj);
  5912. } else {
  5913. int align = IS_I830(dev) ? 16 * 1024 : 256;
  5914. ret = i915_gem_attach_phys_object(dev, obj,
  5915. (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
  5916. align);
  5917. if (ret) {
  5918. DRM_ERROR("failed to attach phys object\n");
  5919. goto fail_locked;
  5920. }
  5921. addr = obj->phys_obj->handle->busaddr;
  5922. }
  5923. if (IS_GEN2(dev))
  5924. I915_WRITE(CURSIZE, (height << 12) | width);
  5925. finish:
  5926. if (intel_crtc->cursor_bo) {
  5927. if (dev_priv->info->cursor_needs_physical) {
  5928. if (intel_crtc->cursor_bo != obj)
  5929. i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
  5930. } else
  5931. i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
  5932. drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
  5933. }
  5934. mutex_unlock(&dev->struct_mutex);
  5935. intel_crtc->cursor_addr = addr;
  5936. intel_crtc->cursor_bo = obj;
  5937. intel_crtc->cursor_width = width;
  5938. intel_crtc->cursor_height = height;
  5939. intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
  5940. return 0;
  5941. fail_unpin:
  5942. i915_gem_object_unpin_from_display_plane(obj);
  5943. fail_locked:
  5944. mutex_unlock(&dev->struct_mutex);
  5945. fail:
  5946. drm_gem_object_unreference_unlocked(&obj->base);
  5947. return ret;
  5948. }
  5949. static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  5950. {
  5951. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5952. intel_crtc->cursor_x = x;
  5953. intel_crtc->cursor_y = y;
  5954. intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
  5955. return 0;
  5956. }
  5957. /** Sets the color ramps on behalf of RandR */
  5958. void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  5959. u16 blue, int regno)
  5960. {
  5961. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5962. intel_crtc->lut_r[regno] = red >> 8;
  5963. intel_crtc->lut_g[regno] = green >> 8;
  5964. intel_crtc->lut_b[regno] = blue >> 8;
  5965. }
  5966. void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  5967. u16 *blue, int regno)
  5968. {
  5969. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5970. *red = intel_crtc->lut_r[regno] << 8;
  5971. *green = intel_crtc->lut_g[regno] << 8;
  5972. *blue = intel_crtc->lut_b[regno] << 8;
  5973. }
  5974. static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  5975. u16 *blue, uint32_t start, uint32_t size)
  5976. {
  5977. int end = (start + size > 256) ? 256 : start + size, i;
  5978. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5979. for (i = start; i < end; i++) {
  5980. intel_crtc->lut_r[i] = red[i] >> 8;
  5981. intel_crtc->lut_g[i] = green[i] >> 8;
  5982. intel_crtc->lut_b[i] = blue[i] >> 8;
  5983. }
  5984. intel_crtc_load_lut(crtc);
  5985. }
  5986. /* VESA 640x480x72Hz mode to set on the pipe */
  5987. static struct drm_display_mode load_detect_mode = {
  5988. DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
  5989. 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  5990. };
  5991. static struct drm_framebuffer *
  5992. intel_framebuffer_create(struct drm_device *dev,
  5993. struct drm_mode_fb_cmd2 *mode_cmd,
  5994. struct drm_i915_gem_object *obj)
  5995. {
  5996. struct intel_framebuffer *intel_fb;
  5997. int ret;
  5998. intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  5999. if (!intel_fb) {
  6000. drm_gem_object_unreference_unlocked(&obj->base);
  6001. return ERR_PTR(-ENOMEM);
  6002. }
  6003. ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
  6004. if (ret) {
  6005. drm_gem_object_unreference_unlocked(&obj->base);
  6006. kfree(intel_fb);
  6007. return ERR_PTR(ret);
  6008. }
  6009. return &intel_fb->base;
  6010. }
  6011. static u32
  6012. intel_framebuffer_pitch_for_width(int width, int bpp)
  6013. {
  6014. u32 pitch = DIV_ROUND_UP(width * bpp, 8);
  6015. return ALIGN(pitch, 64);
  6016. }
  6017. static u32
  6018. intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
  6019. {
  6020. u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
  6021. return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
  6022. }
  6023. static struct drm_framebuffer *
  6024. intel_framebuffer_create_for_mode(struct drm_device *dev,
  6025. struct drm_display_mode *mode,
  6026. int depth, int bpp)
  6027. {
  6028. struct drm_i915_gem_object *obj;
  6029. struct drm_mode_fb_cmd2 mode_cmd = { 0 };
  6030. obj = i915_gem_alloc_object(dev,
  6031. intel_framebuffer_size_for_mode(mode, bpp));
  6032. if (obj == NULL)
  6033. return ERR_PTR(-ENOMEM);
  6034. mode_cmd.width = mode->hdisplay;
  6035. mode_cmd.height = mode->vdisplay;
  6036. mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
  6037. bpp);
  6038. mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
  6039. return intel_framebuffer_create(dev, &mode_cmd, obj);
  6040. }
  6041. static struct drm_framebuffer *
  6042. mode_fits_in_fbdev(struct drm_device *dev,
  6043. struct drm_display_mode *mode)
  6044. {
  6045. struct drm_i915_private *dev_priv = dev->dev_private;
  6046. struct drm_i915_gem_object *obj;
  6047. struct drm_framebuffer *fb;
  6048. if (dev_priv->fbdev == NULL)
  6049. return NULL;
  6050. obj = dev_priv->fbdev->ifb.obj;
  6051. if (obj == NULL)
  6052. return NULL;
  6053. fb = &dev_priv->fbdev->ifb.base;
  6054. if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
  6055. fb->bits_per_pixel))
  6056. return NULL;
  6057. if (obj->base.size < mode->vdisplay * fb->pitches[0])
  6058. return NULL;
  6059. return fb;
  6060. }
  6061. bool intel_get_load_detect_pipe(struct drm_connector *connector,
  6062. struct drm_display_mode *mode,
  6063. struct intel_load_detect_pipe *old)
  6064. {
  6065. struct intel_crtc *intel_crtc;
  6066. struct intel_encoder *intel_encoder =
  6067. intel_attached_encoder(connector);
  6068. struct drm_crtc *possible_crtc;
  6069. struct drm_encoder *encoder = &intel_encoder->base;
  6070. struct drm_crtc *crtc = NULL;
  6071. struct drm_device *dev = encoder->dev;
  6072. struct drm_framebuffer *fb;
  6073. int i = -1;
  6074. DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  6075. connector->base.id, drm_get_connector_name(connector),
  6076. encoder->base.id, drm_get_encoder_name(encoder));
  6077. /*
  6078. * Algorithm gets a little messy:
  6079. *
  6080. * - if the connector already has an assigned crtc, use it (but make
  6081. * sure it's on first)
  6082. *
  6083. * - try to find the first unused crtc that can drive this connector,
  6084. * and use that if we find one
  6085. */
  6086. /* See if we already have a CRTC for this connector */
  6087. if (encoder->crtc) {
  6088. crtc = encoder->crtc;
  6089. mutex_lock(&crtc->mutex);
  6090. old->dpms_mode = connector->dpms;
  6091. old->load_detect_temp = false;
  6092. /* Make sure the crtc and connector are running */
  6093. if (connector->dpms != DRM_MODE_DPMS_ON)
  6094. connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
  6095. return true;
  6096. }
  6097. /* Find an unused one (if possible) */
  6098. list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
  6099. i++;
  6100. if (!(encoder->possible_crtcs & (1 << i)))
  6101. continue;
  6102. if (!possible_crtc->enabled) {
  6103. crtc = possible_crtc;
  6104. break;
  6105. }
  6106. }
  6107. /*
  6108. * If we didn't find an unused CRTC, don't use any.
  6109. */
  6110. if (!crtc) {
  6111. DRM_DEBUG_KMS("no pipe available for load-detect\n");
  6112. return false;
  6113. }
  6114. mutex_lock(&crtc->mutex);
  6115. intel_encoder->new_crtc = to_intel_crtc(crtc);
  6116. to_intel_connector(connector)->new_encoder = intel_encoder;
  6117. intel_crtc = to_intel_crtc(crtc);
  6118. old->dpms_mode = connector->dpms;
  6119. old->load_detect_temp = true;
  6120. old->release_fb = NULL;
  6121. if (!mode)
  6122. mode = &load_detect_mode;
  6123. /* We need a framebuffer large enough to accommodate all accesses
  6124. * that the plane may generate whilst we perform load detection.
  6125. * We can not rely on the fbcon either being present (we get called
  6126. * during its initialisation to detect all boot displays, or it may
  6127. * not even exist) or that it is large enough to satisfy the
  6128. * requested mode.
  6129. */
  6130. fb = mode_fits_in_fbdev(dev, mode);
  6131. if (fb == NULL) {
  6132. DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
  6133. fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
  6134. old->release_fb = fb;
  6135. } else
  6136. DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
  6137. if (IS_ERR(fb)) {
  6138. DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
  6139. mutex_unlock(&crtc->mutex);
  6140. return false;
  6141. }
  6142. if (intel_set_mode(crtc, mode, 0, 0, fb)) {
  6143. DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
  6144. if (old->release_fb)
  6145. old->release_fb->funcs->destroy(old->release_fb);
  6146. mutex_unlock(&crtc->mutex);
  6147. return false;
  6148. }
  6149. /* let the connector get through one full cycle before testing */
  6150. intel_wait_for_vblank(dev, intel_crtc->pipe);
  6151. return true;
  6152. }
  6153. void intel_release_load_detect_pipe(struct drm_connector *connector,
  6154. struct intel_load_detect_pipe *old)
  6155. {
  6156. struct intel_encoder *intel_encoder =
  6157. intel_attached_encoder(connector);
  6158. struct drm_encoder *encoder = &intel_encoder->base;
  6159. struct drm_crtc *crtc = encoder->crtc;
  6160. DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  6161. connector->base.id, drm_get_connector_name(connector),
  6162. encoder->base.id, drm_get_encoder_name(encoder));
  6163. if (old->load_detect_temp) {
  6164. to_intel_connector(connector)->new_encoder = NULL;
  6165. intel_encoder->new_crtc = NULL;
  6166. intel_set_mode(crtc, NULL, 0, 0, NULL);
  6167. if (old->release_fb) {
  6168. drm_framebuffer_unregister_private(old->release_fb);
  6169. drm_framebuffer_unreference(old->release_fb);
  6170. }
  6171. mutex_unlock(&crtc->mutex);
  6172. return;
  6173. }
  6174. /* Switch crtc and encoder back off if necessary */
  6175. if (old->dpms_mode != DRM_MODE_DPMS_ON)
  6176. connector->funcs->dpms(connector, old->dpms_mode);
  6177. mutex_unlock(&crtc->mutex);
  6178. }
  6179. static int i9xx_pll_refclk(struct drm_device *dev,
  6180. const struct intel_crtc_config *pipe_config)
  6181. {
  6182. struct drm_i915_private *dev_priv = dev->dev_private;
  6183. u32 dpll = pipe_config->dpll_hw_state.dpll;
  6184. if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
  6185. return dev_priv->vbt.lvds_ssc_freq * 1000;
  6186. else if (HAS_PCH_SPLIT(dev))
  6187. return 120000;
  6188. else if (!IS_GEN2(dev))
  6189. return 96000;
  6190. else
  6191. return 48000;
  6192. }
  6193. /* Returns the clock of the currently programmed mode of the given pipe. */
  6194. static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  6195. struct intel_crtc_config *pipe_config)
  6196. {
  6197. struct drm_device *dev = crtc->base.dev;
  6198. struct drm_i915_private *dev_priv = dev->dev_private;
  6199. int pipe = pipe_config->cpu_transcoder;
  6200. u32 dpll = pipe_config->dpll_hw_state.dpll;
  6201. u32 fp;
  6202. intel_clock_t clock;
  6203. int refclk = i9xx_pll_refclk(dev, pipe_config);
  6204. if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
  6205. fp = pipe_config->dpll_hw_state.fp0;
  6206. else
  6207. fp = pipe_config->dpll_hw_state.fp1;
  6208. clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
  6209. if (IS_PINEVIEW(dev)) {
  6210. clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
  6211. clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
  6212. } else {
  6213. clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
  6214. clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
  6215. }
  6216. if (!IS_GEN2(dev)) {
  6217. if (IS_PINEVIEW(dev))
  6218. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
  6219. DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
  6220. else
  6221. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
  6222. DPLL_FPA01_P1_POST_DIV_SHIFT);
  6223. switch (dpll & DPLL_MODE_MASK) {
  6224. case DPLLB_MODE_DAC_SERIAL:
  6225. clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
  6226. 5 : 10;
  6227. break;
  6228. case DPLLB_MODE_LVDS:
  6229. clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
  6230. 7 : 14;
  6231. break;
  6232. default:
  6233. DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
  6234. "mode\n", (int)(dpll & DPLL_MODE_MASK));
  6235. return;
  6236. }
  6237. if (IS_PINEVIEW(dev))
  6238. pineview_clock(refclk, &clock);
  6239. else
  6240. i9xx_clock(refclk, &clock);
  6241. } else {
  6242. bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
  6243. if (is_lvds) {
  6244. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
  6245. DPLL_FPA01_P1_POST_DIV_SHIFT);
  6246. clock.p2 = 14;
  6247. } else {
  6248. if (dpll & PLL_P1_DIVIDE_BY_TWO)
  6249. clock.p1 = 2;
  6250. else {
  6251. clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
  6252. DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
  6253. }
  6254. if (dpll & PLL_P2_DIVIDE_BY_4)
  6255. clock.p2 = 4;
  6256. else
  6257. clock.p2 = 2;
  6258. }
  6259. i9xx_clock(refclk, &clock);
  6260. }
  6261. /*
  6262. * This value includes pixel_multiplier. We will use
  6263. * port_clock to compute adjusted_mode.clock in the
  6264. * encoder's get_config() function.
  6265. */
  6266. pipe_config->port_clock = clock.dot;
  6267. }
  6268. int intel_dotclock_calculate(int link_freq,
  6269. const struct intel_link_m_n *m_n)
  6270. {
  6271. /*
  6272. * The calculation for the data clock is:
  6273. * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
  6274. * But we want to avoid losing precison if possible, so:
  6275. * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
  6276. *
  6277. * and the link clock is simpler:
  6278. * link_clock = (m * link_clock) / n
  6279. */
  6280. if (!m_n->link_n)
  6281. return 0;
  6282. return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
  6283. }
  6284. static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  6285. struct intel_crtc_config *pipe_config)
  6286. {
  6287. struct drm_device *dev = crtc->base.dev;
  6288. /* read out port_clock from the DPLL */
  6289. i9xx_crtc_clock_get(crtc, pipe_config);
  6290. /*
  6291. * This value does not include pixel_multiplier.
  6292. * We will check that port_clock and adjusted_mode.clock
  6293. * agree once we know their relationship in the encoder's
  6294. * get_config() function.
  6295. */
  6296. pipe_config->adjusted_mode.clock =
  6297. intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
  6298. &pipe_config->fdi_m_n);
  6299. }
  6300. /** Returns the currently programmed mode of the given pipe. */
  6301. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  6302. struct drm_crtc *crtc)
  6303. {
  6304. struct drm_i915_private *dev_priv = dev->dev_private;
  6305. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6306. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  6307. struct drm_display_mode *mode;
  6308. struct intel_crtc_config pipe_config;
  6309. int htot = I915_READ(HTOTAL(cpu_transcoder));
  6310. int hsync = I915_READ(HSYNC(cpu_transcoder));
  6311. int vtot = I915_READ(VTOTAL(cpu_transcoder));
  6312. int vsync = I915_READ(VSYNC(cpu_transcoder));
  6313. enum pipe pipe = intel_crtc->pipe;
  6314. mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  6315. if (!mode)
  6316. return NULL;
  6317. /*
  6318. * Construct a pipe_config sufficient for getting the clock info
  6319. * back out of crtc_clock_get.
  6320. *
  6321. * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
  6322. * to use a real value here instead.
  6323. */
  6324. pipe_config.cpu_transcoder = (enum transcoder) pipe;
  6325. pipe_config.pixel_multiplier = 1;
  6326. pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
  6327. pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
  6328. pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
  6329. i9xx_crtc_clock_get(intel_crtc, &pipe_config);
  6330. mode->clock = pipe_config.adjusted_mode.clock;
  6331. mode->hdisplay = (htot & 0xffff) + 1;
  6332. mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
  6333. mode->hsync_start = (hsync & 0xffff) + 1;
  6334. mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
  6335. mode->vdisplay = (vtot & 0xffff) + 1;
  6336. mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
  6337. mode->vsync_start = (vsync & 0xffff) + 1;
  6338. mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
  6339. drm_mode_set_name(mode);
  6340. return mode;
  6341. }
  6342. static void intel_increase_pllclock(struct drm_crtc *crtc)
  6343. {
  6344. struct drm_device *dev = crtc->dev;
  6345. drm_i915_private_t *dev_priv = dev->dev_private;
  6346. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6347. int pipe = intel_crtc->pipe;
  6348. int dpll_reg = DPLL(pipe);
  6349. int dpll;
  6350. if (HAS_PCH_SPLIT(dev))
  6351. return;
  6352. if (!dev_priv->lvds_downclock_avail)
  6353. return;
  6354. dpll = I915_READ(dpll_reg);
  6355. if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
  6356. DRM_DEBUG_DRIVER("upclocking LVDS\n");
  6357. assert_panel_unlocked(dev_priv, pipe);
  6358. dpll &= ~DISPLAY_RATE_SELECT_FPA1;
  6359. I915_WRITE(dpll_reg, dpll);
  6360. intel_wait_for_vblank(dev, pipe);
  6361. dpll = I915_READ(dpll_reg);
  6362. if (dpll & DISPLAY_RATE_SELECT_FPA1)
  6363. DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
  6364. }
  6365. }
  6366. static void intel_decrease_pllclock(struct drm_crtc *crtc)
  6367. {
  6368. struct drm_device *dev = crtc->dev;
  6369. drm_i915_private_t *dev_priv = dev->dev_private;
  6370. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6371. if (HAS_PCH_SPLIT(dev))
  6372. return;
  6373. if (!dev_priv->lvds_downclock_avail)
  6374. return;
  6375. /*
  6376. * Since this is called by a timer, we should never get here in
  6377. * the manual case.
  6378. */
  6379. if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
  6380. int pipe = intel_crtc->pipe;
  6381. int dpll_reg = DPLL(pipe);
  6382. int dpll;
  6383. DRM_DEBUG_DRIVER("downclocking LVDS\n");
  6384. assert_panel_unlocked(dev_priv, pipe);
  6385. dpll = I915_READ(dpll_reg);
  6386. dpll |= DISPLAY_RATE_SELECT_FPA1;
  6387. I915_WRITE(dpll_reg, dpll);
  6388. intel_wait_for_vblank(dev, pipe);
  6389. dpll = I915_READ(dpll_reg);
  6390. if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
  6391. DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
  6392. }
  6393. }
  6394. void intel_mark_busy(struct drm_device *dev)
  6395. {
  6396. struct drm_i915_private *dev_priv = dev->dev_private;
  6397. hsw_package_c8_gpu_busy(dev_priv);
  6398. i915_update_gfx_val(dev_priv);
  6399. }
  6400. void intel_mark_idle(struct drm_device *dev)
  6401. {
  6402. struct drm_i915_private *dev_priv = dev->dev_private;
  6403. struct drm_crtc *crtc;
  6404. hsw_package_c8_gpu_idle(dev_priv);
  6405. if (!i915_powersave)
  6406. return;
  6407. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  6408. if (!crtc->fb)
  6409. continue;
  6410. intel_decrease_pllclock(crtc);
  6411. }
  6412. }
  6413. void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
  6414. struct intel_ring_buffer *ring)
  6415. {
  6416. struct drm_device *dev = obj->base.dev;
  6417. struct drm_crtc *crtc;
  6418. if (!i915_powersave)
  6419. return;
  6420. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  6421. if (!crtc->fb)
  6422. continue;
  6423. if (to_intel_framebuffer(crtc->fb)->obj != obj)
  6424. continue;
  6425. intel_increase_pllclock(crtc);
  6426. if (ring && intel_fbc_enabled(dev))
  6427. ring->fbc_dirty = true;
  6428. }
  6429. }
  6430. static void intel_crtc_destroy(struct drm_crtc *crtc)
  6431. {
  6432. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6433. struct drm_device *dev = crtc->dev;
  6434. struct intel_unpin_work *work;
  6435. unsigned long flags;
  6436. spin_lock_irqsave(&dev->event_lock, flags);
  6437. work = intel_crtc->unpin_work;
  6438. intel_crtc->unpin_work = NULL;
  6439. spin_unlock_irqrestore(&dev->event_lock, flags);
  6440. if (work) {
  6441. cancel_work_sync(&work->work);
  6442. kfree(work);
  6443. }
  6444. intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
  6445. drm_crtc_cleanup(crtc);
  6446. kfree(intel_crtc);
  6447. }
  6448. static void intel_unpin_work_fn(struct work_struct *__work)
  6449. {
  6450. struct intel_unpin_work *work =
  6451. container_of(__work, struct intel_unpin_work, work);
  6452. struct drm_device *dev = work->crtc->dev;
  6453. mutex_lock(&dev->struct_mutex);
  6454. intel_unpin_fb_obj(work->old_fb_obj);
  6455. drm_gem_object_unreference(&work->pending_flip_obj->base);
  6456. drm_gem_object_unreference(&work->old_fb_obj->base);
  6457. intel_update_fbc(dev);
  6458. mutex_unlock(&dev->struct_mutex);
  6459. BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
  6460. atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
  6461. kfree(work);
  6462. }
  6463. static void do_intel_finish_page_flip(struct drm_device *dev,
  6464. struct drm_crtc *crtc)
  6465. {
  6466. drm_i915_private_t *dev_priv = dev->dev_private;
  6467. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6468. struct intel_unpin_work *work;
  6469. unsigned long flags;
  6470. /* Ignore early vblank irqs */
  6471. if (intel_crtc == NULL)
  6472. return;
  6473. spin_lock_irqsave(&dev->event_lock, flags);
  6474. work = intel_crtc->unpin_work;
  6475. /* Ensure we don't miss a work->pending update ... */
  6476. smp_rmb();
  6477. if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
  6478. spin_unlock_irqrestore(&dev->event_lock, flags);
  6479. return;
  6480. }
  6481. /* and that the unpin work is consistent wrt ->pending. */
  6482. smp_rmb();
  6483. intel_crtc->unpin_work = NULL;
  6484. if (work->event)
  6485. drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
  6486. drm_vblank_put(dev, intel_crtc->pipe);
  6487. spin_unlock_irqrestore(&dev->event_lock, flags);
  6488. wake_up_all(&dev_priv->pending_flip_queue);
  6489. queue_work(dev_priv->wq, &work->work);
  6490. trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
  6491. }
  6492. void intel_finish_page_flip(struct drm_device *dev, int pipe)
  6493. {
  6494. drm_i915_private_t *dev_priv = dev->dev_private;
  6495. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  6496. do_intel_finish_page_flip(dev, crtc);
  6497. }
  6498. void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
  6499. {
  6500. drm_i915_private_t *dev_priv = dev->dev_private;
  6501. struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
  6502. do_intel_finish_page_flip(dev, crtc);
  6503. }
  6504. void intel_prepare_page_flip(struct drm_device *dev, int plane)
  6505. {
  6506. drm_i915_private_t *dev_priv = dev->dev_private;
  6507. struct intel_crtc *intel_crtc =
  6508. to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
  6509. unsigned long flags;
  6510. /* NB: An MMIO update of the plane base pointer will also
  6511. * generate a page-flip completion irq, i.e. every modeset
  6512. * is also accompanied by a spurious intel_prepare_page_flip().
  6513. */
  6514. spin_lock_irqsave(&dev->event_lock, flags);
  6515. if (intel_crtc->unpin_work)
  6516. atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
  6517. spin_unlock_irqrestore(&dev->event_lock, flags);
  6518. }
  6519. inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
  6520. {
  6521. /* Ensure that the work item is consistent when activating it ... */
  6522. smp_wmb();
  6523. atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
  6524. /* and that it is marked active as soon as the irq could fire. */
  6525. smp_wmb();
  6526. }
  6527. static int intel_gen2_queue_flip(struct drm_device *dev,
  6528. struct drm_crtc *crtc,
  6529. struct drm_framebuffer *fb,
  6530. struct drm_i915_gem_object *obj,
  6531. uint32_t flags)
  6532. {
  6533. struct drm_i915_private *dev_priv = dev->dev_private;
  6534. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6535. u32 flip_mask;
  6536. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  6537. int ret;
  6538. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  6539. if (ret)
  6540. goto err;
  6541. ret = intel_ring_begin(ring, 6);
  6542. if (ret)
  6543. goto err_unpin;
  6544. /* Can't queue multiple flips, so wait for the previous
  6545. * one to finish before executing the next.
  6546. */
  6547. if (intel_crtc->plane)
  6548. flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  6549. else
  6550. flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  6551. intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
  6552. intel_ring_emit(ring, MI_NOOP);
  6553. intel_ring_emit(ring, MI_DISPLAY_FLIP |
  6554. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  6555. intel_ring_emit(ring, fb->pitches[0]);
  6556. intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  6557. intel_ring_emit(ring, 0); /* aux display base address, unused */
  6558. intel_mark_page_flip_active(intel_crtc);
  6559. __intel_ring_advance(ring);
  6560. return 0;
  6561. err_unpin:
  6562. intel_unpin_fb_obj(obj);
  6563. err:
  6564. return ret;
  6565. }
  6566. static int intel_gen3_queue_flip(struct drm_device *dev,
  6567. struct drm_crtc *crtc,
  6568. struct drm_framebuffer *fb,
  6569. struct drm_i915_gem_object *obj,
  6570. uint32_t flags)
  6571. {
  6572. struct drm_i915_private *dev_priv = dev->dev_private;
  6573. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6574. u32 flip_mask;
  6575. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  6576. int ret;
  6577. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  6578. if (ret)
  6579. goto err;
  6580. ret = intel_ring_begin(ring, 6);
  6581. if (ret)
  6582. goto err_unpin;
  6583. if (intel_crtc->plane)
  6584. flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  6585. else
  6586. flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  6587. intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
  6588. intel_ring_emit(ring, MI_NOOP);
  6589. intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
  6590. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  6591. intel_ring_emit(ring, fb->pitches[0]);
  6592. intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  6593. intel_ring_emit(ring, MI_NOOP);
  6594. intel_mark_page_flip_active(intel_crtc);
  6595. __intel_ring_advance(ring);
  6596. return 0;
  6597. err_unpin:
  6598. intel_unpin_fb_obj(obj);
  6599. err:
  6600. return ret;
  6601. }
  6602. static int intel_gen4_queue_flip(struct drm_device *dev,
  6603. struct drm_crtc *crtc,
  6604. struct drm_framebuffer *fb,
  6605. struct drm_i915_gem_object *obj,
  6606. uint32_t flags)
  6607. {
  6608. struct drm_i915_private *dev_priv = dev->dev_private;
  6609. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6610. uint32_t pf, pipesrc;
  6611. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  6612. int ret;
  6613. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  6614. if (ret)
  6615. goto err;
  6616. ret = intel_ring_begin(ring, 4);
  6617. if (ret)
  6618. goto err_unpin;
  6619. /* i965+ uses the linear or tiled offsets from the
  6620. * Display Registers (which do not change across a page-flip)
  6621. * so we need only reprogram the base address.
  6622. */
  6623. intel_ring_emit(ring, MI_DISPLAY_FLIP |
  6624. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  6625. intel_ring_emit(ring, fb->pitches[0]);
  6626. intel_ring_emit(ring,
  6627. (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
  6628. obj->tiling_mode);
  6629. /* XXX Enabling the panel-fitter across page-flip is so far
  6630. * untested on non-native modes, so ignore it for now.
  6631. * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
  6632. */
  6633. pf = 0;
  6634. pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  6635. intel_ring_emit(ring, pf | pipesrc);
  6636. intel_mark_page_flip_active(intel_crtc);
  6637. __intel_ring_advance(ring);
  6638. return 0;
  6639. err_unpin:
  6640. intel_unpin_fb_obj(obj);
  6641. err:
  6642. return ret;
  6643. }
  6644. static int intel_gen6_queue_flip(struct drm_device *dev,
  6645. struct drm_crtc *crtc,
  6646. struct drm_framebuffer *fb,
  6647. struct drm_i915_gem_object *obj,
  6648. uint32_t flags)
  6649. {
  6650. struct drm_i915_private *dev_priv = dev->dev_private;
  6651. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6652. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  6653. uint32_t pf, pipesrc;
  6654. int ret;
  6655. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  6656. if (ret)
  6657. goto err;
  6658. ret = intel_ring_begin(ring, 4);
  6659. if (ret)
  6660. goto err_unpin;
  6661. intel_ring_emit(ring, MI_DISPLAY_FLIP |
  6662. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  6663. intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
  6664. intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  6665. /* Contrary to the suggestions in the documentation,
  6666. * "Enable Panel Fitter" does not seem to be required when page
  6667. * flipping with a non-native mode, and worse causes a normal
  6668. * modeset to fail.
  6669. * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
  6670. */
  6671. pf = 0;
  6672. pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  6673. intel_ring_emit(ring, pf | pipesrc);
  6674. intel_mark_page_flip_active(intel_crtc);
  6675. __intel_ring_advance(ring);
  6676. return 0;
  6677. err_unpin:
  6678. intel_unpin_fb_obj(obj);
  6679. err:
  6680. return ret;
  6681. }
  6682. static int intel_gen7_queue_flip(struct drm_device *dev,
  6683. struct drm_crtc *crtc,
  6684. struct drm_framebuffer *fb,
  6685. struct drm_i915_gem_object *obj,
  6686. uint32_t flags)
  6687. {
  6688. struct drm_i915_private *dev_priv = dev->dev_private;
  6689. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6690. struct intel_ring_buffer *ring;
  6691. uint32_t plane_bit = 0;
  6692. int len, ret;
  6693. ring = obj->ring;
  6694. if (ring == NULL || ring->id != RCS)
  6695. ring = &dev_priv->ring[BCS];
  6696. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  6697. if (ret)
  6698. goto err;
  6699. switch(intel_crtc->plane) {
  6700. case PLANE_A:
  6701. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
  6702. break;
  6703. case PLANE_B:
  6704. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
  6705. break;
  6706. case PLANE_C:
  6707. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
  6708. break;
  6709. default:
  6710. WARN_ONCE(1, "unknown plane in flip command\n");
  6711. ret = -ENODEV;
  6712. goto err_unpin;
  6713. }
  6714. len = 4;
  6715. if (ring->id == RCS)
  6716. len += 6;
  6717. ret = intel_ring_begin(ring, len);
  6718. if (ret)
  6719. goto err_unpin;
  6720. /* Unmask the flip-done completion message. Note that the bspec says that
  6721. * we should do this for both the BCS and RCS, and that we must not unmask
  6722. * more than one flip event at any time (or ensure that one flip message
  6723. * can be sent by waiting for flip-done prior to queueing new flips).
  6724. * Experimentation says that BCS works despite DERRMR masking all
  6725. * flip-done completion events and that unmasking all planes at once
  6726. * for the RCS also doesn't appear to drop events. Setting the DERRMR
  6727. * to zero does lead to lockups within MI_DISPLAY_FLIP.
  6728. */
  6729. if (ring->id == RCS) {
  6730. intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
  6731. intel_ring_emit(ring, DERRMR);
  6732. intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
  6733. DERRMR_PIPEB_PRI_FLIP_DONE |
  6734. DERRMR_PIPEC_PRI_FLIP_DONE));
  6735. intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
  6736. intel_ring_emit(ring, DERRMR);
  6737. intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
  6738. }
  6739. intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
  6740. intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
  6741. intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  6742. intel_ring_emit(ring, (MI_NOOP));
  6743. intel_mark_page_flip_active(intel_crtc);
  6744. __intel_ring_advance(ring);
  6745. return 0;
  6746. err_unpin:
  6747. intel_unpin_fb_obj(obj);
  6748. err:
  6749. return ret;
  6750. }
  6751. static int intel_default_queue_flip(struct drm_device *dev,
  6752. struct drm_crtc *crtc,
  6753. struct drm_framebuffer *fb,
  6754. struct drm_i915_gem_object *obj,
  6755. uint32_t flags)
  6756. {
  6757. return -ENODEV;
  6758. }
  6759. static int intel_crtc_page_flip(struct drm_crtc *crtc,
  6760. struct drm_framebuffer *fb,
  6761. struct drm_pending_vblank_event *event,
  6762. uint32_t page_flip_flags)
  6763. {
  6764. struct drm_device *dev = crtc->dev;
  6765. struct drm_i915_private *dev_priv = dev->dev_private;
  6766. struct drm_framebuffer *old_fb = crtc->fb;
  6767. struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
  6768. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6769. struct intel_unpin_work *work;
  6770. unsigned long flags;
  6771. int ret;
  6772. /* Can't change pixel format via MI display flips. */
  6773. if (fb->pixel_format != crtc->fb->pixel_format)
  6774. return -EINVAL;
  6775. /*
  6776. * TILEOFF/LINOFF registers can't be changed via MI display flips.
  6777. * Note that pitch changes could also affect these register.
  6778. */
  6779. if (INTEL_INFO(dev)->gen > 3 &&
  6780. (fb->offsets[0] != crtc->fb->offsets[0] ||
  6781. fb->pitches[0] != crtc->fb->pitches[0]))
  6782. return -EINVAL;
  6783. work = kzalloc(sizeof *work, GFP_KERNEL);
  6784. if (work == NULL)
  6785. return -ENOMEM;
  6786. work->event = event;
  6787. work->crtc = crtc;
  6788. work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
  6789. INIT_WORK(&work->work, intel_unpin_work_fn);
  6790. ret = drm_vblank_get(dev, intel_crtc->pipe);
  6791. if (ret)
  6792. goto free_work;
  6793. /* We borrow the event spin lock for protecting unpin_work */
  6794. spin_lock_irqsave(&dev->event_lock, flags);
  6795. if (intel_crtc->unpin_work) {
  6796. spin_unlock_irqrestore(&dev->event_lock, flags);
  6797. kfree(work);
  6798. drm_vblank_put(dev, intel_crtc->pipe);
  6799. DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
  6800. return -EBUSY;
  6801. }
  6802. intel_crtc->unpin_work = work;
  6803. spin_unlock_irqrestore(&dev->event_lock, flags);
  6804. if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
  6805. flush_workqueue(dev_priv->wq);
  6806. ret = i915_mutex_lock_interruptible(dev);
  6807. if (ret)
  6808. goto cleanup;
  6809. /* Reference the objects for the scheduled work. */
  6810. drm_gem_object_reference(&work->old_fb_obj->base);
  6811. drm_gem_object_reference(&obj->base);
  6812. crtc->fb = fb;
  6813. work->pending_flip_obj = obj;
  6814. work->enable_stall_check = true;
  6815. atomic_inc(&intel_crtc->unpin_work_count);
  6816. intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
  6817. ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
  6818. if (ret)
  6819. goto cleanup_pending;
  6820. intel_disable_fbc(dev);
  6821. intel_mark_fb_busy(obj, NULL);
  6822. mutex_unlock(&dev->struct_mutex);
  6823. trace_i915_flip_request(intel_crtc->plane, obj);
  6824. return 0;
  6825. cleanup_pending:
  6826. atomic_dec(&intel_crtc->unpin_work_count);
  6827. crtc->fb = old_fb;
  6828. drm_gem_object_unreference(&work->old_fb_obj->base);
  6829. drm_gem_object_unreference(&obj->base);
  6830. mutex_unlock(&dev->struct_mutex);
  6831. cleanup:
  6832. spin_lock_irqsave(&dev->event_lock, flags);
  6833. intel_crtc->unpin_work = NULL;
  6834. spin_unlock_irqrestore(&dev->event_lock, flags);
  6835. drm_vblank_put(dev, intel_crtc->pipe);
  6836. free_work:
  6837. kfree(work);
  6838. return ret;
  6839. }
  6840. static struct drm_crtc_helper_funcs intel_helper_funcs = {
  6841. .mode_set_base_atomic = intel_pipe_set_base_atomic,
  6842. .load_lut = intel_crtc_load_lut,
  6843. };
  6844. static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
  6845. struct drm_crtc *crtc)
  6846. {
  6847. struct drm_device *dev;
  6848. struct drm_crtc *tmp;
  6849. int crtc_mask = 1;
  6850. WARN(!crtc, "checking null crtc?\n");
  6851. dev = crtc->dev;
  6852. list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
  6853. if (tmp == crtc)
  6854. break;
  6855. crtc_mask <<= 1;
  6856. }
  6857. if (encoder->possible_crtcs & crtc_mask)
  6858. return true;
  6859. return false;
  6860. }
  6861. /**
  6862. * intel_modeset_update_staged_output_state
  6863. *
  6864. * Updates the staged output configuration state, e.g. after we've read out the
  6865. * current hw state.
  6866. */
  6867. static void intel_modeset_update_staged_output_state(struct drm_device *dev)
  6868. {
  6869. struct intel_encoder *encoder;
  6870. struct intel_connector *connector;
  6871. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6872. base.head) {
  6873. connector->new_encoder =
  6874. to_intel_encoder(connector->base.encoder);
  6875. }
  6876. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6877. base.head) {
  6878. encoder->new_crtc =
  6879. to_intel_crtc(encoder->base.crtc);
  6880. }
  6881. }
  6882. /**
  6883. * intel_modeset_commit_output_state
  6884. *
  6885. * This function copies the stage display pipe configuration to the real one.
  6886. */
  6887. static void intel_modeset_commit_output_state(struct drm_device *dev)
  6888. {
  6889. struct intel_encoder *encoder;
  6890. struct intel_connector *connector;
  6891. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6892. base.head) {
  6893. connector->base.encoder = &connector->new_encoder->base;
  6894. }
  6895. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6896. base.head) {
  6897. encoder->base.crtc = &encoder->new_crtc->base;
  6898. }
  6899. }
  6900. static void
  6901. connected_sink_compute_bpp(struct intel_connector * connector,
  6902. struct intel_crtc_config *pipe_config)
  6903. {
  6904. int bpp = pipe_config->pipe_bpp;
  6905. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
  6906. connector->base.base.id,
  6907. drm_get_connector_name(&connector->base));
  6908. /* Don't use an invalid EDID bpc value */
  6909. if (connector->base.display_info.bpc &&
  6910. connector->base.display_info.bpc * 3 < bpp) {
  6911. DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
  6912. bpp, connector->base.display_info.bpc*3);
  6913. pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
  6914. }
  6915. /* Clamp bpp to 8 on screens without EDID 1.4 */
  6916. if (connector->base.display_info.bpc == 0 && bpp > 24) {
  6917. DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
  6918. bpp);
  6919. pipe_config->pipe_bpp = 24;
  6920. }
  6921. }
  6922. static int
  6923. compute_baseline_pipe_bpp(struct intel_crtc *crtc,
  6924. struct drm_framebuffer *fb,
  6925. struct intel_crtc_config *pipe_config)
  6926. {
  6927. struct drm_device *dev = crtc->base.dev;
  6928. struct intel_connector *connector;
  6929. int bpp;
  6930. switch (fb->pixel_format) {
  6931. case DRM_FORMAT_C8:
  6932. bpp = 8*3; /* since we go through a colormap */
  6933. break;
  6934. case DRM_FORMAT_XRGB1555:
  6935. case DRM_FORMAT_ARGB1555:
  6936. /* checked in intel_framebuffer_init already */
  6937. if (WARN_ON(INTEL_INFO(dev)->gen > 3))
  6938. return -EINVAL;
  6939. case DRM_FORMAT_RGB565:
  6940. bpp = 6*3; /* min is 18bpp */
  6941. break;
  6942. case DRM_FORMAT_XBGR8888:
  6943. case DRM_FORMAT_ABGR8888:
  6944. /* checked in intel_framebuffer_init already */
  6945. if (WARN_ON(INTEL_INFO(dev)->gen < 4))
  6946. return -EINVAL;
  6947. case DRM_FORMAT_XRGB8888:
  6948. case DRM_FORMAT_ARGB8888:
  6949. bpp = 8*3;
  6950. break;
  6951. case DRM_FORMAT_XRGB2101010:
  6952. case DRM_FORMAT_ARGB2101010:
  6953. case DRM_FORMAT_XBGR2101010:
  6954. case DRM_FORMAT_ABGR2101010:
  6955. /* checked in intel_framebuffer_init already */
  6956. if (WARN_ON(INTEL_INFO(dev)->gen < 4))
  6957. return -EINVAL;
  6958. bpp = 10*3;
  6959. break;
  6960. /* TODO: gen4+ supports 16 bpc floating point, too. */
  6961. default:
  6962. DRM_DEBUG_KMS("unsupported depth\n");
  6963. return -EINVAL;
  6964. }
  6965. pipe_config->pipe_bpp = bpp;
  6966. /* Clamp display bpp to EDID value */
  6967. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6968. base.head) {
  6969. if (!connector->new_encoder ||
  6970. connector->new_encoder->new_crtc != crtc)
  6971. continue;
  6972. connected_sink_compute_bpp(connector, pipe_config);
  6973. }
  6974. return bpp;
  6975. }
  6976. static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
  6977. {
  6978. DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
  6979. "type: 0x%x flags: 0x%x\n",
  6980. mode->clock,
  6981. mode->crtc_hdisplay, mode->crtc_hsync_start,
  6982. mode->crtc_hsync_end, mode->crtc_htotal,
  6983. mode->crtc_vdisplay, mode->crtc_vsync_start,
  6984. mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
  6985. }
  6986. static void intel_dump_pipe_config(struct intel_crtc *crtc,
  6987. struct intel_crtc_config *pipe_config,
  6988. const char *context)
  6989. {
  6990. DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
  6991. context, pipe_name(crtc->pipe));
  6992. DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
  6993. DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
  6994. pipe_config->pipe_bpp, pipe_config->dither);
  6995. DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
  6996. pipe_config->has_pch_encoder,
  6997. pipe_config->fdi_lanes,
  6998. pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
  6999. pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
  7000. pipe_config->fdi_m_n.tu);
  7001. DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
  7002. pipe_config->has_dp_encoder,
  7003. pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
  7004. pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
  7005. pipe_config->dp_m_n.tu);
  7006. DRM_DEBUG_KMS("requested mode:\n");
  7007. drm_mode_debug_printmodeline(&pipe_config->requested_mode);
  7008. DRM_DEBUG_KMS("adjusted mode:\n");
  7009. drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
  7010. intel_dump_crtc_timings(&pipe_config->adjusted_mode);
  7011. DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
  7012. DRM_DEBUG_KMS("pipe src size: %dx%d\n",
  7013. pipe_config->pipe_src_w, pipe_config->pipe_src_h);
  7014. DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
  7015. pipe_config->gmch_pfit.control,
  7016. pipe_config->gmch_pfit.pgm_ratios,
  7017. pipe_config->gmch_pfit.lvds_border_bits);
  7018. DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
  7019. pipe_config->pch_pfit.pos,
  7020. pipe_config->pch_pfit.size);
  7021. DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
  7022. DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
  7023. }
  7024. static bool check_encoder_cloning(struct drm_crtc *crtc)
  7025. {
  7026. int num_encoders = 0;
  7027. bool uncloneable_encoders = false;
  7028. struct intel_encoder *encoder;
  7029. list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
  7030. base.head) {
  7031. if (&encoder->new_crtc->base != crtc)
  7032. continue;
  7033. num_encoders++;
  7034. if (!encoder->cloneable)
  7035. uncloneable_encoders = true;
  7036. }
  7037. return !(num_encoders > 1 && uncloneable_encoders);
  7038. }
  7039. static struct intel_crtc_config *
  7040. intel_modeset_pipe_config(struct drm_crtc *crtc,
  7041. struct drm_framebuffer *fb,
  7042. struct drm_display_mode *mode)
  7043. {
  7044. struct drm_device *dev = crtc->dev;
  7045. struct intel_encoder *encoder;
  7046. struct intel_crtc_config *pipe_config;
  7047. int plane_bpp, ret = -EINVAL;
  7048. bool retry = true;
  7049. if (!check_encoder_cloning(crtc)) {
  7050. DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
  7051. return ERR_PTR(-EINVAL);
  7052. }
  7053. pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
  7054. if (!pipe_config)
  7055. return ERR_PTR(-ENOMEM);
  7056. drm_mode_copy(&pipe_config->adjusted_mode, mode);
  7057. drm_mode_copy(&pipe_config->requested_mode, mode);
  7058. pipe_config->pipe_src_w = mode->hdisplay;
  7059. pipe_config->pipe_src_h = mode->vdisplay;
  7060. pipe_config->cpu_transcoder =
  7061. (enum transcoder) to_intel_crtc(crtc)->pipe;
  7062. pipe_config->shared_dpll = DPLL_ID_PRIVATE;
  7063. /*
  7064. * Sanitize sync polarity flags based on requested ones. If neither
  7065. * positive or negative polarity is requested, treat this as meaning
  7066. * negative polarity.
  7067. */
  7068. if (!(pipe_config->adjusted_mode.flags &
  7069. (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
  7070. pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
  7071. if (!(pipe_config->adjusted_mode.flags &
  7072. (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
  7073. pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
  7074. /* Compute a starting value for pipe_config->pipe_bpp taking the source
  7075. * plane pixel format and any sink constraints into account. Returns the
  7076. * source plane bpp so that dithering can be selected on mismatches
  7077. * after encoders and crtc also have had their say. */
  7078. plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
  7079. fb, pipe_config);
  7080. if (plane_bpp < 0)
  7081. goto fail;
  7082. encoder_retry:
  7083. /* Ensure the port clock defaults are reset when retrying. */
  7084. pipe_config->port_clock = 0;
  7085. pipe_config->pixel_multiplier = 1;
  7086. /* Fill in default crtc timings, allow encoders to overwrite them. */
  7087. drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
  7088. /* Pass our mode to the connectors and the CRTC to give them a chance to
  7089. * adjust it according to limitations or connector properties, and also
  7090. * a chance to reject the mode entirely.
  7091. */
  7092. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7093. base.head) {
  7094. if (&encoder->new_crtc->base != crtc)
  7095. continue;
  7096. if (!(encoder->compute_config(encoder, pipe_config))) {
  7097. DRM_DEBUG_KMS("Encoder config failure\n");
  7098. goto fail;
  7099. }
  7100. }
  7101. /* Set default port clock if not overwritten by the encoder. Needs to be
  7102. * done afterwards in case the encoder adjusts the mode. */
  7103. if (!pipe_config->port_clock)
  7104. pipe_config->port_clock = pipe_config->adjusted_mode.clock *
  7105. pipe_config->pixel_multiplier;
  7106. ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
  7107. if (ret < 0) {
  7108. DRM_DEBUG_KMS("CRTC fixup failed\n");
  7109. goto fail;
  7110. }
  7111. if (ret == RETRY) {
  7112. if (WARN(!retry, "loop in pipe configuration computation\n")) {
  7113. ret = -EINVAL;
  7114. goto fail;
  7115. }
  7116. DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
  7117. retry = false;
  7118. goto encoder_retry;
  7119. }
  7120. pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
  7121. DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
  7122. plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
  7123. return pipe_config;
  7124. fail:
  7125. kfree(pipe_config);
  7126. return ERR_PTR(ret);
  7127. }
  7128. /* Computes which crtcs are affected and sets the relevant bits in the mask. For
  7129. * simplicity we use the crtc's pipe number (because it's easier to obtain). */
  7130. static void
  7131. intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
  7132. unsigned *prepare_pipes, unsigned *disable_pipes)
  7133. {
  7134. struct intel_crtc *intel_crtc;
  7135. struct drm_device *dev = crtc->dev;
  7136. struct intel_encoder *encoder;
  7137. struct intel_connector *connector;
  7138. struct drm_crtc *tmp_crtc;
  7139. *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
  7140. /* Check which crtcs have changed outputs connected to them, these need
  7141. * to be part of the prepare_pipes mask. We don't (yet) support global
  7142. * modeset across multiple crtcs, so modeset_pipes will only have one
  7143. * bit set at most. */
  7144. list_for_each_entry(connector, &dev->mode_config.connector_list,
  7145. base.head) {
  7146. if (connector->base.encoder == &connector->new_encoder->base)
  7147. continue;
  7148. if (connector->base.encoder) {
  7149. tmp_crtc = connector->base.encoder->crtc;
  7150. *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
  7151. }
  7152. if (connector->new_encoder)
  7153. *prepare_pipes |=
  7154. 1 << connector->new_encoder->new_crtc->pipe;
  7155. }
  7156. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7157. base.head) {
  7158. if (encoder->base.crtc == &encoder->new_crtc->base)
  7159. continue;
  7160. if (encoder->base.crtc) {
  7161. tmp_crtc = encoder->base.crtc;
  7162. *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
  7163. }
  7164. if (encoder->new_crtc)
  7165. *prepare_pipes |= 1 << encoder->new_crtc->pipe;
  7166. }
  7167. /* Check for any pipes that will be fully disabled ... */
  7168. list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
  7169. base.head) {
  7170. bool used = false;
  7171. /* Don't try to disable disabled crtcs. */
  7172. if (!intel_crtc->base.enabled)
  7173. continue;
  7174. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7175. base.head) {
  7176. if (encoder->new_crtc == intel_crtc)
  7177. used = true;
  7178. }
  7179. if (!used)
  7180. *disable_pipes |= 1 << intel_crtc->pipe;
  7181. }
  7182. /* set_mode is also used to update properties on life display pipes. */
  7183. intel_crtc = to_intel_crtc(crtc);
  7184. if (crtc->enabled)
  7185. *prepare_pipes |= 1 << intel_crtc->pipe;
  7186. /*
  7187. * For simplicity do a full modeset on any pipe where the output routing
  7188. * changed. We could be more clever, but that would require us to be
  7189. * more careful with calling the relevant encoder->mode_set functions.
  7190. */
  7191. if (*prepare_pipes)
  7192. *modeset_pipes = *prepare_pipes;
  7193. /* ... and mask these out. */
  7194. *modeset_pipes &= ~(*disable_pipes);
  7195. *prepare_pipes &= ~(*disable_pipes);
  7196. /*
  7197. * HACK: We don't (yet) fully support global modesets. intel_set_config
  7198. * obies this rule, but the modeset restore mode of
  7199. * intel_modeset_setup_hw_state does not.
  7200. */
  7201. *modeset_pipes &= 1 << intel_crtc->pipe;
  7202. *prepare_pipes &= 1 << intel_crtc->pipe;
  7203. DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
  7204. *modeset_pipes, *prepare_pipes, *disable_pipes);
  7205. }
  7206. static bool intel_crtc_in_use(struct drm_crtc *crtc)
  7207. {
  7208. struct drm_encoder *encoder;
  7209. struct drm_device *dev = crtc->dev;
  7210. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
  7211. if (encoder->crtc == crtc)
  7212. return true;
  7213. return false;
  7214. }
  7215. static void
  7216. intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
  7217. {
  7218. struct intel_encoder *intel_encoder;
  7219. struct intel_crtc *intel_crtc;
  7220. struct drm_connector *connector;
  7221. list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
  7222. base.head) {
  7223. if (!intel_encoder->base.crtc)
  7224. continue;
  7225. intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
  7226. if (prepare_pipes & (1 << intel_crtc->pipe))
  7227. intel_encoder->connectors_active = false;
  7228. }
  7229. intel_modeset_commit_output_state(dev);
  7230. /* Update computed state. */
  7231. list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
  7232. base.head) {
  7233. intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
  7234. }
  7235. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  7236. if (!connector->encoder || !connector->encoder->crtc)
  7237. continue;
  7238. intel_crtc = to_intel_crtc(connector->encoder->crtc);
  7239. if (prepare_pipes & (1 << intel_crtc->pipe)) {
  7240. struct drm_property *dpms_property =
  7241. dev->mode_config.dpms_property;
  7242. connector->dpms = DRM_MODE_DPMS_ON;
  7243. drm_object_property_set_value(&connector->base,
  7244. dpms_property,
  7245. DRM_MODE_DPMS_ON);
  7246. intel_encoder = to_intel_encoder(connector->encoder);
  7247. intel_encoder->connectors_active = true;
  7248. }
  7249. }
  7250. }
  7251. static bool intel_fuzzy_clock_check(int clock1, int clock2)
  7252. {
  7253. int diff;
  7254. if (clock1 == clock2)
  7255. return true;
  7256. if (!clock1 || !clock2)
  7257. return false;
  7258. diff = abs(clock1 - clock2);
  7259. if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
  7260. return true;
  7261. return false;
  7262. }
  7263. #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
  7264. list_for_each_entry((intel_crtc), \
  7265. &(dev)->mode_config.crtc_list, \
  7266. base.head) \
  7267. if (mask & (1 <<(intel_crtc)->pipe))
  7268. static bool
  7269. intel_pipe_config_compare(struct drm_device *dev,
  7270. struct intel_crtc_config *current_config,
  7271. struct intel_crtc_config *pipe_config)
  7272. {
  7273. #define PIPE_CONF_CHECK_X(name) \
  7274. if (current_config->name != pipe_config->name) { \
  7275. DRM_ERROR("mismatch in " #name " " \
  7276. "(expected 0x%08x, found 0x%08x)\n", \
  7277. current_config->name, \
  7278. pipe_config->name); \
  7279. return false; \
  7280. }
  7281. #define PIPE_CONF_CHECK_I(name) \
  7282. if (current_config->name != pipe_config->name) { \
  7283. DRM_ERROR("mismatch in " #name " " \
  7284. "(expected %i, found %i)\n", \
  7285. current_config->name, \
  7286. pipe_config->name); \
  7287. return false; \
  7288. }
  7289. #define PIPE_CONF_CHECK_FLAGS(name, mask) \
  7290. if ((current_config->name ^ pipe_config->name) & (mask)) { \
  7291. DRM_ERROR("mismatch in " #name "(" #mask ") " \
  7292. "(expected %i, found %i)\n", \
  7293. current_config->name & (mask), \
  7294. pipe_config->name & (mask)); \
  7295. return false; \
  7296. }
  7297. #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
  7298. if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
  7299. DRM_ERROR("mismatch in " #name " " \
  7300. "(expected %i, found %i)\n", \
  7301. current_config->name, \
  7302. pipe_config->name); \
  7303. return false; \
  7304. }
  7305. #define PIPE_CONF_QUIRK(quirk) \
  7306. ((current_config->quirks | pipe_config->quirks) & (quirk))
  7307. PIPE_CONF_CHECK_I(cpu_transcoder);
  7308. PIPE_CONF_CHECK_I(has_pch_encoder);
  7309. PIPE_CONF_CHECK_I(fdi_lanes);
  7310. PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
  7311. PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
  7312. PIPE_CONF_CHECK_I(fdi_m_n.link_m);
  7313. PIPE_CONF_CHECK_I(fdi_m_n.link_n);
  7314. PIPE_CONF_CHECK_I(fdi_m_n.tu);
  7315. PIPE_CONF_CHECK_I(has_dp_encoder);
  7316. PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
  7317. PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
  7318. PIPE_CONF_CHECK_I(dp_m_n.link_m);
  7319. PIPE_CONF_CHECK_I(dp_m_n.link_n);
  7320. PIPE_CONF_CHECK_I(dp_m_n.tu);
  7321. PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
  7322. PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
  7323. PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
  7324. PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
  7325. PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
  7326. PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
  7327. PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
  7328. PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
  7329. PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
  7330. PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
  7331. PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
  7332. PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
  7333. PIPE_CONF_CHECK_I(pixel_multiplier);
  7334. PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
  7335. DRM_MODE_FLAG_INTERLACE);
  7336. if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
  7337. PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
  7338. DRM_MODE_FLAG_PHSYNC);
  7339. PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
  7340. DRM_MODE_FLAG_NHSYNC);
  7341. PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
  7342. DRM_MODE_FLAG_PVSYNC);
  7343. PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
  7344. DRM_MODE_FLAG_NVSYNC);
  7345. }
  7346. PIPE_CONF_CHECK_I(pipe_src_w);
  7347. PIPE_CONF_CHECK_I(pipe_src_h);
  7348. PIPE_CONF_CHECK_I(gmch_pfit.control);
  7349. /* pfit ratios are autocomputed by the hw on gen4+ */
  7350. if (INTEL_INFO(dev)->gen < 4)
  7351. PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
  7352. PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
  7353. PIPE_CONF_CHECK_I(pch_pfit.pos);
  7354. PIPE_CONF_CHECK_I(pch_pfit.size);
  7355. PIPE_CONF_CHECK_I(ips_enabled);
  7356. PIPE_CONF_CHECK_I(double_wide);
  7357. PIPE_CONF_CHECK_I(shared_dpll);
  7358. PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
  7359. PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
  7360. PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
  7361. PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
  7362. if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
  7363. PIPE_CONF_CHECK_I(pipe_bpp);
  7364. if (!IS_HASWELL(dev)) {
  7365. PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.clock);
  7366. PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
  7367. }
  7368. #undef PIPE_CONF_CHECK_X
  7369. #undef PIPE_CONF_CHECK_I
  7370. #undef PIPE_CONF_CHECK_FLAGS
  7371. #undef PIPE_CONF_CHECK_CLOCK_FUZZY
  7372. #undef PIPE_CONF_QUIRK
  7373. return true;
  7374. }
  7375. static void
  7376. check_connector_state(struct drm_device *dev)
  7377. {
  7378. struct intel_connector *connector;
  7379. list_for_each_entry(connector, &dev->mode_config.connector_list,
  7380. base.head) {
  7381. /* This also checks the encoder/connector hw state with the
  7382. * ->get_hw_state callbacks. */
  7383. intel_connector_check_state(connector);
  7384. WARN(&connector->new_encoder->base != connector->base.encoder,
  7385. "connector's staged encoder doesn't match current encoder\n");
  7386. }
  7387. }
  7388. static void
  7389. check_encoder_state(struct drm_device *dev)
  7390. {
  7391. struct intel_encoder *encoder;
  7392. struct intel_connector *connector;
  7393. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7394. base.head) {
  7395. bool enabled = false;
  7396. bool active = false;
  7397. enum pipe pipe, tracked_pipe;
  7398. DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
  7399. encoder->base.base.id,
  7400. drm_get_encoder_name(&encoder->base));
  7401. WARN(&encoder->new_crtc->base != encoder->base.crtc,
  7402. "encoder's stage crtc doesn't match current crtc\n");
  7403. WARN(encoder->connectors_active && !encoder->base.crtc,
  7404. "encoder's active_connectors set, but no crtc\n");
  7405. list_for_each_entry(connector, &dev->mode_config.connector_list,
  7406. base.head) {
  7407. if (connector->base.encoder != &encoder->base)
  7408. continue;
  7409. enabled = true;
  7410. if (connector->base.dpms != DRM_MODE_DPMS_OFF)
  7411. active = true;
  7412. }
  7413. WARN(!!encoder->base.crtc != enabled,
  7414. "encoder's enabled state mismatch "
  7415. "(expected %i, found %i)\n",
  7416. !!encoder->base.crtc, enabled);
  7417. WARN(active && !encoder->base.crtc,
  7418. "active encoder with no crtc\n");
  7419. WARN(encoder->connectors_active != active,
  7420. "encoder's computed active state doesn't match tracked active state "
  7421. "(expected %i, found %i)\n", active, encoder->connectors_active);
  7422. active = encoder->get_hw_state(encoder, &pipe);
  7423. WARN(active != encoder->connectors_active,
  7424. "encoder's hw state doesn't match sw tracking "
  7425. "(expected %i, found %i)\n",
  7426. encoder->connectors_active, active);
  7427. if (!encoder->base.crtc)
  7428. continue;
  7429. tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
  7430. WARN(active && pipe != tracked_pipe,
  7431. "active encoder's pipe doesn't match"
  7432. "(expected %i, found %i)\n",
  7433. tracked_pipe, pipe);
  7434. }
  7435. }
  7436. static void
  7437. check_crtc_state(struct drm_device *dev)
  7438. {
  7439. drm_i915_private_t *dev_priv = dev->dev_private;
  7440. struct intel_crtc *crtc;
  7441. struct intel_encoder *encoder;
  7442. struct intel_crtc_config pipe_config;
  7443. list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  7444. base.head) {
  7445. bool enabled = false;
  7446. bool active = false;
  7447. memset(&pipe_config, 0, sizeof(pipe_config));
  7448. DRM_DEBUG_KMS("[CRTC:%d]\n",
  7449. crtc->base.base.id);
  7450. WARN(crtc->active && !crtc->base.enabled,
  7451. "active crtc, but not enabled in sw tracking\n");
  7452. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7453. base.head) {
  7454. if (encoder->base.crtc != &crtc->base)
  7455. continue;
  7456. enabled = true;
  7457. if (encoder->connectors_active)
  7458. active = true;
  7459. }
  7460. WARN(active != crtc->active,
  7461. "crtc's computed active state doesn't match tracked active state "
  7462. "(expected %i, found %i)\n", active, crtc->active);
  7463. WARN(enabled != crtc->base.enabled,
  7464. "crtc's computed enabled state doesn't match tracked enabled state "
  7465. "(expected %i, found %i)\n", enabled, crtc->base.enabled);
  7466. active = dev_priv->display.get_pipe_config(crtc,
  7467. &pipe_config);
  7468. /* hw state is inconsistent with the pipe A quirk */
  7469. if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
  7470. active = crtc->active;
  7471. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7472. base.head) {
  7473. enum pipe pipe;
  7474. if (encoder->base.crtc != &crtc->base)
  7475. continue;
  7476. if (encoder->get_config &&
  7477. encoder->get_hw_state(encoder, &pipe))
  7478. encoder->get_config(encoder, &pipe_config);
  7479. }
  7480. WARN(crtc->active != active,
  7481. "crtc active state doesn't match with hw state "
  7482. "(expected %i, found %i)\n", crtc->active, active);
  7483. if (active &&
  7484. !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
  7485. WARN(1, "pipe state doesn't match!\n");
  7486. intel_dump_pipe_config(crtc, &pipe_config,
  7487. "[hw state]");
  7488. intel_dump_pipe_config(crtc, &crtc->config,
  7489. "[sw state]");
  7490. }
  7491. }
  7492. }
  7493. static void
  7494. check_shared_dpll_state(struct drm_device *dev)
  7495. {
  7496. drm_i915_private_t *dev_priv = dev->dev_private;
  7497. struct intel_crtc *crtc;
  7498. struct intel_dpll_hw_state dpll_hw_state;
  7499. int i;
  7500. for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  7501. struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
  7502. int enabled_crtcs = 0, active_crtcs = 0;
  7503. bool active;
  7504. memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
  7505. DRM_DEBUG_KMS("%s\n", pll->name);
  7506. active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
  7507. WARN(pll->active > pll->refcount,
  7508. "more active pll users than references: %i vs %i\n",
  7509. pll->active, pll->refcount);
  7510. WARN(pll->active && !pll->on,
  7511. "pll in active use but not on in sw tracking\n");
  7512. WARN(pll->on && !pll->active,
  7513. "pll in on but not on in use in sw tracking\n");
  7514. WARN(pll->on != active,
  7515. "pll on state mismatch (expected %i, found %i)\n",
  7516. pll->on, active);
  7517. list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  7518. base.head) {
  7519. if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
  7520. enabled_crtcs++;
  7521. if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
  7522. active_crtcs++;
  7523. }
  7524. WARN(pll->active != active_crtcs,
  7525. "pll active crtcs mismatch (expected %i, found %i)\n",
  7526. pll->active, active_crtcs);
  7527. WARN(pll->refcount != enabled_crtcs,
  7528. "pll enabled crtcs mismatch (expected %i, found %i)\n",
  7529. pll->refcount, enabled_crtcs);
  7530. WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
  7531. sizeof(dpll_hw_state)),
  7532. "pll hw state mismatch\n");
  7533. }
  7534. }
  7535. void
  7536. intel_modeset_check_state(struct drm_device *dev)
  7537. {
  7538. check_connector_state(dev);
  7539. check_encoder_state(dev);
  7540. check_crtc_state(dev);
  7541. check_shared_dpll_state(dev);
  7542. }
  7543. void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
  7544. int dotclock)
  7545. {
  7546. /*
  7547. * FDI already provided one idea for the dotclock.
  7548. * Yell if the encoder disagrees.
  7549. */
  7550. WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.clock, dotclock),
  7551. "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
  7552. pipe_config->adjusted_mode.clock, dotclock);
  7553. }
  7554. static int __intel_set_mode(struct drm_crtc *crtc,
  7555. struct drm_display_mode *mode,
  7556. int x, int y, struct drm_framebuffer *fb)
  7557. {
  7558. struct drm_device *dev = crtc->dev;
  7559. drm_i915_private_t *dev_priv = dev->dev_private;
  7560. struct drm_display_mode *saved_mode, *saved_hwmode;
  7561. struct intel_crtc_config *pipe_config = NULL;
  7562. struct intel_crtc *intel_crtc;
  7563. unsigned disable_pipes, prepare_pipes, modeset_pipes;
  7564. int ret = 0;
  7565. saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
  7566. if (!saved_mode)
  7567. return -ENOMEM;
  7568. saved_hwmode = saved_mode + 1;
  7569. intel_modeset_affected_pipes(crtc, &modeset_pipes,
  7570. &prepare_pipes, &disable_pipes);
  7571. *saved_hwmode = crtc->hwmode;
  7572. *saved_mode = crtc->mode;
  7573. /* Hack: Because we don't (yet) support global modeset on multiple
  7574. * crtcs, we don't keep track of the new mode for more than one crtc.
  7575. * Hence simply check whether any bit is set in modeset_pipes in all the
  7576. * pieces of code that are not yet converted to deal with mutliple crtcs
  7577. * changing their mode at the same time. */
  7578. if (modeset_pipes) {
  7579. pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
  7580. if (IS_ERR(pipe_config)) {
  7581. ret = PTR_ERR(pipe_config);
  7582. pipe_config = NULL;
  7583. goto out;
  7584. }
  7585. intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
  7586. "[modeset]");
  7587. }
  7588. for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
  7589. intel_crtc_disable(&intel_crtc->base);
  7590. for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
  7591. if (intel_crtc->base.enabled)
  7592. dev_priv->display.crtc_disable(&intel_crtc->base);
  7593. }
  7594. /* crtc->mode is already used by the ->mode_set callbacks, hence we need
  7595. * to set it here already despite that we pass it down the callchain.
  7596. */
  7597. if (modeset_pipes) {
  7598. crtc->mode = *mode;
  7599. /* mode_set/enable/disable functions rely on a correct pipe
  7600. * config. */
  7601. to_intel_crtc(crtc)->config = *pipe_config;
  7602. }
  7603. /* Only after disabling all output pipelines that will be changed can we
  7604. * update the the output configuration. */
  7605. intel_modeset_update_state(dev, prepare_pipes);
  7606. if (dev_priv->display.modeset_global_resources)
  7607. dev_priv->display.modeset_global_resources(dev);
  7608. /* Set up the DPLL and any encoders state that needs to adjust or depend
  7609. * on the DPLL.
  7610. */
  7611. for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
  7612. ret = intel_crtc_mode_set(&intel_crtc->base,
  7613. x, y, fb);
  7614. if (ret)
  7615. goto done;
  7616. }
  7617. /* Now enable the clocks, plane, pipe, and connectors that we set up. */
  7618. for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
  7619. dev_priv->display.crtc_enable(&intel_crtc->base);
  7620. if (modeset_pipes) {
  7621. /* Store real post-adjustment hardware mode. */
  7622. crtc->hwmode = pipe_config->adjusted_mode;
  7623. /* Calculate and store various constants which
  7624. * are later needed by vblank and swap-completion
  7625. * timestamping. They are derived from true hwmode.
  7626. */
  7627. drm_calc_timestamping_constants(crtc);
  7628. }
  7629. /* FIXME: add subpixel order */
  7630. done:
  7631. if (ret && crtc->enabled) {
  7632. crtc->hwmode = *saved_hwmode;
  7633. crtc->mode = *saved_mode;
  7634. }
  7635. out:
  7636. kfree(pipe_config);
  7637. kfree(saved_mode);
  7638. return ret;
  7639. }
  7640. static int intel_set_mode(struct drm_crtc *crtc,
  7641. struct drm_display_mode *mode,
  7642. int x, int y, struct drm_framebuffer *fb)
  7643. {
  7644. int ret;
  7645. ret = __intel_set_mode(crtc, mode, x, y, fb);
  7646. if (ret == 0)
  7647. intel_modeset_check_state(crtc->dev);
  7648. return ret;
  7649. }
  7650. void intel_crtc_restore_mode(struct drm_crtc *crtc)
  7651. {
  7652. intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
  7653. }
  7654. #undef for_each_intel_crtc_masked
  7655. static void intel_set_config_free(struct intel_set_config *config)
  7656. {
  7657. if (!config)
  7658. return;
  7659. kfree(config->save_connector_encoders);
  7660. kfree(config->save_encoder_crtcs);
  7661. kfree(config);
  7662. }
  7663. static int intel_set_config_save_state(struct drm_device *dev,
  7664. struct intel_set_config *config)
  7665. {
  7666. struct drm_encoder *encoder;
  7667. struct drm_connector *connector;
  7668. int count;
  7669. config->save_encoder_crtcs =
  7670. kcalloc(dev->mode_config.num_encoder,
  7671. sizeof(struct drm_crtc *), GFP_KERNEL);
  7672. if (!config->save_encoder_crtcs)
  7673. return -ENOMEM;
  7674. config->save_connector_encoders =
  7675. kcalloc(dev->mode_config.num_connector,
  7676. sizeof(struct drm_encoder *), GFP_KERNEL);
  7677. if (!config->save_connector_encoders)
  7678. return -ENOMEM;
  7679. /* Copy data. Note that driver private data is not affected.
  7680. * Should anything bad happen only the expected state is
  7681. * restored, not the drivers personal bookkeeping.
  7682. */
  7683. count = 0;
  7684. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  7685. config->save_encoder_crtcs[count++] = encoder->crtc;
  7686. }
  7687. count = 0;
  7688. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  7689. config->save_connector_encoders[count++] = connector->encoder;
  7690. }
  7691. return 0;
  7692. }
  7693. static void intel_set_config_restore_state(struct drm_device *dev,
  7694. struct intel_set_config *config)
  7695. {
  7696. struct intel_encoder *encoder;
  7697. struct intel_connector *connector;
  7698. int count;
  7699. count = 0;
  7700. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  7701. encoder->new_crtc =
  7702. to_intel_crtc(config->save_encoder_crtcs[count++]);
  7703. }
  7704. count = 0;
  7705. list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
  7706. connector->new_encoder =
  7707. to_intel_encoder(config->save_connector_encoders[count++]);
  7708. }
  7709. }
  7710. static bool
  7711. is_crtc_connector_off(struct drm_mode_set *set)
  7712. {
  7713. int i;
  7714. if (set->num_connectors == 0)
  7715. return false;
  7716. if (WARN_ON(set->connectors == NULL))
  7717. return false;
  7718. for (i = 0; i < set->num_connectors; i++)
  7719. if (set->connectors[i]->encoder &&
  7720. set->connectors[i]->encoder->crtc == set->crtc &&
  7721. set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
  7722. return true;
  7723. return false;
  7724. }
  7725. static void
  7726. intel_set_config_compute_mode_changes(struct drm_mode_set *set,
  7727. struct intel_set_config *config)
  7728. {
  7729. /* We should be able to check here if the fb has the same properties
  7730. * and then just flip_or_move it */
  7731. if (is_crtc_connector_off(set)) {
  7732. config->mode_changed = true;
  7733. } else if (set->crtc->fb != set->fb) {
  7734. /* If we have no fb then treat it as a full mode set */
  7735. if (set->crtc->fb == NULL) {
  7736. struct intel_crtc *intel_crtc =
  7737. to_intel_crtc(set->crtc);
  7738. if (intel_crtc->active && i915_fastboot) {
  7739. DRM_DEBUG_KMS("crtc has no fb, will flip\n");
  7740. config->fb_changed = true;
  7741. } else {
  7742. DRM_DEBUG_KMS("inactive crtc, full mode set\n");
  7743. config->mode_changed = true;
  7744. }
  7745. } else if (set->fb == NULL) {
  7746. config->mode_changed = true;
  7747. } else if (set->fb->pixel_format !=
  7748. set->crtc->fb->pixel_format) {
  7749. config->mode_changed = true;
  7750. } else {
  7751. config->fb_changed = true;
  7752. }
  7753. }
  7754. if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
  7755. config->fb_changed = true;
  7756. if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
  7757. DRM_DEBUG_KMS("modes are different, full mode set\n");
  7758. drm_mode_debug_printmodeline(&set->crtc->mode);
  7759. drm_mode_debug_printmodeline(set->mode);
  7760. config->mode_changed = true;
  7761. }
  7762. DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
  7763. set->crtc->base.id, config->mode_changed, config->fb_changed);
  7764. }
  7765. static int
  7766. intel_modeset_stage_output_state(struct drm_device *dev,
  7767. struct drm_mode_set *set,
  7768. struct intel_set_config *config)
  7769. {
  7770. struct drm_crtc *new_crtc;
  7771. struct intel_connector *connector;
  7772. struct intel_encoder *encoder;
  7773. int ro;
  7774. /* The upper layers ensure that we either disable a crtc or have a list
  7775. * of connectors. For paranoia, double-check this. */
  7776. WARN_ON(!set->fb && (set->num_connectors != 0));
  7777. WARN_ON(set->fb && (set->num_connectors == 0));
  7778. list_for_each_entry(connector, &dev->mode_config.connector_list,
  7779. base.head) {
  7780. /* Otherwise traverse passed in connector list and get encoders
  7781. * for them. */
  7782. for (ro = 0; ro < set->num_connectors; ro++) {
  7783. if (set->connectors[ro] == &connector->base) {
  7784. connector->new_encoder = connector->encoder;
  7785. break;
  7786. }
  7787. }
  7788. /* If we disable the crtc, disable all its connectors. Also, if
  7789. * the connector is on the changing crtc but not on the new
  7790. * connector list, disable it. */
  7791. if ((!set->fb || ro == set->num_connectors) &&
  7792. connector->base.encoder &&
  7793. connector->base.encoder->crtc == set->crtc) {
  7794. connector->new_encoder = NULL;
  7795. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
  7796. connector->base.base.id,
  7797. drm_get_connector_name(&connector->base));
  7798. }
  7799. if (&connector->new_encoder->base != connector->base.encoder) {
  7800. DRM_DEBUG_KMS("encoder changed, full mode switch\n");
  7801. config->mode_changed = true;
  7802. }
  7803. }
  7804. /* connector->new_encoder is now updated for all connectors. */
  7805. /* Update crtc of enabled connectors. */
  7806. list_for_each_entry(connector, &dev->mode_config.connector_list,
  7807. base.head) {
  7808. if (!connector->new_encoder)
  7809. continue;
  7810. new_crtc = connector->new_encoder->base.crtc;
  7811. for (ro = 0; ro < set->num_connectors; ro++) {
  7812. if (set->connectors[ro] == &connector->base)
  7813. new_crtc = set->crtc;
  7814. }
  7815. /* Make sure the new CRTC will work with the encoder */
  7816. if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
  7817. new_crtc)) {
  7818. return -EINVAL;
  7819. }
  7820. connector->encoder->new_crtc = to_intel_crtc(new_crtc);
  7821. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
  7822. connector->base.base.id,
  7823. drm_get_connector_name(&connector->base),
  7824. new_crtc->base.id);
  7825. }
  7826. /* Check for any encoders that needs to be disabled. */
  7827. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7828. base.head) {
  7829. list_for_each_entry(connector,
  7830. &dev->mode_config.connector_list,
  7831. base.head) {
  7832. if (connector->new_encoder == encoder) {
  7833. WARN_ON(!connector->new_encoder->new_crtc);
  7834. goto next_encoder;
  7835. }
  7836. }
  7837. encoder->new_crtc = NULL;
  7838. next_encoder:
  7839. /* Only now check for crtc changes so we don't miss encoders
  7840. * that will be disabled. */
  7841. if (&encoder->new_crtc->base != encoder->base.crtc) {
  7842. DRM_DEBUG_KMS("crtc changed, full mode switch\n");
  7843. config->mode_changed = true;
  7844. }
  7845. }
  7846. /* Now we've also updated encoder->new_crtc for all encoders. */
  7847. return 0;
  7848. }
  7849. static int intel_crtc_set_config(struct drm_mode_set *set)
  7850. {
  7851. struct drm_device *dev;
  7852. struct drm_mode_set save_set;
  7853. struct intel_set_config *config;
  7854. int ret;
  7855. BUG_ON(!set);
  7856. BUG_ON(!set->crtc);
  7857. BUG_ON(!set->crtc->helper_private);
  7858. /* Enforce sane interface api - has been abused by the fb helper. */
  7859. BUG_ON(!set->mode && set->fb);
  7860. BUG_ON(set->fb && set->num_connectors == 0);
  7861. if (set->fb) {
  7862. DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
  7863. set->crtc->base.id, set->fb->base.id,
  7864. (int)set->num_connectors, set->x, set->y);
  7865. } else {
  7866. DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
  7867. }
  7868. dev = set->crtc->dev;
  7869. ret = -ENOMEM;
  7870. config = kzalloc(sizeof(*config), GFP_KERNEL);
  7871. if (!config)
  7872. goto out_config;
  7873. ret = intel_set_config_save_state(dev, config);
  7874. if (ret)
  7875. goto out_config;
  7876. save_set.crtc = set->crtc;
  7877. save_set.mode = &set->crtc->mode;
  7878. save_set.x = set->crtc->x;
  7879. save_set.y = set->crtc->y;
  7880. save_set.fb = set->crtc->fb;
  7881. /* Compute whether we need a full modeset, only an fb base update or no
  7882. * change at all. In the future we might also check whether only the
  7883. * mode changed, e.g. for LVDS where we only change the panel fitter in
  7884. * such cases. */
  7885. intel_set_config_compute_mode_changes(set, config);
  7886. ret = intel_modeset_stage_output_state(dev, set, config);
  7887. if (ret)
  7888. goto fail;
  7889. if (config->mode_changed) {
  7890. ret = intel_set_mode(set->crtc, set->mode,
  7891. set->x, set->y, set->fb);
  7892. } else if (config->fb_changed) {
  7893. intel_crtc_wait_for_pending_flips(set->crtc);
  7894. ret = intel_pipe_set_base(set->crtc,
  7895. set->x, set->y, set->fb);
  7896. }
  7897. if (ret) {
  7898. DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
  7899. set->crtc->base.id, ret);
  7900. fail:
  7901. intel_set_config_restore_state(dev, config);
  7902. /* Try to restore the config */
  7903. if (config->mode_changed &&
  7904. intel_set_mode(save_set.crtc, save_set.mode,
  7905. save_set.x, save_set.y, save_set.fb))
  7906. DRM_ERROR("failed to restore config after modeset failure\n");
  7907. }
  7908. out_config:
  7909. intel_set_config_free(config);
  7910. return ret;
  7911. }
  7912. static const struct drm_crtc_funcs intel_crtc_funcs = {
  7913. .cursor_set = intel_crtc_cursor_set,
  7914. .cursor_move = intel_crtc_cursor_move,
  7915. .gamma_set = intel_crtc_gamma_set,
  7916. .set_config = intel_crtc_set_config,
  7917. .destroy = intel_crtc_destroy,
  7918. .page_flip = intel_crtc_page_flip,
  7919. };
  7920. static void intel_cpu_pll_init(struct drm_device *dev)
  7921. {
  7922. if (HAS_DDI(dev))
  7923. intel_ddi_pll_init(dev);
  7924. }
  7925. static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
  7926. struct intel_shared_dpll *pll,
  7927. struct intel_dpll_hw_state *hw_state)
  7928. {
  7929. uint32_t val;
  7930. val = I915_READ(PCH_DPLL(pll->id));
  7931. hw_state->dpll = val;
  7932. hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
  7933. hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
  7934. return val & DPLL_VCO_ENABLE;
  7935. }
  7936. static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
  7937. struct intel_shared_dpll *pll)
  7938. {
  7939. I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
  7940. I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
  7941. }
  7942. static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
  7943. struct intel_shared_dpll *pll)
  7944. {
  7945. /* PCH refclock must be enabled first */
  7946. assert_pch_refclk_enabled(dev_priv);
  7947. I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
  7948. /* Wait for the clocks to stabilize. */
  7949. POSTING_READ(PCH_DPLL(pll->id));
  7950. udelay(150);
  7951. /* The pixel multiplier can only be updated once the
  7952. * DPLL is enabled and the clocks are stable.
  7953. *
  7954. * So write it again.
  7955. */
  7956. I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
  7957. POSTING_READ(PCH_DPLL(pll->id));
  7958. udelay(200);
  7959. }
  7960. static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
  7961. struct intel_shared_dpll *pll)
  7962. {
  7963. struct drm_device *dev = dev_priv->dev;
  7964. struct intel_crtc *crtc;
  7965. /* Make sure no transcoder isn't still depending on us. */
  7966. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
  7967. if (intel_crtc_to_shared_dpll(crtc) == pll)
  7968. assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
  7969. }
  7970. I915_WRITE(PCH_DPLL(pll->id), 0);
  7971. POSTING_READ(PCH_DPLL(pll->id));
  7972. udelay(200);
  7973. }
  7974. static char *ibx_pch_dpll_names[] = {
  7975. "PCH DPLL A",
  7976. "PCH DPLL B",
  7977. };
  7978. static void ibx_pch_dpll_init(struct drm_device *dev)
  7979. {
  7980. struct drm_i915_private *dev_priv = dev->dev_private;
  7981. int i;
  7982. dev_priv->num_shared_dpll = 2;
  7983. for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  7984. dev_priv->shared_dplls[i].id = i;
  7985. dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
  7986. dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
  7987. dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
  7988. dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
  7989. dev_priv->shared_dplls[i].get_hw_state =
  7990. ibx_pch_dpll_get_hw_state;
  7991. }
  7992. }
  7993. static void intel_shared_dpll_init(struct drm_device *dev)
  7994. {
  7995. struct drm_i915_private *dev_priv = dev->dev_private;
  7996. if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  7997. ibx_pch_dpll_init(dev);
  7998. else
  7999. dev_priv->num_shared_dpll = 0;
  8000. BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
  8001. DRM_DEBUG_KMS("%i shared PLLs initialized\n",
  8002. dev_priv->num_shared_dpll);
  8003. }
  8004. static void intel_crtc_init(struct drm_device *dev, int pipe)
  8005. {
  8006. drm_i915_private_t *dev_priv = dev->dev_private;
  8007. struct intel_crtc *intel_crtc;
  8008. int i;
  8009. intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
  8010. if (intel_crtc == NULL)
  8011. return;
  8012. drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
  8013. drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
  8014. for (i = 0; i < 256; i++) {
  8015. intel_crtc->lut_r[i] = i;
  8016. intel_crtc->lut_g[i] = i;
  8017. intel_crtc->lut_b[i] = i;
  8018. }
  8019. /* Swap pipes & planes for FBC on pre-965 */
  8020. intel_crtc->pipe = pipe;
  8021. intel_crtc->plane = pipe;
  8022. if (IS_MOBILE(dev) && IS_GEN3(dev)) {
  8023. DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
  8024. intel_crtc->plane = !pipe;
  8025. }
  8026. BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
  8027. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
  8028. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
  8029. dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
  8030. drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
  8031. }
  8032. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  8033. struct drm_file *file)
  8034. {
  8035. struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
  8036. struct drm_mode_object *drmmode_obj;
  8037. struct intel_crtc *crtc;
  8038. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  8039. return -ENODEV;
  8040. drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
  8041. DRM_MODE_OBJECT_CRTC);
  8042. if (!drmmode_obj) {
  8043. DRM_ERROR("no such CRTC id\n");
  8044. return -EINVAL;
  8045. }
  8046. crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
  8047. pipe_from_crtc_id->pipe = crtc->pipe;
  8048. return 0;
  8049. }
  8050. static int intel_encoder_clones(struct intel_encoder *encoder)
  8051. {
  8052. struct drm_device *dev = encoder->base.dev;
  8053. struct intel_encoder *source_encoder;
  8054. int index_mask = 0;
  8055. int entry = 0;
  8056. list_for_each_entry(source_encoder,
  8057. &dev->mode_config.encoder_list, base.head) {
  8058. if (encoder == source_encoder)
  8059. index_mask |= (1 << entry);
  8060. /* Intel hw has only one MUX where enocoders could be cloned. */
  8061. if (encoder->cloneable && source_encoder->cloneable)
  8062. index_mask |= (1 << entry);
  8063. entry++;
  8064. }
  8065. return index_mask;
  8066. }
  8067. static bool has_edp_a(struct drm_device *dev)
  8068. {
  8069. struct drm_i915_private *dev_priv = dev->dev_private;
  8070. if (!IS_MOBILE(dev))
  8071. return false;
  8072. if ((I915_READ(DP_A) & DP_DETECTED) == 0)
  8073. return false;
  8074. if (IS_GEN5(dev) &&
  8075. (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
  8076. return false;
  8077. return true;
  8078. }
  8079. static void intel_setup_outputs(struct drm_device *dev)
  8080. {
  8081. struct drm_i915_private *dev_priv = dev->dev_private;
  8082. struct intel_encoder *encoder;
  8083. bool dpd_is_edp = false;
  8084. intel_lvds_init(dev);
  8085. if (!IS_ULT(dev))
  8086. intel_crt_init(dev);
  8087. if (HAS_DDI(dev)) {
  8088. int found;
  8089. /* Haswell uses DDI functions to detect digital outputs */
  8090. found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
  8091. /* DDI A only supports eDP */
  8092. if (found)
  8093. intel_ddi_init(dev, PORT_A);
  8094. /* DDI B, C and D detection is indicated by the SFUSE_STRAP
  8095. * register */
  8096. found = I915_READ(SFUSE_STRAP);
  8097. if (found & SFUSE_STRAP_DDIB_DETECTED)
  8098. intel_ddi_init(dev, PORT_B);
  8099. if (found & SFUSE_STRAP_DDIC_DETECTED)
  8100. intel_ddi_init(dev, PORT_C);
  8101. if (found & SFUSE_STRAP_DDID_DETECTED)
  8102. intel_ddi_init(dev, PORT_D);
  8103. } else if (HAS_PCH_SPLIT(dev)) {
  8104. int found;
  8105. dpd_is_edp = intel_dpd_is_edp(dev);
  8106. if (has_edp_a(dev))
  8107. intel_dp_init(dev, DP_A, PORT_A);
  8108. if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
  8109. /* PCH SDVOB multiplex with HDMIB */
  8110. found = intel_sdvo_init(dev, PCH_SDVOB, true);
  8111. if (!found)
  8112. intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
  8113. if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
  8114. intel_dp_init(dev, PCH_DP_B, PORT_B);
  8115. }
  8116. if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
  8117. intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
  8118. if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
  8119. intel_hdmi_init(dev, PCH_HDMID, PORT_D);
  8120. if (I915_READ(PCH_DP_C) & DP_DETECTED)
  8121. intel_dp_init(dev, PCH_DP_C, PORT_C);
  8122. if (I915_READ(PCH_DP_D) & DP_DETECTED)
  8123. intel_dp_init(dev, PCH_DP_D, PORT_D);
  8124. } else if (IS_VALLEYVIEW(dev)) {
  8125. /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
  8126. if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
  8127. intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
  8128. PORT_C);
  8129. if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
  8130. intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
  8131. PORT_C);
  8132. }
  8133. if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
  8134. intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
  8135. PORT_B);
  8136. if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
  8137. intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
  8138. }
  8139. intel_dsi_init(dev);
  8140. } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
  8141. bool found = false;
  8142. if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
  8143. DRM_DEBUG_KMS("probing SDVOB\n");
  8144. found = intel_sdvo_init(dev, GEN3_SDVOB, true);
  8145. if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
  8146. DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
  8147. intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
  8148. }
  8149. if (!found && SUPPORTS_INTEGRATED_DP(dev))
  8150. intel_dp_init(dev, DP_B, PORT_B);
  8151. }
  8152. /* Before G4X SDVOC doesn't have its own detect register */
  8153. if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
  8154. DRM_DEBUG_KMS("probing SDVOC\n");
  8155. found = intel_sdvo_init(dev, GEN3_SDVOC, false);
  8156. }
  8157. if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
  8158. if (SUPPORTS_INTEGRATED_HDMI(dev)) {
  8159. DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
  8160. intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
  8161. }
  8162. if (SUPPORTS_INTEGRATED_DP(dev))
  8163. intel_dp_init(dev, DP_C, PORT_C);
  8164. }
  8165. if (SUPPORTS_INTEGRATED_DP(dev) &&
  8166. (I915_READ(DP_D) & DP_DETECTED))
  8167. intel_dp_init(dev, DP_D, PORT_D);
  8168. } else if (IS_GEN2(dev))
  8169. intel_dvo_init(dev);
  8170. if (SUPPORTS_TV(dev))
  8171. intel_tv_init(dev);
  8172. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  8173. encoder->base.possible_crtcs = encoder->crtc_mask;
  8174. encoder->base.possible_clones =
  8175. intel_encoder_clones(encoder);
  8176. }
  8177. intel_init_pch_refclk(dev);
  8178. drm_helper_move_panel_connectors_to_head(dev);
  8179. }
  8180. void intel_framebuffer_fini(struct intel_framebuffer *fb)
  8181. {
  8182. drm_framebuffer_cleanup(&fb->base);
  8183. drm_gem_object_unreference_unlocked(&fb->obj->base);
  8184. }
  8185. static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
  8186. {
  8187. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  8188. intel_framebuffer_fini(intel_fb);
  8189. kfree(intel_fb);
  8190. }
  8191. static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
  8192. struct drm_file *file,
  8193. unsigned int *handle)
  8194. {
  8195. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  8196. struct drm_i915_gem_object *obj = intel_fb->obj;
  8197. return drm_gem_handle_create(file, &obj->base, handle);
  8198. }
  8199. static const struct drm_framebuffer_funcs intel_fb_funcs = {
  8200. .destroy = intel_user_framebuffer_destroy,
  8201. .create_handle = intel_user_framebuffer_create_handle,
  8202. };
  8203. int intel_framebuffer_init(struct drm_device *dev,
  8204. struct intel_framebuffer *intel_fb,
  8205. struct drm_mode_fb_cmd2 *mode_cmd,
  8206. struct drm_i915_gem_object *obj)
  8207. {
  8208. int pitch_limit;
  8209. int ret;
  8210. if (obj->tiling_mode == I915_TILING_Y) {
  8211. DRM_DEBUG("hardware does not support tiling Y\n");
  8212. return -EINVAL;
  8213. }
  8214. if (mode_cmd->pitches[0] & 63) {
  8215. DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
  8216. mode_cmd->pitches[0]);
  8217. return -EINVAL;
  8218. }
  8219. if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
  8220. pitch_limit = 32*1024;
  8221. } else if (INTEL_INFO(dev)->gen >= 4) {
  8222. if (obj->tiling_mode)
  8223. pitch_limit = 16*1024;
  8224. else
  8225. pitch_limit = 32*1024;
  8226. } else if (INTEL_INFO(dev)->gen >= 3) {
  8227. if (obj->tiling_mode)
  8228. pitch_limit = 8*1024;
  8229. else
  8230. pitch_limit = 16*1024;
  8231. } else
  8232. /* XXX DSPC is limited to 4k tiled */
  8233. pitch_limit = 8*1024;
  8234. if (mode_cmd->pitches[0] > pitch_limit) {
  8235. DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
  8236. obj->tiling_mode ? "tiled" : "linear",
  8237. mode_cmd->pitches[0], pitch_limit);
  8238. return -EINVAL;
  8239. }
  8240. if (obj->tiling_mode != I915_TILING_NONE &&
  8241. mode_cmd->pitches[0] != obj->stride) {
  8242. DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
  8243. mode_cmd->pitches[0], obj->stride);
  8244. return -EINVAL;
  8245. }
  8246. /* Reject formats not supported by any plane early. */
  8247. switch (mode_cmd->pixel_format) {
  8248. case DRM_FORMAT_C8:
  8249. case DRM_FORMAT_RGB565:
  8250. case DRM_FORMAT_XRGB8888:
  8251. case DRM_FORMAT_ARGB8888:
  8252. break;
  8253. case DRM_FORMAT_XRGB1555:
  8254. case DRM_FORMAT_ARGB1555:
  8255. if (INTEL_INFO(dev)->gen > 3) {
  8256. DRM_DEBUG("unsupported pixel format: %s\n",
  8257. drm_get_format_name(mode_cmd->pixel_format));
  8258. return -EINVAL;
  8259. }
  8260. break;
  8261. case DRM_FORMAT_XBGR8888:
  8262. case DRM_FORMAT_ABGR8888:
  8263. case DRM_FORMAT_XRGB2101010:
  8264. case DRM_FORMAT_ARGB2101010:
  8265. case DRM_FORMAT_XBGR2101010:
  8266. case DRM_FORMAT_ABGR2101010:
  8267. if (INTEL_INFO(dev)->gen < 4) {
  8268. DRM_DEBUG("unsupported pixel format: %s\n",
  8269. drm_get_format_name(mode_cmd->pixel_format));
  8270. return -EINVAL;
  8271. }
  8272. break;
  8273. case DRM_FORMAT_YUYV:
  8274. case DRM_FORMAT_UYVY:
  8275. case DRM_FORMAT_YVYU:
  8276. case DRM_FORMAT_VYUY:
  8277. if (INTEL_INFO(dev)->gen < 5) {
  8278. DRM_DEBUG("unsupported pixel format: %s\n",
  8279. drm_get_format_name(mode_cmd->pixel_format));
  8280. return -EINVAL;
  8281. }
  8282. break;
  8283. default:
  8284. DRM_DEBUG("unsupported pixel format: %s\n",
  8285. drm_get_format_name(mode_cmd->pixel_format));
  8286. return -EINVAL;
  8287. }
  8288. /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
  8289. if (mode_cmd->offsets[0] != 0)
  8290. return -EINVAL;
  8291. drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
  8292. intel_fb->obj = obj;
  8293. ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
  8294. if (ret) {
  8295. DRM_ERROR("framebuffer init failed %d\n", ret);
  8296. return ret;
  8297. }
  8298. return 0;
  8299. }
  8300. static struct drm_framebuffer *
  8301. intel_user_framebuffer_create(struct drm_device *dev,
  8302. struct drm_file *filp,
  8303. struct drm_mode_fb_cmd2 *mode_cmd)
  8304. {
  8305. struct drm_i915_gem_object *obj;
  8306. obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
  8307. mode_cmd->handles[0]));
  8308. if (&obj->base == NULL)
  8309. return ERR_PTR(-ENOENT);
  8310. return intel_framebuffer_create(dev, mode_cmd, obj);
  8311. }
  8312. static const struct drm_mode_config_funcs intel_mode_funcs = {
  8313. .fb_create = intel_user_framebuffer_create,
  8314. .output_poll_changed = intel_fb_output_poll_changed,
  8315. };
  8316. /* Set up chip specific display functions */
  8317. static void intel_init_display(struct drm_device *dev)
  8318. {
  8319. struct drm_i915_private *dev_priv = dev->dev_private;
  8320. if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
  8321. dev_priv->display.find_dpll = g4x_find_best_dpll;
  8322. else if (IS_VALLEYVIEW(dev))
  8323. dev_priv->display.find_dpll = vlv_find_best_dpll;
  8324. else if (IS_PINEVIEW(dev))
  8325. dev_priv->display.find_dpll = pnv_find_best_dpll;
  8326. else
  8327. dev_priv->display.find_dpll = i9xx_find_best_dpll;
  8328. if (HAS_DDI(dev)) {
  8329. dev_priv->display.get_pipe_config = haswell_get_pipe_config;
  8330. dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
  8331. dev_priv->display.crtc_enable = haswell_crtc_enable;
  8332. dev_priv->display.crtc_disable = haswell_crtc_disable;
  8333. dev_priv->display.off = haswell_crtc_off;
  8334. dev_priv->display.update_plane = ironlake_update_plane;
  8335. } else if (HAS_PCH_SPLIT(dev)) {
  8336. dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
  8337. dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
  8338. dev_priv->display.crtc_enable = ironlake_crtc_enable;
  8339. dev_priv->display.crtc_disable = ironlake_crtc_disable;
  8340. dev_priv->display.off = ironlake_crtc_off;
  8341. dev_priv->display.update_plane = ironlake_update_plane;
  8342. } else if (IS_VALLEYVIEW(dev)) {
  8343. dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
  8344. dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
  8345. dev_priv->display.crtc_enable = valleyview_crtc_enable;
  8346. dev_priv->display.crtc_disable = i9xx_crtc_disable;
  8347. dev_priv->display.off = i9xx_crtc_off;
  8348. dev_priv->display.update_plane = i9xx_update_plane;
  8349. } else {
  8350. dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
  8351. dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
  8352. dev_priv->display.crtc_enable = i9xx_crtc_enable;
  8353. dev_priv->display.crtc_disable = i9xx_crtc_disable;
  8354. dev_priv->display.off = i9xx_crtc_off;
  8355. dev_priv->display.update_plane = i9xx_update_plane;
  8356. }
  8357. /* Returns the core display clock speed */
  8358. if (IS_VALLEYVIEW(dev))
  8359. dev_priv->display.get_display_clock_speed =
  8360. valleyview_get_display_clock_speed;
  8361. else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
  8362. dev_priv->display.get_display_clock_speed =
  8363. i945_get_display_clock_speed;
  8364. else if (IS_I915G(dev))
  8365. dev_priv->display.get_display_clock_speed =
  8366. i915_get_display_clock_speed;
  8367. else if (IS_I945GM(dev) || IS_845G(dev))
  8368. dev_priv->display.get_display_clock_speed =
  8369. i9xx_misc_get_display_clock_speed;
  8370. else if (IS_PINEVIEW(dev))
  8371. dev_priv->display.get_display_clock_speed =
  8372. pnv_get_display_clock_speed;
  8373. else if (IS_I915GM(dev))
  8374. dev_priv->display.get_display_clock_speed =
  8375. i915gm_get_display_clock_speed;
  8376. else if (IS_I865G(dev))
  8377. dev_priv->display.get_display_clock_speed =
  8378. i865_get_display_clock_speed;
  8379. else if (IS_I85X(dev))
  8380. dev_priv->display.get_display_clock_speed =
  8381. i855_get_display_clock_speed;
  8382. else /* 852, 830 */
  8383. dev_priv->display.get_display_clock_speed =
  8384. i830_get_display_clock_speed;
  8385. if (HAS_PCH_SPLIT(dev)) {
  8386. if (IS_GEN5(dev)) {
  8387. dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
  8388. dev_priv->display.write_eld = ironlake_write_eld;
  8389. } else if (IS_GEN6(dev)) {
  8390. dev_priv->display.fdi_link_train = gen6_fdi_link_train;
  8391. dev_priv->display.write_eld = ironlake_write_eld;
  8392. } else if (IS_IVYBRIDGE(dev)) {
  8393. /* FIXME: detect B0+ stepping and use auto training */
  8394. dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
  8395. dev_priv->display.write_eld = ironlake_write_eld;
  8396. dev_priv->display.modeset_global_resources =
  8397. ivb_modeset_global_resources;
  8398. } else if (IS_HASWELL(dev)) {
  8399. dev_priv->display.fdi_link_train = hsw_fdi_link_train;
  8400. dev_priv->display.write_eld = haswell_write_eld;
  8401. dev_priv->display.modeset_global_resources =
  8402. haswell_modeset_global_resources;
  8403. }
  8404. } else if (IS_G4X(dev)) {
  8405. dev_priv->display.write_eld = g4x_write_eld;
  8406. }
  8407. /* Default just returns -ENODEV to indicate unsupported */
  8408. dev_priv->display.queue_flip = intel_default_queue_flip;
  8409. switch (INTEL_INFO(dev)->gen) {
  8410. case 2:
  8411. dev_priv->display.queue_flip = intel_gen2_queue_flip;
  8412. break;
  8413. case 3:
  8414. dev_priv->display.queue_flip = intel_gen3_queue_flip;
  8415. break;
  8416. case 4:
  8417. case 5:
  8418. dev_priv->display.queue_flip = intel_gen4_queue_flip;
  8419. break;
  8420. case 6:
  8421. dev_priv->display.queue_flip = intel_gen6_queue_flip;
  8422. break;
  8423. case 7:
  8424. dev_priv->display.queue_flip = intel_gen7_queue_flip;
  8425. break;
  8426. }
  8427. }
  8428. /*
  8429. * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
  8430. * resume, or other times. This quirk makes sure that's the case for
  8431. * affected systems.
  8432. */
  8433. static void quirk_pipea_force(struct drm_device *dev)
  8434. {
  8435. struct drm_i915_private *dev_priv = dev->dev_private;
  8436. dev_priv->quirks |= QUIRK_PIPEA_FORCE;
  8437. DRM_INFO("applying pipe a force quirk\n");
  8438. }
  8439. /*
  8440. * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
  8441. */
  8442. static void quirk_ssc_force_disable(struct drm_device *dev)
  8443. {
  8444. struct drm_i915_private *dev_priv = dev->dev_private;
  8445. dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
  8446. DRM_INFO("applying lvds SSC disable quirk\n");
  8447. }
  8448. /*
  8449. * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
  8450. * brightness value
  8451. */
  8452. static void quirk_invert_brightness(struct drm_device *dev)
  8453. {
  8454. struct drm_i915_private *dev_priv = dev->dev_private;
  8455. dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
  8456. DRM_INFO("applying inverted panel brightness quirk\n");
  8457. }
  8458. /*
  8459. * Some machines (Dell XPS13) suffer broken backlight controls if
  8460. * BLM_PCH_PWM_ENABLE is set.
  8461. */
  8462. static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
  8463. {
  8464. struct drm_i915_private *dev_priv = dev->dev_private;
  8465. dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
  8466. DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
  8467. }
  8468. struct intel_quirk {
  8469. int device;
  8470. int subsystem_vendor;
  8471. int subsystem_device;
  8472. void (*hook)(struct drm_device *dev);
  8473. };
  8474. /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
  8475. struct intel_dmi_quirk {
  8476. void (*hook)(struct drm_device *dev);
  8477. const struct dmi_system_id (*dmi_id_list)[];
  8478. };
  8479. static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
  8480. {
  8481. DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
  8482. return 1;
  8483. }
  8484. static const struct intel_dmi_quirk intel_dmi_quirks[] = {
  8485. {
  8486. .dmi_id_list = &(const struct dmi_system_id[]) {
  8487. {
  8488. .callback = intel_dmi_reverse_brightness,
  8489. .ident = "NCR Corporation",
  8490. .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
  8491. DMI_MATCH(DMI_PRODUCT_NAME, ""),
  8492. },
  8493. },
  8494. { } /* terminating entry */
  8495. },
  8496. .hook = quirk_invert_brightness,
  8497. },
  8498. };
  8499. static struct intel_quirk intel_quirks[] = {
  8500. /* HP Mini needs pipe A force quirk (LP: #322104) */
  8501. { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
  8502. /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
  8503. { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
  8504. /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
  8505. { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
  8506. /* 830/845 need to leave pipe A & dpll A up */
  8507. { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  8508. { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  8509. /* Lenovo U160 cannot use SSC on LVDS */
  8510. { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
  8511. /* Sony Vaio Y cannot use SSC on LVDS */
  8512. { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
  8513. /* Acer Aspire 5734Z must invert backlight brightness */
  8514. { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
  8515. /* Acer/eMachines G725 */
  8516. { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
  8517. /* Acer/eMachines e725 */
  8518. { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
  8519. /* Acer/Packard Bell NCL20 */
  8520. { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
  8521. /* Acer Aspire 4736Z */
  8522. { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
  8523. /* Dell XPS13 HD Sandy Bridge */
  8524. { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
  8525. /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
  8526. { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
  8527. };
  8528. static void intel_init_quirks(struct drm_device *dev)
  8529. {
  8530. struct pci_dev *d = dev->pdev;
  8531. int i;
  8532. for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
  8533. struct intel_quirk *q = &intel_quirks[i];
  8534. if (d->device == q->device &&
  8535. (d->subsystem_vendor == q->subsystem_vendor ||
  8536. q->subsystem_vendor == PCI_ANY_ID) &&
  8537. (d->subsystem_device == q->subsystem_device ||
  8538. q->subsystem_device == PCI_ANY_ID))
  8539. q->hook(dev);
  8540. }
  8541. for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
  8542. if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
  8543. intel_dmi_quirks[i].hook(dev);
  8544. }
  8545. }
  8546. /* Disable the VGA plane that we never use */
  8547. static void i915_disable_vga(struct drm_device *dev)
  8548. {
  8549. struct drm_i915_private *dev_priv = dev->dev_private;
  8550. u8 sr1;
  8551. u32 vga_reg = i915_vgacntrl_reg(dev);
  8552. vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
  8553. outb(SR01, VGA_SR_INDEX);
  8554. sr1 = inb(VGA_SR_DATA);
  8555. outb(sr1 | 1<<5, VGA_SR_DATA);
  8556. /* Disable VGA memory on Intel HD */
  8557. if (HAS_PCH_SPLIT(dev)) {
  8558. outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
  8559. vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
  8560. VGA_RSRC_NORMAL_IO |
  8561. VGA_RSRC_NORMAL_MEM);
  8562. }
  8563. vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
  8564. udelay(300);
  8565. I915_WRITE(vga_reg, VGA_DISP_DISABLE);
  8566. POSTING_READ(vga_reg);
  8567. }
  8568. static void i915_enable_vga(struct drm_device *dev)
  8569. {
  8570. /* Enable VGA memory on Intel HD */
  8571. if (HAS_PCH_SPLIT(dev)) {
  8572. vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
  8573. outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
  8574. vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
  8575. VGA_RSRC_LEGACY_MEM |
  8576. VGA_RSRC_NORMAL_IO |
  8577. VGA_RSRC_NORMAL_MEM);
  8578. vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
  8579. }
  8580. }
  8581. void intel_modeset_init_hw(struct drm_device *dev)
  8582. {
  8583. intel_init_power_well(dev);
  8584. intel_prepare_ddi(dev);
  8585. intel_init_clock_gating(dev);
  8586. mutex_lock(&dev->struct_mutex);
  8587. intel_enable_gt_powersave(dev);
  8588. mutex_unlock(&dev->struct_mutex);
  8589. }
  8590. void intel_modeset_suspend_hw(struct drm_device *dev)
  8591. {
  8592. intel_suspend_hw(dev);
  8593. }
  8594. void intel_modeset_init(struct drm_device *dev)
  8595. {
  8596. struct drm_i915_private *dev_priv = dev->dev_private;
  8597. int i, j, ret;
  8598. drm_mode_config_init(dev);
  8599. dev->mode_config.min_width = 0;
  8600. dev->mode_config.min_height = 0;
  8601. dev->mode_config.preferred_depth = 24;
  8602. dev->mode_config.prefer_shadow = 1;
  8603. dev->mode_config.funcs = &intel_mode_funcs;
  8604. intel_init_quirks(dev);
  8605. intel_init_pm(dev);
  8606. if (INTEL_INFO(dev)->num_pipes == 0)
  8607. return;
  8608. intel_init_display(dev);
  8609. if (IS_GEN2(dev)) {
  8610. dev->mode_config.max_width = 2048;
  8611. dev->mode_config.max_height = 2048;
  8612. } else if (IS_GEN3(dev)) {
  8613. dev->mode_config.max_width = 4096;
  8614. dev->mode_config.max_height = 4096;
  8615. } else {
  8616. dev->mode_config.max_width = 8192;
  8617. dev->mode_config.max_height = 8192;
  8618. }
  8619. dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
  8620. DRM_DEBUG_KMS("%d display pipe%s available.\n",
  8621. INTEL_INFO(dev)->num_pipes,
  8622. INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
  8623. for_each_pipe(i) {
  8624. intel_crtc_init(dev, i);
  8625. for (j = 0; j < dev_priv->num_plane; j++) {
  8626. ret = intel_plane_init(dev, i, j);
  8627. if (ret)
  8628. DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
  8629. pipe_name(i), sprite_name(i, j), ret);
  8630. }
  8631. }
  8632. intel_cpu_pll_init(dev);
  8633. intel_shared_dpll_init(dev);
  8634. /* Just disable it once at startup */
  8635. i915_disable_vga(dev);
  8636. intel_setup_outputs(dev);
  8637. /* Just in case the BIOS is doing something questionable. */
  8638. intel_disable_fbc(dev);
  8639. }
  8640. static void
  8641. intel_connector_break_all_links(struct intel_connector *connector)
  8642. {
  8643. connector->base.dpms = DRM_MODE_DPMS_OFF;
  8644. connector->base.encoder = NULL;
  8645. connector->encoder->connectors_active = false;
  8646. connector->encoder->base.crtc = NULL;
  8647. }
  8648. static void intel_enable_pipe_a(struct drm_device *dev)
  8649. {
  8650. struct intel_connector *connector;
  8651. struct drm_connector *crt = NULL;
  8652. struct intel_load_detect_pipe load_detect_temp;
  8653. /* We can't just switch on the pipe A, we need to set things up with a
  8654. * proper mode and output configuration. As a gross hack, enable pipe A
  8655. * by enabling the load detect pipe once. */
  8656. list_for_each_entry(connector,
  8657. &dev->mode_config.connector_list,
  8658. base.head) {
  8659. if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
  8660. crt = &connector->base;
  8661. break;
  8662. }
  8663. }
  8664. if (!crt)
  8665. return;
  8666. if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
  8667. intel_release_load_detect_pipe(crt, &load_detect_temp);
  8668. }
  8669. static bool
  8670. intel_check_plane_mapping(struct intel_crtc *crtc)
  8671. {
  8672. struct drm_device *dev = crtc->base.dev;
  8673. struct drm_i915_private *dev_priv = dev->dev_private;
  8674. u32 reg, val;
  8675. if (INTEL_INFO(dev)->num_pipes == 1)
  8676. return true;
  8677. reg = DSPCNTR(!crtc->plane);
  8678. val = I915_READ(reg);
  8679. if ((val & DISPLAY_PLANE_ENABLE) &&
  8680. (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
  8681. return false;
  8682. return true;
  8683. }
  8684. static void intel_sanitize_crtc(struct intel_crtc *crtc)
  8685. {
  8686. struct drm_device *dev = crtc->base.dev;
  8687. struct drm_i915_private *dev_priv = dev->dev_private;
  8688. u32 reg;
  8689. /* Clear any frame start delays used for debugging left by the BIOS */
  8690. reg = PIPECONF(crtc->config.cpu_transcoder);
  8691. I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
  8692. /* We need to sanitize the plane -> pipe mapping first because this will
  8693. * disable the crtc (and hence change the state) if it is wrong. Note
  8694. * that gen4+ has a fixed plane -> pipe mapping. */
  8695. if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
  8696. struct intel_connector *connector;
  8697. bool plane;
  8698. DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
  8699. crtc->base.base.id);
  8700. /* Pipe has the wrong plane attached and the plane is active.
  8701. * Temporarily change the plane mapping and disable everything
  8702. * ... */
  8703. plane = crtc->plane;
  8704. crtc->plane = !plane;
  8705. dev_priv->display.crtc_disable(&crtc->base);
  8706. crtc->plane = plane;
  8707. /* ... and break all links. */
  8708. list_for_each_entry(connector, &dev->mode_config.connector_list,
  8709. base.head) {
  8710. if (connector->encoder->base.crtc != &crtc->base)
  8711. continue;
  8712. intel_connector_break_all_links(connector);
  8713. }
  8714. WARN_ON(crtc->active);
  8715. crtc->base.enabled = false;
  8716. }
  8717. if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
  8718. crtc->pipe == PIPE_A && !crtc->active) {
  8719. /* BIOS forgot to enable pipe A, this mostly happens after
  8720. * resume. Force-enable the pipe to fix this, the update_dpms
  8721. * call below we restore the pipe to the right state, but leave
  8722. * the required bits on. */
  8723. intel_enable_pipe_a(dev);
  8724. }
  8725. /* Adjust the state of the output pipe according to whether we
  8726. * have active connectors/encoders. */
  8727. intel_crtc_update_dpms(&crtc->base);
  8728. if (crtc->active != crtc->base.enabled) {
  8729. struct intel_encoder *encoder;
  8730. /* This can happen either due to bugs in the get_hw_state
  8731. * functions or because the pipe is force-enabled due to the
  8732. * pipe A quirk. */
  8733. DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
  8734. crtc->base.base.id,
  8735. crtc->base.enabled ? "enabled" : "disabled",
  8736. crtc->active ? "enabled" : "disabled");
  8737. crtc->base.enabled = crtc->active;
  8738. /* Because we only establish the connector -> encoder ->
  8739. * crtc links if something is active, this means the
  8740. * crtc is now deactivated. Break the links. connector
  8741. * -> encoder links are only establish when things are
  8742. * actually up, hence no need to break them. */
  8743. WARN_ON(crtc->active);
  8744. for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
  8745. WARN_ON(encoder->connectors_active);
  8746. encoder->base.crtc = NULL;
  8747. }
  8748. }
  8749. }
  8750. static void intel_sanitize_encoder(struct intel_encoder *encoder)
  8751. {
  8752. struct intel_connector *connector;
  8753. struct drm_device *dev = encoder->base.dev;
  8754. /* We need to check both for a crtc link (meaning that the
  8755. * encoder is active and trying to read from a pipe) and the
  8756. * pipe itself being active. */
  8757. bool has_active_crtc = encoder->base.crtc &&
  8758. to_intel_crtc(encoder->base.crtc)->active;
  8759. if (encoder->connectors_active && !has_active_crtc) {
  8760. DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
  8761. encoder->base.base.id,
  8762. drm_get_encoder_name(&encoder->base));
  8763. /* Connector is active, but has no active pipe. This is
  8764. * fallout from our resume register restoring. Disable
  8765. * the encoder manually again. */
  8766. if (encoder->base.crtc) {
  8767. DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
  8768. encoder->base.base.id,
  8769. drm_get_encoder_name(&encoder->base));
  8770. encoder->disable(encoder);
  8771. }
  8772. /* Inconsistent output/port/pipe state happens presumably due to
  8773. * a bug in one of the get_hw_state functions. Or someplace else
  8774. * in our code, like the register restore mess on resume. Clamp
  8775. * things to off as a safer default. */
  8776. list_for_each_entry(connector,
  8777. &dev->mode_config.connector_list,
  8778. base.head) {
  8779. if (connector->encoder != encoder)
  8780. continue;
  8781. intel_connector_break_all_links(connector);
  8782. }
  8783. }
  8784. /* Enabled encoders without active connectors will be fixed in
  8785. * the crtc fixup. */
  8786. }
  8787. void i915_redisable_vga(struct drm_device *dev)
  8788. {
  8789. struct drm_i915_private *dev_priv = dev->dev_private;
  8790. u32 vga_reg = i915_vgacntrl_reg(dev);
  8791. /* This function can be called both from intel_modeset_setup_hw_state or
  8792. * at a very early point in our resume sequence, where the power well
  8793. * structures are not yet restored. Since this function is at a very
  8794. * paranoid "someone might have enabled VGA while we were not looking"
  8795. * level, just check if the power well is enabled instead of trying to
  8796. * follow the "don't touch the power well if we don't need it" policy
  8797. * the rest of the driver uses. */
  8798. if (HAS_POWER_WELL(dev) &&
  8799. (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
  8800. return;
  8801. if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
  8802. DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
  8803. i915_disable_vga(dev);
  8804. }
  8805. }
  8806. static void intel_modeset_readout_hw_state(struct drm_device *dev)
  8807. {
  8808. struct drm_i915_private *dev_priv = dev->dev_private;
  8809. enum pipe pipe;
  8810. struct intel_crtc *crtc;
  8811. struct intel_encoder *encoder;
  8812. struct intel_connector *connector;
  8813. int i;
  8814. list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  8815. base.head) {
  8816. memset(&crtc->config, 0, sizeof(crtc->config));
  8817. crtc->active = dev_priv->display.get_pipe_config(crtc,
  8818. &crtc->config);
  8819. crtc->base.enabled = crtc->active;
  8820. DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
  8821. crtc->base.base.id,
  8822. crtc->active ? "enabled" : "disabled");
  8823. }
  8824. /* FIXME: Smash this into the new shared dpll infrastructure. */
  8825. if (HAS_DDI(dev))
  8826. intel_ddi_setup_hw_pll_state(dev);
  8827. for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  8828. struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
  8829. pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
  8830. pll->active = 0;
  8831. list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  8832. base.head) {
  8833. if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
  8834. pll->active++;
  8835. }
  8836. pll->refcount = pll->active;
  8837. DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
  8838. pll->name, pll->refcount, pll->on);
  8839. }
  8840. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  8841. base.head) {
  8842. pipe = 0;
  8843. if (encoder->get_hw_state(encoder, &pipe)) {
  8844. crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  8845. encoder->base.crtc = &crtc->base;
  8846. if (encoder->get_config)
  8847. encoder->get_config(encoder, &crtc->config);
  8848. } else {
  8849. encoder->base.crtc = NULL;
  8850. }
  8851. encoder->connectors_active = false;
  8852. DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
  8853. encoder->base.base.id,
  8854. drm_get_encoder_name(&encoder->base),
  8855. encoder->base.crtc ? "enabled" : "disabled",
  8856. pipe);
  8857. }
  8858. list_for_each_entry(connector, &dev->mode_config.connector_list,
  8859. base.head) {
  8860. if (connector->get_hw_state(connector)) {
  8861. connector->base.dpms = DRM_MODE_DPMS_ON;
  8862. connector->encoder->connectors_active = true;
  8863. connector->base.encoder = &connector->encoder->base;
  8864. } else {
  8865. connector->base.dpms = DRM_MODE_DPMS_OFF;
  8866. connector->base.encoder = NULL;
  8867. }
  8868. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
  8869. connector->base.base.id,
  8870. drm_get_connector_name(&connector->base),
  8871. connector->base.encoder ? "enabled" : "disabled");
  8872. }
  8873. }
  8874. /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
  8875. * and i915 state tracking structures. */
  8876. void intel_modeset_setup_hw_state(struct drm_device *dev,
  8877. bool force_restore)
  8878. {
  8879. struct drm_i915_private *dev_priv = dev->dev_private;
  8880. enum pipe pipe;
  8881. struct drm_plane *plane;
  8882. struct intel_crtc *crtc;
  8883. struct intel_encoder *encoder;
  8884. int i;
  8885. intel_modeset_readout_hw_state(dev);
  8886. /*
  8887. * Now that we have the config, copy it to each CRTC struct
  8888. * Note that this could go away if we move to using crtc_config
  8889. * checking everywhere.
  8890. */
  8891. list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  8892. base.head) {
  8893. if (crtc->active && i915_fastboot) {
  8894. intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
  8895. DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
  8896. crtc->base.base.id);
  8897. drm_mode_debug_printmodeline(&crtc->base.mode);
  8898. }
  8899. }
  8900. /* HW state is read out, now we need to sanitize this mess. */
  8901. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  8902. base.head) {
  8903. intel_sanitize_encoder(encoder);
  8904. }
  8905. for_each_pipe(pipe) {
  8906. crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  8907. intel_sanitize_crtc(crtc);
  8908. intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
  8909. }
  8910. for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  8911. struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
  8912. if (!pll->on || pll->active)
  8913. continue;
  8914. DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
  8915. pll->disable(dev_priv, pll);
  8916. pll->on = false;
  8917. }
  8918. if (force_restore) {
  8919. /*
  8920. * We need to use raw interfaces for restoring state to avoid
  8921. * checking (bogus) intermediate states.
  8922. */
  8923. for_each_pipe(pipe) {
  8924. struct drm_crtc *crtc =
  8925. dev_priv->pipe_to_crtc_mapping[pipe];
  8926. __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
  8927. crtc->fb);
  8928. }
  8929. list_for_each_entry(plane, &dev->mode_config.plane_list, head)
  8930. intel_plane_restore(plane);
  8931. i915_redisable_vga(dev);
  8932. } else {
  8933. intel_modeset_update_staged_output_state(dev);
  8934. }
  8935. intel_modeset_check_state(dev);
  8936. drm_mode_config_reset(dev);
  8937. }
  8938. void intel_modeset_gem_init(struct drm_device *dev)
  8939. {
  8940. intel_modeset_init_hw(dev);
  8941. intel_setup_overlay(dev);
  8942. intel_modeset_setup_hw_state(dev, false);
  8943. }
  8944. void intel_modeset_cleanup(struct drm_device *dev)
  8945. {
  8946. struct drm_i915_private *dev_priv = dev->dev_private;
  8947. struct drm_crtc *crtc;
  8948. /*
  8949. * Interrupts and polling as the first thing to avoid creating havoc.
  8950. * Too much stuff here (turning of rps, connectors, ...) would
  8951. * experience fancy races otherwise.
  8952. */
  8953. drm_irq_uninstall(dev);
  8954. cancel_work_sync(&dev_priv->hotplug_work);
  8955. /*
  8956. * Due to the hpd irq storm handling the hotplug work can re-arm the
  8957. * poll handlers. Hence disable polling after hpd handling is shut down.
  8958. */
  8959. drm_kms_helper_poll_fini(dev);
  8960. mutex_lock(&dev->struct_mutex);
  8961. intel_unregister_dsm_handler();
  8962. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  8963. /* Skip inactive CRTCs */
  8964. if (!crtc->fb)
  8965. continue;
  8966. intel_increase_pllclock(crtc);
  8967. }
  8968. intel_disable_fbc(dev);
  8969. i915_enable_vga(dev);
  8970. intel_disable_gt_powersave(dev);
  8971. ironlake_teardown_rc6(dev);
  8972. mutex_unlock(&dev->struct_mutex);
  8973. /* flush any delayed tasks or pending work */
  8974. flush_scheduled_work();
  8975. /* destroy backlight, if any, before the connectors */
  8976. intel_panel_destroy_backlight(dev);
  8977. drm_mode_config_cleanup(dev);
  8978. intel_cleanup_overlay(dev);
  8979. }
  8980. /*
  8981. * Return which encoder is currently attached for connector.
  8982. */
  8983. struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
  8984. {
  8985. return &intel_attached_encoder(connector)->base;
  8986. }
  8987. void intel_connector_attach_encoder(struct intel_connector *connector,
  8988. struct intel_encoder *encoder)
  8989. {
  8990. connector->encoder = encoder;
  8991. drm_mode_connector_attach_encoder(&connector->base,
  8992. &encoder->base);
  8993. }
  8994. /*
  8995. * set vga decode state - true == enable VGA decode
  8996. */
  8997. int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
  8998. {
  8999. struct drm_i915_private *dev_priv = dev->dev_private;
  9000. u16 gmch_ctrl;
  9001. pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
  9002. if (state)
  9003. gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
  9004. else
  9005. gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
  9006. pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
  9007. return 0;
  9008. }
  9009. struct intel_display_error_state {
  9010. u32 power_well_driver;
  9011. int num_transcoders;
  9012. struct intel_cursor_error_state {
  9013. u32 control;
  9014. u32 position;
  9015. u32 base;
  9016. u32 size;
  9017. } cursor[I915_MAX_PIPES];
  9018. struct intel_pipe_error_state {
  9019. u32 source;
  9020. } pipe[I915_MAX_PIPES];
  9021. struct intel_plane_error_state {
  9022. u32 control;
  9023. u32 stride;
  9024. u32 size;
  9025. u32 pos;
  9026. u32 addr;
  9027. u32 surface;
  9028. u32 tile_offset;
  9029. } plane[I915_MAX_PIPES];
  9030. struct intel_transcoder_error_state {
  9031. enum transcoder cpu_transcoder;
  9032. u32 conf;
  9033. u32 htotal;
  9034. u32 hblank;
  9035. u32 hsync;
  9036. u32 vtotal;
  9037. u32 vblank;
  9038. u32 vsync;
  9039. } transcoder[4];
  9040. };
  9041. struct intel_display_error_state *
  9042. intel_display_capture_error_state(struct drm_device *dev)
  9043. {
  9044. drm_i915_private_t *dev_priv = dev->dev_private;
  9045. struct intel_display_error_state *error;
  9046. int transcoders[] = {
  9047. TRANSCODER_A,
  9048. TRANSCODER_B,
  9049. TRANSCODER_C,
  9050. TRANSCODER_EDP,
  9051. };
  9052. int i;
  9053. if (INTEL_INFO(dev)->num_pipes == 0)
  9054. return NULL;
  9055. error = kmalloc(sizeof(*error), GFP_ATOMIC);
  9056. if (error == NULL)
  9057. return NULL;
  9058. if (HAS_POWER_WELL(dev))
  9059. error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
  9060. for_each_pipe(i) {
  9061. if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
  9062. error->cursor[i].control = I915_READ(CURCNTR(i));
  9063. error->cursor[i].position = I915_READ(CURPOS(i));
  9064. error->cursor[i].base = I915_READ(CURBASE(i));
  9065. } else {
  9066. error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
  9067. error->cursor[i].position = I915_READ(CURPOS_IVB(i));
  9068. error->cursor[i].base = I915_READ(CURBASE_IVB(i));
  9069. }
  9070. error->plane[i].control = I915_READ(DSPCNTR(i));
  9071. error->plane[i].stride = I915_READ(DSPSTRIDE(i));
  9072. if (INTEL_INFO(dev)->gen <= 3) {
  9073. error->plane[i].size = I915_READ(DSPSIZE(i));
  9074. error->plane[i].pos = I915_READ(DSPPOS(i));
  9075. }
  9076. if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
  9077. error->plane[i].addr = I915_READ(DSPADDR(i));
  9078. if (INTEL_INFO(dev)->gen >= 4) {
  9079. error->plane[i].surface = I915_READ(DSPSURF(i));
  9080. error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
  9081. }
  9082. error->pipe[i].source = I915_READ(PIPESRC(i));
  9083. }
  9084. error->num_transcoders = INTEL_INFO(dev)->num_pipes;
  9085. if (HAS_DDI(dev_priv->dev))
  9086. error->num_transcoders++; /* Account for eDP. */
  9087. for (i = 0; i < error->num_transcoders; i++) {
  9088. enum transcoder cpu_transcoder = transcoders[i];
  9089. error->transcoder[i].cpu_transcoder = cpu_transcoder;
  9090. error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
  9091. error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
  9092. error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
  9093. error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
  9094. error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
  9095. error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
  9096. error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
  9097. }
  9098. /* In the code above we read the registers without checking if the power
  9099. * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
  9100. * prevent the next I915_WRITE from detecting it and printing an error
  9101. * message. */
  9102. intel_uncore_clear_errors(dev);
  9103. return error;
  9104. }
  9105. #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
  9106. void
  9107. intel_display_print_error_state(struct drm_i915_error_state_buf *m,
  9108. struct drm_device *dev,
  9109. struct intel_display_error_state *error)
  9110. {
  9111. int i;
  9112. if (!error)
  9113. return;
  9114. err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
  9115. if (HAS_POWER_WELL(dev))
  9116. err_printf(m, "PWR_WELL_CTL2: %08x\n",
  9117. error->power_well_driver);
  9118. for_each_pipe(i) {
  9119. err_printf(m, "Pipe [%d]:\n", i);
  9120. err_printf(m, " SRC: %08x\n", error->pipe[i].source);
  9121. err_printf(m, "Plane [%d]:\n", i);
  9122. err_printf(m, " CNTR: %08x\n", error->plane[i].control);
  9123. err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
  9124. if (INTEL_INFO(dev)->gen <= 3) {
  9125. err_printf(m, " SIZE: %08x\n", error->plane[i].size);
  9126. err_printf(m, " POS: %08x\n", error->plane[i].pos);
  9127. }
  9128. if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
  9129. err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
  9130. if (INTEL_INFO(dev)->gen >= 4) {
  9131. err_printf(m, " SURF: %08x\n", error->plane[i].surface);
  9132. err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
  9133. }
  9134. err_printf(m, "Cursor [%d]:\n", i);
  9135. err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
  9136. err_printf(m, " POS: %08x\n", error->cursor[i].position);
  9137. err_printf(m, " BASE: %08x\n", error->cursor[i].base);
  9138. }
  9139. for (i = 0; i < error->num_transcoders; i++) {
  9140. err_printf(m, " CPU transcoder: %c\n",
  9141. transcoder_name(error->transcoder[i].cpu_transcoder));
  9142. err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
  9143. err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
  9144. err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
  9145. err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
  9146. err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
  9147. err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
  9148. err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
  9149. }
  9150. }