i7300_edac.c 34 KB

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  1. /*
  2. * Intel 7300 class Memory Controllers kernel module (Clarksboro)
  3. *
  4. * This file may be distributed under the terms of the
  5. * GNU General Public License version 2 only.
  6. *
  7. * Copyright (c) 2010 by:
  8. * Mauro Carvalho Chehab <mchehab@redhat.com>
  9. *
  10. * Red Hat Inc. http://www.redhat.com
  11. *
  12. * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet
  13. * http://www.intel.com/Assets/PDF/datasheet/318082.pdf
  14. *
  15. * TODO: The chipset allow checking for PCI Express errors also. Currently,
  16. * the driver covers only memory error errors
  17. *
  18. * This driver uses "csrows" EDAC attribute to represent DIMM slot#
  19. */
  20. #include <linux/module.h>
  21. #include <linux/init.h>
  22. #include <linux/pci.h>
  23. #include <linux/pci_ids.h>
  24. #include <linux/slab.h>
  25. #include <linux/edac.h>
  26. #include <linux/mmzone.h>
  27. #include "edac_core.h"
  28. /*
  29. * Alter this version for the I7300 module when modifications are made
  30. */
  31. #define I7300_REVISION " Ver: 1.0.0 " __DATE__
  32. #define EDAC_MOD_STR "i7300_edac"
  33. #define i7300_printk(level, fmt, arg...) \
  34. edac_printk(level, "i7300", fmt, ##arg)
  35. #define i7300_mc_printk(mci, level, fmt, arg...) \
  36. edac_mc_chipset_printk(mci, level, "i7300", fmt, ##arg)
  37. /*
  38. * Memory topology is organized as:
  39. * Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0)
  40. * Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0)
  41. * Each channel can have to 8 DIMM sets (called as SLOTS)
  42. * Slots should generally be filled in pairs
  43. * Except on Single Channel mode of operation
  44. * just slot 0/channel0 filled on this mode
  45. * On normal operation mode, the two channels on a branch should be
  46. * filled together for the same SLOT#
  47. * When in mirrored mode, Branch 1 replicate memory at Branch 0, so, the four
  48. * channels on both branches should be filled
  49. */
  50. /* Limits for i7300 */
  51. #define MAX_SLOTS 8
  52. #define MAX_BRANCHES 2
  53. #define MAX_CH_PER_BRANCH 2
  54. #define MAX_CHANNELS (MAX_CH_PER_BRANCH * MAX_BRANCHES)
  55. #define MAX_MIR 3
  56. #define to_channel(ch, branch) ((((branch)) << 1) | (ch))
  57. #define to_csrow(slot, ch, branch) \
  58. (to_channel(ch, branch) | ((slot) << 2))
  59. /*
  60. * I7300 devices
  61. * All 3 functions of Device 16 (0,1,2) share the SAME DID and
  62. * uses PCI_DEVICE_ID_INTEL_I7300_MCH_ERR for device 16 (0,1,2),
  63. * PCI_DEVICE_ID_INTEL_I7300_MCH_FB0 and PCI_DEVICE_ID_INTEL_I7300_MCH_FB1
  64. * for device 21 (0,1).
  65. */
  66. /****************************************************
  67. * i7300 Register definitions for memory enumberation
  68. ****************************************************/
  69. /*
  70. * Device 16,
  71. * Function 0: System Address (not documented)
  72. * Function 1: Memory Branch Map, Control, Errors Register
  73. */
  74. /* OFFSETS for Function 0 */
  75. #define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */
  76. #define MAXCH 0x56 /* Max Channel Number */
  77. #define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */
  78. /* OFFSETS for Function 1 */
  79. #define MC_SETTINGS 0x40
  80. #define IS_MIRRORED(mc) ((mc) & (1 << 16))
  81. #define IS_ECC_ENABLED(mc) ((mc) & (1 << 5))
  82. #define IS_RETRY_ENABLED(mc) ((mc) & (1 << 31))
  83. #define IS_SCRBALGO_ENHANCED(mc) ((mc) & (1 << 8))
  84. #define MC_SETTINGS_A 0x58
  85. #define IS_SINGLE_MODE(mca) ((mca) & (1 << 14))
  86. #define TOLM 0x6C
  87. #define REDMEMB 0x7C
  88. #define MIR0 0x80
  89. #define MIR1 0x84
  90. #define MIR2 0x88
  91. /*
  92. * Note: Other Intel EDAC drivers use AMBPRESENT to identify if the available
  93. * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it
  94. * seems that we cannot use this information directly for the same usage.
  95. * Each memory slot may have up to 2 AMB interfaces, one for income and another
  96. * for outcome interface to the next slot.
  97. * For now, the driver just stores the AMB present registers, but rely only at
  98. * the MTR info to detect memory.
  99. * Datasheet is also not clear about how to map each AMBPRESENT registers to
  100. * one of the 4 available channels.
  101. */
  102. #define AMBPRESENT_0 0x64
  103. #define AMBPRESENT_1 0x66
  104. const static u16 mtr_regs [MAX_SLOTS] = {
  105. 0x80, 0x84, 0x88, 0x8c,
  106. 0x82, 0x86, 0x8a, 0x8e
  107. };
  108. /* Defines to extract the vaious fields from the
  109. * MTRx - Memory Technology Registers
  110. */
  111. #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 8))
  112. #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 7))
  113. #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 6)) ? 8 : 4)
  114. #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 5)) ? 8 : 4)
  115. #define MTR_DIMM_RANKS(mtr) (((mtr) & (1 << 4)) ? 1 : 0)
  116. #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)
  117. #define MTR_DRAM_BANKS_ADDR_BITS 2
  118. #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)
  119. #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
  120. #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
  121. #ifdef CONFIG_EDAC_DEBUG
  122. /* MTR NUMROW */
  123. static const char *numrow_toString[] = {
  124. "8,192 - 13 rows",
  125. "16,384 - 14 rows",
  126. "32,768 - 15 rows",
  127. "65,536 - 16 rows"
  128. };
  129. /* MTR NUMCOL */
  130. static const char *numcol_toString[] = {
  131. "1,024 - 10 columns",
  132. "2,048 - 11 columns",
  133. "4,096 - 12 columns",
  134. "reserved"
  135. };
  136. #endif
  137. /************************************************
  138. * i7300 Register definitions for error detection
  139. ************************************************/
  140. /*
  141. * Device 16.1: FBD Error Registers
  142. */
  143. #define FERR_FAT_FBD 0x98
  144. static const char *ferr_fat_fbd_name[] = {
  145. [22] = "Non-Redundant Fast Reset Timeout",
  146. [2] = ">Tmid Thermal event with intelligent throttling disabled",
  147. [1] = "Memory or FBD configuration CRC read error",
  148. [0] = "Memory Write error on non-redundant retry or "
  149. "FBD configuration Write error on retry",
  150. };
  151. #define GET_FBD_FAT_IDX(fbderr) (fbderr & (3 << 28))
  152. #define FERR_FAT_FBD_ERR_MASK ((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3))
  153. #define FERR_NF_FBD 0xa0
  154. static const char *ferr_nf_fbd_name[] = {
  155. [24] = "DIMM-Spare Copy Completed",
  156. [23] = "DIMM-Spare Copy Initiated",
  157. [22] = "Redundant Fast Reset Timeout",
  158. [21] = "Memory Write error on redundant retry",
  159. [18] = "SPD protocol Error",
  160. [17] = "FBD Northbound parity error on FBD Sync Status",
  161. [16] = "Correctable Patrol Data ECC",
  162. [15] = "Correctable Resilver- or Spare-Copy Data ECC",
  163. [14] = "Correctable Mirrored Demand Data ECC",
  164. [13] = "Correctable Non-Mirrored Demand Data ECC",
  165. [11] = "Memory or FBD configuration CRC read error",
  166. [10] = "FBD Configuration Write error on first attempt",
  167. [9] = "Memory Write error on first attempt",
  168. [8] = "Non-Aliased Uncorrectable Patrol Data ECC",
  169. [7] = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
  170. [6] = "Non-Aliased Uncorrectable Mirrored Demand Data ECC",
  171. [5] = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC",
  172. [4] = "Aliased Uncorrectable Patrol Data ECC",
  173. [3] = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
  174. [2] = "Aliased Uncorrectable Mirrored Demand Data ECC",
  175. [1] = "Aliased Uncorrectable Non-Mirrored Demand Data ECC",
  176. [0] = "Uncorrectable Data ECC on Replay",
  177. };
  178. #define GET_FBD_NF_IDX(fbderr) (fbderr & (3 << 28))
  179. #define FERR_NF_FBD_ERR_MASK ((1 << 24) | (1 << 23) | (1 << 22) | (1 << 21) |\
  180. (1 << 18) | (1 << 17) | (1 << 16) | (1 << 15) |\
  181. (1 << 14) | (1 << 13) | (1 << 11) | (1 << 10) |\
  182. (1 << 9) | (1 << 8) | (1 << 7) | (1 << 6) |\
  183. (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2) |\
  184. (1 << 1) | (1 << 0))
  185. #define EMASK_FBD 0xa8
  186. #define EMASK_FBD_ERR_MASK ((1 << 27) | (1 << 26) | (1 << 25) | (1 << 24) |\
  187. (1 << 22) | (1 << 21) | (1 << 20) | (1 << 19) |\
  188. (1 << 18) | (1 << 17) | (1 << 16) | (1 << 14) |\
  189. (1 << 13) | (1 << 12) | (1 << 11) | (1 << 10) |\
  190. (1 << 9) | (1 << 8) | (1 << 7) | (1 << 6) |\
  191. (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2) |\
  192. (1 << 1) | (1 << 0))
  193. /*
  194. * Device 16.2: Global Error Registers
  195. */
  196. #define FERR_GLOBAL_HI 0x48
  197. static const char *ferr_global_hi_name[] = {
  198. [3] = "FSB 3 Fatal Error",
  199. [2] = "FSB 2 Fatal Error",
  200. [1] = "FSB 1 Fatal Error",
  201. [0] = "FSB 0 Fatal Error",
  202. };
  203. #define ferr_global_hi_is_fatal(errno) 1
  204. #define FERR_GLOBAL_LO 0x40
  205. static const char *ferr_global_lo_name[] = {
  206. [31] = "Internal MCH Fatal Error",
  207. [30] = "Intel QuickData Technology Device Fatal Error",
  208. [29] = "FSB1 Fatal Error",
  209. [28] = "FSB0 Fatal Error",
  210. [27] = "FBD Channel 3 Fatal Error",
  211. [26] = "FBD Channel 2 Fatal Error",
  212. [25] = "FBD Channel 1 Fatal Error",
  213. [24] = "FBD Channel 0 Fatal Error",
  214. [23] = "PCI Express Device 7Fatal Error",
  215. [22] = "PCI Express Device 6 Fatal Error",
  216. [21] = "PCI Express Device 5 Fatal Error",
  217. [20] = "PCI Express Device 4 Fatal Error",
  218. [19] = "PCI Express Device 3 Fatal Error",
  219. [18] = "PCI Express Device 2 Fatal Error",
  220. [17] = "PCI Express Device 1 Fatal Error",
  221. [16] = "ESI Fatal Error",
  222. [15] = "Internal MCH Non-Fatal Error",
  223. [14] = "Intel QuickData Technology Device Non Fatal Error",
  224. [13] = "FSB1 Non-Fatal Error",
  225. [12] = "FSB 0 Non-Fatal Error",
  226. [11] = "FBD Channel 3 Non-Fatal Error",
  227. [10] = "FBD Channel 2 Non-Fatal Error",
  228. [9] = "FBD Channel 1 Non-Fatal Error",
  229. [8] = "FBD Channel 0 Non-Fatal Error",
  230. [7] = "PCI Express Device 7 Non-Fatal Error",
  231. [6] = "PCI Express Device 6 Non-Fatal Error",
  232. [5] = "PCI Express Device 5 Non-Fatal Error",
  233. [4] = "PCI Express Device 4 Non-Fatal Error",
  234. [3] = "PCI Express Device 3 Non-Fatal Error",
  235. [2] = "PCI Express Device 2 Non-Fatal Error",
  236. [1] = "PCI Express Device 1 Non-Fatal Error",
  237. [0] = "ESI Non-Fatal Error",
  238. };
  239. #define ferr_global_lo_is_fatal(errno) ((errno < 16) ? 0 : 1)
  240. #define NRECMEMA 0xbe
  241. #define NRECMEMA_BANK(v) (((v) >> 12) & 7)
  242. #define NRECMEMA_RANK(v) (((v) >> 8) & 15)
  243. #define NRECMEMB 0xc0
  244. #define NRECMEMB_IS_WR(v) ((v) & (1 << 31))
  245. #define NRECMEMB_CAS(v) (((v) >> 16) & 0x1fff)
  246. #define NRECMEMB_RAS(v) ((v) & 0xffff)
  247. /* Device name and register DID (Device ID) */
  248. struct i7300_dev_info {
  249. const char *ctl_name; /* name for this device */
  250. u16 fsb_mapping_errors; /* DID for the branchmap,control */
  251. };
  252. /* Table of devices attributes supported by this driver */
  253. static const struct i7300_dev_info i7300_devs[] = {
  254. {
  255. .ctl_name = "I7300",
  256. .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I7300_MCH_ERR,
  257. },
  258. };
  259. struct i7300_dimm_info {
  260. int megabytes; /* size, 0 means not present */
  261. };
  262. /* driver private data structure */
  263. struct i7300_pvt {
  264. struct pci_dev *pci_dev_16_0_fsb_ctlr; /* 16.0 */
  265. struct pci_dev *pci_dev_16_1_fsb_addr_map; /* 16.1 */
  266. struct pci_dev *pci_dev_16_2_fsb_err_regs; /* 16.2 */
  267. struct pci_dev *pci_dev_2x_0_fbd_branch[MAX_BRANCHES]; /* 21.0 and 22.0 */
  268. u16 tolm; /* top of low memory */
  269. u64 ambase; /* AMB BAR */
  270. u32 mc_settings; /* Report several settings */
  271. u32 mc_settings_a;
  272. u16 mir[MAX_MIR]; /* Memory Interleave Reg*/
  273. u16 mtr[MAX_SLOTS][MAX_BRANCHES]; /* Memory Technlogy Reg */
  274. u16 ambpresent[MAX_CHANNELS]; /* AMB present regs */
  275. /* DIMM information matrix, allocating architecture maximums */
  276. struct i7300_dimm_info dimm_info[MAX_SLOTS][MAX_CHANNELS];
  277. /* Temporary buffer for use when preparing error messages */
  278. char *tmp_prt_buffer;
  279. };
  280. /* FIXME: Why do we need to have this static? */
  281. static struct edac_pci_ctl_info *i7300_pci;
  282. /********************************************
  283. * i7300 Functions related to error detection
  284. ********************************************/
  285. const char *get_err_from_table(const char *table[], int size, int pos)
  286. {
  287. if (pos >= size)
  288. return "Reserved";
  289. return table[pos];
  290. }
  291. #define GET_ERR_FROM_TABLE(table, pos) \
  292. get_err_from_table(table, ARRAY_SIZE(table), pos)
  293. /*
  294. * i7300_process_error_global Retrieve the hardware error information from
  295. * the hardware and cache it in the 'info'
  296. * structure
  297. */
  298. static void i7300_process_error_global(struct mem_ctl_info *mci)
  299. {
  300. struct i7300_pvt *pvt;
  301. u32 errnum, value;
  302. unsigned long errors;
  303. const char *specific;
  304. bool is_fatal;
  305. pvt = mci->pvt_info;
  306. /* read in the 1st FATAL error register */
  307. pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
  308. FERR_GLOBAL_HI, &value);
  309. if (unlikely(value)) {
  310. errors = value;
  311. errnum = find_first_bit(&errors,
  312. ARRAY_SIZE(ferr_global_hi_name));
  313. specific = GET_ERR_FROM_TABLE(ferr_global_hi_name, errnum);
  314. is_fatal = ferr_global_hi_is_fatal(errnum);
  315. /* Clear the error bit */
  316. pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
  317. FERR_GLOBAL_HI, value);
  318. goto error_global;
  319. }
  320. pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
  321. FERR_GLOBAL_LO, &value);
  322. if (unlikely(value)) {
  323. errors = value;
  324. errnum = find_first_bit(&errors,
  325. ARRAY_SIZE(ferr_global_lo_name));
  326. specific = GET_ERR_FROM_TABLE(ferr_global_lo_name, errnum);
  327. is_fatal = ferr_global_lo_is_fatal(errnum);
  328. /* Clear the error bit */
  329. pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
  330. FERR_GLOBAL_LO, value);
  331. goto error_global;
  332. }
  333. return;
  334. error_global:
  335. i7300_mc_printk(mci, KERN_EMERG, "%s misc error: %s\n",
  336. is_fatal ? "Fatal" : "NOT fatal", specific);
  337. }
  338. /*
  339. * i7300_process_fbd_error Retrieve the hardware error information from
  340. * the hardware and cache it in the 'info'
  341. * structure
  342. */
  343. static void i7300_process_fbd_error(struct mem_ctl_info *mci)
  344. {
  345. struct i7300_pvt *pvt;
  346. u32 errnum, value;
  347. u16 val16;
  348. int branch, bank, rank, cas, ras;
  349. unsigned long errors;
  350. const char *specific;
  351. bool is_fatal, is_wr;
  352. pvt = mci->pvt_info;
  353. /* read in the 1st FATAL error register */
  354. pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
  355. FERR_FAT_FBD, &value);
  356. if (unlikely(value & FERR_FAT_FBD_ERR_MASK)) {
  357. errors = value & FERR_FAT_FBD_ERR_MASK ;
  358. errnum = find_first_bit(&errors,
  359. ARRAY_SIZE(ferr_fat_fbd_name));
  360. specific = GET_ERR_FROM_TABLE(ferr_fat_fbd_name, errnum);
  361. is_fatal = 1;
  362. branch = (GET_FBD_FAT_IDX(value) == 2) ? 1 : 0;
  363. pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map,
  364. NRECMEMA, &val16);
  365. bank = NRECMEMA_BANK(val16);
  366. rank = NRECMEMA_RANK(val16);
  367. pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
  368. NRECMEMB, &value);
  369. is_wr = NRECMEMB_IS_WR(value);
  370. cas = NRECMEMB_CAS(value);
  371. ras = NRECMEMB_RAS(value);
  372. snprintf(pvt->tmp_prt_buffer, PAGE_SIZE,
  373. "FATAL (Branch=%d DRAM-Bank=%d %s "
  374. "RAS=%d CAS=%d Err=0x%lx (%s))",
  375. branch >> 1, bank,
  376. is_wr ? "RDWR" : "RD",
  377. ras, cas,
  378. errors, specific);
  379. /* Call the helper to output message */
  380. edac_mc_handle_fbd_ue(mci, rank, branch << 1,
  381. (branch << 1) + 1,
  382. pvt->tmp_prt_buffer);
  383. return;
  384. }
  385. /* read in the 1st NON-FATAL error register */
  386. pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
  387. FERR_NF_FBD, &value);
  388. if (unlikely(value & FERR_NF_FBD_ERR_MASK)) {
  389. errors = value & FERR_NF_FBD_ERR_MASK;
  390. errnum = find_first_bit(&errors,
  391. ARRAY_SIZE(ferr_nf_fbd_name));
  392. specific = GET_ERR_FROM_TABLE(ferr_nf_fbd_name, errnum);
  393. is_fatal = 0;
  394. /* Clear the error bit */
  395. pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
  396. FERR_GLOBAL_LO, value);
  397. goto error_fbd;
  398. }
  399. return;
  400. error_fbd:
  401. i7300_mc_printk(mci, KERN_EMERG, "%s FBD error on branch %d: %s\n",
  402. is_fatal ? "Fatal" : "NOT fatal", branch, specific);
  403. }
  404. /*
  405. * i7300_check_error Retrieve the hardware error information from
  406. * the hardware and cache it in the 'info'
  407. * structure
  408. */
  409. static void i7300_check_error(struct mem_ctl_info *mci)
  410. {
  411. i7300_process_error_global(mci);
  412. i7300_process_fbd_error(mci);
  413. };
  414. /*
  415. * i7300_clear_error Retrieve any error from the hardware
  416. * but do NOT process that error.
  417. * Used for 'clearing' out of previous errors
  418. * Called by the Core module.
  419. */
  420. static void i7300_clear_error(struct mem_ctl_info *mci)
  421. {
  422. struct i7300_pvt *pvt = mci->pvt_info;
  423. u32 value;
  424. /*
  425. * All error values are RWC - we need to read and write 1 to the
  426. * bit that we want to cleanup
  427. */
  428. /* Clear global error registers */
  429. pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
  430. FERR_GLOBAL_HI, &value);
  431. pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
  432. FERR_GLOBAL_HI, value);
  433. pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
  434. FERR_GLOBAL_LO, &value);
  435. pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
  436. FERR_GLOBAL_LO, value);
  437. /* Clear FBD error registers */
  438. pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
  439. FERR_FAT_FBD, &value);
  440. pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
  441. FERR_FAT_FBD, value);
  442. pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
  443. FERR_NF_FBD, &value);
  444. pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
  445. FERR_NF_FBD, value);
  446. }
  447. /*
  448. * i7300_enable_error_reporting
  449. * Turn on the memory reporting features of the hardware
  450. */
  451. static void i7300_enable_error_reporting(struct mem_ctl_info *mci)
  452. {
  453. struct i7300_pvt *pvt = mci->pvt_info;
  454. u32 fbd_error_mask;
  455. /* Read the FBD Error Mask Register */
  456. pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
  457. EMASK_FBD, &fbd_error_mask);
  458. /* Enable with a '0' */
  459. fbd_error_mask &= ~(EMASK_FBD_ERR_MASK);
  460. pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
  461. EMASK_FBD, fbd_error_mask);
  462. }
  463. /************************************************
  464. * i7300 Functions related to memory enumberation
  465. ************************************************/
  466. /*
  467. * determine_mtr(pvt, csrow, channel)
  468. *
  469. * return the proper MTR register as determine by the csrow and desired channel
  470. */
  471. static int decode_mtr(struct i7300_pvt *pvt,
  472. int slot, int ch, int branch,
  473. struct i7300_dimm_info *dinfo,
  474. struct csrow_info *p_csrow)
  475. {
  476. int mtr, ans, addrBits, channel;
  477. channel = to_channel(ch, branch);
  478. mtr = pvt->mtr[slot][branch];
  479. ans = MTR_DIMMS_PRESENT(mtr) ? 1 : 0;
  480. debugf2("\tMTR%d CH%d: DIMMs are %s (mtr)\n",
  481. slot, channel,
  482. ans ? "Present" : "NOT Present");
  483. /* Determine if there is a DIMM present in this DIMM slot */
  484. #if 0
  485. if (!amb_present || !ans)
  486. return 0;
  487. #else
  488. if (!ans)
  489. return 0;
  490. #endif
  491. /* Start with the number of bits for a Bank
  492. * on the DRAM */
  493. addrBits = MTR_DRAM_BANKS_ADDR_BITS;
  494. /* Add thenumber of ROW bits */
  495. addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
  496. /* add the number of COLUMN bits */
  497. addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
  498. /* add the number of RANK bits */
  499. addrBits += MTR_DIMM_RANKS(mtr);
  500. addrBits += 6; /* add 64 bits per DIMM */
  501. addrBits -= 20; /* divide by 2^^20 */
  502. addrBits -= 3; /* 8 bits per bytes */
  503. dinfo->megabytes = 1 << addrBits;
  504. debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
  505. debugf2("\t\tELECTRICAL THROTTLING is %s\n",
  506. MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled");
  507. debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
  508. debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANKS(mtr) ? "double" : "single");
  509. debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]);
  510. debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]);
  511. debugf2("\t\tSIZE: %d MB\n", dinfo->megabytes);
  512. p_csrow->grain = 8;
  513. p_csrow->nr_pages = dinfo->megabytes << 8;
  514. p_csrow->mtype = MEM_FB_DDR2;
  515. /*
  516. * The type of error detection actually depends of the
  517. * mode of operation. When it is just one single memory chip, at
  518. * socket 0, channel 0, it uses 8-byte-over-32-byte SECDED+ code.
  519. * In normal or mirrored mode, it uses Lockstep mode,
  520. * with the possibility of using an extended algorithm for x8 memories
  521. * See datasheet Sections 7.3.6 to 7.3.8
  522. */
  523. if (IS_SINGLE_MODE(pvt->mc_settings_a)) {
  524. p_csrow->edac_mode = EDAC_SECDED;
  525. debugf2("\t\tECC code is 8-byte-over-32-byte SECDED+ code\n");
  526. } else {
  527. debugf2("\t\tECC code is on Lockstep mode\n");
  528. if (MTR_DRAM_WIDTH(mtr) == 8)
  529. p_csrow->edac_mode = EDAC_S8ECD8ED;
  530. else
  531. p_csrow->edac_mode = EDAC_S4ECD4ED;
  532. }
  533. /* ask what device type on this row */
  534. if (MTR_DRAM_WIDTH(mtr) == 8) {
  535. debugf2("\t\tScrub algorithm for x8 is on %s mode\n",
  536. IS_SCRBALGO_ENHANCED(pvt->mc_settings) ?
  537. "enhanced" : "normal");
  538. p_csrow->dtype = DEV_X8;
  539. } else
  540. p_csrow->dtype = DEV_X4;
  541. return mtr;
  542. }
  543. /*
  544. * print_dimm_size
  545. *
  546. * also will output a DIMM matrix map, if debug is enabled, for viewing
  547. * how the DIMMs are populated
  548. */
  549. static void print_dimm_size(struct i7300_pvt *pvt)
  550. {
  551. struct i7300_dimm_info *dinfo;
  552. char *p;
  553. int space, n;
  554. int channel, slot;
  555. space = PAGE_SIZE;
  556. p = pvt->tmp_prt_buffer;
  557. n = snprintf(p, space, " ");
  558. p += n;
  559. space -= n;
  560. for (channel = 0; channel < MAX_CHANNELS; channel++) {
  561. n = snprintf(p, space, "channel %d | ", channel);
  562. p += n;
  563. space -= n;
  564. }
  565. debugf2("%s\n", pvt->tmp_prt_buffer);
  566. p = pvt->tmp_prt_buffer;
  567. space = PAGE_SIZE;
  568. n = snprintf(p, space, "-------------------------------"
  569. "------------------------------");
  570. p += n;
  571. space -= n;
  572. debugf2("%s\n", pvt->tmp_prt_buffer);
  573. p = pvt->tmp_prt_buffer;
  574. space = PAGE_SIZE;
  575. for (slot = 0; slot < MAX_SLOTS; slot++) {
  576. n = snprintf(p, space, "csrow/SLOT %d ", slot);
  577. p += n;
  578. space -= n;
  579. for (channel = 0; channel < MAX_CHANNELS; channel++) {
  580. dinfo = &pvt->dimm_info[slot][channel];
  581. n = snprintf(p, space, "%4d MB | ", dinfo->megabytes);
  582. p += n;
  583. space -= n;
  584. }
  585. debugf2("%s\n", pvt->tmp_prt_buffer);
  586. p = pvt->tmp_prt_buffer;
  587. space = PAGE_SIZE;
  588. }
  589. n = snprintf(p, space, "-------------------------------"
  590. "------------------------------");
  591. p += n;
  592. space -= n;
  593. debugf2("%s\n", pvt->tmp_prt_buffer);
  594. p = pvt->tmp_prt_buffer;
  595. space = PAGE_SIZE;
  596. }
  597. /*
  598. * i7300_init_csrows Initialize the 'csrows' table within
  599. * the mci control structure with the
  600. * addressing of memory.
  601. *
  602. * return:
  603. * 0 success
  604. * 1 no actual memory found on this MC
  605. */
  606. static int i7300_init_csrows(struct mem_ctl_info *mci)
  607. {
  608. struct i7300_pvt *pvt;
  609. struct i7300_dimm_info *dinfo;
  610. struct csrow_info *p_csrow;
  611. int empty;
  612. int mtr;
  613. int ch, branch, slot, channel;
  614. pvt = mci->pvt_info;
  615. empty = 1; /* Assume NO memory */
  616. debugf2("Memory Technology Registers:\n");
  617. /* Get the AMB present registers for the four channels */
  618. for (branch = 0; branch < MAX_BRANCHES; branch++) {
  619. /* Read and dump branch 0's MTRs */
  620. channel = to_channel(0, branch);
  621. pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], AMBPRESENT_0,
  622. &pvt->ambpresent[channel]);
  623. debugf2("\t\tAMB-present CH%d = 0x%x:\n",
  624. channel, pvt->ambpresent[channel]);
  625. channel = to_channel(1, branch);
  626. pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], AMBPRESENT_1,
  627. &pvt->ambpresent[channel]);
  628. debugf2("\t\tAMB-present CH%d = 0x%x:\n",
  629. channel, pvt->ambpresent[channel]);
  630. }
  631. /* Get the set of MTR[0-7] regs by each branch */
  632. for (slot = 0; slot < MAX_SLOTS; slot++) {
  633. int where = mtr_regs[slot];
  634. for (branch = 0; branch < MAX_BRANCHES; branch++) {
  635. pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
  636. where,
  637. &pvt->mtr[slot][branch]);
  638. for (ch = 0; ch < MAX_BRANCHES; ch++) {
  639. int channel = to_channel(ch, branch);
  640. dinfo = &pvt->dimm_info[slot][channel];
  641. p_csrow = &mci->csrows[slot];
  642. mtr = decode_mtr(pvt, slot, ch, branch,
  643. dinfo, p_csrow);
  644. /* if no DIMMS on this row, continue */
  645. if (!MTR_DIMMS_PRESENT(mtr))
  646. continue;
  647. p_csrow->csrow_idx = slot;
  648. /* FAKE OUT VALUES, FIXME */
  649. p_csrow->first_page = 0 + slot * 20;
  650. p_csrow->last_page = 9 + slot * 20;
  651. p_csrow->page_mask = 0xfff;
  652. empty = 0;
  653. }
  654. }
  655. }
  656. return empty;
  657. }
  658. static void decode_mir(int mir_no, u16 mir[MAX_MIR])
  659. {
  660. if (mir[mir_no] & 3)
  661. debugf2("MIR%d: limit= 0x%x Branch(es) that participate: %s %s\n",
  662. mir_no,
  663. (mir[mir_no] >> 4) & 0xfff,
  664. (mir[mir_no] & 1) ? "B0" : "",
  665. (mir[mir_no] & 2) ? "B1": "");
  666. }
  667. /*
  668. * i7300_get_mc_regs read in the necessary registers and
  669. * cache locally
  670. *
  671. * Fills in the private data members
  672. */
  673. static int i7300_get_mc_regs(struct mem_ctl_info *mci)
  674. {
  675. struct i7300_pvt *pvt;
  676. u32 actual_tolm;
  677. int i, rc;
  678. pvt = mci->pvt_info;
  679. pci_read_config_dword(pvt->pci_dev_16_0_fsb_ctlr, AMBASE,
  680. (u32 *) &pvt->ambase);
  681. debugf2("AMBASE= 0x%lx\n", (long unsigned int)pvt->ambase);
  682. /* Get the Branch Map regs */
  683. pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, TOLM, &pvt->tolm);
  684. pvt->tolm >>= 12;
  685. debugf2("TOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm,
  686. pvt->tolm);
  687. actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28));
  688. debugf2("Actual TOLM byte addr=%u.%03u GB (0x%x)\n",
  689. actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28);
  690. /* Get memory controller settings */
  691. pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS,
  692. &pvt->mc_settings);
  693. pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS_A,
  694. &pvt->mc_settings_a);
  695. if (IS_SINGLE_MODE(pvt->mc_settings_a))
  696. debugf0("Memory controller operating on single mode\n");
  697. else
  698. debugf0("Memory controller operating on %s mode\n",
  699. IS_MIRRORED(pvt->mc_settings) ? "mirrored" : "non-mirrored");
  700. debugf0("Error detection is %s\n",
  701. IS_ECC_ENABLED(pvt->mc_settings) ? "enabled" : "disabled");
  702. debugf0("Retry is %s\n",
  703. IS_RETRY_ENABLED(pvt->mc_settings) ? "enabled" : "disabled");
  704. /* Get Memory Interleave Range registers */
  705. pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR0, &pvt->mir[0]);
  706. pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR1, &pvt->mir[1]);
  707. pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR2, &pvt->mir[2]);
  708. /* Decode the MIR regs */
  709. for (i = 0; i < MAX_MIR; i++)
  710. decode_mir(i, pvt->mir);
  711. rc = i7300_init_csrows(mci);
  712. if (rc < 0)
  713. return rc;
  714. /* Go and determine the size of each DIMM and place in an
  715. * orderly matrix */
  716. print_dimm_size(pvt);
  717. return 0;
  718. }
  719. /*************************************************
  720. * i7300 Functions related to device probe/release
  721. *************************************************/
  722. /*
  723. * i7300_put_devices 'put' all the devices that we have
  724. * reserved via 'get'
  725. */
  726. static void i7300_put_devices(struct mem_ctl_info *mci)
  727. {
  728. struct i7300_pvt *pvt;
  729. int branch;
  730. pvt = mci->pvt_info;
  731. /* Decrement usage count for devices */
  732. for (branch = 0; branch < MAX_CH_PER_BRANCH; branch++)
  733. pci_dev_put(pvt->pci_dev_2x_0_fbd_branch[branch]);
  734. pci_dev_put(pvt->pci_dev_16_2_fsb_err_regs);
  735. pci_dev_put(pvt->pci_dev_16_1_fsb_addr_map);
  736. }
  737. /*
  738. * i7300_get_devices Find and perform 'get' operation on the MCH's
  739. * device/functions we want to reference for this driver
  740. *
  741. * Need to 'get' device 16 func 1 and func 2
  742. */
  743. static int i7300_get_devices(struct mem_ctl_info *mci, int dev_idx)
  744. {
  745. struct i7300_pvt *pvt;
  746. struct pci_dev *pdev;
  747. pvt = mci->pvt_info;
  748. /* Attempt to 'get' the MCH register we want */
  749. pdev = NULL;
  750. while (!pvt->pci_dev_16_1_fsb_addr_map || !pvt->pci_dev_16_2_fsb_err_regs) {
  751. pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
  752. PCI_DEVICE_ID_INTEL_I7300_MCH_ERR, pdev);
  753. if (!pdev) {
  754. /* End of list, leave */
  755. i7300_printk(KERN_ERR,
  756. "'system address,Process Bus' "
  757. "device not found:"
  758. "vendor 0x%x device 0x%x ERR funcs "
  759. "(broken BIOS?)\n",
  760. PCI_VENDOR_ID_INTEL,
  761. PCI_DEVICE_ID_INTEL_I7300_MCH_ERR);
  762. goto error;
  763. }
  764. /* Store device 16 funcs 1 and 2 */
  765. switch (PCI_FUNC(pdev->devfn)) {
  766. case 1:
  767. pvt->pci_dev_16_1_fsb_addr_map = pdev;
  768. break;
  769. case 2:
  770. pvt->pci_dev_16_2_fsb_err_regs = pdev;
  771. break;
  772. }
  773. }
  774. debugf1("System Address, processor bus- PCI Bus ID: %s %x:%x\n",
  775. pci_name(pvt->pci_dev_16_0_fsb_ctlr),
  776. pvt->pci_dev_16_0_fsb_ctlr->vendor, pvt->pci_dev_16_0_fsb_ctlr->device);
  777. debugf1("Branchmap, control and errors - PCI Bus ID: %s %x:%x\n",
  778. pci_name(pvt->pci_dev_16_1_fsb_addr_map),
  779. pvt->pci_dev_16_1_fsb_addr_map->vendor, pvt->pci_dev_16_1_fsb_addr_map->device);
  780. debugf1("FSB Error Regs - PCI Bus ID: %s %x:%x\n",
  781. pci_name(pvt->pci_dev_16_2_fsb_err_regs),
  782. pvt->pci_dev_16_2_fsb_err_regs->vendor, pvt->pci_dev_16_2_fsb_err_regs->device);
  783. pvt->pci_dev_2x_0_fbd_branch[0] = pci_get_device(PCI_VENDOR_ID_INTEL,
  784. PCI_DEVICE_ID_INTEL_I7300_MCH_FB0,
  785. NULL);
  786. if (!pvt->pci_dev_2x_0_fbd_branch[0]) {
  787. i7300_printk(KERN_ERR,
  788. "MC: 'BRANCH 0' device not found:"
  789. "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
  790. PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_FB0);
  791. goto error;
  792. }
  793. pvt->pci_dev_2x_0_fbd_branch[1] = pci_get_device(PCI_VENDOR_ID_INTEL,
  794. PCI_DEVICE_ID_INTEL_I7300_MCH_FB1,
  795. NULL);
  796. if (!pvt->pci_dev_2x_0_fbd_branch[1]) {
  797. i7300_printk(KERN_ERR,
  798. "MC: 'BRANCH 1' device not found:"
  799. "vendor 0x%x device 0x%x Func 0 "
  800. "(broken BIOS?)\n",
  801. PCI_VENDOR_ID_INTEL,
  802. PCI_DEVICE_ID_INTEL_I7300_MCH_FB1);
  803. goto error;
  804. }
  805. return 0;
  806. error:
  807. i7300_put_devices(mci);
  808. return -ENODEV;
  809. }
  810. /*
  811. * i7300_probe1 Probe for ONE instance of device to see if it is
  812. * present.
  813. * return:
  814. * 0 for FOUND a device
  815. * < 0 for error code
  816. */
  817. static int i7300_probe1(struct pci_dev *pdev, int dev_idx)
  818. {
  819. struct mem_ctl_info *mci;
  820. struct i7300_pvt *pvt;
  821. int num_channels;
  822. int num_dimms_per_channel;
  823. int num_csrows;
  824. if (dev_idx >= ARRAY_SIZE(i7300_devs))
  825. return -EINVAL;
  826. debugf0("MC: " __FILE__ ": %s(), pdev bus %u dev=0x%x fn=0x%x\n",
  827. __func__,
  828. pdev->bus->number,
  829. PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
  830. /* We only are looking for func 0 of the set */
  831. if (PCI_FUNC(pdev->devfn) != 0)
  832. return -ENODEV;
  833. /* As we don't have a motherboard identification routine to determine
  834. * actual number of slots/dimms per channel, we thus utilize the
  835. * resource as specified by the chipset. Thus, we might have
  836. * have more DIMMs per channel than actually on the mobo, but this
  837. * allows the driver to support upto the chipset max, without
  838. * some fancy mobo determination.
  839. */
  840. num_dimms_per_channel = MAX_SLOTS;
  841. num_channels = MAX_CHANNELS;
  842. num_csrows = MAX_SLOTS * MAX_CHANNELS;
  843. debugf0("MC: %s(): Number of - Channels= %d DIMMS= %d CSROWS= %d\n",
  844. __func__, num_channels, num_dimms_per_channel, num_csrows);
  845. /* allocate a new MC control structure */
  846. mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0);
  847. if (mci == NULL)
  848. return -ENOMEM;
  849. debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
  850. mci->dev = &pdev->dev; /* record ptr to the generic device */
  851. pvt = mci->pvt_info;
  852. pvt->pci_dev_16_0_fsb_ctlr = pdev; /* Record this device in our private */
  853. pvt->tmp_prt_buffer = kmalloc(PAGE_SIZE, GFP_KERNEL);
  854. if (!pvt->tmp_prt_buffer) {
  855. edac_mc_free(mci);
  856. return -ENOMEM;
  857. }
  858. /* 'get' the pci devices we want to reserve for our use */
  859. if (i7300_get_devices(mci, dev_idx))
  860. goto fail0;
  861. mci->mc_idx = 0;
  862. mci->mtype_cap = MEM_FLAG_FB_DDR2;
  863. mci->edac_ctl_cap = EDAC_FLAG_NONE;
  864. mci->edac_cap = EDAC_FLAG_NONE;
  865. mci->mod_name = "i7300_edac.c";
  866. mci->mod_ver = I7300_REVISION;
  867. mci->ctl_name = i7300_devs[dev_idx].ctl_name;
  868. mci->dev_name = pci_name(pdev);
  869. mci->ctl_page_to_phys = NULL;
  870. /* Set the function pointer to an actual operation function */
  871. mci->edac_check = i7300_check_error;
  872. /* initialize the MC control structure 'csrows' table
  873. * with the mapping and control information */
  874. if (i7300_get_mc_regs(mci)) {
  875. debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n"
  876. " because i7300_init_csrows() returned nonzero "
  877. "value\n");
  878. mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
  879. } else {
  880. debugf1("MC: Enable error reporting now\n");
  881. i7300_enable_error_reporting(mci);
  882. }
  883. /* add this new MC control structure to EDAC's list of MCs */
  884. if (edac_mc_add_mc(mci)) {
  885. debugf0("MC: " __FILE__
  886. ": %s(): failed edac_mc_add_mc()\n", __func__);
  887. /* FIXME: perhaps some code should go here that disables error
  888. * reporting if we just enabled it
  889. */
  890. goto fail1;
  891. }
  892. i7300_clear_error(mci);
  893. /* allocating generic PCI control info */
  894. i7300_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
  895. if (!i7300_pci) {
  896. printk(KERN_WARNING
  897. "%s(): Unable to create PCI control\n",
  898. __func__);
  899. printk(KERN_WARNING
  900. "%s(): PCI error report via EDAC not setup\n",
  901. __func__);
  902. }
  903. return 0;
  904. /* Error exit unwinding stack */
  905. fail1:
  906. i7300_put_devices(mci);
  907. fail0:
  908. kfree(pvt->tmp_prt_buffer);
  909. edac_mc_free(mci);
  910. return -ENODEV;
  911. }
  912. /*
  913. * i7300_init_one constructor for one instance of device
  914. *
  915. * returns:
  916. * negative on error
  917. * count (>= 0)
  918. */
  919. static int __devinit i7300_init_one(struct pci_dev *pdev,
  920. const struct pci_device_id *id)
  921. {
  922. int rc;
  923. debugf0("MC: " __FILE__ ": %s()\n", __func__);
  924. /* wake up device */
  925. rc = pci_enable_device(pdev);
  926. if (rc == -EIO)
  927. return rc;
  928. /* now probe and enable the device */
  929. return i7300_probe1(pdev, id->driver_data);
  930. }
  931. /*
  932. * i7300_remove_one destructor for one instance of device
  933. *
  934. */
  935. static void __devexit i7300_remove_one(struct pci_dev *pdev)
  936. {
  937. struct mem_ctl_info *mci;
  938. char *tmp;
  939. debugf0(__FILE__ ": %s()\n", __func__);
  940. if (i7300_pci)
  941. edac_pci_release_generic_ctl(i7300_pci);
  942. mci = edac_mc_del_mc(&pdev->dev);
  943. if (!mci)
  944. return;
  945. tmp = ((struct i7300_pvt *)mci->pvt_info)->tmp_prt_buffer;
  946. /* retrieve references to resources, and free those resources */
  947. i7300_put_devices(mci);
  948. kfree(tmp);
  949. edac_mc_free(mci);
  950. }
  951. /*
  952. * pci_device_id table for which devices we are looking for
  953. *
  954. * The "E500P" device is the first device supported.
  955. */
  956. static const struct pci_device_id i7300_pci_tbl[] __devinitdata = {
  957. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR)},
  958. {0,} /* 0 terminated list. */
  959. };
  960. MODULE_DEVICE_TABLE(pci, i7300_pci_tbl);
  961. /*
  962. * i7300_driver pci_driver structure for this module
  963. *
  964. */
  965. static struct pci_driver i7300_driver = {
  966. .name = "i7300_edac",
  967. .probe = i7300_init_one,
  968. .remove = __devexit_p(i7300_remove_one),
  969. .id_table = i7300_pci_tbl,
  970. };
  971. /*
  972. * i7300_init Module entry function
  973. * Try to initialize this module for its devices
  974. */
  975. static int __init i7300_init(void)
  976. {
  977. int pci_rc;
  978. debugf2("MC: " __FILE__ ": %s()\n", __func__);
  979. /* Ensure that the OPSTATE is set correctly for POLL or NMI */
  980. opstate_init();
  981. pci_rc = pci_register_driver(&i7300_driver);
  982. return (pci_rc < 0) ? pci_rc : 0;
  983. }
  984. /*
  985. * i7300_exit() Module exit function
  986. * Unregister the driver
  987. */
  988. static void __exit i7300_exit(void)
  989. {
  990. debugf2("MC: " __FILE__ ": %s()\n", __func__);
  991. pci_unregister_driver(&i7300_driver);
  992. }
  993. module_init(i7300_init);
  994. module_exit(i7300_exit);
  995. MODULE_LICENSE("GPL");
  996. MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
  997. MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
  998. MODULE_DESCRIPTION("MC Driver for Intel I7300 memory controllers - "
  999. I7300_REVISION);
  1000. module_param(edac_op_state, int, 0444);
  1001. MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");