osdep.h 6.2 KB

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  1. /*****************************************************************************
  2. * *
  3. * File: osdep.h *
  4. * $Revision: 1.9 $ *
  5. * $Date: 2005/03/23 07:41:27 $ *
  6. * Description: *
  7. * part of the Chelsio 10Gb Ethernet Driver. *
  8. * *
  9. * This program is free software; you can redistribute it and/or modify *
  10. * it under the terms of the GNU General Public License, version 2, as *
  11. * published by the Free Software Foundation. *
  12. * *
  13. * You should have received a copy of the GNU General Public License along *
  14. * with this program; if not, write to the Free Software Foundation, Inc., *
  15. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  16. * *
  17. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
  18. * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
  19. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
  20. * *
  21. * http://www.chelsio.com *
  22. * *
  23. * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
  24. * All rights reserved. *
  25. * *
  26. * Maintainers: maintainers@chelsio.com *
  27. * *
  28. * Authors: Dimitrios Michailidis <dm@chelsio.com> *
  29. * Tina Yang <tainay@chelsio.com> *
  30. * Felix Marti <felix@chelsio.com> *
  31. * Scott Bardone <sbardone@chelsio.com> *
  32. * Kurt Ottaway <kottaway@chelsio.com> *
  33. * Frank DiMambro <frank@chelsio.com> *
  34. * *
  35. * History: *
  36. * *
  37. ****************************************************************************/
  38. #ifndef __CHELSIO_OSDEP_H
  39. #define __CHELSIO_OSDEP_H
  40. #include <linux/version.h>
  41. #include <linux/module.h>
  42. #include <linux/config.h>
  43. #include <linux/types.h>
  44. #include <linux/delay.h>
  45. #include <linux/pci.h>
  46. #include <linux/ethtool.h>
  47. #include <linux/mii.h>
  48. #include <linux/crc32.h>
  49. #include <linux/init.h>
  50. #include <asm/io.h>
  51. #include "cxgb2.h"
  52. #define DRV_NAME "cxgb"
  53. #define PFX DRV_NAME ": "
  54. #define CH_ERR(fmt, ...) printk(KERN_ERR PFX fmt, ## __VA_ARGS__)
  55. #define CH_WARN(fmt, ...) printk(KERN_WARNING PFX fmt, ## __VA_ARGS__)
  56. #define CH_ALERT(fmt, ...) printk(KERN_ALERT PFX fmt, ## __VA_ARGS__)
  57. /*
  58. * More powerful macro that selectively prints messages based on msg_enable.
  59. * For info and debugging messages.
  60. */
  61. #define CH_MSG(adapter, level, category, fmt, ...) do { \
  62. if ((adapter)->msg_enable & NETIF_MSG_##category) \
  63. printk(KERN_##level PFX "%s: " fmt, (adapter)->name, \
  64. ## __VA_ARGS__); \
  65. } while (0)
  66. #ifdef DEBUG
  67. # define CH_DBG(adapter, category, fmt, ...) \
  68. CH_MSG(adapter, DEBUG, category, fmt, ## __VA_ARGS__)
  69. #else
  70. # define CH_DBG(fmt, ...)
  71. #endif
  72. /* Additional NETIF_MSG_* categories */
  73. #define NETIF_MSG_MMIO 0x8000000
  74. #define CH_DEVICE(devid, ssid, idx) \
  75. { PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, ssid, 0, 0, idx }
  76. #define SUPPORTED_PAUSE (1 << 13)
  77. #define SUPPORTED_LOOPBACK (1 << 15)
  78. #define ADVERTISED_PAUSE (1 << 13)
  79. #define ADVERTISED_ASYM_PAUSE (1 << 14)
  80. /*
  81. * Now that we have included the driver's main data structure,
  82. * we typedef it to something the rest of the system understands.
  83. */
  84. typedef struct adapter adapter_t;
  85. #define TPI_LOCK(adapter) spin_lock(&(adapter)->tpi_lock)
  86. #define TPI_UNLOCK(adapter) spin_unlock(&(adapter)->tpi_lock)
  87. void t1_elmer0_ext_intr(adapter_t *adapter);
  88. void t1_link_changed(adapter_t *adapter, int port_id, int link_status,
  89. int speed, int duplex, int fc);
  90. static inline u16 t1_read_reg_2(adapter_t *adapter, u32 reg_addr)
  91. {
  92. u16 val = readw(adapter->regs + reg_addr);
  93. CH_DBG(adapter, MMIO, "read register 0x%x value 0x%x\n", reg_addr,
  94. val);
  95. return val;
  96. }
  97. static inline void t1_write_reg_2(adapter_t *adapter, u32 reg_addr, u16 val)
  98. {
  99. CH_DBG(adapter, MMIO, "setting register 0x%x to 0x%x\n", reg_addr,
  100. val);
  101. writew(val, adapter->regs + reg_addr);
  102. }
  103. static inline u32 t1_read_reg_4(adapter_t *adapter, u32 reg_addr)
  104. {
  105. u32 val = readl(adapter->regs + reg_addr);
  106. CH_DBG(adapter, MMIO, "read register 0x%x value 0x%x\n", reg_addr,
  107. val);
  108. return val;
  109. }
  110. static inline void t1_write_reg_4(adapter_t *adapter, u32 reg_addr, u32 val)
  111. {
  112. CH_DBG(adapter, MMIO, "setting register 0x%x to 0x%x\n", reg_addr,
  113. val);
  114. writel(val, adapter->regs + reg_addr);
  115. }
  116. static inline const char *port_name(adapter_t *adapter, int port_idx)
  117. {
  118. return adapter->port[port_idx].dev->name;
  119. }
  120. static inline void t1_set_hw_addr(adapter_t *adapter, int port_idx,
  121. u8 hw_addr[])
  122. {
  123. memcpy(adapter->port[port_idx].dev->dev_addr, hw_addr, ETH_ALEN);
  124. }
  125. struct t1_rx_mode {
  126. struct net_device *dev;
  127. u32 idx;
  128. struct dev_mc_list *list;
  129. };
  130. #define t1_rx_mode_promisc(rm) (rm->dev->flags & IFF_PROMISC)
  131. #define t1_rx_mode_allmulti(rm) (rm->dev->flags & IFF_ALLMULTI)
  132. #define t1_rx_mode_mc_cnt(rm) (rm->dev->mc_count)
  133. static inline u8 *t1_get_next_mcaddr(struct t1_rx_mode *rm)
  134. {
  135. u8 *addr = 0;
  136. if (rm->idx++ < rm->dev->mc_count) {
  137. addr = rm->list->dmi_addr;
  138. rm->list = rm->list->next;
  139. }
  140. return addr;
  141. }
  142. #endif