jmb38x_ms.c 22 KB

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  1. /*
  2. * jmb38x_ms.c - JMicron jmb38x MemoryStick card reader
  3. *
  4. * Copyright (C) 2008 Alex Dubov <oakad@yahoo.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. */
  11. #include <linux/spinlock.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/pci.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/delay.h>
  16. #include <linux/highmem.h>
  17. #include <linux/memstick.h>
  18. #define DRIVER_NAME "jmb38x_ms"
  19. static int no_dma;
  20. module_param(no_dma, bool, 0644);
  21. enum {
  22. DMA_ADDRESS = 0x00,
  23. BLOCK = 0x04,
  24. DMA_CONTROL = 0x08,
  25. TPC_P0 = 0x0c,
  26. TPC_P1 = 0x10,
  27. TPC = 0x14,
  28. HOST_CONTROL = 0x18,
  29. DATA = 0x1c,
  30. STATUS = 0x20,
  31. INT_STATUS = 0x24,
  32. INT_STATUS_ENABLE = 0x28,
  33. INT_SIGNAL_ENABLE = 0x2c,
  34. TIMER = 0x30,
  35. TIMER_CONTROL = 0x34,
  36. PAD_OUTPUT_ENABLE = 0x38,
  37. PAD_PU_PD = 0x3c,
  38. CLOCK_DELAY = 0x40,
  39. ADMA_ADDRESS = 0x44,
  40. CLOCK_CONTROL = 0x48,
  41. LED_CONTROL = 0x4c,
  42. VERSION = 0x50
  43. };
  44. struct jmb38x_ms_host {
  45. struct jmb38x_ms *chip;
  46. void __iomem *addr;
  47. spinlock_t lock;
  48. int id;
  49. char host_id[DEVICE_ID_SIZE];
  50. int irq;
  51. unsigned int block_pos;
  52. unsigned long timeout_jiffies;
  53. struct timer_list timer;
  54. struct memstick_request *req;
  55. unsigned char eject:1,
  56. use_dma:1;
  57. unsigned char cmd_flags;
  58. unsigned char io_pos;
  59. unsigned int io_word[2];
  60. };
  61. struct jmb38x_ms {
  62. struct pci_dev *pdev;
  63. int host_cnt;
  64. struct memstick_host *hosts[];
  65. };
  66. #define BLOCK_COUNT_MASK 0xffff0000
  67. #define BLOCK_SIZE_MASK 0x00000fff
  68. #define DMA_CONTROL_ENABLE 0x00000001
  69. #define TPC_DATA_SEL 0x00008000
  70. #define TPC_DIR 0x00004000
  71. #define TPC_WAIT_INT 0x00002000
  72. #define TPC_GET_INT 0x00000800
  73. #define TPC_CODE_SZ_MASK 0x00000700
  74. #define TPC_DATA_SZ_MASK 0x00000007
  75. #define HOST_CONTROL_RESET_REQ 0x00008000
  76. #define HOST_CONTROL_REI 0x00004000
  77. #define HOST_CONTROL_LED 0x00000400
  78. #define HOST_CONTROL_FAST_CLK 0x00000200
  79. #define HOST_CONTROL_RESET 0x00000100
  80. #define HOST_CONTROL_POWER_EN 0x00000080
  81. #define HOST_CONTROL_CLOCK_EN 0x00000040
  82. #define HOST_CONTROL_IF_SHIFT 4
  83. #define HOST_CONTROL_IF_SERIAL 0x0
  84. #define HOST_CONTROL_IF_PAR4 0x1
  85. #define HOST_CONTROL_IF_PAR8 0x3
  86. #define STATUS_HAS_MEDIA 0x00000400
  87. #define STATUS_FIFO_EMPTY 0x00000200
  88. #define STATUS_FIFO_FULL 0x00000100
  89. #define INT_STATUS_TPC_ERR 0x00080000
  90. #define INT_STATUS_CRC_ERR 0x00040000
  91. #define INT_STATUS_TIMER_TO 0x00020000
  92. #define INT_STATUS_HSK_TO 0x00010000
  93. #define INT_STATUS_ANY_ERR 0x00008000
  94. #define INT_STATUS_FIFO_WRDY 0x00000080
  95. #define INT_STATUS_FIFO_RRDY 0x00000040
  96. #define INT_STATUS_MEDIA_OUT 0x00000010
  97. #define INT_STATUS_MEDIA_IN 0x00000008
  98. #define INT_STATUS_DMA_BOUNDARY 0x00000004
  99. #define INT_STATUS_EOTRAN 0x00000002
  100. #define INT_STATUS_EOTPC 0x00000001
  101. #define INT_STATUS_ALL 0x000f801f
  102. #define PAD_OUTPUT_ENABLE_MS 0x0F3F
  103. #define PAD_PU_PD_OFF 0x7FFF0000
  104. #define PAD_PU_PD_ON_MS_SOCK0 0x5f8f0000
  105. #define PAD_PU_PD_ON_MS_SOCK1 0x0f0f0000
  106. enum {
  107. CMD_READY = 0x01,
  108. FIFO_READY = 0x02,
  109. REG_DATA = 0x04,
  110. AUTO_GET_INT = 0x08
  111. };
  112. static unsigned int jmb38x_ms_read_data(struct jmb38x_ms_host *host,
  113. unsigned char *buf, unsigned int length)
  114. {
  115. unsigned int off = 0;
  116. while (host->io_pos && length) {
  117. buf[off++] = host->io_word[0] & 0xff;
  118. host->io_word[0] >>= 8;
  119. length--;
  120. host->io_pos--;
  121. }
  122. if (!length)
  123. return off;
  124. while (!(STATUS_FIFO_EMPTY & readl(host->addr + STATUS))) {
  125. if (length < 4)
  126. break;
  127. *(unsigned int *)(buf + off) = __raw_readl(host->addr + DATA);
  128. length -= 4;
  129. off += 4;
  130. }
  131. if (length
  132. && !(STATUS_FIFO_EMPTY & readl(host->addr + STATUS))) {
  133. host->io_word[0] = readl(host->addr + DATA);
  134. for (host->io_pos = 4; host->io_pos; --host->io_pos) {
  135. buf[off++] = host->io_word[0] & 0xff;
  136. host->io_word[0] >>= 8;
  137. length--;
  138. if (!length)
  139. break;
  140. }
  141. }
  142. return off;
  143. }
  144. static unsigned int jmb38x_ms_read_reg_data(struct jmb38x_ms_host *host,
  145. unsigned char *buf,
  146. unsigned int length)
  147. {
  148. unsigned int off = 0;
  149. while (host->io_pos > 4 && length) {
  150. buf[off++] = host->io_word[0] & 0xff;
  151. host->io_word[0] >>= 8;
  152. length--;
  153. host->io_pos--;
  154. }
  155. if (!length)
  156. return off;
  157. while (host->io_pos && length) {
  158. buf[off++] = host->io_word[1] & 0xff;
  159. host->io_word[1] >>= 8;
  160. length--;
  161. host->io_pos--;
  162. }
  163. return off;
  164. }
  165. static unsigned int jmb38x_ms_write_data(struct jmb38x_ms_host *host,
  166. unsigned char *buf,
  167. unsigned int length)
  168. {
  169. unsigned int off = 0;
  170. if (host->io_pos) {
  171. while (host->io_pos < 4 && length) {
  172. host->io_word[0] |= buf[off++] << (host->io_pos * 8);
  173. host->io_pos++;
  174. length--;
  175. }
  176. }
  177. if (host->io_pos == 4
  178. && !(STATUS_FIFO_FULL & readl(host->addr + STATUS))) {
  179. writel(host->io_word[0], host->addr + DATA);
  180. host->io_pos = 0;
  181. host->io_word[0] = 0;
  182. } else if (host->io_pos) {
  183. return off;
  184. }
  185. if (!length)
  186. return off;
  187. while (!(STATUS_FIFO_FULL & readl(host->addr + STATUS))) {
  188. if (length < 4)
  189. break;
  190. __raw_writel(*(unsigned int *)(buf + off),
  191. host->addr + DATA);
  192. length -= 4;
  193. off += 4;
  194. }
  195. switch (length) {
  196. case 3:
  197. host->io_word[0] |= buf[off + 2] << 16;
  198. host->io_pos++;
  199. case 2:
  200. host->io_word[0] |= buf[off + 1] << 8;
  201. host->io_pos++;
  202. case 1:
  203. host->io_word[0] |= buf[off];
  204. host->io_pos++;
  205. }
  206. off += host->io_pos;
  207. return off;
  208. }
  209. static unsigned int jmb38x_ms_write_reg_data(struct jmb38x_ms_host *host,
  210. unsigned char *buf,
  211. unsigned int length)
  212. {
  213. unsigned int off = 0;
  214. while (host->io_pos < 4 && length) {
  215. host->io_word[0] &= ~(0xff << (host->io_pos * 8));
  216. host->io_word[0] |= buf[off++] << (host->io_pos * 8);
  217. host->io_pos++;
  218. length--;
  219. }
  220. if (!length)
  221. return off;
  222. while (host->io_pos < 8 && length) {
  223. host->io_word[1] &= ~(0xff << (host->io_pos * 8));
  224. host->io_word[1] |= buf[off++] << (host->io_pos * 8);
  225. host->io_pos++;
  226. length--;
  227. }
  228. return off;
  229. }
  230. static int jmb38x_ms_transfer_data(struct jmb38x_ms_host *host)
  231. {
  232. unsigned int length;
  233. unsigned int off;
  234. unsigned int t_size, p_cnt;
  235. unsigned char *buf;
  236. struct page *pg;
  237. unsigned long flags = 0;
  238. if (host->req->long_data) {
  239. length = host->req->sg.length - host->block_pos;
  240. off = host->req->sg.offset + host->block_pos;
  241. } else {
  242. length = host->req->data_len - host->block_pos;
  243. off = 0;
  244. }
  245. while (length) {
  246. unsigned int uninitialized_var(p_off);
  247. if (host->req->long_data) {
  248. pg = nth_page(sg_page(&host->req->sg),
  249. off >> PAGE_SHIFT);
  250. p_off = offset_in_page(off);
  251. p_cnt = PAGE_SIZE - p_off;
  252. p_cnt = min(p_cnt, length);
  253. local_irq_save(flags);
  254. buf = kmap_atomic(pg, KM_BIO_SRC_IRQ) + p_off;
  255. } else {
  256. buf = host->req->data + host->block_pos;
  257. p_cnt = host->req->data_len - host->block_pos;
  258. }
  259. if (host->req->data_dir == WRITE)
  260. t_size = !(host->cmd_flags & REG_DATA)
  261. ? jmb38x_ms_write_data(host, buf, p_cnt)
  262. : jmb38x_ms_write_reg_data(host, buf, p_cnt);
  263. else
  264. t_size = !(host->cmd_flags & REG_DATA)
  265. ? jmb38x_ms_read_data(host, buf, p_cnt)
  266. : jmb38x_ms_read_reg_data(host, buf, p_cnt);
  267. if (host->req->long_data) {
  268. kunmap_atomic(buf - p_off, KM_BIO_SRC_IRQ);
  269. local_irq_restore(flags);
  270. }
  271. if (!t_size)
  272. break;
  273. host->block_pos += t_size;
  274. length -= t_size;
  275. off += t_size;
  276. }
  277. if (!length && host->req->data_dir == WRITE) {
  278. if (host->cmd_flags & REG_DATA) {
  279. writel(host->io_word[0], host->addr + TPC_P0);
  280. writel(host->io_word[1], host->addr + TPC_P1);
  281. } else if (host->io_pos) {
  282. writel(host->io_word[0], host->addr + DATA);
  283. }
  284. }
  285. return length;
  286. }
  287. static int jmb38x_ms_issue_cmd(struct memstick_host *msh)
  288. {
  289. struct jmb38x_ms_host *host = memstick_priv(msh);
  290. unsigned char *data;
  291. unsigned int data_len, cmd, t_val;
  292. if (!(STATUS_HAS_MEDIA & readl(host->addr + STATUS))) {
  293. dev_dbg(msh->cdev.dev, "no media status\n");
  294. host->req->error = -ETIME;
  295. return host->req->error;
  296. }
  297. dev_dbg(msh->cdev.dev, "control %08x\n",
  298. readl(host->addr + HOST_CONTROL));
  299. dev_dbg(msh->cdev.dev, "status %08x\n", readl(host->addr + INT_STATUS));
  300. dev_dbg(msh->cdev.dev, "hstatus %08x\n", readl(host->addr + STATUS));
  301. host->cmd_flags = 0;
  302. host->block_pos = 0;
  303. host->io_pos = 0;
  304. host->io_word[0] = 0;
  305. host->io_word[1] = 0;
  306. cmd = host->req->tpc << 16;
  307. cmd |= TPC_DATA_SEL;
  308. if (host->req->data_dir == READ)
  309. cmd |= TPC_DIR;
  310. if (host->req->need_card_int)
  311. cmd |= TPC_WAIT_INT;
  312. if (host->req->get_int_reg)
  313. cmd |= TPC_GET_INT;
  314. data = host->req->data;
  315. host->use_dma = !no_dma;
  316. if (host->req->long_data) {
  317. data_len = host->req->sg.length;
  318. } else {
  319. data_len = host->req->data_len;
  320. host->use_dma = 0;
  321. }
  322. if (data_len <= 8) {
  323. cmd &= ~(TPC_DATA_SEL | 0xf);
  324. host->cmd_flags |= REG_DATA;
  325. cmd |= data_len & 0xf;
  326. host->use_dma = 0;
  327. }
  328. if (host->use_dma) {
  329. if (1 != pci_map_sg(host->chip->pdev, &host->req->sg, 1,
  330. host->req->data_dir == READ
  331. ? PCI_DMA_FROMDEVICE
  332. : PCI_DMA_TODEVICE)) {
  333. host->req->error = -ENOMEM;
  334. return host->req->error;
  335. }
  336. data_len = sg_dma_len(&host->req->sg);
  337. writel(sg_dma_address(&host->req->sg),
  338. host->addr + DMA_ADDRESS);
  339. writel(((1 << 16) & BLOCK_COUNT_MASK)
  340. | (data_len & BLOCK_SIZE_MASK),
  341. host->addr + BLOCK);
  342. writel(DMA_CONTROL_ENABLE, host->addr + DMA_CONTROL);
  343. } else if (!(host->cmd_flags & REG_DATA)) {
  344. writel(((1 << 16) & BLOCK_COUNT_MASK)
  345. | (data_len & BLOCK_SIZE_MASK),
  346. host->addr + BLOCK);
  347. t_val = readl(host->addr + INT_STATUS_ENABLE);
  348. t_val |= host->req->data_dir == READ
  349. ? INT_STATUS_FIFO_RRDY
  350. : INT_STATUS_FIFO_WRDY;
  351. writel(t_val, host->addr + INT_STATUS_ENABLE);
  352. writel(t_val, host->addr + INT_SIGNAL_ENABLE);
  353. } else {
  354. cmd &= ~(TPC_DATA_SEL | 0xf);
  355. host->cmd_flags |= REG_DATA;
  356. cmd |= data_len & 0xf;
  357. if (host->req->data_dir == WRITE) {
  358. jmb38x_ms_transfer_data(host);
  359. writel(host->io_word[0], host->addr + TPC_P0);
  360. writel(host->io_word[1], host->addr + TPC_P1);
  361. }
  362. }
  363. mod_timer(&host->timer, jiffies + host->timeout_jiffies);
  364. writel(HOST_CONTROL_LED | readl(host->addr + HOST_CONTROL),
  365. host->addr + HOST_CONTROL);
  366. host->req->error = 0;
  367. writel(cmd, host->addr + TPC);
  368. dev_dbg(msh->cdev.dev, "executing TPC %08x, len %x\n", cmd, data_len);
  369. return 0;
  370. }
  371. static void jmb38x_ms_complete_cmd(struct memstick_host *msh, int last)
  372. {
  373. struct jmb38x_ms_host *host = memstick_priv(msh);
  374. unsigned int t_val = 0;
  375. int rc;
  376. del_timer(&host->timer);
  377. dev_dbg(msh->cdev.dev, "c control %08x\n",
  378. readl(host->addr + HOST_CONTROL));
  379. dev_dbg(msh->cdev.dev, "c status %08x\n",
  380. readl(host->addr + INT_STATUS));
  381. dev_dbg(msh->cdev.dev, "c hstatus %08x\n", readl(host->addr + STATUS));
  382. if (host->req->get_int_reg) {
  383. t_val = readl(host->addr + TPC_P0);
  384. host->req->int_reg = (t_val & 0xff);
  385. }
  386. if (host->use_dma) {
  387. writel(0, host->addr + DMA_CONTROL);
  388. pci_unmap_sg(host->chip->pdev, &host->req->sg, 1,
  389. host->req->data_dir == READ
  390. ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE);
  391. } else {
  392. t_val = readl(host->addr + INT_STATUS_ENABLE);
  393. if (host->req->data_dir == READ)
  394. t_val &= ~INT_STATUS_FIFO_RRDY;
  395. else
  396. t_val &= ~INT_STATUS_FIFO_WRDY;
  397. writel(t_val, host->addr + INT_STATUS_ENABLE);
  398. writel(t_val, host->addr + INT_SIGNAL_ENABLE);
  399. }
  400. writel((~HOST_CONTROL_LED) & readl(host->addr + HOST_CONTROL),
  401. host->addr + HOST_CONTROL);
  402. if (!last) {
  403. do {
  404. rc = memstick_next_req(msh, &host->req);
  405. } while (!rc && jmb38x_ms_issue_cmd(msh));
  406. } else {
  407. do {
  408. rc = memstick_next_req(msh, &host->req);
  409. if (!rc)
  410. host->req->error = -ETIME;
  411. } while (!rc);
  412. }
  413. }
  414. static irqreturn_t jmb38x_ms_isr(int irq, void *dev_id)
  415. {
  416. struct memstick_host *msh = dev_id;
  417. struct jmb38x_ms_host *host = memstick_priv(msh);
  418. unsigned int irq_status;
  419. spin_lock(&host->lock);
  420. irq_status = readl(host->addr + INT_STATUS);
  421. dev_dbg(&host->chip->pdev->dev, "irq_status = %08x\n", irq_status);
  422. if (irq_status == 0 || irq_status == (~0)) {
  423. spin_unlock(&host->lock);
  424. return IRQ_NONE;
  425. }
  426. if (host->req) {
  427. if (irq_status & INT_STATUS_ANY_ERR) {
  428. if (irq_status & INT_STATUS_CRC_ERR)
  429. host->req->error = -EILSEQ;
  430. else
  431. host->req->error = -ETIME;
  432. } else {
  433. if (host->use_dma) {
  434. if (irq_status & INT_STATUS_EOTRAN)
  435. host->cmd_flags |= FIFO_READY;
  436. } else {
  437. if (irq_status & (INT_STATUS_FIFO_RRDY
  438. | INT_STATUS_FIFO_WRDY))
  439. jmb38x_ms_transfer_data(host);
  440. if (irq_status & INT_STATUS_EOTRAN) {
  441. jmb38x_ms_transfer_data(host);
  442. host->cmd_flags |= FIFO_READY;
  443. }
  444. }
  445. if (irq_status & INT_STATUS_EOTPC) {
  446. host->cmd_flags |= CMD_READY;
  447. if (host->cmd_flags & REG_DATA) {
  448. if (host->req->data_dir == READ) {
  449. host->io_word[0]
  450. = readl(host->addr
  451. + TPC_P0);
  452. host->io_word[1]
  453. = readl(host->addr
  454. + TPC_P1);
  455. host->io_pos = 8;
  456. jmb38x_ms_transfer_data(host);
  457. }
  458. host->cmd_flags |= FIFO_READY;
  459. }
  460. }
  461. }
  462. }
  463. if (irq_status & (INT_STATUS_MEDIA_IN | INT_STATUS_MEDIA_OUT)) {
  464. dev_dbg(&host->chip->pdev->dev, "media changed\n");
  465. memstick_detect_change(msh);
  466. }
  467. writel(irq_status, host->addr + INT_STATUS);
  468. if (host->req
  469. && (((host->cmd_flags & CMD_READY)
  470. && (host->cmd_flags & FIFO_READY))
  471. || host->req->error))
  472. jmb38x_ms_complete_cmd(msh, 0);
  473. spin_unlock(&host->lock);
  474. return IRQ_HANDLED;
  475. }
  476. static void jmb38x_ms_abort(unsigned long data)
  477. {
  478. struct memstick_host *msh = (struct memstick_host *)data;
  479. struct jmb38x_ms_host *host = memstick_priv(msh);
  480. unsigned long flags;
  481. dev_dbg(&host->chip->pdev->dev, "abort\n");
  482. spin_lock_irqsave(&host->lock, flags);
  483. if (host->req) {
  484. host->req->error = -ETIME;
  485. jmb38x_ms_complete_cmd(msh, 0);
  486. }
  487. spin_unlock_irqrestore(&host->lock, flags);
  488. }
  489. static void jmb38x_ms_request(struct memstick_host *msh)
  490. {
  491. struct jmb38x_ms_host *host = memstick_priv(msh);
  492. unsigned long flags;
  493. int rc;
  494. spin_lock_irqsave(&host->lock, flags);
  495. if (host->req) {
  496. spin_unlock_irqrestore(&host->lock, flags);
  497. BUG();
  498. return;
  499. }
  500. do {
  501. rc = memstick_next_req(msh, &host->req);
  502. } while (!rc && jmb38x_ms_issue_cmd(msh));
  503. spin_unlock_irqrestore(&host->lock, flags);
  504. }
  505. static void jmb38x_ms_reset(struct jmb38x_ms_host *host)
  506. {
  507. unsigned int host_ctl = readl(host->addr + HOST_CONTROL);
  508. writel(host_ctl | HOST_CONTROL_RESET_REQ | HOST_CONTROL_RESET,
  509. host->addr + HOST_CONTROL);
  510. while (HOST_CONTROL_RESET_REQ
  511. & (host_ctl = readl(host->addr + HOST_CONTROL))) {
  512. ndelay(100);
  513. dev_dbg(&host->chip->pdev->dev, "reset\n");
  514. }
  515. writel(INT_STATUS_ALL, host->addr + INT_STATUS_ENABLE);
  516. writel(INT_STATUS_ALL, host->addr + INT_SIGNAL_ENABLE);
  517. dev_dbg(&host->chip->pdev->dev, "reset\n");
  518. }
  519. static void jmb38x_ms_set_param(struct memstick_host *msh,
  520. enum memstick_param param,
  521. int value)
  522. {
  523. struct jmb38x_ms_host *host = memstick_priv(msh);
  524. unsigned int host_ctl;
  525. unsigned long flags;
  526. spin_lock_irqsave(&host->lock, flags);
  527. switch (param) {
  528. case MEMSTICK_POWER:
  529. if (value == MEMSTICK_POWER_ON) {
  530. jmb38x_ms_reset(host);
  531. writel(host->id ? PAD_PU_PD_ON_MS_SOCK1
  532. : PAD_PU_PD_ON_MS_SOCK0,
  533. host->addr + PAD_PU_PD);
  534. writel(PAD_OUTPUT_ENABLE_MS,
  535. host->addr + PAD_OUTPUT_ENABLE);
  536. host_ctl = readl(host->addr + HOST_CONTROL);
  537. host_ctl |= 7;
  538. writel(host_ctl | (HOST_CONTROL_POWER_EN
  539. | HOST_CONTROL_CLOCK_EN),
  540. host->addr + HOST_CONTROL);
  541. dev_dbg(&host->chip->pdev->dev, "power on\n");
  542. } else if (value == MEMSTICK_POWER_OFF) {
  543. writel(readl(host->addr + HOST_CONTROL)
  544. & ~(HOST_CONTROL_POWER_EN
  545. | HOST_CONTROL_CLOCK_EN),
  546. host->addr + HOST_CONTROL);
  547. writel(0, host->addr + PAD_OUTPUT_ENABLE);
  548. writel(PAD_PU_PD_OFF, host->addr + PAD_PU_PD);
  549. dev_dbg(&host->chip->pdev->dev, "power off\n");
  550. }
  551. break;
  552. case MEMSTICK_INTERFACE:
  553. /* jmb38x_ms_reset(host); */
  554. host_ctl = readl(host->addr + HOST_CONTROL);
  555. host_ctl &= ~(3 << HOST_CONTROL_IF_SHIFT);
  556. /* host_ctl |= 7; */
  557. if (value == MEMSTICK_SERIAL) {
  558. host_ctl &= ~HOST_CONTROL_FAST_CLK;
  559. host_ctl |= HOST_CONTROL_IF_SERIAL
  560. << HOST_CONTROL_IF_SHIFT;
  561. host_ctl |= HOST_CONTROL_REI;
  562. writel(0, host->addr + CLOCK_DELAY);
  563. } else if (value == MEMSTICK_PAR4) {
  564. host_ctl |= HOST_CONTROL_FAST_CLK;
  565. host_ctl |= HOST_CONTROL_IF_PAR4
  566. << HOST_CONTROL_IF_SHIFT;
  567. host_ctl &= ~HOST_CONTROL_REI;
  568. writel(4, host->addr + CLOCK_DELAY);
  569. } else if (value == MEMSTICK_PAR8) {
  570. host_ctl |= HOST_CONTROL_FAST_CLK;
  571. host_ctl |= HOST_CONTROL_IF_PAR8
  572. << HOST_CONTROL_IF_SHIFT;
  573. host_ctl &= ~HOST_CONTROL_REI;
  574. writel(4, host->addr + CLOCK_DELAY);
  575. }
  576. writel(host_ctl, host->addr + HOST_CONTROL);
  577. break;
  578. };
  579. spin_unlock_irqrestore(&host->lock, flags);
  580. }
  581. #ifdef CONFIG_PM
  582. static int jmb38x_ms_suspend(struct pci_dev *dev, pm_message_t state)
  583. {
  584. struct jmb38x_ms *jm = pci_get_drvdata(dev);
  585. int cnt;
  586. for (cnt = 0; cnt < jm->host_cnt; ++cnt) {
  587. if (!jm->hosts[cnt])
  588. break;
  589. memstick_suspend_host(jm->hosts[cnt]);
  590. }
  591. pci_save_state(dev);
  592. pci_enable_wake(dev, pci_choose_state(dev, state), 0);
  593. pci_disable_device(dev);
  594. pci_set_power_state(dev, pci_choose_state(dev, state));
  595. return 0;
  596. }
  597. static int jmb38x_ms_resume(struct pci_dev *dev)
  598. {
  599. struct jmb38x_ms *jm = pci_get_drvdata(dev);
  600. int rc;
  601. pci_set_power_state(dev, PCI_D0);
  602. pci_restore_state(dev);
  603. rc = pci_enable_device(dev);
  604. if (rc)
  605. return rc;
  606. pci_set_master(dev);
  607. pci_read_config_dword(dev, 0xac, &rc);
  608. pci_write_config_dword(dev, 0xac, rc | 0x00470000);
  609. for (rc = 0; rc < jm->host_cnt; ++rc) {
  610. if (!jm->hosts[rc])
  611. break;
  612. memstick_resume_host(jm->hosts[rc]);
  613. memstick_detect_change(jm->hosts[rc]);
  614. }
  615. return 0;
  616. }
  617. #else
  618. #define jmb38x_ms_suspend NULL
  619. #define jmb38x_ms_resume NULL
  620. #endif /* CONFIG_PM */
  621. static int jmb38x_ms_count_slots(struct pci_dev *pdev)
  622. {
  623. int cnt, rc = 0;
  624. for (cnt = 0; cnt < PCI_ROM_RESOURCE; ++cnt) {
  625. if (!(IORESOURCE_MEM & pci_resource_flags(pdev, cnt)))
  626. break;
  627. if (256 != pci_resource_len(pdev, cnt))
  628. break;
  629. ++rc;
  630. }
  631. return rc;
  632. }
  633. static struct memstick_host *jmb38x_ms_alloc_host(struct jmb38x_ms *jm, int cnt)
  634. {
  635. struct memstick_host *msh;
  636. struct jmb38x_ms_host *host;
  637. msh = memstick_alloc_host(sizeof(struct jmb38x_ms_host),
  638. &jm->pdev->dev);
  639. if (!msh)
  640. return NULL;
  641. host = memstick_priv(msh);
  642. host->chip = jm;
  643. host->addr = ioremap(pci_resource_start(jm->pdev, cnt),
  644. pci_resource_len(jm->pdev, cnt));
  645. if (!host->addr)
  646. goto err_out_free;
  647. spin_lock_init(&host->lock);
  648. host->id = cnt;
  649. snprintf(host->host_id, DEVICE_ID_SIZE, DRIVER_NAME ":slot%d",
  650. host->id);
  651. host->irq = jm->pdev->irq;
  652. host->timeout_jiffies = msecs_to_jiffies(4000);
  653. msh->request = jmb38x_ms_request;
  654. msh->set_param = jmb38x_ms_set_param;
  655. /*
  656. msh->caps = MEMSTICK_CAP_AUTO_GET_INT | MEMSTICK_CAP_PAR4
  657. | MEMSTICK_CAP_PAR8;
  658. */
  659. msh->caps = MEMSTICK_CAP_PAR4 | MEMSTICK_CAP_PAR8;
  660. setup_timer(&host->timer, jmb38x_ms_abort, (unsigned long)msh);
  661. if (!request_irq(host->irq, jmb38x_ms_isr, IRQF_SHARED, host->host_id,
  662. msh))
  663. return msh;
  664. iounmap(host->addr);
  665. err_out_free:
  666. kfree(msh);
  667. return NULL;
  668. }
  669. static void jmb38x_ms_free_host(struct memstick_host *msh)
  670. {
  671. struct jmb38x_ms_host *host = memstick_priv(msh);
  672. free_irq(host->irq, msh);
  673. iounmap(host->addr);
  674. memstick_free_host(msh);
  675. }
  676. static int jmb38x_ms_probe(struct pci_dev *pdev,
  677. const struct pci_device_id *dev_id)
  678. {
  679. struct jmb38x_ms *jm;
  680. int pci_dev_busy = 0;
  681. int rc, cnt;
  682. rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  683. if (rc)
  684. return rc;
  685. rc = pci_enable_device(pdev);
  686. if (rc)
  687. return rc;
  688. pci_set_master(pdev);
  689. rc = pci_request_regions(pdev, DRIVER_NAME);
  690. if (rc) {
  691. pci_dev_busy = 1;
  692. goto err_out;
  693. }
  694. pci_read_config_dword(pdev, 0xac, &rc);
  695. pci_write_config_dword(pdev, 0xac, rc | 0x00470000);
  696. cnt = jmb38x_ms_count_slots(pdev);
  697. if (!cnt) {
  698. rc = -ENODEV;
  699. pci_dev_busy = 1;
  700. goto err_out;
  701. }
  702. jm = kzalloc(sizeof(struct jmb38x_ms)
  703. + cnt * sizeof(struct memstick_host *), GFP_KERNEL);
  704. if (!jm) {
  705. rc = -ENOMEM;
  706. goto err_out_int;
  707. }
  708. jm->pdev = pdev;
  709. jm->host_cnt = cnt;
  710. pci_set_drvdata(pdev, jm);
  711. for (cnt = 0; cnt < jm->host_cnt; ++cnt) {
  712. jm->hosts[cnt] = jmb38x_ms_alloc_host(jm, cnt);
  713. if (!jm->hosts[cnt])
  714. break;
  715. rc = memstick_add_host(jm->hosts[cnt]);
  716. if (rc) {
  717. jmb38x_ms_free_host(jm->hosts[cnt]);
  718. jm->hosts[cnt] = NULL;
  719. break;
  720. }
  721. }
  722. if (cnt)
  723. return 0;
  724. rc = -ENODEV;
  725. pci_set_drvdata(pdev, NULL);
  726. kfree(jm);
  727. err_out_int:
  728. pci_release_regions(pdev);
  729. err_out:
  730. if (!pci_dev_busy)
  731. pci_disable_device(pdev);
  732. return rc;
  733. }
  734. static void jmb38x_ms_remove(struct pci_dev *dev)
  735. {
  736. struct jmb38x_ms *jm = pci_get_drvdata(dev);
  737. struct jmb38x_ms_host *host;
  738. int cnt;
  739. unsigned long flags;
  740. for (cnt = 0; cnt < jm->host_cnt; ++cnt) {
  741. if (!jm->hosts[cnt])
  742. break;
  743. host = memstick_priv(jm->hosts[cnt]);
  744. writel(0, host->addr + INT_SIGNAL_ENABLE);
  745. writel(0, host->addr + INT_STATUS_ENABLE);
  746. mmiowb();
  747. dev_dbg(&jm->pdev->dev, "interrupts off\n");
  748. spin_lock_irqsave(&host->lock, flags);
  749. if (host->req) {
  750. host->req->error = -ETIME;
  751. jmb38x_ms_complete_cmd(jm->hosts[cnt], 1);
  752. }
  753. spin_unlock_irqrestore(&host->lock, flags);
  754. memstick_remove_host(jm->hosts[cnt]);
  755. dev_dbg(&jm->pdev->dev, "host removed\n");
  756. jmb38x_ms_free_host(jm->hosts[cnt]);
  757. }
  758. pci_set_drvdata(dev, NULL);
  759. pci_release_regions(dev);
  760. pci_disable_device(dev);
  761. kfree(jm);
  762. }
  763. static struct pci_device_id jmb38x_ms_id_tbl [] = {
  764. { PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_MS, PCI_ANY_ID,
  765. PCI_ANY_ID, 0, 0, 0 },
  766. { }
  767. };
  768. static struct pci_driver jmb38x_ms_driver = {
  769. .name = DRIVER_NAME,
  770. .id_table = jmb38x_ms_id_tbl,
  771. .probe = jmb38x_ms_probe,
  772. .remove = jmb38x_ms_remove,
  773. .suspend = jmb38x_ms_suspend,
  774. .resume = jmb38x_ms_resume
  775. };
  776. static int __init jmb38x_ms_init(void)
  777. {
  778. return pci_register_driver(&jmb38x_ms_driver);
  779. }
  780. static void __exit jmb38x_ms_exit(void)
  781. {
  782. pci_unregister_driver(&jmb38x_ms_driver);
  783. }
  784. MODULE_AUTHOR("Alex Dubov");
  785. MODULE_DESCRIPTION("JMicron jmb38x MemoryStick driver");
  786. MODULE_LICENSE("GPL");
  787. MODULE_DEVICE_TABLE(pci, jmb38x_ms_id_tbl);
  788. module_init(jmb38x_ms_init);
  789. module_exit(jmb38x_ms_exit);