i915_irq.c 40 KB

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  1. /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
  2. */
  3. /*
  4. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  5. * All Rights Reserved.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the
  9. * "Software"), to deal in the Software without restriction, including
  10. * without limitation the rights to use, copy, modify, merge, publish,
  11. * distribute, sub license, and/or sell copies of the Software, and to
  12. * permit persons to whom the Software is furnished to do so, subject to
  13. * the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the
  16. * next paragraph) shall be included in all copies or substantial portions
  17. * of the Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26. *
  27. */
  28. #include <linux/sysrq.h>
  29. #include <linux/slab.h>
  30. #include "drmP.h"
  31. #include "drm.h"
  32. #include "i915_drm.h"
  33. #include "i915_drv.h"
  34. #include "i915_trace.h"
  35. #include "intel_drv.h"
  36. #define MAX_NOPID ((u32)~0)
  37. /**
  38. * Interrupts that are always left unmasked.
  39. *
  40. * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  41. * we leave them always unmasked in IMR and then control enabling them through
  42. * PIPESTAT alone.
  43. */
  44. #define I915_INTERRUPT_ENABLE_FIX \
  45. (I915_ASLE_INTERRUPT | \
  46. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
  47. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
  48. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
  49. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
  50. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  51. /** Interrupts that we mask and unmask at runtime. */
  52. #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
  53. #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  54. PIPE_VBLANK_INTERRUPT_STATUS)
  55. #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  56. PIPE_VBLANK_INTERRUPT_ENABLE)
  57. #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
  58. DRM_I915_VBLANK_PIPE_B)
  59. void
  60. ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  61. {
  62. if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  63. dev_priv->gt_irq_mask_reg &= ~mask;
  64. I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  65. (void) I915_READ(GTIMR);
  66. }
  67. }
  68. void
  69. ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  70. {
  71. if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  72. dev_priv->gt_irq_mask_reg |= mask;
  73. I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  74. (void) I915_READ(GTIMR);
  75. }
  76. }
  77. /* For display hotplug interrupt */
  78. void
  79. ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  80. {
  81. if ((dev_priv->irq_mask_reg & mask) != 0) {
  82. dev_priv->irq_mask_reg &= ~mask;
  83. I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  84. (void) I915_READ(DEIMR);
  85. }
  86. }
  87. static inline void
  88. ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  89. {
  90. if ((dev_priv->irq_mask_reg & mask) != mask) {
  91. dev_priv->irq_mask_reg |= mask;
  92. I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  93. (void) I915_READ(DEIMR);
  94. }
  95. }
  96. void
  97. i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
  98. {
  99. if ((dev_priv->irq_mask_reg & mask) != 0) {
  100. dev_priv->irq_mask_reg &= ~mask;
  101. I915_WRITE(IMR, dev_priv->irq_mask_reg);
  102. (void) I915_READ(IMR);
  103. }
  104. }
  105. void
  106. i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
  107. {
  108. if ((dev_priv->irq_mask_reg & mask) != mask) {
  109. dev_priv->irq_mask_reg |= mask;
  110. I915_WRITE(IMR, dev_priv->irq_mask_reg);
  111. (void) I915_READ(IMR);
  112. }
  113. }
  114. static inline u32
  115. i915_pipestat(int pipe)
  116. {
  117. if (pipe == 0)
  118. return PIPEASTAT;
  119. if (pipe == 1)
  120. return PIPEBSTAT;
  121. BUG();
  122. }
  123. void
  124. i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  125. {
  126. if ((dev_priv->pipestat[pipe] & mask) != mask) {
  127. u32 reg = i915_pipestat(pipe);
  128. dev_priv->pipestat[pipe] |= mask;
  129. /* Enable the interrupt, clear any pending status */
  130. I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  131. (void) I915_READ(reg);
  132. }
  133. }
  134. void
  135. i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  136. {
  137. if ((dev_priv->pipestat[pipe] & mask) != 0) {
  138. u32 reg = i915_pipestat(pipe);
  139. dev_priv->pipestat[pipe] &= ~mask;
  140. I915_WRITE(reg, dev_priv->pipestat[pipe]);
  141. (void) I915_READ(reg);
  142. }
  143. }
  144. /**
  145. * intel_enable_asle - enable ASLE interrupt for OpRegion
  146. */
  147. void intel_enable_asle (struct drm_device *dev)
  148. {
  149. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  150. if (HAS_PCH_SPLIT(dev))
  151. ironlake_enable_display_irq(dev_priv, DE_GSE);
  152. else {
  153. i915_enable_pipestat(dev_priv, 1,
  154. I915_LEGACY_BLC_EVENT_ENABLE);
  155. if (IS_I965G(dev))
  156. i915_enable_pipestat(dev_priv, 0,
  157. I915_LEGACY_BLC_EVENT_ENABLE);
  158. }
  159. }
  160. /**
  161. * i915_pipe_enabled - check if a pipe is enabled
  162. * @dev: DRM device
  163. * @pipe: pipe to check
  164. *
  165. * Reading certain registers when the pipe is disabled can hang the chip.
  166. * Use this routine to make sure the PLL is running and the pipe is active
  167. * before reading such registers if unsure.
  168. */
  169. static int
  170. i915_pipe_enabled(struct drm_device *dev, int pipe)
  171. {
  172. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  173. unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
  174. if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
  175. return 1;
  176. return 0;
  177. }
  178. /* Called from drm generic code, passed a 'crtc', which
  179. * we use as a pipe index
  180. */
  181. u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
  182. {
  183. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  184. unsigned long high_frame;
  185. unsigned long low_frame;
  186. u32 high1, high2, low, count;
  187. high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
  188. low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
  189. if (!i915_pipe_enabled(dev, pipe)) {
  190. DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
  191. "pipe %d\n", pipe);
  192. return 0;
  193. }
  194. /*
  195. * High & low register fields aren't synchronized, so make sure
  196. * we get a low value that's stable across two reads of the high
  197. * register.
  198. */
  199. do {
  200. high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
  201. PIPE_FRAME_HIGH_SHIFT);
  202. low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
  203. PIPE_FRAME_LOW_SHIFT);
  204. high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
  205. PIPE_FRAME_HIGH_SHIFT);
  206. } while (high1 != high2);
  207. count = (high1 << 8) | low;
  208. return count;
  209. }
  210. u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
  211. {
  212. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  213. int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
  214. if (!i915_pipe_enabled(dev, pipe)) {
  215. DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
  216. "pipe %d\n", pipe);
  217. return 0;
  218. }
  219. return I915_READ(reg);
  220. }
  221. /*
  222. * Handle hotplug events outside the interrupt handler proper.
  223. */
  224. static void i915_hotplug_work_func(struct work_struct *work)
  225. {
  226. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  227. hotplug_work);
  228. struct drm_device *dev = dev_priv->dev;
  229. struct drm_mode_config *mode_config = &dev->mode_config;
  230. struct drm_encoder *encoder;
  231. if (mode_config->num_encoder) {
  232. list_for_each_entry(encoder, &mode_config->encoder_list, head) {
  233. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  234. if (intel_encoder->hot_plug)
  235. (*intel_encoder->hot_plug) (intel_encoder);
  236. }
  237. }
  238. /* Just fire off a uevent and let userspace tell us what to do */
  239. drm_helper_hpd_irq_event(dev);
  240. }
  241. static void i915_handle_rps_change(struct drm_device *dev)
  242. {
  243. drm_i915_private_t *dev_priv = dev->dev_private;
  244. u32 busy_up, busy_down, max_avg, min_avg;
  245. u16 rgvswctl;
  246. u8 new_delay = dev_priv->cur_delay;
  247. I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS) & ~MEMINT_EVAL_CHG);
  248. busy_up = I915_READ(RCPREVBSYTUPAVG);
  249. busy_down = I915_READ(RCPREVBSYTDNAVG);
  250. max_avg = I915_READ(RCBMAXAVG);
  251. min_avg = I915_READ(RCBMINAVG);
  252. /* Handle RCS change request from hw */
  253. if (busy_up > max_avg) {
  254. if (dev_priv->cur_delay != dev_priv->max_delay)
  255. new_delay = dev_priv->cur_delay - 1;
  256. if (new_delay < dev_priv->max_delay)
  257. new_delay = dev_priv->max_delay;
  258. } else if (busy_down < min_avg) {
  259. if (dev_priv->cur_delay != dev_priv->min_delay)
  260. new_delay = dev_priv->cur_delay + 1;
  261. if (new_delay > dev_priv->min_delay)
  262. new_delay = dev_priv->min_delay;
  263. }
  264. DRM_DEBUG("rps change requested: %d -> %d\n",
  265. dev_priv->cur_delay, new_delay);
  266. rgvswctl = I915_READ(MEMSWCTL);
  267. if (rgvswctl & MEMCTL_CMD_STS) {
  268. DRM_ERROR("gpu busy, RCS change rejected\n");
  269. return; /* still busy with another command */
  270. }
  271. /* Program the new state */
  272. rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
  273. (new_delay << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
  274. I915_WRITE(MEMSWCTL, rgvswctl);
  275. POSTING_READ(MEMSWCTL);
  276. rgvswctl |= MEMCTL_CMD_STS;
  277. I915_WRITE(MEMSWCTL, rgvswctl);
  278. dev_priv->cur_delay = new_delay;
  279. DRM_DEBUG("rps changed\n");
  280. return;
  281. }
  282. irqreturn_t ironlake_irq_handler(struct drm_device *dev)
  283. {
  284. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  285. int ret = IRQ_NONE;
  286. u32 de_iir, gt_iir, de_ier, pch_iir;
  287. struct drm_i915_master_private *master_priv;
  288. /* disable master interrupt before clearing iir */
  289. de_ier = I915_READ(DEIER);
  290. I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
  291. (void)I915_READ(DEIER);
  292. de_iir = I915_READ(DEIIR);
  293. gt_iir = I915_READ(GTIIR);
  294. pch_iir = I915_READ(SDEIIR);
  295. if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
  296. goto done;
  297. ret = IRQ_HANDLED;
  298. if (dev->primary->master) {
  299. master_priv = dev->primary->master->driver_priv;
  300. if (master_priv->sarea_priv)
  301. master_priv->sarea_priv->last_dispatch =
  302. READ_BREADCRUMB(dev_priv);
  303. }
  304. if (gt_iir & GT_PIPE_NOTIFY) {
  305. u32 seqno = i915_get_gem_seqno(dev);
  306. dev_priv->mm.irq_gem_seqno = seqno;
  307. trace_i915_gem_request_complete(dev, seqno);
  308. DRM_WAKEUP(&dev_priv->irq_queue);
  309. dev_priv->hangcheck_count = 0;
  310. mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
  311. }
  312. if (de_iir & DE_GSE)
  313. ironlake_opregion_gse_intr(dev);
  314. if (de_iir & DE_PLANEA_FLIP_DONE) {
  315. intel_prepare_page_flip(dev, 0);
  316. intel_finish_page_flip(dev, 0);
  317. }
  318. if (de_iir & DE_PLANEB_FLIP_DONE) {
  319. intel_prepare_page_flip(dev, 1);
  320. intel_finish_page_flip(dev, 1);
  321. }
  322. if (de_iir & DE_PIPEA_VBLANK)
  323. drm_handle_vblank(dev, 0);
  324. if (de_iir & DE_PIPEB_VBLANK)
  325. drm_handle_vblank(dev, 1);
  326. /* check event from PCH */
  327. if ((de_iir & DE_PCH_EVENT) &&
  328. (pch_iir & SDE_HOTPLUG_MASK)) {
  329. queue_work(dev_priv->wq, &dev_priv->hotplug_work);
  330. }
  331. if (de_iir & DE_PCU_EVENT) {
  332. I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS));
  333. i915_handle_rps_change(dev);
  334. }
  335. /* should clear PCH hotplug event before clear CPU irq */
  336. I915_WRITE(SDEIIR, pch_iir);
  337. I915_WRITE(GTIIR, gt_iir);
  338. I915_WRITE(DEIIR, de_iir);
  339. done:
  340. I915_WRITE(DEIER, de_ier);
  341. (void)I915_READ(DEIER);
  342. return ret;
  343. }
  344. /**
  345. * i915_error_work_func - do process context error handling work
  346. * @work: work struct
  347. *
  348. * Fire an error uevent so userspace can see that a hang or error
  349. * was detected.
  350. */
  351. static void i915_error_work_func(struct work_struct *work)
  352. {
  353. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  354. error_work);
  355. struct drm_device *dev = dev_priv->dev;
  356. char *error_event[] = { "ERROR=1", NULL };
  357. char *reset_event[] = { "RESET=1", NULL };
  358. char *reset_done_event[] = { "ERROR=0", NULL };
  359. DRM_DEBUG_DRIVER("generating error event\n");
  360. kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
  361. if (atomic_read(&dev_priv->mm.wedged)) {
  362. if (IS_I965G(dev)) {
  363. DRM_DEBUG_DRIVER("resetting chip\n");
  364. kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
  365. if (!i965_reset(dev, GDRST_RENDER)) {
  366. atomic_set(&dev_priv->mm.wedged, 0);
  367. kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
  368. }
  369. } else {
  370. DRM_DEBUG_DRIVER("reboot required\n");
  371. }
  372. }
  373. }
  374. static struct drm_i915_error_object *
  375. i915_error_object_create(struct drm_device *dev,
  376. struct drm_gem_object *src)
  377. {
  378. struct drm_i915_error_object *dst;
  379. struct drm_i915_gem_object *src_priv;
  380. int page, page_count;
  381. if (src == NULL)
  382. return NULL;
  383. src_priv = to_intel_bo(src);
  384. if (src_priv->pages == NULL)
  385. return NULL;
  386. page_count = src->size / PAGE_SIZE;
  387. dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
  388. if (dst == NULL)
  389. return NULL;
  390. for (page = 0; page < page_count; page++) {
  391. void *s, *d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
  392. unsigned long flags;
  393. if (d == NULL)
  394. goto unwind;
  395. local_irq_save(flags);
  396. s = kmap_atomic(src_priv->pages[page], KM_IRQ0);
  397. memcpy(d, s, PAGE_SIZE);
  398. kunmap_atomic(s, KM_IRQ0);
  399. local_irq_restore(flags);
  400. dst->pages[page] = d;
  401. }
  402. dst->page_count = page_count;
  403. dst->gtt_offset = src_priv->gtt_offset;
  404. return dst;
  405. unwind:
  406. while (page--)
  407. kfree(dst->pages[page]);
  408. kfree(dst);
  409. return NULL;
  410. }
  411. static void
  412. i915_error_object_free(struct drm_i915_error_object *obj)
  413. {
  414. int page;
  415. if (obj == NULL)
  416. return;
  417. for (page = 0; page < obj->page_count; page++)
  418. kfree(obj->pages[page]);
  419. kfree(obj);
  420. }
  421. static void
  422. i915_error_state_free(struct drm_device *dev,
  423. struct drm_i915_error_state *error)
  424. {
  425. i915_error_object_free(error->batchbuffer[0]);
  426. i915_error_object_free(error->batchbuffer[1]);
  427. i915_error_object_free(error->ringbuffer);
  428. kfree(error->active_bo);
  429. kfree(error);
  430. }
  431. static u32
  432. i915_get_bbaddr(struct drm_device *dev, u32 *ring)
  433. {
  434. u32 cmd;
  435. if (IS_I830(dev) || IS_845G(dev))
  436. cmd = MI_BATCH_BUFFER;
  437. else if (IS_I965G(dev))
  438. cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
  439. MI_BATCH_NON_SECURE_I965);
  440. else
  441. cmd = (MI_BATCH_BUFFER_START | (2 << 6));
  442. return ring[0] == cmd ? ring[1] : 0;
  443. }
  444. static u32
  445. i915_ringbuffer_last_batch(struct drm_device *dev)
  446. {
  447. struct drm_i915_private *dev_priv = dev->dev_private;
  448. u32 head, bbaddr;
  449. u32 *ring;
  450. /* Locate the current position in the ringbuffer and walk back
  451. * to find the most recently dispatched batch buffer.
  452. */
  453. bbaddr = 0;
  454. head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  455. ring = (u32 *)(dev_priv->render_ring.virtual_start + head);
  456. while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
  457. bbaddr = i915_get_bbaddr(dev, ring);
  458. if (bbaddr)
  459. break;
  460. }
  461. if (bbaddr == 0) {
  462. ring = (u32 *)(dev_priv->render_ring.virtual_start
  463. + dev_priv->render_ring.size);
  464. while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
  465. bbaddr = i915_get_bbaddr(dev, ring);
  466. if (bbaddr)
  467. break;
  468. }
  469. }
  470. return bbaddr;
  471. }
  472. /**
  473. * i915_capture_error_state - capture an error record for later analysis
  474. * @dev: drm device
  475. *
  476. * Should be called when an error is detected (either a hang or an error
  477. * interrupt) to capture error state from the time of the error. Fills
  478. * out a structure which becomes available in debugfs for user level tools
  479. * to pick up.
  480. */
  481. static void i915_capture_error_state(struct drm_device *dev)
  482. {
  483. struct drm_i915_private *dev_priv = dev->dev_private;
  484. struct drm_i915_gem_object *obj_priv;
  485. struct drm_i915_error_state *error;
  486. struct drm_gem_object *batchbuffer[2];
  487. unsigned long flags;
  488. u32 bbaddr;
  489. int count;
  490. spin_lock_irqsave(&dev_priv->error_lock, flags);
  491. error = dev_priv->first_error;
  492. spin_unlock_irqrestore(&dev_priv->error_lock, flags);
  493. if (error)
  494. return;
  495. error = kmalloc(sizeof(*error), GFP_ATOMIC);
  496. if (!error) {
  497. DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
  498. return;
  499. }
  500. error->seqno = i915_get_gem_seqno(dev);
  501. error->eir = I915_READ(EIR);
  502. error->pgtbl_er = I915_READ(PGTBL_ER);
  503. error->pipeastat = I915_READ(PIPEASTAT);
  504. error->pipebstat = I915_READ(PIPEBSTAT);
  505. error->instpm = I915_READ(INSTPM);
  506. if (!IS_I965G(dev)) {
  507. error->ipeir = I915_READ(IPEIR);
  508. error->ipehr = I915_READ(IPEHR);
  509. error->instdone = I915_READ(INSTDONE);
  510. error->acthd = I915_READ(ACTHD);
  511. error->bbaddr = 0;
  512. } else {
  513. error->ipeir = I915_READ(IPEIR_I965);
  514. error->ipehr = I915_READ(IPEHR_I965);
  515. error->instdone = I915_READ(INSTDONE_I965);
  516. error->instps = I915_READ(INSTPS);
  517. error->instdone1 = I915_READ(INSTDONE1);
  518. error->acthd = I915_READ(ACTHD_I965);
  519. error->bbaddr = I915_READ64(BB_ADDR);
  520. }
  521. bbaddr = i915_ringbuffer_last_batch(dev);
  522. /* Grab the current batchbuffer, most likely to have crashed. */
  523. batchbuffer[0] = NULL;
  524. batchbuffer[1] = NULL;
  525. count = 0;
  526. list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
  527. struct drm_gem_object *obj = &obj_priv->base;
  528. if (batchbuffer[0] == NULL &&
  529. bbaddr >= obj_priv->gtt_offset &&
  530. bbaddr < obj_priv->gtt_offset + obj->size)
  531. batchbuffer[0] = obj;
  532. if (batchbuffer[1] == NULL &&
  533. error->acthd >= obj_priv->gtt_offset &&
  534. error->acthd < obj_priv->gtt_offset + obj->size &&
  535. batchbuffer[0] != obj)
  536. batchbuffer[1] = obj;
  537. count++;
  538. }
  539. /* We need to copy these to an anonymous buffer as the simplest
  540. * method to avoid being overwritten by userpace.
  541. */
  542. error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
  543. error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
  544. /* Record the ringbuffer */
  545. error->ringbuffer = i915_error_object_create(dev,
  546. dev_priv->render_ring.gem_object);
  547. /* Record buffers on the active list. */
  548. error->active_bo = NULL;
  549. error->active_bo_count = 0;
  550. if (count)
  551. error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
  552. GFP_ATOMIC);
  553. if (error->active_bo) {
  554. int i = 0;
  555. list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
  556. struct drm_gem_object *obj = &obj_priv->base;
  557. error->active_bo[i].size = obj->size;
  558. error->active_bo[i].name = obj->name;
  559. error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
  560. error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
  561. error->active_bo[i].read_domains = obj->read_domains;
  562. error->active_bo[i].write_domain = obj->write_domain;
  563. error->active_bo[i].fence_reg = obj_priv->fence_reg;
  564. error->active_bo[i].pinned = 0;
  565. if (obj_priv->pin_count > 0)
  566. error->active_bo[i].pinned = 1;
  567. if (obj_priv->user_pin_count > 0)
  568. error->active_bo[i].pinned = -1;
  569. error->active_bo[i].tiling = obj_priv->tiling_mode;
  570. error->active_bo[i].dirty = obj_priv->dirty;
  571. error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
  572. if (++i == count)
  573. break;
  574. }
  575. error->active_bo_count = i;
  576. }
  577. do_gettimeofday(&error->time);
  578. spin_lock_irqsave(&dev_priv->error_lock, flags);
  579. if (dev_priv->first_error == NULL) {
  580. dev_priv->first_error = error;
  581. error = NULL;
  582. }
  583. spin_unlock_irqrestore(&dev_priv->error_lock, flags);
  584. if (error)
  585. i915_error_state_free(dev, error);
  586. }
  587. void i915_destroy_error_state(struct drm_device *dev)
  588. {
  589. struct drm_i915_private *dev_priv = dev->dev_private;
  590. struct drm_i915_error_state *error;
  591. spin_lock(&dev_priv->error_lock);
  592. error = dev_priv->first_error;
  593. dev_priv->first_error = NULL;
  594. spin_unlock(&dev_priv->error_lock);
  595. if (error)
  596. i915_error_state_free(dev, error);
  597. }
  598. /**
  599. * i915_handle_error - handle an error interrupt
  600. * @dev: drm device
  601. *
  602. * Do some basic checking of regsiter state at error interrupt time and
  603. * dump it to the syslog. Also call i915_capture_error_state() to make
  604. * sure we get a record and make it available in debugfs. Fire a uevent
  605. * so userspace knows something bad happened (should trigger collection
  606. * of a ring dump etc.).
  607. */
  608. static void i915_handle_error(struct drm_device *dev, bool wedged)
  609. {
  610. struct drm_i915_private *dev_priv = dev->dev_private;
  611. u32 eir = I915_READ(EIR);
  612. u32 pipea_stats = I915_READ(PIPEASTAT);
  613. u32 pipeb_stats = I915_READ(PIPEBSTAT);
  614. i915_capture_error_state(dev);
  615. printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
  616. eir);
  617. if (IS_G4X(dev)) {
  618. if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
  619. u32 ipeir = I915_READ(IPEIR_I965);
  620. printk(KERN_ERR " IPEIR: 0x%08x\n",
  621. I915_READ(IPEIR_I965));
  622. printk(KERN_ERR " IPEHR: 0x%08x\n",
  623. I915_READ(IPEHR_I965));
  624. printk(KERN_ERR " INSTDONE: 0x%08x\n",
  625. I915_READ(INSTDONE_I965));
  626. printk(KERN_ERR " INSTPS: 0x%08x\n",
  627. I915_READ(INSTPS));
  628. printk(KERN_ERR " INSTDONE1: 0x%08x\n",
  629. I915_READ(INSTDONE1));
  630. printk(KERN_ERR " ACTHD: 0x%08x\n",
  631. I915_READ(ACTHD_I965));
  632. I915_WRITE(IPEIR_I965, ipeir);
  633. (void)I915_READ(IPEIR_I965);
  634. }
  635. if (eir & GM45_ERROR_PAGE_TABLE) {
  636. u32 pgtbl_err = I915_READ(PGTBL_ER);
  637. printk(KERN_ERR "page table error\n");
  638. printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
  639. pgtbl_err);
  640. I915_WRITE(PGTBL_ER, pgtbl_err);
  641. (void)I915_READ(PGTBL_ER);
  642. }
  643. }
  644. if (IS_I9XX(dev)) {
  645. if (eir & I915_ERROR_PAGE_TABLE) {
  646. u32 pgtbl_err = I915_READ(PGTBL_ER);
  647. printk(KERN_ERR "page table error\n");
  648. printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
  649. pgtbl_err);
  650. I915_WRITE(PGTBL_ER, pgtbl_err);
  651. (void)I915_READ(PGTBL_ER);
  652. }
  653. }
  654. if (eir & I915_ERROR_MEMORY_REFRESH) {
  655. printk(KERN_ERR "memory refresh error\n");
  656. printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
  657. pipea_stats);
  658. printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
  659. pipeb_stats);
  660. /* pipestat has already been acked */
  661. }
  662. if (eir & I915_ERROR_INSTRUCTION) {
  663. printk(KERN_ERR "instruction error\n");
  664. printk(KERN_ERR " INSTPM: 0x%08x\n",
  665. I915_READ(INSTPM));
  666. if (!IS_I965G(dev)) {
  667. u32 ipeir = I915_READ(IPEIR);
  668. printk(KERN_ERR " IPEIR: 0x%08x\n",
  669. I915_READ(IPEIR));
  670. printk(KERN_ERR " IPEHR: 0x%08x\n",
  671. I915_READ(IPEHR));
  672. printk(KERN_ERR " INSTDONE: 0x%08x\n",
  673. I915_READ(INSTDONE));
  674. printk(KERN_ERR " ACTHD: 0x%08x\n",
  675. I915_READ(ACTHD));
  676. I915_WRITE(IPEIR, ipeir);
  677. (void)I915_READ(IPEIR);
  678. } else {
  679. u32 ipeir = I915_READ(IPEIR_I965);
  680. printk(KERN_ERR " IPEIR: 0x%08x\n",
  681. I915_READ(IPEIR_I965));
  682. printk(KERN_ERR " IPEHR: 0x%08x\n",
  683. I915_READ(IPEHR_I965));
  684. printk(KERN_ERR " INSTDONE: 0x%08x\n",
  685. I915_READ(INSTDONE_I965));
  686. printk(KERN_ERR " INSTPS: 0x%08x\n",
  687. I915_READ(INSTPS));
  688. printk(KERN_ERR " INSTDONE1: 0x%08x\n",
  689. I915_READ(INSTDONE1));
  690. printk(KERN_ERR " ACTHD: 0x%08x\n",
  691. I915_READ(ACTHD_I965));
  692. I915_WRITE(IPEIR_I965, ipeir);
  693. (void)I915_READ(IPEIR_I965);
  694. }
  695. }
  696. I915_WRITE(EIR, eir);
  697. (void)I915_READ(EIR);
  698. eir = I915_READ(EIR);
  699. if (eir) {
  700. /*
  701. * some errors might have become stuck,
  702. * mask them.
  703. */
  704. DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
  705. I915_WRITE(EMR, I915_READ(EMR) | eir);
  706. I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  707. }
  708. if (wedged) {
  709. atomic_set(&dev_priv->mm.wedged, 1);
  710. /*
  711. * Wakeup waiting processes so they don't hang
  712. */
  713. DRM_WAKEUP(&dev_priv->irq_queue);
  714. }
  715. queue_work(dev_priv->wq, &dev_priv->error_work);
  716. }
  717. irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
  718. {
  719. struct drm_device *dev = (struct drm_device *) arg;
  720. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  721. struct drm_i915_master_private *master_priv;
  722. u32 iir, new_iir;
  723. u32 pipea_stats, pipeb_stats;
  724. u32 vblank_status;
  725. u32 vblank_enable;
  726. int vblank = 0;
  727. unsigned long irqflags;
  728. int irq_received;
  729. int ret = IRQ_NONE;
  730. atomic_inc(&dev_priv->irq_received);
  731. if (HAS_PCH_SPLIT(dev))
  732. return ironlake_irq_handler(dev);
  733. iir = I915_READ(IIR);
  734. if (IS_I965G(dev)) {
  735. vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
  736. vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
  737. } else {
  738. vblank_status = I915_VBLANK_INTERRUPT_STATUS;
  739. vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
  740. }
  741. for (;;) {
  742. irq_received = iir != 0;
  743. /* Can't rely on pipestat interrupt bit in iir as it might
  744. * have been cleared after the pipestat interrupt was received.
  745. * It doesn't set the bit in iir again, but it still produces
  746. * interrupts (for non-MSI).
  747. */
  748. spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
  749. pipea_stats = I915_READ(PIPEASTAT);
  750. pipeb_stats = I915_READ(PIPEBSTAT);
  751. if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  752. i915_handle_error(dev, false);
  753. /*
  754. * Clear the PIPE(A|B)STAT regs before the IIR
  755. */
  756. if (pipea_stats & 0x8000ffff) {
  757. if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS)
  758. DRM_DEBUG_DRIVER("pipe a underrun\n");
  759. I915_WRITE(PIPEASTAT, pipea_stats);
  760. irq_received = 1;
  761. }
  762. if (pipeb_stats & 0x8000ffff) {
  763. if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS)
  764. DRM_DEBUG_DRIVER("pipe b underrun\n");
  765. I915_WRITE(PIPEBSTAT, pipeb_stats);
  766. irq_received = 1;
  767. }
  768. spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
  769. if (!irq_received)
  770. break;
  771. ret = IRQ_HANDLED;
  772. /* Consume port. Then clear IIR or we'll miss events */
  773. if ((I915_HAS_HOTPLUG(dev)) &&
  774. (iir & I915_DISPLAY_PORT_INTERRUPT)) {
  775. u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
  776. DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
  777. hotplug_status);
  778. if (hotplug_status & dev_priv->hotplug_supported_mask)
  779. queue_work(dev_priv->wq,
  780. &dev_priv->hotplug_work);
  781. I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
  782. I915_READ(PORT_HOTPLUG_STAT);
  783. }
  784. I915_WRITE(IIR, iir);
  785. new_iir = I915_READ(IIR); /* Flush posted writes */
  786. if (dev->primary->master) {
  787. master_priv = dev->primary->master->driver_priv;
  788. if (master_priv->sarea_priv)
  789. master_priv->sarea_priv->last_dispatch =
  790. READ_BREADCRUMB(dev_priv);
  791. }
  792. if (iir & I915_USER_INTERRUPT) {
  793. u32 seqno = i915_get_gem_seqno(dev);
  794. dev_priv->mm.irq_gem_seqno = seqno;
  795. trace_i915_gem_request_complete(dev, seqno);
  796. DRM_WAKEUP(&dev_priv->irq_queue);
  797. dev_priv->hangcheck_count = 0;
  798. mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
  799. }
  800. if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
  801. intel_prepare_page_flip(dev, 0);
  802. if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
  803. intel_prepare_page_flip(dev, 1);
  804. if (pipea_stats & vblank_status) {
  805. vblank++;
  806. drm_handle_vblank(dev, 0);
  807. intel_finish_page_flip(dev, 0);
  808. }
  809. if (pipeb_stats & vblank_status) {
  810. vblank++;
  811. drm_handle_vblank(dev, 1);
  812. intel_finish_page_flip(dev, 1);
  813. }
  814. if ((pipea_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
  815. (pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
  816. (iir & I915_ASLE_INTERRUPT))
  817. opregion_asle_intr(dev);
  818. /* With MSI, interrupts are only generated when iir
  819. * transitions from zero to nonzero. If another bit got
  820. * set while we were handling the existing iir bits, then
  821. * we would never get another interrupt.
  822. *
  823. * This is fine on non-MSI as well, as if we hit this path
  824. * we avoid exiting the interrupt handler only to generate
  825. * another one.
  826. *
  827. * Note that for MSI this could cause a stray interrupt report
  828. * if an interrupt landed in the time between writing IIR and
  829. * the posting read. This should be rare enough to never
  830. * trigger the 99% of 100,000 interrupts test for disabling
  831. * stray interrupts.
  832. */
  833. iir = new_iir;
  834. }
  835. return ret;
  836. }
  837. static int i915_emit_irq(struct drm_device * dev)
  838. {
  839. drm_i915_private_t *dev_priv = dev->dev_private;
  840. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  841. i915_kernel_lost_context(dev);
  842. DRM_DEBUG_DRIVER("\n");
  843. dev_priv->counter++;
  844. if (dev_priv->counter > 0x7FFFFFFFUL)
  845. dev_priv->counter = 1;
  846. if (master_priv->sarea_priv)
  847. master_priv->sarea_priv->last_enqueue = dev_priv->counter;
  848. BEGIN_LP_RING(4);
  849. OUT_RING(MI_STORE_DWORD_INDEX);
  850. OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
  851. OUT_RING(dev_priv->counter);
  852. OUT_RING(MI_USER_INTERRUPT);
  853. ADVANCE_LP_RING();
  854. return dev_priv->counter;
  855. }
  856. void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
  857. {
  858. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  859. struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
  860. if (dev_priv->trace_irq_seqno == 0)
  861. render_ring->user_irq_get(dev, render_ring);
  862. dev_priv->trace_irq_seqno = seqno;
  863. }
  864. static int i915_wait_irq(struct drm_device * dev, int irq_nr)
  865. {
  866. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  867. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  868. int ret = 0;
  869. struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
  870. DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
  871. READ_BREADCRUMB(dev_priv));
  872. if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
  873. if (master_priv->sarea_priv)
  874. master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
  875. return 0;
  876. }
  877. if (master_priv->sarea_priv)
  878. master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
  879. render_ring->user_irq_get(dev, render_ring);
  880. DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
  881. READ_BREADCRUMB(dev_priv) >= irq_nr);
  882. render_ring->user_irq_put(dev, render_ring);
  883. if (ret == -EBUSY) {
  884. DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
  885. READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
  886. }
  887. return ret;
  888. }
  889. /* Needs the lock as it touches the ring.
  890. */
  891. int i915_irq_emit(struct drm_device *dev, void *data,
  892. struct drm_file *file_priv)
  893. {
  894. drm_i915_private_t *dev_priv = dev->dev_private;
  895. drm_i915_irq_emit_t *emit = data;
  896. int result;
  897. if (!dev_priv || !dev_priv->render_ring.virtual_start) {
  898. DRM_ERROR("called with no initialization\n");
  899. return -EINVAL;
  900. }
  901. RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
  902. mutex_lock(&dev->struct_mutex);
  903. result = i915_emit_irq(dev);
  904. mutex_unlock(&dev->struct_mutex);
  905. if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
  906. DRM_ERROR("copy_to_user\n");
  907. return -EFAULT;
  908. }
  909. return 0;
  910. }
  911. /* Doesn't need the hardware lock.
  912. */
  913. int i915_irq_wait(struct drm_device *dev, void *data,
  914. struct drm_file *file_priv)
  915. {
  916. drm_i915_private_t *dev_priv = dev->dev_private;
  917. drm_i915_irq_wait_t *irqwait = data;
  918. if (!dev_priv) {
  919. DRM_ERROR("called with no initialization\n");
  920. return -EINVAL;
  921. }
  922. return i915_wait_irq(dev, irqwait->irq_seq);
  923. }
  924. /* Called from drm generic code, passed 'crtc' which
  925. * we use as a pipe index
  926. */
  927. int i915_enable_vblank(struct drm_device *dev, int pipe)
  928. {
  929. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  930. unsigned long irqflags;
  931. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  932. u32 pipeconf;
  933. pipeconf = I915_READ(pipeconf_reg);
  934. if (!(pipeconf & PIPEACONF_ENABLE))
  935. return -EINVAL;
  936. spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
  937. if (HAS_PCH_SPLIT(dev))
  938. ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
  939. DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
  940. else if (IS_I965G(dev))
  941. i915_enable_pipestat(dev_priv, pipe,
  942. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  943. else
  944. i915_enable_pipestat(dev_priv, pipe,
  945. PIPE_VBLANK_INTERRUPT_ENABLE);
  946. spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
  947. return 0;
  948. }
  949. /* Called from drm generic code, passed 'crtc' which
  950. * we use as a pipe index
  951. */
  952. void i915_disable_vblank(struct drm_device *dev, int pipe)
  953. {
  954. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  955. unsigned long irqflags;
  956. spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
  957. if (HAS_PCH_SPLIT(dev))
  958. ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
  959. DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
  960. else
  961. i915_disable_pipestat(dev_priv, pipe,
  962. PIPE_VBLANK_INTERRUPT_ENABLE |
  963. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  964. spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
  965. }
  966. void i915_enable_interrupt (struct drm_device *dev)
  967. {
  968. struct drm_i915_private *dev_priv = dev->dev_private;
  969. if (!HAS_PCH_SPLIT(dev))
  970. opregion_enable_asle(dev);
  971. dev_priv->irq_enabled = 1;
  972. }
  973. /* Set the vblank monitor pipe
  974. */
  975. int i915_vblank_pipe_set(struct drm_device *dev, void *data,
  976. struct drm_file *file_priv)
  977. {
  978. drm_i915_private_t *dev_priv = dev->dev_private;
  979. if (!dev_priv) {
  980. DRM_ERROR("called with no initialization\n");
  981. return -EINVAL;
  982. }
  983. return 0;
  984. }
  985. int i915_vblank_pipe_get(struct drm_device *dev, void *data,
  986. struct drm_file *file_priv)
  987. {
  988. drm_i915_private_t *dev_priv = dev->dev_private;
  989. drm_i915_vblank_pipe_t *pipe = data;
  990. if (!dev_priv) {
  991. DRM_ERROR("called with no initialization\n");
  992. return -EINVAL;
  993. }
  994. pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
  995. return 0;
  996. }
  997. /**
  998. * Schedule buffer swap at given vertical blank.
  999. */
  1000. int i915_vblank_swap(struct drm_device *dev, void *data,
  1001. struct drm_file *file_priv)
  1002. {
  1003. /* The delayed swap mechanism was fundamentally racy, and has been
  1004. * removed. The model was that the client requested a delayed flip/swap
  1005. * from the kernel, then waited for vblank before continuing to perform
  1006. * rendering. The problem was that the kernel might wake the client
  1007. * up before it dispatched the vblank swap (since the lock has to be
  1008. * held while touching the ringbuffer), in which case the client would
  1009. * clear and start the next frame before the swap occurred, and
  1010. * flicker would occur in addition to likely missing the vblank.
  1011. *
  1012. * In the absence of this ioctl, userland falls back to a correct path
  1013. * of waiting for a vblank, then dispatching the swap on its own.
  1014. * Context switching to userland and back is plenty fast enough for
  1015. * meeting the requirements of vblank swapping.
  1016. */
  1017. return -EINVAL;
  1018. }
  1019. struct drm_i915_gem_request *i915_get_tail_request(struct drm_device *dev) {
  1020. drm_i915_private_t *dev_priv = dev->dev_private;
  1021. return list_entry(dev_priv->mm.request_list.prev, struct drm_i915_gem_request, list);
  1022. }
  1023. /**
  1024. * This is called when the chip hasn't reported back with completed
  1025. * batchbuffers in a long time. The first time this is called we simply record
  1026. * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
  1027. * again, we assume the chip is wedged and try to fix it.
  1028. */
  1029. void i915_hangcheck_elapsed(unsigned long data)
  1030. {
  1031. struct drm_device *dev = (struct drm_device *)data;
  1032. drm_i915_private_t *dev_priv = dev->dev_private;
  1033. uint32_t acthd;
  1034. /* No reset support on this chip yet. */
  1035. if (IS_GEN6(dev))
  1036. return;
  1037. if (!IS_I965G(dev))
  1038. acthd = I915_READ(ACTHD);
  1039. else
  1040. acthd = I915_READ(ACTHD_I965);
  1041. /* If all work is done then ACTHD clearly hasn't advanced. */
  1042. if (list_empty(&dev_priv->mm.request_list) ||
  1043. i915_seqno_passed(i915_get_gem_seqno(dev), i915_get_tail_request(dev)->seqno)) {
  1044. dev_priv->hangcheck_count = 0;
  1045. return;
  1046. }
  1047. if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) {
  1048. DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
  1049. i915_handle_error(dev, true);
  1050. return;
  1051. }
  1052. /* Reset timer case chip hangs without another request being added */
  1053. mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
  1054. if (acthd != dev_priv->last_acthd)
  1055. dev_priv->hangcheck_count = 0;
  1056. else
  1057. dev_priv->hangcheck_count++;
  1058. dev_priv->last_acthd = acthd;
  1059. }
  1060. /* drm_dma.h hooks
  1061. */
  1062. static void ironlake_irq_preinstall(struct drm_device *dev)
  1063. {
  1064. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1065. I915_WRITE(HWSTAM, 0xeffe);
  1066. /* XXX hotplug from PCH */
  1067. I915_WRITE(DEIMR, 0xffffffff);
  1068. I915_WRITE(DEIER, 0x0);
  1069. (void) I915_READ(DEIER);
  1070. /* and GT */
  1071. I915_WRITE(GTIMR, 0xffffffff);
  1072. I915_WRITE(GTIER, 0x0);
  1073. (void) I915_READ(GTIER);
  1074. /* south display irq */
  1075. I915_WRITE(SDEIMR, 0xffffffff);
  1076. I915_WRITE(SDEIER, 0x0);
  1077. (void) I915_READ(SDEIER);
  1078. }
  1079. static int ironlake_irq_postinstall(struct drm_device *dev)
  1080. {
  1081. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1082. /* enable kind of interrupts always enabled */
  1083. u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
  1084. DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
  1085. u32 render_mask = GT_PIPE_NOTIFY;
  1086. u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
  1087. SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
  1088. dev_priv->irq_mask_reg = ~display_mask;
  1089. dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
  1090. /* should always can generate irq */
  1091. I915_WRITE(DEIIR, I915_READ(DEIIR));
  1092. I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  1093. I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
  1094. (void) I915_READ(DEIER);
  1095. /* user interrupt should be enabled, but masked initial */
  1096. dev_priv->gt_irq_mask_reg = 0xffffffff;
  1097. dev_priv->gt_irq_enable_reg = render_mask;
  1098. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1099. I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  1100. I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
  1101. (void) I915_READ(GTIER);
  1102. dev_priv->pch_irq_mask_reg = ~hotplug_mask;
  1103. dev_priv->pch_irq_enable_reg = hotplug_mask;
  1104. I915_WRITE(SDEIIR, I915_READ(SDEIIR));
  1105. I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
  1106. I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
  1107. (void) I915_READ(SDEIER);
  1108. if (IS_IRONLAKE_M(dev)) {
  1109. /* Clear & enable PCU event interrupts */
  1110. I915_WRITE(DEIIR, DE_PCU_EVENT);
  1111. I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
  1112. ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
  1113. }
  1114. return 0;
  1115. }
  1116. void i915_driver_irq_preinstall(struct drm_device * dev)
  1117. {
  1118. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1119. atomic_set(&dev_priv->irq_received, 0);
  1120. INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
  1121. INIT_WORK(&dev_priv->error_work, i915_error_work_func);
  1122. if (HAS_PCH_SPLIT(dev)) {
  1123. ironlake_irq_preinstall(dev);
  1124. return;
  1125. }
  1126. if (I915_HAS_HOTPLUG(dev)) {
  1127. I915_WRITE(PORT_HOTPLUG_EN, 0);
  1128. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  1129. }
  1130. I915_WRITE(HWSTAM, 0xeffe);
  1131. I915_WRITE(PIPEASTAT, 0);
  1132. I915_WRITE(PIPEBSTAT, 0);
  1133. I915_WRITE(IMR, 0xffffffff);
  1134. I915_WRITE(IER, 0x0);
  1135. (void) I915_READ(IER);
  1136. }
  1137. /*
  1138. * Must be called after intel_modeset_init or hotplug interrupts won't be
  1139. * enabled correctly.
  1140. */
  1141. int i915_driver_irq_postinstall(struct drm_device *dev)
  1142. {
  1143. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1144. u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
  1145. u32 error_mask;
  1146. DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
  1147. dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
  1148. if (HAS_PCH_SPLIT(dev))
  1149. return ironlake_irq_postinstall(dev);
  1150. /* Unmask the interrupts that we always want on. */
  1151. dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
  1152. dev_priv->pipestat[0] = 0;
  1153. dev_priv->pipestat[1] = 0;
  1154. if (I915_HAS_HOTPLUG(dev)) {
  1155. u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
  1156. /* Note HDMI and DP share bits */
  1157. if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
  1158. hotplug_en |= HDMIB_HOTPLUG_INT_EN;
  1159. if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
  1160. hotplug_en |= HDMIC_HOTPLUG_INT_EN;
  1161. if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
  1162. hotplug_en |= HDMID_HOTPLUG_INT_EN;
  1163. if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
  1164. hotplug_en |= SDVOC_HOTPLUG_INT_EN;
  1165. if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
  1166. hotplug_en |= SDVOB_HOTPLUG_INT_EN;
  1167. if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS)
  1168. hotplug_en |= CRT_HOTPLUG_INT_EN;
  1169. /* Ignore TV since it's buggy */
  1170. I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  1171. /* Enable in IER... */
  1172. enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
  1173. /* and unmask in IMR */
  1174. i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
  1175. }
  1176. /*
  1177. * Enable some error detection, note the instruction error mask
  1178. * bit is reserved, so we leave it masked.
  1179. */
  1180. if (IS_G4X(dev)) {
  1181. error_mask = ~(GM45_ERROR_PAGE_TABLE |
  1182. GM45_ERROR_MEM_PRIV |
  1183. GM45_ERROR_CP_PRIV |
  1184. I915_ERROR_MEMORY_REFRESH);
  1185. } else {
  1186. error_mask = ~(I915_ERROR_PAGE_TABLE |
  1187. I915_ERROR_MEMORY_REFRESH);
  1188. }
  1189. I915_WRITE(EMR, error_mask);
  1190. /* Disable pipe interrupt enables, clear pending pipe status */
  1191. I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
  1192. I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
  1193. /* Clear pending interrupt status */
  1194. I915_WRITE(IIR, I915_READ(IIR));
  1195. I915_WRITE(IER, enable_mask);
  1196. I915_WRITE(IMR, dev_priv->irq_mask_reg);
  1197. (void) I915_READ(IER);
  1198. opregion_enable_asle(dev);
  1199. return 0;
  1200. }
  1201. static void ironlake_irq_uninstall(struct drm_device *dev)
  1202. {
  1203. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1204. I915_WRITE(HWSTAM, 0xffffffff);
  1205. I915_WRITE(DEIMR, 0xffffffff);
  1206. I915_WRITE(DEIER, 0x0);
  1207. I915_WRITE(DEIIR, I915_READ(DEIIR));
  1208. I915_WRITE(GTIMR, 0xffffffff);
  1209. I915_WRITE(GTIER, 0x0);
  1210. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1211. }
  1212. void i915_driver_irq_uninstall(struct drm_device * dev)
  1213. {
  1214. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1215. if (!dev_priv)
  1216. return;
  1217. dev_priv->vblank_pipe = 0;
  1218. if (HAS_PCH_SPLIT(dev)) {
  1219. ironlake_irq_uninstall(dev);
  1220. return;
  1221. }
  1222. if (I915_HAS_HOTPLUG(dev)) {
  1223. I915_WRITE(PORT_HOTPLUG_EN, 0);
  1224. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  1225. }
  1226. I915_WRITE(HWSTAM, 0xffffffff);
  1227. I915_WRITE(PIPEASTAT, 0);
  1228. I915_WRITE(PIPEBSTAT, 0);
  1229. I915_WRITE(IMR, 0xffffffff);
  1230. I915_WRITE(IER, 0x0);
  1231. I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
  1232. I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
  1233. I915_WRITE(IIR, I915_READ(IIR));
  1234. }