rt2500pci.c 59 KB

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  1. /*
  2. Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
  3. <http://rt2x00.serialmonkey.com>
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the
  14. Free Software Foundation, Inc.,
  15. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16. */
  17. /*
  18. Module: rt2500pci
  19. Abstract: rt2500pci device specific routines.
  20. Supported chipsets: RT2560.
  21. */
  22. /*
  23. * Set enviroment defines for rt2x00.h
  24. */
  25. #define DRV_NAME "rt2500pci"
  26. #include <linux/delay.h>
  27. #include <linux/etherdevice.h>
  28. #include <linux/init.h>
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/pci.h>
  32. #include <linux/eeprom_93cx6.h>
  33. #include "rt2x00.h"
  34. #include "rt2x00pci.h"
  35. #include "rt2500pci.h"
  36. /*
  37. * Register access.
  38. * All access to the CSR registers will go through the methods
  39. * rt2x00pci_register_read and rt2x00pci_register_write.
  40. * BBP and RF register require indirect register access,
  41. * and use the CSR registers BBPCSR and RFCSR to achieve this.
  42. * These indirect registers work with busy bits,
  43. * and we will try maximal REGISTER_BUSY_COUNT times to access
  44. * the register while taking a REGISTER_BUSY_DELAY us delay
  45. * between each attampt. When the busy bit is still set at that time,
  46. * the access attempt is considered to have failed,
  47. * and we will print an error.
  48. */
  49. static u32 rt2500pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
  50. {
  51. u32 reg;
  52. unsigned int i;
  53. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  54. rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  55. if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  56. break;
  57. udelay(REGISTER_BUSY_DELAY);
  58. }
  59. return reg;
  60. }
  61. static void rt2500pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
  62. const unsigned int word, const u8 value)
  63. {
  64. u32 reg;
  65. /*
  66. * Wait until the BBP becomes ready.
  67. */
  68. reg = rt2500pci_bbp_check(rt2x00dev);
  69. if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  70. ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  71. return;
  72. }
  73. /*
  74. * Write the data into the BBP.
  75. */
  76. reg = 0;
  77. rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  78. rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  79. rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  80. rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  81. rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  82. }
  83. static void rt2500pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
  84. const unsigned int word, u8 *value)
  85. {
  86. u32 reg;
  87. /*
  88. * Wait until the BBP becomes ready.
  89. */
  90. reg = rt2500pci_bbp_check(rt2x00dev);
  91. if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  92. ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
  93. return;
  94. }
  95. /*
  96. * Write the request into the BBP.
  97. */
  98. reg = 0;
  99. rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  100. rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  101. rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
  102. rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  103. /*
  104. * Wait until the BBP becomes ready.
  105. */
  106. reg = rt2500pci_bbp_check(rt2x00dev);
  107. if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  108. ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
  109. *value = 0xff;
  110. return;
  111. }
  112. *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
  113. }
  114. static void rt2500pci_rf_write(const struct rt2x00_dev *rt2x00dev,
  115. const unsigned int word, const u32 value)
  116. {
  117. u32 reg;
  118. unsigned int i;
  119. if (!word)
  120. return;
  121. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  122. rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
  123. if (!rt2x00_get_field32(reg, RFCSR_BUSY))
  124. goto rf_write;
  125. udelay(REGISTER_BUSY_DELAY);
  126. }
  127. ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
  128. return;
  129. rf_write:
  130. reg = 0;
  131. rt2x00_set_field32(&reg, RFCSR_VALUE, value);
  132. rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
  133. rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
  134. rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
  135. rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
  136. rt2x00_rf_write(rt2x00dev, word, value);
  137. }
  138. static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
  139. {
  140. struct rt2x00_dev *rt2x00dev = eeprom->data;
  141. u32 reg;
  142. rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
  143. eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
  144. eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
  145. eeprom->reg_data_clock =
  146. !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
  147. eeprom->reg_chip_select =
  148. !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
  149. }
  150. static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
  151. {
  152. struct rt2x00_dev *rt2x00dev = eeprom->data;
  153. u32 reg = 0;
  154. rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
  155. rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
  156. rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
  157. !!eeprom->reg_data_clock);
  158. rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
  159. !!eeprom->reg_chip_select);
  160. rt2x00pci_register_write(rt2x00dev, CSR21, reg);
  161. }
  162. #ifdef CONFIG_RT2X00_LIB_DEBUGFS
  163. #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
  164. static void rt2500pci_read_csr(const struct rt2x00_dev *rt2x00dev,
  165. const unsigned int word, u32 *data)
  166. {
  167. rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
  168. }
  169. static void rt2500pci_write_csr(const struct rt2x00_dev *rt2x00dev,
  170. const unsigned int word, u32 data)
  171. {
  172. rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
  173. }
  174. static const struct rt2x00debug rt2500pci_rt2x00debug = {
  175. .owner = THIS_MODULE,
  176. .csr = {
  177. .read = rt2500pci_read_csr,
  178. .write = rt2500pci_write_csr,
  179. .word_size = sizeof(u32),
  180. .word_count = CSR_REG_SIZE / sizeof(u32),
  181. },
  182. .eeprom = {
  183. .read = rt2x00_eeprom_read,
  184. .write = rt2x00_eeprom_write,
  185. .word_size = sizeof(u16),
  186. .word_count = EEPROM_SIZE / sizeof(u16),
  187. },
  188. .bbp = {
  189. .read = rt2500pci_bbp_read,
  190. .write = rt2500pci_bbp_write,
  191. .word_size = sizeof(u8),
  192. .word_count = BBP_SIZE / sizeof(u8),
  193. },
  194. .rf = {
  195. .read = rt2x00_rf_read,
  196. .write = rt2500pci_rf_write,
  197. .word_size = sizeof(u32),
  198. .word_count = RF_SIZE / sizeof(u32),
  199. },
  200. };
  201. #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
  202. #ifdef CONFIG_RT2500PCI_RFKILL
  203. static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
  204. {
  205. u32 reg;
  206. rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
  207. return rt2x00_get_field32(reg, GPIOCSR_BIT0);
  208. }
  209. #else
  210. #define rt2500pci_rfkill_poll NULL
  211. #endif /* CONFIG_RT2500PCI_RFKILL */
  212. /*
  213. * Configuration handlers.
  214. */
  215. static void rt2500pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
  216. __le32 *mac)
  217. {
  218. rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac,
  219. (2 * sizeof(__le32)));
  220. }
  221. static void rt2500pci_config_bssid(struct rt2x00_dev *rt2x00dev,
  222. __le32 *bssid)
  223. {
  224. rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid,
  225. (2 * sizeof(__le32)));
  226. }
  227. static void rt2500pci_config_type(struct rt2x00_dev *rt2x00dev, const int type)
  228. {
  229. struct interface *intf = &rt2x00dev->interface;
  230. u32 reg;
  231. rt2x00pci_register_write(rt2x00dev, CSR14, 0);
  232. /*
  233. * Enable beacon config
  234. */
  235. rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
  236. rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
  237. PREAMBLE + get_duration(IEEE80211_HEADER, 2));
  238. rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN,
  239. rt2x00lib_get_ring(rt2x00dev,
  240. IEEE80211_TX_QUEUE_BEACON)
  241. ->tx_params.cw_min);
  242. rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
  243. /*
  244. * Enable synchronisation.
  245. */
  246. rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
  247. rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
  248. rt2x00_set_field32(&reg, CSR14_TBCN, 1);
  249. rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
  250. if (is_interface_type(intf, IEEE80211_IF_TYPE_IBSS) ||
  251. is_interface_type(intf, IEEE80211_IF_TYPE_AP))
  252. rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 2);
  253. else if (is_interface_type(intf, IEEE80211_IF_TYPE_STA))
  254. rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 1);
  255. else
  256. rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
  257. rt2x00pci_register_write(rt2x00dev, CSR14, reg);
  258. }
  259. static void rt2500pci_config_rate(struct rt2x00_dev *rt2x00dev, const int rate)
  260. {
  261. struct ieee80211_conf *conf = &rt2x00dev->hw->conf;
  262. u32 reg;
  263. u32 preamble;
  264. u16 value;
  265. if (DEVICE_GET_RATE_FIELD(rate, PREAMBLE))
  266. preamble = SHORT_PREAMBLE;
  267. else
  268. preamble = PREAMBLE;
  269. reg = DEVICE_GET_RATE_FIELD(rate, RATEMASK) & DEV_BASIC_RATEMASK;
  270. rt2x00pci_register_write(rt2x00dev, ARCSR1, reg);
  271. rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
  272. value = ((conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) ?
  273. SHORT_DIFS : DIFS) +
  274. PLCP + preamble + get_duration(ACK_SIZE, 10);
  275. rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, value);
  276. value = SIFS + PLCP + preamble + get_duration(ACK_SIZE, 10);
  277. rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, value);
  278. rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
  279. preamble = DEVICE_GET_RATE_FIELD(rate, PREAMBLE) ? 0x08 : 0x00;
  280. rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
  281. rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble);
  282. rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
  283. rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
  284. rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
  285. rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
  286. rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble);
  287. rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
  288. rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
  289. rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
  290. rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
  291. rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble);
  292. rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
  293. rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
  294. rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
  295. rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
  296. rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble);
  297. rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
  298. rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
  299. rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
  300. }
  301. static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
  302. const int phymode)
  303. {
  304. struct ieee80211_hw_mode *mode;
  305. struct ieee80211_rate *rate;
  306. if (phymode == MODE_IEEE80211A)
  307. rt2x00dev->curr_hwmode = HWMODE_A;
  308. else if (phymode == MODE_IEEE80211B)
  309. rt2x00dev->curr_hwmode = HWMODE_B;
  310. else
  311. rt2x00dev->curr_hwmode = HWMODE_G;
  312. mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode];
  313. rate = &mode->rates[mode->num_rates - 1];
  314. rt2500pci_config_rate(rt2x00dev, rate->val2);
  315. }
  316. static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
  317. const int index, const int channel,
  318. const int txpower)
  319. {
  320. struct rf_channel reg;
  321. u8 r70;
  322. /*
  323. * Fill rf_reg structure.
  324. */
  325. memcpy(&reg, &rt2x00dev->spec.channels[index], sizeof(reg));
  326. /*
  327. * Set TXpower.
  328. */
  329. rt2x00_set_field32(&reg.rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
  330. /*
  331. * Switch on tuning bits.
  332. * For RT2523 devices we do not need to update the R1 register.
  333. */
  334. if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
  335. rt2x00_set_field32(&reg.rf1, RF1_TUNER, 1);
  336. rt2x00_set_field32(&reg.rf3, RF3_TUNER, 1);
  337. /*
  338. * For RT2525 we should first set the channel to half band higher.
  339. */
  340. if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
  341. static const u32 vals[] = {
  342. 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
  343. 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
  344. 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
  345. 0x00080d2e, 0x00080d3a
  346. };
  347. rt2500pci_rf_write(rt2x00dev, 1, reg.rf1);
  348. rt2500pci_rf_write(rt2x00dev, 2, vals[channel - 1]);
  349. rt2500pci_rf_write(rt2x00dev, 3, reg.rf3);
  350. if (reg.rf4)
  351. rt2500pci_rf_write(rt2x00dev, 4, reg.rf4);
  352. }
  353. rt2500pci_rf_write(rt2x00dev, 1, reg.rf1);
  354. rt2500pci_rf_write(rt2x00dev, 2, reg.rf2);
  355. rt2500pci_rf_write(rt2x00dev, 3, reg.rf3);
  356. if (reg.rf4)
  357. rt2500pci_rf_write(rt2x00dev, 4, reg.rf4);
  358. /*
  359. * Channel 14 requires the Japan filter bit to be set.
  360. */
  361. r70 = 0x46;
  362. rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, channel == 14);
  363. rt2500pci_bbp_write(rt2x00dev, 70, r70);
  364. msleep(1);
  365. /*
  366. * Switch off tuning bits.
  367. * For RT2523 devices we do not need to update the R1 register.
  368. */
  369. if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
  370. rt2x00_set_field32(&reg.rf1, RF1_TUNER, 0);
  371. rt2500pci_rf_write(rt2x00dev, 1, reg.rf1);
  372. }
  373. rt2x00_set_field32(&reg.rf3, RF3_TUNER, 0);
  374. rt2500pci_rf_write(rt2x00dev, 3, reg.rf3);
  375. /*
  376. * Clear false CRC during channel switch.
  377. */
  378. rt2x00pci_register_read(rt2x00dev, CNT0, &reg.rf1);
  379. }
  380. static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
  381. const int txpower)
  382. {
  383. u32 rf3;
  384. rt2x00_rf_read(rt2x00dev, 3, &rf3);
  385. rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
  386. rt2500pci_rf_write(rt2x00dev, 3, rf3);
  387. }
  388. static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
  389. const int antenna_tx, const int antenna_rx)
  390. {
  391. u32 reg;
  392. u8 r14;
  393. u8 r2;
  394. rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
  395. rt2500pci_bbp_read(rt2x00dev, 14, &r14);
  396. rt2500pci_bbp_read(rt2x00dev, 2, &r2);
  397. /*
  398. * Configure the TX antenna.
  399. */
  400. switch (antenna_tx) {
  401. case ANTENNA_SW_DIVERSITY:
  402. case ANTENNA_HW_DIVERSITY:
  403. rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
  404. rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
  405. rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
  406. break;
  407. case ANTENNA_A:
  408. rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
  409. rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
  410. rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
  411. break;
  412. case ANTENNA_B:
  413. rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
  414. rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
  415. rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
  416. break;
  417. }
  418. /*
  419. * Configure the RX antenna.
  420. */
  421. switch (antenna_rx) {
  422. case ANTENNA_SW_DIVERSITY:
  423. case ANTENNA_HW_DIVERSITY:
  424. rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
  425. break;
  426. case ANTENNA_A:
  427. rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
  428. break;
  429. case ANTENNA_B:
  430. rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
  431. break;
  432. }
  433. /*
  434. * RT2525E and RT5222 need to flip TX I/Q
  435. */
  436. if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
  437. rt2x00_rf(&rt2x00dev->chip, RF5222)) {
  438. rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
  439. rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
  440. rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
  441. /*
  442. * RT2525E does not need RX I/Q Flip.
  443. */
  444. if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
  445. rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
  446. } else {
  447. rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
  448. rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
  449. }
  450. rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
  451. rt2500pci_bbp_write(rt2x00dev, 14, r14);
  452. rt2500pci_bbp_write(rt2x00dev, 2, r2);
  453. }
  454. static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
  455. const int short_slot_time,
  456. const int beacon_int)
  457. {
  458. u32 reg;
  459. rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
  460. rt2x00_set_field32(&reg, CSR11_SLOT_TIME,
  461. short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME);
  462. rt2x00pci_register_write(rt2x00dev, CSR11, reg);
  463. rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
  464. rt2x00_set_field32(&reg, CSR18_SIFS, SIFS);
  465. rt2x00_set_field32(&reg, CSR18_PIFS,
  466. short_slot_time ? SHORT_PIFS : PIFS);
  467. rt2x00pci_register_write(rt2x00dev, CSR18, reg);
  468. rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
  469. rt2x00_set_field32(&reg, CSR19_DIFS,
  470. short_slot_time ? SHORT_DIFS : DIFS);
  471. rt2x00_set_field32(&reg, CSR19_EIFS, EIFS);
  472. rt2x00pci_register_write(rt2x00dev, CSR19, reg);
  473. rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
  474. rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
  475. rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
  476. rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
  477. rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
  478. rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, beacon_int * 16);
  479. rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, beacon_int * 16);
  480. rt2x00pci_register_write(rt2x00dev, CSR12, reg);
  481. }
  482. static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
  483. const unsigned int flags,
  484. struct ieee80211_conf *conf)
  485. {
  486. int short_slot_time = conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME;
  487. if (flags & CONFIG_UPDATE_PHYMODE)
  488. rt2500pci_config_phymode(rt2x00dev, conf->phymode);
  489. if (flags & CONFIG_UPDATE_CHANNEL)
  490. rt2500pci_config_channel(rt2x00dev, conf->channel_val,
  491. conf->channel, conf->power_level);
  492. if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
  493. rt2500pci_config_txpower(rt2x00dev, conf->power_level);
  494. if (flags & CONFIG_UPDATE_ANTENNA)
  495. rt2500pci_config_antenna(rt2x00dev, conf->antenna_sel_tx,
  496. conf->antenna_sel_rx);
  497. if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
  498. rt2500pci_config_duration(rt2x00dev, short_slot_time,
  499. conf->beacon_int);
  500. }
  501. /*
  502. * LED functions.
  503. */
  504. static void rt2500pci_enable_led(struct rt2x00_dev *rt2x00dev)
  505. {
  506. u32 reg;
  507. rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
  508. rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
  509. rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
  510. if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
  511. rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
  512. rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
  513. } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
  514. rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
  515. rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
  516. } else {
  517. rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
  518. rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
  519. }
  520. rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
  521. }
  522. static void rt2500pci_disable_led(struct rt2x00_dev *rt2x00dev)
  523. {
  524. u32 reg;
  525. rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
  526. rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
  527. rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
  528. rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
  529. }
  530. /*
  531. * Link tuning
  532. */
  533. static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev)
  534. {
  535. u32 reg;
  536. /*
  537. * Update FCS error count from register.
  538. */
  539. rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
  540. rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
  541. /*
  542. * Update False CCA count from register.
  543. */
  544. rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
  545. rt2x00dev->link.false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
  546. }
  547. static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
  548. {
  549. rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
  550. rt2x00dev->link.vgc_level = 0x48;
  551. }
  552. static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
  553. {
  554. int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
  555. u8 r17;
  556. /*
  557. * To prevent collisions with MAC ASIC on chipsets
  558. * up to version C the link tuning should halt after 20
  559. * seconds.
  560. */
  561. if (rt2x00_get_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
  562. rt2x00dev->link.count > 20)
  563. return;
  564. rt2500pci_bbp_read(rt2x00dev, 17, &r17);
  565. /*
  566. * Chipset versions C and lower should directly continue
  567. * to the dynamic CCA tuning.
  568. */
  569. if (rt2x00_get_rev(&rt2x00dev->chip) < RT2560_VERSION_D)
  570. goto dynamic_cca_tune;
  571. /*
  572. * A too low RSSI will cause too much false CCA which will
  573. * then corrupt the R17 tuning. To remidy this the tuning should
  574. * be stopped (While making sure the R17 value will not exceed limits)
  575. */
  576. if (rssi < -80 && rt2x00dev->link.count > 20) {
  577. if (r17 >= 0x41) {
  578. r17 = rt2x00dev->link.vgc_level;
  579. rt2500pci_bbp_write(rt2x00dev, 17, r17);
  580. }
  581. return;
  582. }
  583. /*
  584. * Special big-R17 for short distance
  585. */
  586. if (rssi >= -58) {
  587. if (r17 != 0x50)
  588. rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
  589. return;
  590. }
  591. /*
  592. * Special mid-R17 for middle distance
  593. */
  594. if (rssi >= -74) {
  595. if (r17 != 0x41)
  596. rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
  597. return;
  598. }
  599. /*
  600. * Leave short or middle distance condition, restore r17
  601. * to the dynamic tuning range.
  602. */
  603. if (r17 >= 0x41) {
  604. rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
  605. return;
  606. }
  607. dynamic_cca_tune:
  608. /*
  609. * R17 is inside the dynamic tuning range,
  610. * start tuning the link based on the false cca counter.
  611. */
  612. if (rt2x00dev->link.false_cca > 512 && r17 < 0x40) {
  613. rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
  614. rt2x00dev->link.vgc_level = r17;
  615. } else if (rt2x00dev->link.false_cca < 100 && r17 > 0x32) {
  616. rt2500pci_bbp_write(rt2x00dev, 17, --r17);
  617. rt2x00dev->link.vgc_level = r17;
  618. }
  619. }
  620. /*
  621. * Initialization functions.
  622. */
  623. static void rt2500pci_init_rxring(struct rt2x00_dev *rt2x00dev)
  624. {
  625. struct data_ring *ring = rt2x00dev->rx;
  626. struct data_desc *rxd;
  627. unsigned int i;
  628. u32 word;
  629. memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
  630. for (i = 0; i < ring->stats.limit; i++) {
  631. rxd = ring->entry[i].priv;
  632. rt2x00_desc_read(rxd, 1, &word);
  633. rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
  634. ring->entry[i].data_dma);
  635. rt2x00_desc_write(rxd, 1, word);
  636. rt2x00_desc_read(rxd, 0, &word);
  637. rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
  638. rt2x00_desc_write(rxd, 0, word);
  639. }
  640. rt2x00_ring_index_clear(rt2x00dev->rx);
  641. }
  642. static void rt2500pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
  643. {
  644. struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
  645. struct data_desc *txd;
  646. unsigned int i;
  647. u32 word;
  648. memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
  649. for (i = 0; i < ring->stats.limit; i++) {
  650. txd = ring->entry[i].priv;
  651. rt2x00_desc_read(txd, 1, &word);
  652. rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
  653. ring->entry[i].data_dma);
  654. rt2x00_desc_write(txd, 1, word);
  655. rt2x00_desc_read(txd, 0, &word);
  656. rt2x00_set_field32(&word, TXD_W0_VALID, 0);
  657. rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
  658. rt2x00_desc_write(txd, 0, word);
  659. }
  660. rt2x00_ring_index_clear(ring);
  661. }
  662. static int rt2500pci_init_rings(struct rt2x00_dev *rt2x00dev)
  663. {
  664. u32 reg;
  665. /*
  666. * Initialize rings.
  667. */
  668. rt2500pci_init_rxring(rt2x00dev);
  669. rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
  670. rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
  671. rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
  672. rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
  673. /*
  674. * Initialize registers.
  675. */
  676. rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
  677. rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
  678. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
  679. rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
  680. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
  681. rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
  682. rt2x00dev->bcn[1].stats.limit);
  683. rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
  684. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
  685. rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
  686. rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
  687. rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
  688. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
  689. rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
  690. rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
  691. rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
  692. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
  693. rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
  694. rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
  695. rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
  696. rt2x00dev->bcn[1].data_dma);
  697. rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
  698. rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
  699. rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
  700. rt2x00dev->bcn[0].data_dma);
  701. rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
  702. rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
  703. rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
  704. rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
  705. rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
  706. rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
  707. rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
  708. rt2x00dev->rx->data_dma);
  709. rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
  710. return 0;
  711. }
  712. static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
  713. {
  714. u32 reg;
  715. rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
  716. rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
  717. rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
  718. rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
  719. rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
  720. rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
  721. rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
  722. rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
  723. rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
  724. rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
  725. rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
  726. rt2x00dev->rx->data_size / 128);
  727. rt2x00pci_register_write(rt2x00dev, CSR9, reg);
  728. /*
  729. * Always use CWmin and CWmax set in descriptor.
  730. */
  731. rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
  732. rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
  733. rt2x00pci_register_write(rt2x00dev, CSR11, reg);
  734. rt2x00pci_register_write(rt2x00dev, CNT3, 0);
  735. rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
  736. rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
  737. rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
  738. rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
  739. rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
  740. rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
  741. rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
  742. rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
  743. rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
  744. rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
  745. rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
  746. rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
  747. rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
  748. rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
  749. rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
  750. rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
  751. rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
  752. rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
  753. rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
  754. rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
  755. rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
  756. rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
  757. rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
  758. rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
  759. rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
  760. rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
  761. rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
  762. rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
  763. rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
  764. rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
  765. rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
  766. rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
  767. rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
  768. rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
  769. rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
  770. rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
  771. rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
  772. rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
  773. rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
  774. rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
  775. rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
  776. rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
  777. rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
  778. rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
  779. rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
  780. rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
  781. rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
  782. rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
  783. rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
  784. rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
  785. if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
  786. return -EBUSY;
  787. rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
  788. rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
  789. rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
  790. rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
  791. rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
  792. rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
  793. rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
  794. rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
  795. rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
  796. rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
  797. rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
  798. rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
  799. rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
  800. rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
  801. rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
  802. rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
  803. rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
  804. rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
  805. rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
  806. rt2x00pci_register_write(rt2x00dev, CSR1, reg);
  807. rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
  808. rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
  809. rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
  810. rt2x00pci_register_write(rt2x00dev, CSR1, reg);
  811. /*
  812. * We must clear the FCS and FIFO error count.
  813. * These registers are cleared on read,
  814. * so we may pass a useless variable to store the value.
  815. */
  816. rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
  817. rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
  818. return 0;
  819. }
  820. static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
  821. {
  822. unsigned int i;
  823. u16 eeprom;
  824. u8 reg_id;
  825. u8 value;
  826. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  827. rt2500pci_bbp_read(rt2x00dev, 0, &value);
  828. if ((value != 0xff) && (value != 0x00))
  829. goto continue_csr_init;
  830. NOTICE(rt2x00dev, "Waiting for BBP register.\n");
  831. udelay(REGISTER_BUSY_DELAY);
  832. }
  833. ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
  834. return -EACCES;
  835. continue_csr_init:
  836. rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
  837. rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
  838. rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
  839. rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
  840. rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
  841. rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
  842. rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
  843. rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
  844. rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
  845. rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
  846. rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
  847. rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
  848. rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
  849. rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
  850. rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
  851. rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
  852. rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
  853. rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
  854. rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
  855. rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
  856. rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
  857. rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
  858. rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
  859. rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
  860. rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
  861. rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
  862. rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
  863. rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
  864. rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
  865. rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
  866. DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
  867. for (i = 0; i < EEPROM_BBP_SIZE; i++) {
  868. rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
  869. if (eeprom != 0xffff && eeprom != 0x0000) {
  870. reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
  871. value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
  872. DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
  873. reg_id, value);
  874. rt2500pci_bbp_write(rt2x00dev, reg_id, value);
  875. }
  876. }
  877. DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
  878. return 0;
  879. }
  880. /*
  881. * Device state switch handlers.
  882. */
  883. static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
  884. enum dev_state state)
  885. {
  886. u32 reg;
  887. rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
  888. rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
  889. state == STATE_RADIO_RX_OFF);
  890. rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
  891. }
  892. static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
  893. enum dev_state state)
  894. {
  895. int mask = (state == STATE_RADIO_IRQ_OFF);
  896. u32 reg;
  897. /*
  898. * When interrupts are being enabled, the interrupt registers
  899. * should clear the register to assure a clean state.
  900. */
  901. if (state == STATE_RADIO_IRQ_ON) {
  902. rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
  903. rt2x00pci_register_write(rt2x00dev, CSR7, reg);
  904. }
  905. /*
  906. * Only toggle the interrupts bits we are going to use.
  907. * Non-checked interrupt bits are disabled by default.
  908. */
  909. rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
  910. rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
  911. rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
  912. rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
  913. rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
  914. rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
  915. rt2x00pci_register_write(rt2x00dev, CSR8, reg);
  916. }
  917. static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
  918. {
  919. /*
  920. * Initialize all registers.
  921. */
  922. if (rt2500pci_init_rings(rt2x00dev) ||
  923. rt2500pci_init_registers(rt2x00dev) ||
  924. rt2500pci_init_bbp(rt2x00dev)) {
  925. ERROR(rt2x00dev, "Register initialization failed.\n");
  926. return -EIO;
  927. }
  928. /*
  929. * Enable interrupts.
  930. */
  931. rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
  932. /*
  933. * Enable LED
  934. */
  935. rt2500pci_enable_led(rt2x00dev);
  936. return 0;
  937. }
  938. static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
  939. {
  940. u32 reg;
  941. /*
  942. * Disable LED
  943. */
  944. rt2500pci_disable_led(rt2x00dev);
  945. rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
  946. /*
  947. * Disable synchronisation.
  948. */
  949. rt2x00pci_register_write(rt2x00dev, CSR14, 0);
  950. /*
  951. * Cancel RX and TX.
  952. */
  953. rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
  954. rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
  955. rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
  956. /*
  957. * Disable interrupts.
  958. */
  959. rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
  960. }
  961. static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
  962. enum dev_state state)
  963. {
  964. u32 reg;
  965. unsigned int i;
  966. char put_to_sleep;
  967. char bbp_state;
  968. char rf_state;
  969. put_to_sleep = (state != STATE_AWAKE);
  970. rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
  971. rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
  972. rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
  973. rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
  974. rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
  975. rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
  976. /*
  977. * Device is not guaranteed to be in the requested state yet.
  978. * We must wait until the register indicates that the
  979. * device has entered the correct state.
  980. */
  981. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  982. rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
  983. bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
  984. rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
  985. if (bbp_state == state && rf_state == state)
  986. return 0;
  987. msleep(10);
  988. }
  989. NOTICE(rt2x00dev, "Device failed to enter state %d, "
  990. "current device state: bbp %d and rf %d.\n",
  991. state, bbp_state, rf_state);
  992. return -EBUSY;
  993. }
  994. static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
  995. enum dev_state state)
  996. {
  997. int retval = 0;
  998. switch (state) {
  999. case STATE_RADIO_ON:
  1000. retval = rt2500pci_enable_radio(rt2x00dev);
  1001. break;
  1002. case STATE_RADIO_OFF:
  1003. rt2500pci_disable_radio(rt2x00dev);
  1004. break;
  1005. case STATE_RADIO_RX_ON:
  1006. case STATE_RADIO_RX_OFF:
  1007. rt2500pci_toggle_rx(rt2x00dev, state);
  1008. break;
  1009. case STATE_DEEP_SLEEP:
  1010. case STATE_SLEEP:
  1011. case STATE_STANDBY:
  1012. case STATE_AWAKE:
  1013. retval = rt2500pci_set_state(rt2x00dev, state);
  1014. break;
  1015. default:
  1016. retval = -ENOTSUPP;
  1017. break;
  1018. }
  1019. return retval;
  1020. }
  1021. /*
  1022. * TX descriptor initialization
  1023. */
  1024. static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
  1025. struct data_desc *txd,
  1026. struct txdata_entry_desc *desc,
  1027. struct ieee80211_hdr *ieee80211hdr,
  1028. unsigned int length,
  1029. struct ieee80211_tx_control *control)
  1030. {
  1031. u32 word;
  1032. /*
  1033. * Start writing the descriptor words.
  1034. */
  1035. rt2x00_desc_read(txd, 2, &word);
  1036. rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
  1037. rt2x00_set_field32(&word, TXD_W2_AIFS, desc->aifs);
  1038. rt2x00_set_field32(&word, TXD_W2_CWMIN, desc->cw_min);
  1039. rt2x00_set_field32(&word, TXD_W2_CWMAX, desc->cw_max);
  1040. rt2x00_desc_write(txd, 2, word);
  1041. rt2x00_desc_read(txd, 3, &word);
  1042. rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, desc->signal);
  1043. rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, desc->service);
  1044. rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, desc->length_low);
  1045. rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, desc->length_high);
  1046. rt2x00_desc_write(txd, 3, word);
  1047. rt2x00_desc_read(txd, 10, &word);
  1048. rt2x00_set_field32(&word, TXD_W10_RTS,
  1049. test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
  1050. rt2x00_desc_write(txd, 10, word);
  1051. rt2x00_desc_read(txd, 0, &word);
  1052. rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
  1053. rt2x00_set_field32(&word, TXD_W0_VALID, 1);
  1054. rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
  1055. test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
  1056. rt2x00_set_field32(&word, TXD_W0_ACK,
  1057. !(control->flags & IEEE80211_TXCTL_NO_ACK));
  1058. rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
  1059. test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
  1060. rt2x00_set_field32(&word, TXD_W0_OFDM,
  1061. test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
  1062. rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
  1063. rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
  1064. rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
  1065. !!(control->flags &
  1066. IEEE80211_TXCTL_LONG_RETRY_LIMIT));
  1067. rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
  1068. rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
  1069. rt2x00_desc_write(txd, 0, word);
  1070. }
  1071. /*
  1072. * TX data initialization
  1073. */
  1074. static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
  1075. unsigned int queue)
  1076. {
  1077. u32 reg;
  1078. if (queue == IEEE80211_TX_QUEUE_BEACON) {
  1079. rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
  1080. if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
  1081. rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
  1082. rt2x00pci_register_write(rt2x00dev, CSR14, reg);
  1083. }
  1084. return;
  1085. }
  1086. rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
  1087. if (queue == IEEE80211_TX_QUEUE_DATA0)
  1088. rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
  1089. else if (queue == IEEE80211_TX_QUEUE_DATA1)
  1090. rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
  1091. else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
  1092. rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
  1093. rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
  1094. }
  1095. /*
  1096. * RX control handlers
  1097. */
  1098. static void rt2500pci_fill_rxdone(struct data_entry *entry,
  1099. struct rxdata_entry_desc *desc)
  1100. {
  1101. struct data_desc *rxd = entry->priv;
  1102. u32 word0;
  1103. u32 word2;
  1104. rt2x00_desc_read(rxd, 0, &word0);
  1105. rt2x00_desc_read(rxd, 2, &word2);
  1106. desc->flags = 0;
  1107. if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
  1108. desc->flags |= RX_FLAG_FAILED_FCS_CRC;
  1109. if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
  1110. desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
  1111. desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
  1112. desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
  1113. entry->ring->rt2x00dev->rssi_offset;
  1114. desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
  1115. desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
  1116. }
  1117. /*
  1118. * Interrupt functions.
  1119. */
  1120. static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
  1121. {
  1122. struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
  1123. struct data_entry *entry;
  1124. struct data_desc *txd;
  1125. u32 word;
  1126. int tx_status;
  1127. int retry;
  1128. while (!rt2x00_ring_empty(ring)) {
  1129. entry = rt2x00_get_data_entry_done(ring);
  1130. txd = entry->priv;
  1131. rt2x00_desc_read(txd, 0, &word);
  1132. if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
  1133. !rt2x00_get_field32(word, TXD_W0_VALID))
  1134. break;
  1135. /*
  1136. * Obtain the status about this packet.
  1137. */
  1138. tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
  1139. retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
  1140. rt2x00lib_txdone(entry, tx_status, retry);
  1141. /*
  1142. * Make this entry available for reuse.
  1143. */
  1144. entry->flags = 0;
  1145. rt2x00_set_field32(&word, TXD_W0_VALID, 0);
  1146. rt2x00_desc_write(txd, 0, word);
  1147. rt2x00_ring_index_done_inc(ring);
  1148. }
  1149. /*
  1150. * If the data ring was full before the txdone handler
  1151. * we must make sure the packet queue in the mac80211 stack
  1152. * is reenabled when the txdone handler has finished.
  1153. */
  1154. entry = ring->entry;
  1155. if (!rt2x00_ring_full(ring))
  1156. ieee80211_wake_queue(rt2x00dev->hw,
  1157. entry->tx_status.control.queue);
  1158. }
  1159. static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
  1160. {
  1161. struct rt2x00_dev *rt2x00dev = dev_instance;
  1162. u32 reg;
  1163. /*
  1164. * Get the interrupt sources & saved to local variable.
  1165. * Write register value back to clear pending interrupts.
  1166. */
  1167. rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
  1168. rt2x00pci_register_write(rt2x00dev, CSR7, reg);
  1169. if (!reg)
  1170. return IRQ_NONE;
  1171. if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
  1172. return IRQ_HANDLED;
  1173. /*
  1174. * Handle interrupts, walk through all bits
  1175. * and run the tasks, the bits are checked in order of
  1176. * priority.
  1177. */
  1178. /*
  1179. * 1 - Beacon timer expired interrupt.
  1180. */
  1181. if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
  1182. rt2x00lib_beacondone(rt2x00dev);
  1183. /*
  1184. * 2 - Rx ring done interrupt.
  1185. */
  1186. if (rt2x00_get_field32(reg, CSR7_RXDONE))
  1187. rt2x00pci_rxdone(rt2x00dev);
  1188. /*
  1189. * 3 - Atim ring transmit done interrupt.
  1190. */
  1191. if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
  1192. rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
  1193. /*
  1194. * 4 - Priority ring transmit done interrupt.
  1195. */
  1196. if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
  1197. rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
  1198. /*
  1199. * 5 - Tx ring transmit done interrupt.
  1200. */
  1201. if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
  1202. rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
  1203. return IRQ_HANDLED;
  1204. }
  1205. /*
  1206. * Device probe functions.
  1207. */
  1208. static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
  1209. {
  1210. struct eeprom_93cx6 eeprom;
  1211. u32 reg;
  1212. u16 word;
  1213. u8 *mac;
  1214. rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
  1215. eeprom.data = rt2x00dev;
  1216. eeprom.register_read = rt2500pci_eepromregister_read;
  1217. eeprom.register_write = rt2500pci_eepromregister_write;
  1218. eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
  1219. PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
  1220. eeprom.reg_data_in = 0;
  1221. eeprom.reg_data_out = 0;
  1222. eeprom.reg_data_clock = 0;
  1223. eeprom.reg_chip_select = 0;
  1224. eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
  1225. EEPROM_SIZE / sizeof(u16));
  1226. /*
  1227. * Start validation of the data that has been read.
  1228. */
  1229. mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
  1230. if (!is_valid_ether_addr(mac)) {
  1231. DECLARE_MAC_BUF(macbuf);
  1232. random_ether_addr(mac);
  1233. EEPROM(rt2x00dev, "MAC: %s\n",
  1234. print_mac(macbuf, mac));
  1235. }
  1236. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
  1237. if (word == 0xffff) {
  1238. rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
  1239. rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 0);
  1240. rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 0);
  1241. rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE, 0);
  1242. rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
  1243. rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
  1244. rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
  1245. rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
  1246. EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
  1247. }
  1248. rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
  1249. if (word == 0xffff) {
  1250. rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
  1251. rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
  1252. rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
  1253. rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
  1254. EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
  1255. }
  1256. rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
  1257. if (word == 0xffff) {
  1258. rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
  1259. DEFAULT_RSSI_OFFSET);
  1260. rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
  1261. EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
  1262. }
  1263. return 0;
  1264. }
  1265. static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
  1266. {
  1267. u32 reg;
  1268. u16 value;
  1269. u16 eeprom;
  1270. /*
  1271. * Read EEPROM word for configuration.
  1272. */
  1273. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
  1274. /*
  1275. * Identify RF chipset.
  1276. */
  1277. value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
  1278. rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
  1279. rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
  1280. if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
  1281. !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
  1282. !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
  1283. !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
  1284. !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
  1285. !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
  1286. ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
  1287. return -ENODEV;
  1288. }
  1289. /*
  1290. * Identify default antenna configuration.
  1291. */
  1292. rt2x00dev->hw->conf.antenna_sel_tx =
  1293. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
  1294. rt2x00dev->hw->conf.antenna_sel_rx =
  1295. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
  1296. /*
  1297. * Store led mode, for correct led behaviour.
  1298. */
  1299. rt2x00dev->led_mode =
  1300. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
  1301. /*
  1302. * Detect if this device has an hardware controlled radio.
  1303. */
  1304. #ifdef CONFIG_RT2500PCI_RFKILL
  1305. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
  1306. __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
  1307. #endif /* CONFIG_RT2500PCI_RFKILL */
  1308. /*
  1309. * Check if the BBP tuning should be enabled.
  1310. */
  1311. rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
  1312. if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
  1313. __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
  1314. /*
  1315. * Read the RSSI <-> dBm offset information.
  1316. */
  1317. rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
  1318. rt2x00dev->rssi_offset =
  1319. rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
  1320. return 0;
  1321. }
  1322. /*
  1323. * RF value list for RF2522
  1324. * Supports: 2.4 GHz
  1325. */
  1326. static const struct rf_channel rf_vals_bg_2522[] = {
  1327. { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
  1328. { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
  1329. { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
  1330. { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
  1331. { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
  1332. { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
  1333. { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
  1334. { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
  1335. { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
  1336. { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
  1337. { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
  1338. { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
  1339. { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
  1340. { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
  1341. };
  1342. /*
  1343. * RF value list for RF2523
  1344. * Supports: 2.4 GHz
  1345. */
  1346. static const struct rf_channel rf_vals_bg_2523[] = {
  1347. { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
  1348. { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
  1349. { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
  1350. { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
  1351. { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
  1352. { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
  1353. { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
  1354. { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
  1355. { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
  1356. { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
  1357. { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
  1358. { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
  1359. { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
  1360. { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
  1361. };
  1362. /*
  1363. * RF value list for RF2524
  1364. * Supports: 2.4 GHz
  1365. */
  1366. static const struct rf_channel rf_vals_bg_2524[] = {
  1367. { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
  1368. { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
  1369. { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
  1370. { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
  1371. { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
  1372. { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
  1373. { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
  1374. { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
  1375. { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
  1376. { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
  1377. { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
  1378. { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
  1379. { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
  1380. { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
  1381. };
  1382. /*
  1383. * RF value list for RF2525
  1384. * Supports: 2.4 GHz
  1385. */
  1386. static const struct rf_channel rf_vals_bg_2525[] = {
  1387. { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
  1388. { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
  1389. { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
  1390. { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
  1391. { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
  1392. { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
  1393. { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
  1394. { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
  1395. { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
  1396. { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
  1397. { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
  1398. { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
  1399. { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
  1400. { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
  1401. };
  1402. /*
  1403. * RF value list for RF2525e
  1404. * Supports: 2.4 GHz
  1405. */
  1406. static const struct rf_channel rf_vals_bg_2525e[] = {
  1407. { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
  1408. { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
  1409. { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
  1410. { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
  1411. { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
  1412. { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
  1413. { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
  1414. { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
  1415. { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
  1416. { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
  1417. { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
  1418. { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
  1419. { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
  1420. { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
  1421. };
  1422. /*
  1423. * RF value list for RF5222
  1424. * Supports: 2.4 GHz & 5.2 GHz
  1425. */
  1426. static const struct rf_channel rf_vals_5222[] = {
  1427. { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
  1428. { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
  1429. { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
  1430. { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
  1431. { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
  1432. { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
  1433. { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
  1434. { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
  1435. { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
  1436. { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
  1437. { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
  1438. { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
  1439. { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
  1440. { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
  1441. /* 802.11 UNI / HyperLan 2 */
  1442. { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
  1443. { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
  1444. { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
  1445. { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
  1446. { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
  1447. { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
  1448. { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
  1449. { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
  1450. /* 802.11 HyperLan 2 */
  1451. { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
  1452. { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
  1453. { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
  1454. { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
  1455. { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
  1456. { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
  1457. { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
  1458. { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
  1459. { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
  1460. { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
  1461. /* 802.11 UNII */
  1462. { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
  1463. { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
  1464. { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
  1465. { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
  1466. { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
  1467. };
  1468. static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
  1469. {
  1470. struct hw_mode_spec *spec = &rt2x00dev->spec;
  1471. u8 *txpower;
  1472. unsigned int i;
  1473. /*
  1474. * Initialize all hw fields.
  1475. */
  1476. rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
  1477. rt2x00dev->hw->extra_tx_headroom = 0;
  1478. rt2x00dev->hw->max_signal = MAX_SIGNAL;
  1479. rt2x00dev->hw->max_rssi = MAX_RX_SSI;
  1480. rt2x00dev->hw->queues = 2;
  1481. SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
  1482. SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
  1483. rt2x00_eeprom_addr(rt2x00dev,
  1484. EEPROM_MAC_ADDR_0));
  1485. /*
  1486. * Convert tx_power array in eeprom.
  1487. */
  1488. txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
  1489. for (i = 0; i < 14; i++)
  1490. txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
  1491. /*
  1492. * Initialize hw_mode information.
  1493. */
  1494. spec->num_modes = 2;
  1495. spec->num_rates = 12;
  1496. spec->tx_power_a = NULL;
  1497. spec->tx_power_bg = txpower;
  1498. spec->tx_power_default = DEFAULT_TXPOWER;
  1499. if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
  1500. spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
  1501. spec->channels = rf_vals_bg_2522;
  1502. } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
  1503. spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
  1504. spec->channels = rf_vals_bg_2523;
  1505. } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
  1506. spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
  1507. spec->channels = rf_vals_bg_2524;
  1508. } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
  1509. spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
  1510. spec->channels = rf_vals_bg_2525;
  1511. } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
  1512. spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
  1513. spec->channels = rf_vals_bg_2525e;
  1514. } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
  1515. spec->num_channels = ARRAY_SIZE(rf_vals_5222);
  1516. spec->channels = rf_vals_5222;
  1517. spec->num_modes = 3;
  1518. }
  1519. }
  1520. static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
  1521. {
  1522. int retval;
  1523. /*
  1524. * Allocate eeprom data.
  1525. */
  1526. retval = rt2500pci_validate_eeprom(rt2x00dev);
  1527. if (retval)
  1528. return retval;
  1529. retval = rt2500pci_init_eeprom(rt2x00dev);
  1530. if (retval)
  1531. return retval;
  1532. /*
  1533. * Initialize hw specifications.
  1534. */
  1535. rt2500pci_probe_hw_mode(rt2x00dev);
  1536. /*
  1537. * This device requires the beacon ring
  1538. */
  1539. __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
  1540. /*
  1541. * Set the rssi offset.
  1542. */
  1543. rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
  1544. return 0;
  1545. }
  1546. /*
  1547. * IEEE80211 stack callback functions.
  1548. */
  1549. static void rt2500pci_configure_filter(struct ieee80211_hw *hw,
  1550. unsigned int changed_flags,
  1551. unsigned int *total_flags,
  1552. int mc_count,
  1553. struct dev_addr_list *mc_list)
  1554. {
  1555. struct rt2x00_dev *rt2x00dev = hw->priv;
  1556. struct interface *intf = &rt2x00dev->interface;
  1557. u32 reg;
  1558. /*
  1559. * Mask off any flags we are going to ignore from
  1560. * the total_flags field.
  1561. */
  1562. *total_flags &=
  1563. FIF_ALLMULTI |
  1564. FIF_FCSFAIL |
  1565. FIF_PLCPFAIL |
  1566. FIF_CONTROL |
  1567. FIF_OTHER_BSS |
  1568. FIF_PROMISC_IN_BSS;
  1569. /*
  1570. * Apply some rules to the filters:
  1571. * - Some filters imply different filters to be set.
  1572. * - Some things we can't filter out at all.
  1573. * - Some filters are set based on interface type.
  1574. */
  1575. if (mc_count)
  1576. *total_flags |= FIF_ALLMULTI;
  1577. if (*total_flags & FIF_OTHER_BSS ||
  1578. *total_flags & FIF_PROMISC_IN_BSS)
  1579. *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
  1580. if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
  1581. *total_flags |= FIF_PROMISC_IN_BSS;
  1582. /*
  1583. * Check if there is any work left for us.
  1584. */
  1585. if (intf->filter == *total_flags)
  1586. return;
  1587. intf->filter = *total_flags;
  1588. /*
  1589. * Start configuration steps.
  1590. * Note that the version error will always be dropped
  1591. * and broadcast frames will always be accepted since
  1592. * there is no filter for it at this time.
  1593. */
  1594. rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
  1595. rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
  1596. !(*total_flags & FIF_FCSFAIL));
  1597. rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
  1598. !(*total_flags & FIF_PLCPFAIL));
  1599. rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
  1600. !(*total_flags & FIF_CONTROL));
  1601. rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
  1602. !(*total_flags & FIF_PROMISC_IN_BSS));
  1603. rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
  1604. !(*total_flags & FIF_PROMISC_IN_BSS));
  1605. rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
  1606. rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
  1607. !(*total_flags & FIF_ALLMULTI));
  1608. rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
  1609. rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
  1610. }
  1611. static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
  1612. u32 short_retry, u32 long_retry)
  1613. {
  1614. struct rt2x00_dev *rt2x00dev = hw->priv;
  1615. u32 reg;
  1616. rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
  1617. rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
  1618. rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
  1619. rt2x00pci_register_write(rt2x00dev, CSR11, reg);
  1620. return 0;
  1621. }
  1622. static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
  1623. {
  1624. struct rt2x00_dev *rt2x00dev = hw->priv;
  1625. u64 tsf;
  1626. u32 reg;
  1627. rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
  1628. tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
  1629. rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
  1630. tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
  1631. return tsf;
  1632. }
  1633. static void rt2500pci_reset_tsf(struct ieee80211_hw *hw)
  1634. {
  1635. struct rt2x00_dev *rt2x00dev = hw->priv;
  1636. rt2x00pci_register_write(rt2x00dev, CSR16, 0);
  1637. rt2x00pci_register_write(rt2x00dev, CSR17, 0);
  1638. }
  1639. static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
  1640. {
  1641. struct rt2x00_dev *rt2x00dev = hw->priv;
  1642. u32 reg;
  1643. rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
  1644. return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
  1645. }
  1646. static const struct ieee80211_ops rt2500pci_mac80211_ops = {
  1647. .tx = rt2x00mac_tx,
  1648. .start = rt2x00mac_start,
  1649. .stop = rt2x00mac_stop,
  1650. .add_interface = rt2x00mac_add_interface,
  1651. .remove_interface = rt2x00mac_remove_interface,
  1652. .config = rt2x00mac_config,
  1653. .config_interface = rt2x00mac_config_interface,
  1654. .configure_filter = rt2500pci_configure_filter,
  1655. .get_stats = rt2x00mac_get_stats,
  1656. .set_retry_limit = rt2500pci_set_retry_limit,
  1657. .conf_tx = rt2x00mac_conf_tx,
  1658. .get_tx_stats = rt2x00mac_get_tx_stats,
  1659. .get_tsf = rt2500pci_get_tsf,
  1660. .reset_tsf = rt2500pci_reset_tsf,
  1661. .beacon_update = rt2x00pci_beacon_update,
  1662. .tx_last_beacon = rt2500pci_tx_last_beacon,
  1663. };
  1664. static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
  1665. .irq_handler = rt2500pci_interrupt,
  1666. .probe_hw = rt2500pci_probe_hw,
  1667. .initialize = rt2x00pci_initialize,
  1668. .uninitialize = rt2x00pci_uninitialize,
  1669. .set_device_state = rt2500pci_set_device_state,
  1670. .rfkill_poll = rt2500pci_rfkill_poll,
  1671. .link_stats = rt2500pci_link_stats,
  1672. .reset_tuner = rt2500pci_reset_tuner,
  1673. .link_tuner = rt2500pci_link_tuner,
  1674. .write_tx_desc = rt2500pci_write_tx_desc,
  1675. .write_tx_data = rt2x00pci_write_tx_data,
  1676. .kick_tx_queue = rt2500pci_kick_tx_queue,
  1677. .fill_rxdone = rt2500pci_fill_rxdone,
  1678. .config_mac_addr = rt2500pci_config_mac_addr,
  1679. .config_bssid = rt2500pci_config_bssid,
  1680. .config_type = rt2500pci_config_type,
  1681. .config = rt2500pci_config,
  1682. };
  1683. static const struct rt2x00_ops rt2500pci_ops = {
  1684. .name = DRV_NAME,
  1685. .rxd_size = RXD_DESC_SIZE,
  1686. .txd_size = TXD_DESC_SIZE,
  1687. .eeprom_size = EEPROM_SIZE,
  1688. .rf_size = RF_SIZE,
  1689. .lib = &rt2500pci_rt2x00_ops,
  1690. .hw = &rt2500pci_mac80211_ops,
  1691. #ifdef CONFIG_RT2X00_LIB_DEBUGFS
  1692. .debugfs = &rt2500pci_rt2x00debug,
  1693. #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
  1694. };
  1695. /*
  1696. * RT2500pci module information.
  1697. */
  1698. static struct pci_device_id rt2500pci_device_table[] = {
  1699. { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
  1700. { 0, }
  1701. };
  1702. MODULE_AUTHOR(DRV_PROJECT);
  1703. MODULE_VERSION(DRV_VERSION);
  1704. MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
  1705. MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
  1706. MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
  1707. MODULE_LICENSE("GPL");
  1708. static struct pci_driver rt2500pci_driver = {
  1709. .name = DRV_NAME,
  1710. .id_table = rt2500pci_device_table,
  1711. .probe = rt2x00pci_probe,
  1712. .remove = __devexit_p(rt2x00pci_remove),
  1713. .suspend = rt2x00pci_suspend,
  1714. .resume = rt2x00pci_resume,
  1715. };
  1716. static int __init rt2500pci_init(void)
  1717. {
  1718. return pci_register_driver(&rt2500pci_driver);
  1719. }
  1720. static void __exit rt2500pci_exit(void)
  1721. {
  1722. pci_unregister_driver(&rt2500pci_driver);
  1723. }
  1724. module_init(rt2500pci_init);
  1725. module_exit(rt2500pci_exit);