init.c 40 KB

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  1. /*
  2. * Copyright (c) 2011 Atheros Communications Inc.
  3. * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18. #include <linux/moduleparam.h>
  19. #include <linux/errno.h>
  20. #include <linux/export.h>
  21. #include <linux/of.h>
  22. #include <linux/mmc/sdio_func.h>
  23. #include "core.h"
  24. #include "cfg80211.h"
  25. #include "target.h"
  26. #include "debug.h"
  27. #include "hif-ops.h"
  28. static const struct ath6kl_hw hw_list[] = {
  29. {
  30. .id = AR6003_HW_2_0_VERSION,
  31. .name = "ar6003 hw 2.0",
  32. .dataset_patch_addr = 0x57e884,
  33. .app_load_addr = 0x543180,
  34. .board_ext_data_addr = 0x57e500,
  35. .reserved_ram_size = 6912,
  36. .refclk_hz = 26000000,
  37. .uarttx_pin = 8,
  38. /* hw2.0 needs override address hardcoded */
  39. .app_start_override_addr = 0x944C00,
  40. .fw = {
  41. .dir = AR6003_HW_2_0_FW_DIR,
  42. .otp = AR6003_HW_2_0_OTP_FILE,
  43. .fw = AR6003_HW_2_0_FIRMWARE_FILE,
  44. .tcmd = AR6003_HW_2_0_TCMD_FIRMWARE_FILE,
  45. .patch = AR6003_HW_2_0_PATCH_FILE,
  46. },
  47. .fw_board = AR6003_HW_2_0_BOARD_DATA_FILE,
  48. .fw_default_board = AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE,
  49. },
  50. {
  51. .id = AR6003_HW_2_1_1_VERSION,
  52. .name = "ar6003 hw 2.1.1",
  53. .dataset_patch_addr = 0x57ff74,
  54. .app_load_addr = 0x1234,
  55. .board_ext_data_addr = 0x542330,
  56. .reserved_ram_size = 512,
  57. .refclk_hz = 26000000,
  58. .uarttx_pin = 8,
  59. .testscript_addr = 0x57ef74,
  60. .fw = {
  61. .dir = AR6003_HW_2_1_1_FW_DIR,
  62. .otp = AR6003_HW_2_1_1_OTP_FILE,
  63. .fw = AR6003_HW_2_1_1_FIRMWARE_FILE,
  64. .tcmd = AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE,
  65. .patch = AR6003_HW_2_1_1_PATCH_FILE,
  66. .utf = AR6003_HW_2_1_1_UTF_FIRMWARE_FILE,
  67. .testscript = AR6003_HW_2_1_1_TESTSCRIPT_FILE,
  68. },
  69. .fw_board = AR6003_HW_2_1_1_BOARD_DATA_FILE,
  70. .fw_default_board = AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE,
  71. },
  72. {
  73. .id = AR6004_HW_1_0_VERSION,
  74. .name = "ar6004 hw 1.0",
  75. .dataset_patch_addr = 0x57e884,
  76. .app_load_addr = 0x1234,
  77. .board_ext_data_addr = 0x437000,
  78. .reserved_ram_size = 19456,
  79. .board_addr = 0x433900,
  80. .refclk_hz = 26000000,
  81. .uarttx_pin = 11,
  82. .fw = {
  83. .dir = AR6004_HW_1_0_FW_DIR,
  84. .fw = AR6004_HW_1_0_FIRMWARE_FILE,
  85. },
  86. .fw_board = AR6004_HW_1_0_BOARD_DATA_FILE,
  87. .fw_default_board = AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE,
  88. },
  89. {
  90. .id = AR6004_HW_1_1_VERSION,
  91. .name = "ar6004 hw 1.1",
  92. .dataset_patch_addr = 0x57e884,
  93. .app_load_addr = 0x1234,
  94. .board_ext_data_addr = 0x437000,
  95. .reserved_ram_size = 11264,
  96. .board_addr = 0x43d400,
  97. .refclk_hz = 40000000,
  98. .uarttx_pin = 11,
  99. .fw = {
  100. .dir = AR6004_HW_1_1_FW_DIR,
  101. .fw = AR6004_HW_1_1_FIRMWARE_FILE,
  102. },
  103. .fw_board = AR6004_HW_1_1_BOARD_DATA_FILE,
  104. .fw_default_board = AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE,
  105. },
  106. };
  107. /*
  108. * Include definitions here that can be used to tune the WLAN module
  109. * behavior. Different customers can tune the behavior as per their needs,
  110. * here.
  111. */
  112. /*
  113. * This configuration item enable/disable keepalive support.
  114. * Keepalive support: In the absence of any data traffic to AP, null
  115. * frames will be sent to the AP at periodic interval, to keep the association
  116. * active. This configuration item defines the periodic interval.
  117. * Use value of zero to disable keepalive support
  118. * Default: 60 seconds
  119. */
  120. #define WLAN_CONFIG_KEEP_ALIVE_INTERVAL 60
  121. /*
  122. * This configuration item sets the value of disconnect timeout
  123. * Firmware delays sending the disconnec event to the host for this
  124. * timeout after is gets disconnected from the current AP.
  125. * If the firmware successly roams within the disconnect timeout
  126. * it sends a new connect event
  127. */
  128. #define WLAN_CONFIG_DISCONNECT_TIMEOUT 10
  129. #define ATH6KL_DATA_OFFSET 64
  130. struct sk_buff *ath6kl_buf_alloc(int size)
  131. {
  132. struct sk_buff *skb;
  133. u16 reserved;
  134. /* Add chacheline space at front and back of buffer */
  135. reserved = (2 * L1_CACHE_BYTES) + ATH6KL_DATA_OFFSET +
  136. sizeof(struct htc_packet) + ATH6KL_HTC_ALIGN_BYTES;
  137. skb = dev_alloc_skb(size + reserved);
  138. if (skb)
  139. skb_reserve(skb, reserved - L1_CACHE_BYTES);
  140. return skb;
  141. }
  142. void ath6kl_init_profile_info(struct ath6kl_vif *vif)
  143. {
  144. vif->ssid_len = 0;
  145. memset(vif->ssid, 0, sizeof(vif->ssid));
  146. vif->dot11_auth_mode = OPEN_AUTH;
  147. vif->auth_mode = NONE_AUTH;
  148. vif->prwise_crypto = NONE_CRYPT;
  149. vif->prwise_crypto_len = 0;
  150. vif->grp_crypto = NONE_CRYPT;
  151. vif->grp_crypto_len = 0;
  152. memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list));
  153. memset(vif->req_bssid, 0, sizeof(vif->req_bssid));
  154. memset(vif->bssid, 0, sizeof(vif->bssid));
  155. vif->bss_ch = 0;
  156. }
  157. static int ath6kl_set_host_app_area(struct ath6kl *ar)
  158. {
  159. u32 address, data;
  160. struct host_app_area host_app_area;
  161. /* Fetch the address of the host_app_area_s
  162. * instance in the host interest area */
  163. address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_app_host_interest));
  164. address = TARG_VTOP(ar->target_type, address);
  165. if (ath6kl_diag_read32(ar, address, &data))
  166. return -EIO;
  167. address = TARG_VTOP(ar->target_type, data);
  168. host_app_area.wmi_protocol_ver = cpu_to_le32(WMI_PROTOCOL_VERSION);
  169. if (ath6kl_diag_write(ar, address, (u8 *) &host_app_area,
  170. sizeof(struct host_app_area)))
  171. return -EIO;
  172. return 0;
  173. }
  174. static inline void set_ac2_ep_map(struct ath6kl *ar,
  175. u8 ac,
  176. enum htc_endpoint_id ep)
  177. {
  178. ar->ac2ep_map[ac] = ep;
  179. ar->ep2ac_map[ep] = ac;
  180. }
  181. /* connect to a service */
  182. static int ath6kl_connectservice(struct ath6kl *ar,
  183. struct htc_service_connect_req *con_req,
  184. char *desc)
  185. {
  186. int status;
  187. struct htc_service_connect_resp response;
  188. memset(&response, 0, sizeof(response));
  189. status = ath6kl_htc_conn_service(ar->htc_target, con_req, &response);
  190. if (status) {
  191. ath6kl_err("failed to connect to %s service status:%d\n",
  192. desc, status);
  193. return status;
  194. }
  195. switch (con_req->svc_id) {
  196. case WMI_CONTROL_SVC:
  197. if (test_bit(WMI_ENABLED, &ar->flag))
  198. ath6kl_wmi_set_control_ep(ar->wmi, response.endpoint);
  199. ar->ctrl_ep = response.endpoint;
  200. break;
  201. case WMI_DATA_BE_SVC:
  202. set_ac2_ep_map(ar, WMM_AC_BE, response.endpoint);
  203. break;
  204. case WMI_DATA_BK_SVC:
  205. set_ac2_ep_map(ar, WMM_AC_BK, response.endpoint);
  206. break;
  207. case WMI_DATA_VI_SVC:
  208. set_ac2_ep_map(ar, WMM_AC_VI, response.endpoint);
  209. break;
  210. case WMI_DATA_VO_SVC:
  211. set_ac2_ep_map(ar, WMM_AC_VO, response.endpoint);
  212. break;
  213. default:
  214. ath6kl_err("service id is not mapped %d\n", con_req->svc_id);
  215. return -EINVAL;
  216. }
  217. return 0;
  218. }
  219. static int ath6kl_init_service_ep(struct ath6kl *ar)
  220. {
  221. struct htc_service_connect_req connect;
  222. memset(&connect, 0, sizeof(connect));
  223. /* these fields are the same for all service endpoints */
  224. connect.ep_cb.rx = ath6kl_rx;
  225. connect.ep_cb.rx_refill = ath6kl_rx_refill;
  226. connect.ep_cb.tx_full = ath6kl_tx_queue_full;
  227. /*
  228. * Set the max queue depth so that our ath6kl_tx_queue_full handler
  229. * gets called.
  230. */
  231. connect.max_txq_depth = MAX_DEFAULT_SEND_QUEUE_DEPTH;
  232. connect.ep_cb.rx_refill_thresh = ATH6KL_MAX_RX_BUFFERS / 4;
  233. if (!connect.ep_cb.rx_refill_thresh)
  234. connect.ep_cb.rx_refill_thresh++;
  235. /* connect to control service */
  236. connect.svc_id = WMI_CONTROL_SVC;
  237. if (ath6kl_connectservice(ar, &connect, "WMI CONTROL"))
  238. return -EIO;
  239. connect.flags |= HTC_FLGS_TX_BNDL_PAD_EN;
  240. /*
  241. * Limit the HTC message size on the send path, although e can
  242. * receive A-MSDU frames of 4K, we will only send ethernet-sized
  243. * (802.3) frames on the send path.
  244. */
  245. connect.max_rxmsg_sz = WMI_MAX_TX_DATA_FRAME_LENGTH;
  246. /*
  247. * To reduce the amount of committed memory for larger A_MSDU
  248. * frames, use the recv-alloc threshold mechanism for larger
  249. * packets.
  250. */
  251. connect.ep_cb.rx_alloc_thresh = ATH6KL_BUFFER_SIZE;
  252. connect.ep_cb.rx_allocthresh = ath6kl_alloc_amsdu_rxbuf;
  253. /*
  254. * For the remaining data services set the connection flag to
  255. * reduce dribbling, if configured to do so.
  256. */
  257. connect.conn_flags |= HTC_CONN_FLGS_REDUCE_CRED_DRIB;
  258. connect.conn_flags &= ~HTC_CONN_FLGS_THRESH_MASK;
  259. connect.conn_flags |= HTC_CONN_FLGS_THRESH_LVL_HALF;
  260. connect.svc_id = WMI_DATA_BE_SVC;
  261. if (ath6kl_connectservice(ar, &connect, "WMI DATA BE"))
  262. return -EIO;
  263. /* connect to back-ground map this to WMI LOW_PRI */
  264. connect.svc_id = WMI_DATA_BK_SVC;
  265. if (ath6kl_connectservice(ar, &connect, "WMI DATA BK"))
  266. return -EIO;
  267. /* connect to Video service, map this to to HI PRI */
  268. connect.svc_id = WMI_DATA_VI_SVC;
  269. if (ath6kl_connectservice(ar, &connect, "WMI DATA VI"))
  270. return -EIO;
  271. /*
  272. * Connect to VO service, this is currently not mapped to a WMI
  273. * priority stream due to historical reasons. WMI originally
  274. * defined 3 priorities over 3 mailboxes We can change this when
  275. * WMI is reworked so that priorities are not dependent on
  276. * mailboxes.
  277. */
  278. connect.svc_id = WMI_DATA_VO_SVC;
  279. if (ath6kl_connectservice(ar, &connect, "WMI DATA VO"))
  280. return -EIO;
  281. return 0;
  282. }
  283. void ath6kl_init_control_info(struct ath6kl_vif *vif)
  284. {
  285. ath6kl_init_profile_info(vif);
  286. vif->def_txkey_index = 0;
  287. memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list));
  288. vif->ch_hint = 0;
  289. }
  290. /*
  291. * Set HTC/Mbox operational parameters, this can only be called when the
  292. * target is in the BMI phase.
  293. */
  294. static int ath6kl_set_htc_params(struct ath6kl *ar, u32 mbox_isr_yield_val,
  295. u8 htc_ctrl_buf)
  296. {
  297. int status;
  298. u32 blk_size;
  299. blk_size = ar->mbox_info.block_size;
  300. if (htc_ctrl_buf)
  301. blk_size |= ((u32)htc_ctrl_buf) << 16;
  302. /* set the host interest area for the block size */
  303. status = ath6kl_bmi_write_hi32(ar, hi_mbox_io_block_sz, blk_size);
  304. if (status) {
  305. ath6kl_err("bmi_write_memory for IO block size failed\n");
  306. goto out;
  307. }
  308. ath6kl_dbg(ATH6KL_DBG_TRC, "block size set: %d (target addr:0x%X)\n",
  309. blk_size,
  310. ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_mbox_io_block_sz)));
  311. if (mbox_isr_yield_val) {
  312. /* set the host interest area for the mbox ISR yield limit */
  313. status = ath6kl_bmi_write_hi32(ar, hi_mbox_isr_yield_limit,
  314. mbox_isr_yield_val);
  315. if (status) {
  316. ath6kl_err("bmi_write_memory for yield limit failed\n");
  317. goto out;
  318. }
  319. }
  320. out:
  321. return status;
  322. }
  323. static int ath6kl_target_config_wlan_params(struct ath6kl *ar, int idx)
  324. {
  325. int ret;
  326. /*
  327. * Configure the device for rx dot11 header rules. "0,0" are the
  328. * default values. Required if checksum offload is needed. Set
  329. * RxMetaVersion to 2.
  330. */
  331. ret = ath6kl_wmi_set_rx_frame_format_cmd(ar->wmi, idx,
  332. ar->rx_meta_ver, 0, 0);
  333. if (ret) {
  334. ath6kl_err("unable to set the rx frame format: %d\n", ret);
  335. return ret;
  336. }
  337. if (ar->conf_flags & ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN) {
  338. ret = ath6kl_wmi_pmparams_cmd(ar->wmi, idx, 0, 1, 0, 0, 1,
  339. IGNORE_PS_FAIL_DURING_SCAN);
  340. if (ret) {
  341. ath6kl_err("unable to set power save fail event policy: %d\n",
  342. ret);
  343. return ret;
  344. }
  345. }
  346. if (!(ar->conf_flags & ATH6KL_CONF_IGNORE_ERP_BARKER)) {
  347. ret = ath6kl_wmi_set_lpreamble_cmd(ar->wmi, idx, 0,
  348. WMI_FOLLOW_BARKER_IN_ERP);
  349. if (ret) {
  350. ath6kl_err("unable to set barker preamble policy: %d\n",
  351. ret);
  352. return ret;
  353. }
  354. }
  355. ret = ath6kl_wmi_set_keepalive_cmd(ar->wmi, idx,
  356. WLAN_CONFIG_KEEP_ALIVE_INTERVAL);
  357. if (ret) {
  358. ath6kl_err("unable to set keep alive interval: %d\n", ret);
  359. return ret;
  360. }
  361. ret = ath6kl_wmi_disctimeout_cmd(ar->wmi, idx,
  362. WLAN_CONFIG_DISCONNECT_TIMEOUT);
  363. if (ret) {
  364. ath6kl_err("unable to set disconnect timeout: %d\n", ret);
  365. return ret;
  366. }
  367. if (!(ar->conf_flags & ATH6KL_CONF_ENABLE_TX_BURST)) {
  368. ret = ath6kl_wmi_set_wmm_txop(ar->wmi, idx, WMI_TXOP_DISABLED);
  369. if (ret) {
  370. ath6kl_err("unable to set txop bursting: %d\n", ret);
  371. return ret;
  372. }
  373. }
  374. if (ar->p2p && (ar->vif_max == 1 || idx)) {
  375. ret = ath6kl_wmi_info_req_cmd(ar->wmi, idx,
  376. P2P_FLAG_CAPABILITIES_REQ |
  377. P2P_FLAG_MACADDR_REQ |
  378. P2P_FLAG_HMODEL_REQ);
  379. if (ret) {
  380. ath6kl_dbg(ATH6KL_DBG_TRC, "failed to request P2P "
  381. "capabilities (%d) - assuming P2P not "
  382. "supported\n", ret);
  383. ar->p2p = false;
  384. }
  385. }
  386. if (ar->p2p && (ar->vif_max == 1 || idx)) {
  387. /* Enable Probe Request reporting for P2P */
  388. ret = ath6kl_wmi_probe_report_req_cmd(ar->wmi, idx, true);
  389. if (ret) {
  390. ath6kl_dbg(ATH6KL_DBG_TRC, "failed to enable Probe "
  391. "Request reporting (%d)\n", ret);
  392. }
  393. }
  394. return ret;
  395. }
  396. int ath6kl_configure_target(struct ath6kl *ar)
  397. {
  398. u32 param, ram_reserved_size;
  399. u8 fw_iftype, fw_mode = 0, fw_submode = 0;
  400. int i, status;
  401. param = !!(ar->conf_flags & ATH6KL_CONF_UART_DEBUG);
  402. if (ath6kl_bmi_write_hi32(ar, hi_serial_enable, param)) {
  403. ath6kl_err("bmi_write_memory for uart debug failed\n");
  404. return -EIO;
  405. }
  406. /*
  407. * Note: Even though the firmware interface type is
  408. * chosen as BSS_STA for all three interfaces, can
  409. * be configured to IBSS/AP as long as the fw submode
  410. * remains normal mode (0 - AP, STA and IBSS). But
  411. * due to an target assert in firmware only one interface is
  412. * configured for now.
  413. */
  414. fw_iftype = HI_OPTION_FW_MODE_BSS_STA;
  415. for (i = 0; i < ar->vif_max; i++)
  416. fw_mode |= fw_iftype << (i * HI_OPTION_FW_MODE_BITS);
  417. /*
  418. * By default, submodes :
  419. * vif[0] - AP/STA/IBSS
  420. * vif[1] - "P2P dev"/"P2P GO"/"P2P Client"
  421. * vif[2] - "P2P dev"/"P2P GO"/"P2P Client"
  422. */
  423. for (i = 0; i < ar->max_norm_iface; i++)
  424. fw_submode |= HI_OPTION_FW_SUBMODE_NONE <<
  425. (i * HI_OPTION_FW_SUBMODE_BITS);
  426. for (i = ar->max_norm_iface; i < ar->vif_max; i++)
  427. fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV <<
  428. (i * HI_OPTION_FW_SUBMODE_BITS);
  429. if (ar->p2p && ar->vif_max == 1)
  430. fw_submode = HI_OPTION_FW_SUBMODE_P2PDEV;
  431. if (ath6kl_bmi_write_hi32(ar, hi_app_host_interest,
  432. HTC_PROTOCOL_VERSION) != 0) {
  433. ath6kl_err("bmi_write_memory for htc version failed\n");
  434. return -EIO;
  435. }
  436. /* set the firmware mode to STA/IBSS/AP */
  437. param = 0;
  438. if (ath6kl_bmi_read_hi32(ar, hi_option_flag, &param) != 0) {
  439. ath6kl_err("bmi_read_memory for setting fwmode failed\n");
  440. return -EIO;
  441. }
  442. param |= (ar->vif_max << HI_OPTION_NUM_DEV_SHIFT);
  443. param |= fw_mode << HI_OPTION_FW_MODE_SHIFT;
  444. param |= fw_submode << HI_OPTION_FW_SUBMODE_SHIFT;
  445. param |= (0 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
  446. param |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
  447. if (ath6kl_bmi_write_hi32(ar, hi_option_flag, param) != 0) {
  448. ath6kl_err("bmi_write_memory for setting fwmode failed\n");
  449. return -EIO;
  450. }
  451. ath6kl_dbg(ATH6KL_DBG_TRC, "firmware mode set\n");
  452. /*
  453. * Hardcode the address use for the extended board data
  454. * Ideally this should be pre-allocate by the OS at boot time
  455. * But since it is a new feature and board data is loaded
  456. * at init time, we have to workaround this from host.
  457. * It is difficult to patch the firmware boot code,
  458. * but possible in theory.
  459. */
  460. param = ar->hw.board_ext_data_addr;
  461. ram_reserved_size = ar->hw.reserved_ram_size;
  462. if (ath6kl_bmi_write_hi32(ar, hi_board_ext_data, param) != 0) {
  463. ath6kl_err("bmi_write_memory for hi_board_ext_data failed\n");
  464. return -EIO;
  465. }
  466. if (ath6kl_bmi_write_hi32(ar, hi_end_ram_reserve_sz,
  467. ram_reserved_size) != 0) {
  468. ath6kl_err("bmi_write_memory for hi_end_ram_reserve_sz failed\n");
  469. return -EIO;
  470. }
  471. /* set the block size for the target */
  472. if (ath6kl_set_htc_params(ar, MBOX_YIELD_LIMIT, 0))
  473. /* use default number of control buffers */
  474. return -EIO;
  475. /* Configure GPIO AR600x UART */
  476. status = ath6kl_bmi_write_hi32(ar, hi_dbg_uart_txpin,
  477. ar->hw.uarttx_pin);
  478. if (status)
  479. return status;
  480. /* Configure target refclk_hz */
  481. status = ath6kl_bmi_write_hi32(ar, hi_refclk_hz, ar->hw.refclk_hz);
  482. if (status)
  483. return status;
  484. return 0;
  485. }
  486. /* firmware upload */
  487. static int ath6kl_get_fw(struct ath6kl *ar, const char *filename,
  488. u8 **fw, size_t *fw_len)
  489. {
  490. const struct firmware *fw_entry;
  491. int ret;
  492. ret = request_firmware(&fw_entry, filename, ar->dev);
  493. if (ret)
  494. return ret;
  495. *fw_len = fw_entry->size;
  496. *fw = kmemdup(fw_entry->data, fw_entry->size, GFP_KERNEL);
  497. if (*fw == NULL)
  498. ret = -ENOMEM;
  499. release_firmware(fw_entry);
  500. return ret;
  501. }
  502. #ifdef CONFIG_OF
  503. /*
  504. * Check the device tree for a board-id and use it to construct
  505. * the pathname to the firmware file. Used (for now) to find a
  506. * fallback to the "bdata.bin" file--typically a symlink to the
  507. * appropriate board-specific file.
  508. */
  509. static bool check_device_tree(struct ath6kl *ar)
  510. {
  511. static const char *board_id_prop = "atheros,board-id";
  512. struct device_node *node;
  513. char board_filename[64];
  514. const char *board_id;
  515. int ret;
  516. for_each_compatible_node(node, NULL, "atheros,ath6kl") {
  517. board_id = of_get_property(node, board_id_prop, NULL);
  518. if (board_id == NULL) {
  519. ath6kl_warn("No \"%s\" property on %s node.\n",
  520. board_id_prop, node->name);
  521. continue;
  522. }
  523. snprintf(board_filename, sizeof(board_filename),
  524. "%s/bdata.%s.bin", ar->hw.fw.dir, board_id);
  525. ret = ath6kl_get_fw(ar, board_filename, &ar->fw_board,
  526. &ar->fw_board_len);
  527. if (ret) {
  528. ath6kl_err("Failed to get DT board file %s: %d\n",
  529. board_filename, ret);
  530. continue;
  531. }
  532. return true;
  533. }
  534. return false;
  535. }
  536. #else
  537. static bool check_device_tree(struct ath6kl *ar)
  538. {
  539. return false;
  540. }
  541. #endif /* CONFIG_OF */
  542. static int ath6kl_fetch_board_file(struct ath6kl *ar)
  543. {
  544. const char *filename;
  545. int ret;
  546. if (ar->fw_board != NULL)
  547. return 0;
  548. if (WARN_ON(ar->hw.fw_board == NULL))
  549. return -EINVAL;
  550. filename = ar->hw.fw_board;
  551. ret = ath6kl_get_fw(ar, filename, &ar->fw_board,
  552. &ar->fw_board_len);
  553. if (ret == 0) {
  554. /* managed to get proper board file */
  555. return 0;
  556. }
  557. if (check_device_tree(ar)) {
  558. /* got board file from device tree */
  559. return 0;
  560. }
  561. /* there was no proper board file, try to use default instead */
  562. ath6kl_warn("Failed to get board file %s (%d), trying to find default board file.\n",
  563. filename, ret);
  564. filename = ar->hw.fw_default_board;
  565. ret = ath6kl_get_fw(ar, filename, &ar->fw_board,
  566. &ar->fw_board_len);
  567. if (ret) {
  568. ath6kl_err("Failed to get default board file %s: %d\n",
  569. filename, ret);
  570. return ret;
  571. }
  572. ath6kl_warn("WARNING! No proper board file was not found, instead using a default board file.\n");
  573. ath6kl_warn("Most likely your hardware won't work as specified. Install correct board file!\n");
  574. return 0;
  575. }
  576. static int ath6kl_fetch_otp_file(struct ath6kl *ar)
  577. {
  578. char filename[100];
  579. int ret;
  580. if (ar->fw_otp != NULL)
  581. return 0;
  582. if (ar->hw.fw.otp == NULL) {
  583. ath6kl_dbg(ATH6KL_DBG_BOOT,
  584. "no OTP file configured for this hw\n");
  585. return 0;
  586. }
  587. snprintf(filename, sizeof(filename), "%s/%s",
  588. ar->hw.fw.dir, ar->hw.fw.otp);
  589. ret = ath6kl_get_fw(ar, filename, &ar->fw_otp,
  590. &ar->fw_otp_len);
  591. if (ret) {
  592. ath6kl_err("Failed to get OTP file %s: %d\n",
  593. filename, ret);
  594. return ret;
  595. }
  596. return 0;
  597. }
  598. static int ath6kl_fetch_testmode_file(struct ath6kl *ar)
  599. {
  600. char filename[100];
  601. int ret;
  602. if (ar->testmode == 0)
  603. return 0;
  604. ath6kl_dbg(ATH6KL_DBG_BOOT, "testmode %d\n", ar->testmode);
  605. if (ar->testmode == 2) {
  606. if (ar->hw.fw.utf == NULL) {
  607. ath6kl_warn("testmode 2 not supported\n");
  608. return -EOPNOTSUPP;
  609. }
  610. snprintf(filename, sizeof(filename), "%s/%s",
  611. ar->hw.fw.dir, ar->hw.fw.utf);
  612. } else {
  613. if (ar->hw.fw.tcmd == NULL) {
  614. ath6kl_warn("testmode 1 not supported\n");
  615. return -EOPNOTSUPP;
  616. }
  617. snprintf(filename, sizeof(filename), "%s/%s",
  618. ar->hw.fw.dir, ar->hw.fw.tcmd);
  619. }
  620. set_bit(TESTMODE, &ar->flag);
  621. ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len);
  622. if (ret) {
  623. ath6kl_err("Failed to get testmode %d firmware file %s: %d\n",
  624. ar->testmode, filename, ret);
  625. return ret;
  626. }
  627. return 0;
  628. }
  629. static int ath6kl_fetch_fw_file(struct ath6kl *ar)
  630. {
  631. char filename[100];
  632. int ret;
  633. if (ar->fw != NULL)
  634. return 0;
  635. /* FIXME: remove WARN_ON() as we won't support FW API 1 for long */
  636. if (WARN_ON(ar->hw.fw.fw == NULL))
  637. return -EINVAL;
  638. snprintf(filename, sizeof(filename), "%s/%s",
  639. ar->hw.fw.dir, ar->hw.fw.fw);
  640. ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len);
  641. if (ret) {
  642. ath6kl_err("Failed to get firmware file %s: %d\n",
  643. filename, ret);
  644. return ret;
  645. }
  646. return 0;
  647. }
  648. static int ath6kl_fetch_patch_file(struct ath6kl *ar)
  649. {
  650. char filename[100];
  651. int ret;
  652. if (ar->fw_patch != NULL)
  653. return 0;
  654. if (ar->hw.fw.patch == NULL)
  655. return 0;
  656. snprintf(filename, sizeof(filename), "%s/%s",
  657. ar->hw.fw.dir, ar->hw.fw.patch);
  658. ret = ath6kl_get_fw(ar, filename, &ar->fw_patch,
  659. &ar->fw_patch_len);
  660. if (ret) {
  661. ath6kl_err("Failed to get patch file %s: %d\n",
  662. filename, ret);
  663. return ret;
  664. }
  665. return 0;
  666. }
  667. static int ath6kl_fetch_testscript_file(struct ath6kl *ar)
  668. {
  669. char filename[100];
  670. int ret;
  671. if (ar->testmode != 2)
  672. return 0;
  673. if (ar->fw_testscript != NULL)
  674. return 0;
  675. if (ar->hw.fw.testscript == NULL)
  676. return 0;
  677. snprintf(filename, sizeof(filename), "%s/%s",
  678. ar->hw.fw.dir, ar->hw.fw.testscript);
  679. ret = ath6kl_get_fw(ar, filename, &ar->fw_testscript,
  680. &ar->fw_testscript_len);
  681. if (ret) {
  682. ath6kl_err("Failed to get testscript file %s: %d\n",
  683. filename, ret);
  684. return ret;
  685. }
  686. return 0;
  687. }
  688. static int ath6kl_fetch_fw_api1(struct ath6kl *ar)
  689. {
  690. int ret;
  691. ret = ath6kl_fetch_otp_file(ar);
  692. if (ret)
  693. return ret;
  694. ret = ath6kl_fetch_fw_file(ar);
  695. if (ret)
  696. return ret;
  697. ret = ath6kl_fetch_patch_file(ar);
  698. if (ret)
  699. return ret;
  700. ret = ath6kl_fetch_testscript_file(ar);
  701. if (ret)
  702. return ret;
  703. return 0;
  704. }
  705. static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name)
  706. {
  707. size_t magic_len, len, ie_len;
  708. const struct firmware *fw;
  709. struct ath6kl_fw_ie *hdr;
  710. char filename[100];
  711. const u8 *data;
  712. int ret, ie_id, i, index, bit;
  713. __le32 *val;
  714. snprintf(filename, sizeof(filename), "%s/%s", ar->hw.fw.dir, name);
  715. ret = request_firmware(&fw, filename, ar->dev);
  716. if (ret)
  717. return ret;
  718. data = fw->data;
  719. len = fw->size;
  720. /* magic also includes the null byte, check that as well */
  721. magic_len = strlen(ATH6KL_FIRMWARE_MAGIC) + 1;
  722. if (len < magic_len) {
  723. ret = -EINVAL;
  724. goto out;
  725. }
  726. if (memcmp(data, ATH6KL_FIRMWARE_MAGIC, magic_len) != 0) {
  727. ret = -EINVAL;
  728. goto out;
  729. }
  730. len -= magic_len;
  731. data += magic_len;
  732. /* loop elements */
  733. while (len > sizeof(struct ath6kl_fw_ie)) {
  734. /* hdr is unaligned! */
  735. hdr = (struct ath6kl_fw_ie *) data;
  736. ie_id = le32_to_cpup(&hdr->id);
  737. ie_len = le32_to_cpup(&hdr->len);
  738. len -= sizeof(*hdr);
  739. data += sizeof(*hdr);
  740. if (len < ie_len) {
  741. ret = -EINVAL;
  742. goto out;
  743. }
  744. switch (ie_id) {
  745. case ATH6KL_FW_IE_OTP_IMAGE:
  746. ath6kl_dbg(ATH6KL_DBG_BOOT, "found otp image ie (%zd B)\n",
  747. ie_len);
  748. ar->fw_otp = kmemdup(data, ie_len, GFP_KERNEL);
  749. if (ar->fw_otp == NULL) {
  750. ret = -ENOMEM;
  751. goto out;
  752. }
  753. ar->fw_otp_len = ie_len;
  754. break;
  755. case ATH6KL_FW_IE_FW_IMAGE:
  756. ath6kl_dbg(ATH6KL_DBG_BOOT, "found fw image ie (%zd B)\n",
  757. ie_len);
  758. /* in testmode we already might have a fw file */
  759. if (ar->fw != NULL)
  760. break;
  761. ar->fw = kmemdup(data, ie_len, GFP_KERNEL);
  762. if (ar->fw == NULL) {
  763. ret = -ENOMEM;
  764. goto out;
  765. }
  766. ar->fw_len = ie_len;
  767. break;
  768. case ATH6KL_FW_IE_PATCH_IMAGE:
  769. ath6kl_dbg(ATH6KL_DBG_BOOT, "found patch image ie (%zd B)\n",
  770. ie_len);
  771. ar->fw_patch = kmemdup(data, ie_len, GFP_KERNEL);
  772. if (ar->fw_patch == NULL) {
  773. ret = -ENOMEM;
  774. goto out;
  775. }
  776. ar->fw_patch_len = ie_len;
  777. break;
  778. case ATH6KL_FW_IE_RESERVED_RAM_SIZE:
  779. val = (__le32 *) data;
  780. ar->hw.reserved_ram_size = le32_to_cpup(val);
  781. ath6kl_dbg(ATH6KL_DBG_BOOT,
  782. "found reserved ram size ie 0x%d\n",
  783. ar->hw.reserved_ram_size);
  784. break;
  785. case ATH6KL_FW_IE_CAPABILITIES:
  786. if (ie_len < DIV_ROUND_UP(ATH6KL_FW_CAPABILITY_MAX, 8))
  787. break;
  788. ath6kl_dbg(ATH6KL_DBG_BOOT,
  789. "found firmware capabilities ie (%zd B)\n",
  790. ie_len);
  791. for (i = 0; i < ATH6KL_FW_CAPABILITY_MAX; i++) {
  792. index = i / 8;
  793. bit = i % 8;
  794. if (data[index] & (1 << bit))
  795. __set_bit(i, ar->fw_capabilities);
  796. }
  797. ath6kl_dbg_dump(ATH6KL_DBG_BOOT, "capabilities", "",
  798. ar->fw_capabilities,
  799. sizeof(ar->fw_capabilities));
  800. break;
  801. case ATH6KL_FW_IE_PATCH_ADDR:
  802. if (ie_len != sizeof(*val))
  803. break;
  804. val = (__le32 *) data;
  805. ar->hw.dataset_patch_addr = le32_to_cpup(val);
  806. ath6kl_dbg(ATH6KL_DBG_BOOT,
  807. "found patch address ie 0x%x\n",
  808. ar->hw.dataset_patch_addr);
  809. break;
  810. case ATH6KL_FW_IE_BOARD_ADDR:
  811. if (ie_len != sizeof(*val))
  812. break;
  813. val = (__le32 *) data;
  814. ar->hw.board_addr = le32_to_cpup(val);
  815. ath6kl_dbg(ATH6KL_DBG_BOOT,
  816. "found board address ie 0x%x\n",
  817. ar->hw.board_addr);
  818. break;
  819. case ATH6KL_FW_IE_VIF_MAX:
  820. if (ie_len != sizeof(*val))
  821. break;
  822. val = (__le32 *) data;
  823. ar->vif_max = min_t(unsigned int, le32_to_cpup(val),
  824. ATH6KL_VIF_MAX);
  825. if (ar->vif_max > 1 && !ar->p2p)
  826. ar->max_norm_iface = 2;
  827. ath6kl_dbg(ATH6KL_DBG_BOOT,
  828. "found vif max ie %d\n", ar->vif_max);
  829. break;
  830. default:
  831. ath6kl_dbg(ATH6KL_DBG_BOOT, "Unknown fw ie: %u\n",
  832. le32_to_cpup(&hdr->id));
  833. break;
  834. }
  835. len -= ie_len;
  836. data += ie_len;
  837. };
  838. ret = 0;
  839. out:
  840. release_firmware(fw);
  841. return ret;
  842. }
  843. int ath6kl_init_fetch_firmwares(struct ath6kl *ar)
  844. {
  845. int ret;
  846. ret = ath6kl_fetch_board_file(ar);
  847. if (ret)
  848. return ret;
  849. ret = ath6kl_fetch_testmode_file(ar);
  850. if (ret)
  851. return ret;
  852. ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API3_FILE);
  853. if (ret == 0) {
  854. ar->fw_api = 3;
  855. goto out;
  856. }
  857. ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API2_FILE);
  858. if (ret == 0) {
  859. ar->fw_api = 2;
  860. goto out;
  861. }
  862. ret = ath6kl_fetch_fw_api1(ar);
  863. if (ret)
  864. return ret;
  865. ar->fw_api = 1;
  866. out:
  867. ath6kl_dbg(ATH6KL_DBG_BOOT, "using fw api %d\n", ar->fw_api);
  868. return 0;
  869. }
  870. static int ath6kl_upload_board_file(struct ath6kl *ar)
  871. {
  872. u32 board_address, board_ext_address, param;
  873. u32 board_data_size, board_ext_data_size;
  874. int ret;
  875. if (WARN_ON(ar->fw_board == NULL))
  876. return -ENOENT;
  877. /*
  878. * Determine where in Target RAM to write Board Data.
  879. * For AR6004, host determine Target RAM address for
  880. * writing board data.
  881. */
  882. if (ar->hw.board_addr != 0) {
  883. board_address = ar->hw.board_addr;
  884. ath6kl_bmi_write_hi32(ar, hi_board_data,
  885. board_address);
  886. } else {
  887. ath6kl_bmi_read_hi32(ar, hi_board_data, &board_address);
  888. }
  889. /* determine where in target ram to write extended board data */
  890. ath6kl_bmi_read_hi32(ar, hi_board_ext_data, &board_ext_address);
  891. if (ar->target_type == TARGET_TYPE_AR6003 &&
  892. board_ext_address == 0) {
  893. ath6kl_err("Failed to get board file target address.\n");
  894. return -EINVAL;
  895. }
  896. switch (ar->target_type) {
  897. case TARGET_TYPE_AR6003:
  898. board_data_size = AR6003_BOARD_DATA_SZ;
  899. board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ;
  900. if (ar->fw_board_len > (board_data_size + board_ext_data_size))
  901. board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ_V2;
  902. break;
  903. case TARGET_TYPE_AR6004:
  904. board_data_size = AR6004_BOARD_DATA_SZ;
  905. board_ext_data_size = AR6004_BOARD_EXT_DATA_SZ;
  906. break;
  907. default:
  908. WARN_ON(1);
  909. return -EINVAL;
  910. break;
  911. }
  912. if (board_ext_address &&
  913. ar->fw_board_len == (board_data_size + board_ext_data_size)) {
  914. /* write extended board data */
  915. ath6kl_dbg(ATH6KL_DBG_BOOT,
  916. "writing extended board data to 0x%x (%d B)\n",
  917. board_ext_address, board_ext_data_size);
  918. ret = ath6kl_bmi_write(ar, board_ext_address,
  919. ar->fw_board + board_data_size,
  920. board_ext_data_size);
  921. if (ret) {
  922. ath6kl_err("Failed to write extended board data: %d\n",
  923. ret);
  924. return ret;
  925. }
  926. /* record that extended board data is initialized */
  927. param = (board_ext_data_size << 16) | 1;
  928. ath6kl_bmi_write_hi32(ar, hi_board_ext_data_config, param);
  929. }
  930. if (ar->fw_board_len < board_data_size) {
  931. ath6kl_err("Too small board file: %zu\n", ar->fw_board_len);
  932. ret = -EINVAL;
  933. return ret;
  934. }
  935. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing board file to 0x%x (%d B)\n",
  936. board_address, board_data_size);
  937. ret = ath6kl_bmi_write(ar, board_address, ar->fw_board,
  938. board_data_size);
  939. if (ret) {
  940. ath6kl_err("Board file bmi write failed: %d\n", ret);
  941. return ret;
  942. }
  943. /* record the fact that Board Data IS initialized */
  944. ath6kl_bmi_write_hi32(ar, hi_board_data_initialized, 1);
  945. return ret;
  946. }
  947. static int ath6kl_upload_otp(struct ath6kl *ar)
  948. {
  949. u32 address, param;
  950. bool from_hw = false;
  951. int ret;
  952. if (ar->fw_otp == NULL)
  953. return 0;
  954. address = ar->hw.app_load_addr;
  955. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing otp to 0x%x (%zd B)\n", address,
  956. ar->fw_otp_len);
  957. ret = ath6kl_bmi_fast_download(ar, address, ar->fw_otp,
  958. ar->fw_otp_len);
  959. if (ret) {
  960. ath6kl_err("Failed to upload OTP file: %d\n", ret);
  961. return ret;
  962. }
  963. /* read firmware start address */
  964. ret = ath6kl_bmi_read_hi32(ar, hi_app_start, &address);
  965. if (ret) {
  966. ath6kl_err("Failed to read hi_app_start: %d\n", ret);
  967. return ret;
  968. }
  969. if (ar->hw.app_start_override_addr == 0) {
  970. ar->hw.app_start_override_addr = address;
  971. from_hw = true;
  972. }
  973. ath6kl_dbg(ATH6KL_DBG_BOOT, "app_start_override_addr%s 0x%x\n",
  974. from_hw ? " (from hw)" : "",
  975. ar->hw.app_start_override_addr);
  976. /* execute the OTP code */
  977. ath6kl_dbg(ATH6KL_DBG_BOOT, "executing OTP at 0x%x\n",
  978. ar->hw.app_start_override_addr);
  979. param = 0;
  980. ath6kl_bmi_execute(ar, ar->hw.app_start_override_addr, &param);
  981. return ret;
  982. }
  983. static int ath6kl_upload_firmware(struct ath6kl *ar)
  984. {
  985. u32 address;
  986. int ret;
  987. if (WARN_ON(ar->fw == NULL))
  988. return 0;
  989. address = ar->hw.app_load_addr;
  990. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing firmware to 0x%x (%zd B)\n",
  991. address, ar->fw_len);
  992. ret = ath6kl_bmi_fast_download(ar, address, ar->fw, ar->fw_len);
  993. if (ret) {
  994. ath6kl_err("Failed to write firmware: %d\n", ret);
  995. return ret;
  996. }
  997. /*
  998. * Set starting address for firmware
  999. * Don't need to setup app_start override addr on AR6004
  1000. */
  1001. if (ar->target_type != TARGET_TYPE_AR6004) {
  1002. address = ar->hw.app_start_override_addr;
  1003. ath6kl_bmi_set_app_start(ar, address);
  1004. }
  1005. return ret;
  1006. }
  1007. static int ath6kl_upload_patch(struct ath6kl *ar)
  1008. {
  1009. u32 address;
  1010. int ret;
  1011. if (ar->fw_patch == NULL)
  1012. return 0;
  1013. address = ar->hw.dataset_patch_addr;
  1014. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing patch to 0x%x (%zd B)\n",
  1015. address, ar->fw_patch_len);
  1016. ret = ath6kl_bmi_write(ar, address, ar->fw_patch, ar->fw_patch_len);
  1017. if (ret) {
  1018. ath6kl_err("Failed to write patch file: %d\n", ret);
  1019. return ret;
  1020. }
  1021. ath6kl_bmi_write_hi32(ar, hi_dset_list_head, address);
  1022. return 0;
  1023. }
  1024. static int ath6kl_upload_testscript(struct ath6kl *ar)
  1025. {
  1026. u32 address;
  1027. int ret;
  1028. if (ar->testmode != 2)
  1029. return 0;
  1030. if (ar->fw_testscript == NULL)
  1031. return 0;
  1032. address = ar->hw.testscript_addr;
  1033. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing testscript to 0x%x (%zd B)\n",
  1034. address, ar->fw_testscript_len);
  1035. ret = ath6kl_bmi_write(ar, address, ar->fw_testscript,
  1036. ar->fw_testscript_len);
  1037. if (ret) {
  1038. ath6kl_err("Failed to write testscript file: %d\n", ret);
  1039. return ret;
  1040. }
  1041. ath6kl_bmi_write_hi32(ar, hi_ota_testscript, address);
  1042. ath6kl_bmi_write_hi32(ar, hi_end_ram_reserve_sz, 4096);
  1043. ath6kl_bmi_write_hi32(ar, hi_test_apps_related, 1);
  1044. return 0;
  1045. }
  1046. static int ath6kl_init_upload(struct ath6kl *ar)
  1047. {
  1048. u32 param, options, sleep, address;
  1049. int status = 0;
  1050. if (ar->target_type != TARGET_TYPE_AR6003 &&
  1051. ar->target_type != TARGET_TYPE_AR6004)
  1052. return -EINVAL;
  1053. /* temporarily disable system sleep */
  1054. address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
  1055. status = ath6kl_bmi_reg_read(ar, address, &param);
  1056. if (status)
  1057. return status;
  1058. options = param;
  1059. param |= ATH6KL_OPTION_SLEEP_DISABLE;
  1060. status = ath6kl_bmi_reg_write(ar, address, param);
  1061. if (status)
  1062. return status;
  1063. address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
  1064. status = ath6kl_bmi_reg_read(ar, address, &param);
  1065. if (status)
  1066. return status;
  1067. sleep = param;
  1068. param |= SM(SYSTEM_SLEEP_DISABLE, 1);
  1069. status = ath6kl_bmi_reg_write(ar, address, param);
  1070. if (status)
  1071. return status;
  1072. ath6kl_dbg(ATH6KL_DBG_TRC, "old options: %d, old sleep: %d\n",
  1073. options, sleep);
  1074. /* program analog PLL register */
  1075. /* no need to control 40/44MHz clock on AR6004 */
  1076. if (ar->target_type != TARGET_TYPE_AR6004) {
  1077. status = ath6kl_bmi_reg_write(ar, ATH6KL_ANALOG_PLL_REGISTER,
  1078. 0xF9104001);
  1079. if (status)
  1080. return status;
  1081. /* Run at 80/88MHz by default */
  1082. param = SM(CPU_CLOCK_STANDARD, 1);
  1083. address = RTC_BASE_ADDRESS + CPU_CLOCK_ADDRESS;
  1084. status = ath6kl_bmi_reg_write(ar, address, param);
  1085. if (status)
  1086. return status;
  1087. }
  1088. param = 0;
  1089. address = RTC_BASE_ADDRESS + LPO_CAL_ADDRESS;
  1090. param = SM(LPO_CAL_ENABLE, 1);
  1091. status = ath6kl_bmi_reg_write(ar, address, param);
  1092. if (status)
  1093. return status;
  1094. /* WAR to avoid SDIO CRC err */
  1095. if (ar->version.target_ver == AR6003_HW_2_0_VERSION ||
  1096. ar->version.target_ver == AR6003_HW_2_1_1_VERSION) {
  1097. ath6kl_err("temporary war to avoid sdio crc error\n");
  1098. param = 0x20;
  1099. address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS;
  1100. status = ath6kl_bmi_reg_write(ar, address, param);
  1101. if (status)
  1102. return status;
  1103. address = GPIO_BASE_ADDRESS + GPIO_PIN11_ADDRESS;
  1104. status = ath6kl_bmi_reg_write(ar, address, param);
  1105. if (status)
  1106. return status;
  1107. address = GPIO_BASE_ADDRESS + GPIO_PIN12_ADDRESS;
  1108. status = ath6kl_bmi_reg_write(ar, address, param);
  1109. if (status)
  1110. return status;
  1111. address = GPIO_BASE_ADDRESS + GPIO_PIN13_ADDRESS;
  1112. status = ath6kl_bmi_reg_write(ar, address, param);
  1113. if (status)
  1114. return status;
  1115. }
  1116. /* write EEPROM data to Target RAM */
  1117. status = ath6kl_upload_board_file(ar);
  1118. if (status)
  1119. return status;
  1120. /* transfer One time Programmable data */
  1121. status = ath6kl_upload_otp(ar);
  1122. if (status)
  1123. return status;
  1124. /* Download Target firmware */
  1125. status = ath6kl_upload_firmware(ar);
  1126. if (status)
  1127. return status;
  1128. status = ath6kl_upload_patch(ar);
  1129. if (status)
  1130. return status;
  1131. /* Download the test script */
  1132. status = ath6kl_upload_testscript(ar);
  1133. if (status)
  1134. return status;
  1135. /* Restore system sleep */
  1136. address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
  1137. status = ath6kl_bmi_reg_write(ar, address, sleep);
  1138. if (status)
  1139. return status;
  1140. address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
  1141. param = options | 0x20;
  1142. status = ath6kl_bmi_reg_write(ar, address, param);
  1143. if (status)
  1144. return status;
  1145. return status;
  1146. }
  1147. int ath6kl_init_hw_params(struct ath6kl *ar)
  1148. {
  1149. const struct ath6kl_hw *uninitialized_var(hw);
  1150. int i;
  1151. for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
  1152. hw = &hw_list[i];
  1153. if (hw->id == ar->version.target_ver)
  1154. break;
  1155. }
  1156. if (i == ARRAY_SIZE(hw_list)) {
  1157. ath6kl_err("Unsupported hardware version: 0x%x\n",
  1158. ar->version.target_ver);
  1159. return -EINVAL;
  1160. }
  1161. ar->hw = *hw;
  1162. ath6kl_dbg(ATH6KL_DBG_BOOT,
  1163. "target_ver 0x%x target_type 0x%x dataset_patch 0x%x app_load_addr 0x%x\n",
  1164. ar->version.target_ver, ar->target_type,
  1165. ar->hw.dataset_patch_addr, ar->hw.app_load_addr);
  1166. ath6kl_dbg(ATH6KL_DBG_BOOT,
  1167. "app_start_override_addr 0x%x board_ext_data_addr 0x%x reserved_ram_size 0x%x",
  1168. ar->hw.app_start_override_addr, ar->hw.board_ext_data_addr,
  1169. ar->hw.reserved_ram_size);
  1170. ath6kl_dbg(ATH6KL_DBG_BOOT,
  1171. "refclk_hz %d uarttx_pin %d",
  1172. ar->hw.refclk_hz, ar->hw.uarttx_pin);
  1173. return 0;
  1174. }
  1175. static const char *ath6kl_init_get_hif_name(enum ath6kl_hif_type type)
  1176. {
  1177. switch (type) {
  1178. case ATH6KL_HIF_TYPE_SDIO:
  1179. return "sdio";
  1180. case ATH6KL_HIF_TYPE_USB:
  1181. return "usb";
  1182. }
  1183. return NULL;
  1184. }
  1185. int ath6kl_init_hw_start(struct ath6kl *ar)
  1186. {
  1187. long timeleft;
  1188. int ret, i;
  1189. ath6kl_dbg(ATH6KL_DBG_BOOT, "hw start\n");
  1190. ret = ath6kl_hif_power_on(ar);
  1191. if (ret)
  1192. return ret;
  1193. ret = ath6kl_configure_target(ar);
  1194. if (ret)
  1195. goto err_power_off;
  1196. ret = ath6kl_init_upload(ar);
  1197. if (ret)
  1198. goto err_power_off;
  1199. /* Do we need to finish the BMI phase */
  1200. /* FIXME: return error from ath6kl_bmi_done() */
  1201. if (ath6kl_bmi_done(ar)) {
  1202. ret = -EIO;
  1203. goto err_power_off;
  1204. }
  1205. /*
  1206. * The reason we have to wait for the target here is that the
  1207. * driver layer has to init BMI in order to set the host block
  1208. * size.
  1209. */
  1210. if (ath6kl_htc_wait_target(ar->htc_target)) {
  1211. ret = -EIO;
  1212. goto err_power_off;
  1213. }
  1214. if (ath6kl_init_service_ep(ar)) {
  1215. ret = -EIO;
  1216. goto err_cleanup_scatter;
  1217. }
  1218. /* setup credit distribution */
  1219. ath6kl_credit_setup(ar->htc_target, &ar->credit_state_info);
  1220. /* start HTC */
  1221. ret = ath6kl_htc_start(ar->htc_target);
  1222. if (ret) {
  1223. /* FIXME: call this */
  1224. ath6kl_cookie_cleanup(ar);
  1225. goto err_cleanup_scatter;
  1226. }
  1227. /* Wait for Wmi event to be ready */
  1228. timeleft = wait_event_interruptible_timeout(ar->event_wq,
  1229. test_bit(WMI_READY,
  1230. &ar->flag),
  1231. WMI_TIMEOUT);
  1232. ath6kl_dbg(ATH6KL_DBG_BOOT, "firmware booted\n");
  1233. if (test_and_clear_bit(FIRST_BOOT, &ar->flag)) {
  1234. ath6kl_info("%s %s fw %s api %d%s\n",
  1235. ar->hw.name,
  1236. ath6kl_init_get_hif_name(ar->hif_type),
  1237. ar->wiphy->fw_version,
  1238. ar->fw_api,
  1239. test_bit(TESTMODE, &ar->flag) ? " testmode" : "");
  1240. }
  1241. if (ar->version.abi_ver != ATH6KL_ABI_VERSION) {
  1242. ath6kl_err("abi version mismatch: host(0x%x), target(0x%x)\n",
  1243. ATH6KL_ABI_VERSION, ar->version.abi_ver);
  1244. ret = -EIO;
  1245. goto err_htc_stop;
  1246. }
  1247. if (!timeleft || signal_pending(current)) {
  1248. ath6kl_err("wmi is not ready or wait was interrupted\n");
  1249. ret = -EIO;
  1250. goto err_htc_stop;
  1251. }
  1252. ath6kl_dbg(ATH6KL_DBG_TRC, "%s: wmi is ready\n", __func__);
  1253. /* communicate the wmi protocol verision to the target */
  1254. /* FIXME: return error */
  1255. if ((ath6kl_set_host_app_area(ar)) != 0)
  1256. ath6kl_err("unable to set the host app area\n");
  1257. for (i = 0; i < ar->vif_max; i++) {
  1258. ret = ath6kl_target_config_wlan_params(ar, i);
  1259. if (ret)
  1260. goto err_htc_stop;
  1261. }
  1262. ar->state = ATH6KL_STATE_ON;
  1263. return 0;
  1264. err_htc_stop:
  1265. ath6kl_htc_stop(ar->htc_target);
  1266. err_cleanup_scatter:
  1267. ath6kl_hif_cleanup_scatter(ar);
  1268. err_power_off:
  1269. ath6kl_hif_power_off(ar);
  1270. return ret;
  1271. }
  1272. int ath6kl_init_hw_stop(struct ath6kl *ar)
  1273. {
  1274. int ret;
  1275. ath6kl_dbg(ATH6KL_DBG_BOOT, "hw stop\n");
  1276. ath6kl_htc_stop(ar->htc_target);
  1277. ath6kl_hif_stop(ar);
  1278. ath6kl_bmi_reset(ar);
  1279. ret = ath6kl_hif_power_off(ar);
  1280. if (ret)
  1281. ath6kl_warn("failed to power off hif: %d\n", ret);
  1282. ar->state = ATH6KL_STATE_OFF;
  1283. return 0;
  1284. }
  1285. /* FIXME: move this to cfg80211.c and rename to ath6kl_cfg80211_vif_stop() */
  1286. void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready)
  1287. {
  1288. static u8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  1289. bool discon_issued;
  1290. netif_stop_queue(vif->ndev);
  1291. clear_bit(WLAN_ENABLED, &vif->flags);
  1292. if (wmi_ready) {
  1293. discon_issued = test_bit(CONNECTED, &vif->flags) ||
  1294. test_bit(CONNECT_PEND, &vif->flags);
  1295. ath6kl_disconnect(vif);
  1296. del_timer(&vif->disconnect_timer);
  1297. if (discon_issued)
  1298. ath6kl_disconnect_event(vif, DISCONNECT_CMD,
  1299. (vif->nw_type & AP_NETWORK) ?
  1300. bcast_mac : vif->bssid,
  1301. 0, NULL, 0);
  1302. }
  1303. if (vif->scan_req) {
  1304. cfg80211_scan_done(vif->scan_req, true);
  1305. vif->scan_req = NULL;
  1306. }
  1307. }
  1308. void ath6kl_stop_txrx(struct ath6kl *ar)
  1309. {
  1310. struct ath6kl_vif *vif, *tmp_vif;
  1311. int i;
  1312. set_bit(DESTROY_IN_PROGRESS, &ar->flag);
  1313. if (down_interruptible(&ar->sem)) {
  1314. ath6kl_err("down_interruptible failed\n");
  1315. return;
  1316. }
  1317. for (i = 0; i < AP_MAX_NUM_STA; i++)
  1318. aggr_reset_state(ar->sta_list[i].aggr_conn);
  1319. spin_lock_bh(&ar->list_lock);
  1320. list_for_each_entry_safe(vif, tmp_vif, &ar->vif_list, list) {
  1321. list_del(&vif->list);
  1322. spin_unlock_bh(&ar->list_lock);
  1323. ath6kl_cleanup_vif(vif, test_bit(WMI_READY, &ar->flag));
  1324. rtnl_lock();
  1325. ath6kl_cfg80211_vif_cleanup(vif);
  1326. rtnl_unlock();
  1327. spin_lock_bh(&ar->list_lock);
  1328. }
  1329. spin_unlock_bh(&ar->list_lock);
  1330. clear_bit(WMI_READY, &ar->flag);
  1331. /*
  1332. * After wmi_shudown all WMI events will be dropped. We
  1333. * need to cleanup the buffers allocated in AP mode and
  1334. * give disconnect notification to stack, which usually
  1335. * happens in the disconnect_event. Simulate the disconnect
  1336. * event by calling the function directly. Sometimes
  1337. * disconnect_event will be received when the debug logs
  1338. * are collected.
  1339. */
  1340. ath6kl_wmi_shutdown(ar->wmi);
  1341. clear_bit(WMI_ENABLED, &ar->flag);
  1342. if (ar->htc_target) {
  1343. ath6kl_dbg(ATH6KL_DBG_TRC, "%s: shut down htc\n", __func__);
  1344. ath6kl_htc_stop(ar->htc_target);
  1345. }
  1346. /*
  1347. * Try to reset the device if we can. The driver may have been
  1348. * configure NOT to reset the target during a debug session.
  1349. */
  1350. ath6kl_dbg(ATH6KL_DBG_TRC,
  1351. "attempting to reset target on instance destroy\n");
  1352. ath6kl_reset_device(ar, ar->target_type, true, true);
  1353. clear_bit(WLAN_ENABLED, &ar->flag);
  1354. up(&ar->sem);
  1355. }
  1356. EXPORT_SYMBOL(ath6kl_stop_txrx);