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mach-s5p6440
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regs-clock.h

regs-clock.h 4.3 KB
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  1. /* linux/arch/arm/mach-s5p6440/include/mach/regs-clock.h
    2. 

  2.  *
    3. 

  3.  * Copyright (c) 2009 Samsung Electronics Co., Ltd.
    4. 

  4.  *		http://www.samsung.com/
    5. 

  5.  *
    6. 

  6.  * S5P6440 - Clock register definitions
    7. 

  7.  *
    8. 

  8.  * This program is free software; you can redistribute it and/or modify
    9. 

  9.  * it under the terms of the GNU General Public License version 2 as
    10. 

  10.  * published by the Free Software Foundation.
    11. 

  11. */
    12. 

  12. 

  13. #ifndef __ASM_ARCH_REGS_CLOCK_H
    14. 

  14. #define __ASM_ARCH_REGS_CLOCK_H __FILE__
    15. 

  15. 

  16. #include <mach/map.h>
    17. 

  17. 

  18. #define S5P_CLKREG(x)		(S3C_VA_SYS + (x))
    19. 

  19. 

  20. #define S5P_APLL_LOCK		S5P_CLKREG(0x00)
    21. 

  21. #define S5P_MPLL_LOCK		S5P_CLKREG(0x04)
    22. 

  22. #define S5P_EPLL_LOCK		S5P_CLKREG(0x08)
    23. 

  23. #define S5P_APLL_CON		S5P_CLKREG(0x0C)
    24. 

  24. #define S5P_MPLL_CON		S5P_CLKREG(0x10)
    25. 

  25. #define S5P_EPLL_CON		S5P_CLKREG(0x14)
    26. 

  26. #define S5P_EPLL_CON_K		S5P_CLKREG(0x18)
    27. 

  27. #define S5P_CLK_SRC0		S5P_CLKREG(0x1C)
    28. 

  28. #define S5P_CLK_DIV0		S5P_CLKREG(0x20)
    29. 

  29. #define S5P_CLK_DIV1		S5P_CLKREG(0x24)
    30. 

  30. #define S5P_CLK_DIV2		S5P_CLKREG(0x28)
    31. 

  31. #define S5P_CLK_OUT		S5P_CLKREG(0x2C)
    32. 

  32. #define S5P_CLK_GATE_HCLK0	S5P_CLKREG(0x30)
    33. 

  33. #define S5P_CLK_GATE_PCLK	S5P_CLKREG(0x34)
    34. 

  34. #define S5P_CLK_GATE_SCLK0	S5P_CLKREG(0x38)
    35. 

  35. #define S5P_CLK_GATE_MEM0	S5P_CLKREG(0x3C)
    36. 

  36. #define S5P_CLK_DIV3		S5P_CLKREG(0x40)
    37. 

  37. #define S5P_CLK_GATE_HCLK1	S5P_CLKREG(0x44)
    38. 

  38. #define S5P_CLK_GATE_SCLK1	S5P_CLKREG(0x48)
    39. 

  39. #define S5P_AHB_CON0           	S5P_CLKREG(0x100)
    40. 

  40. #define S5P_CLK_SRC1           	S5P_CLKREG(0x10C)
    41. 

  41. #define S5P_SWRESET		S5P_CLKREG(0x114)
    42. 

  42. #define S5P_SYS_ID		S5P_CLKREG(0x118)
    43. 

  43. #define S5P_SYS_OTHERS		S5P_CLKREG(0x11C)
    44. 

  44. #define S5P_MEM_CFG_STAT	S5P_CLKREG(0x12C)
    45. 

  45. #define S5P_PWR_CFG		S5P_CLKREG(0x804)
    46. 

  46. #define S5P_EINT_WAKEUP_MASK	S5P_CLKREG(0x808)
    47. 

  47. #define S5P_NORMAL_CFG		S5P_CLKREG(0x810)
    48. 

  48. #define S5P_STOP_CFG		S5P_CLKREG(0x814)
    49. 

  49. #define S5P_SLEEP_CFG		S5P_CLKREG(0x818)
    50. 

  50. #define S5P_OSC_FREQ		S5P_CLKREG(0x820)
    51. 

  51. #define S5P_OSC_STABLE		S5P_CLKREG(0x824)
    52. 

  52. #define S5P_PWR_STABLE		S5P_CLKREG(0x828)
    53. 

  53. #define S5P_MTC_STABLE		S5P_CLKREG(0x830)
    54. 

  54. #define S5P_OTHERS		S5P_CLKREG(0x900)
    55. 

  55. #define S5P_RST_STAT		S5P_CLKREG(0x904)
    56. 

  56. #define S5P_WAKEUP_STAT		S5P_CLKREG(0x908)
    57. 

  57. #define S5P_SLPEN		S5P_CLKREG(0x930)
    58. 

  58. #define S5P_INFORM0		S5P_CLKREG(0xA00)
    59. 

  59. #define S5P_INFORM1		S5P_CLKREG(0xA04)
    60. 

  60. #define S5P_INFORM2		S5P_CLKREG(0xA08)
    61. 

  61. #define S5P_INFORM3		S5P_CLKREG(0xA0C)
    62. 

  62. 

  63. /* CLKDIV0 */
    64. 

  64. #define S5P_CLKDIV0_PCLK_MASK		(0xf << 12)
    65. 

  65. #define S5P_CLKDIV0_PCLK_SHIFT		(12)
    66. 

  66. #define S5P_CLKDIV0_HCLK_MASK		(0xf << 8)
    67. 

  67. #define S5P_CLKDIV0_HCLK_SHIFT		(8)
    68. 

  68. #define S5P_CLKDIV0_MPLL_MASK		(0x1 << 4)
    69. 

  69. #define S5P_CLKDIV0_ARM_MASK		(0xf << 0)
    70. 

  70. #define S5P_CLKDIV0_ARM_SHIFT		(0)
    71. 

  71. 

  72. /* CLKDIV3 */
    73. 

  73. #define S5P_CLKDIV3_PCLK_LOW_MASK	(0xf << 12)
    74. 

  74. #define S5P_CLKDIV3_PCLK_LOW_SHIFT	(12)
    75. 

  75. #define S5P_CLKDIV3_HCLK_LOW_MASK	(0xf << 8)
    76. 

  76. #define S5P_CLKDIV3_HCLK_LOW_SHIFT	(8)
    77. 

  77. 

  78. /* HCLK0 GATE Registers */
    79. 

  79. #define S5P_CLKCON_HCLK0_USB		(1<<20)
    80. 

  80. #define S5P_CLKCON_HCLK0_HSMMC2		(1<<19)
    81. 

  81. #define S5P_CLKCON_HCLK0_HSMMC1		(1<<18)
    82. 

  82. #define S5P_CLKCON_HCLK0_HSMMC0		(1<<17)
    83. 

  83. #define S5P_CLKCON_HCLK0_POST0		(1<<5)
    84. 

  84. 

  85. /* HCLK1 GATE Registers */
    86. 

  86. #define S5P_CLKCON_HCLK1_DISPCON	(1<<1)
    87. 

  87. 

  88. /* PCLK GATE Registers */
    89. 

  89. #define S5P_CLKCON_PCLK_IIS2		(1<<26)
    90. 

  90. #define S5P_CLKCON_PCLK_SPI1		(1<<22)
    91. 

  91. #define S5P_CLKCON_PCLK_SPI0		(1<<21)
    92. 

  92. #define S5P_CLKCON_PCLK_GPIO		(1<<18)
    93. 

  93. #define S5P_CLKCON_PCLK_IIC0		(1<<17)
    94. 

  94. #define S5P_CLKCON_PCLK_TSADC		(1<<12)
    95. 

  95. #define S5P_CLKCON_PCLK_PWM		(1<<7)
    96. 

  96. #define S5P_CLKCON_PCLK_RTC		(1<<6)
    97. 

  97. #define S5P_CLKCON_PCLK_WDT		(1<<5)
    98. 

  98. #define S5P_CLKCON_PCLK_UART3		(1<<4)
    99. 

  99. #define S5P_CLKCON_PCLK_UART2		(1<<3)
    100. 

  100. #define S5P_CLKCON_PCLK_UART1		(1<<2)
    101. 

  101. #define S5P_CLKCON_PCLK_UART0		(1<<1)
    102. 

  102. 

  103. /* SCLK0 GATE Registers */
    104. 

  104. #define S5P_CLKCON_SCLK0_MMC2_48	(1<<29)
    105. 

  105. #define S5P_CLKCON_SCLK0_MMC1_48	(1<<28)
    106. 

  106. #define S5P_CLKCON_SCLK0_MMC0_48	(1<<27)
    107. 

  107. #define S5P_CLKCON_SCLK0_MMC2		(1<<26)
    108. 

  108. #define S5P_CLKCON_SCLK0_MMC1		(1<<25)
    109. 

  109. #define S5P_CLKCON_SCLK0_MMC0		(1<<24)
    110. 

  110. #define S5P_CLKCON_SCLK0_SPI1_48 	(1<<23)
    111. 

  111. #define S5P_CLKCON_SCLK0_SPI0_48 	(1<<22)
    112. 

  112. #define S5P_CLKCON_SCLK0_SPI1		(1<<21)
    113. 

  113. #define S5P_CLKCON_SCLK0_SPI0		(1<<20)
    114. 

  114. #define S5P_CLKCON_SCLK0_UART		(1<<5)
    115. 

  115. 

  116. /* SCLK1 GATE Registers */
    117. 

  117. 

  118. /* MEM0 GATE Registers */
    119. 

  119. #define S5P_CLKCON_MEM0_HCLK_NFCON	(1<<2)
    120. 

  120. 

  121. /*OTHERS Resgister */
    122. 

  122. #define S5P_OTHERS_USB_SIG_MASK		(1<<16)
    123. 

  123. #define S5P_OTHERS_HCLK_LOW_SEL_MPLL	(1<<6)
    124. 

  124. 

  125. /* Compatibility defines */
    126. 

  126. #define ARM_CLK_DIV			S5P_CLK_DIV0
    127. 

  127. #define ARM_DIV_RATIO_SHIFT		0
    128. 

  128. #define ARM_DIV_MASK			(0xf << ARM_DIV_RATIO_SHIFT)
    129. 

  129. 

  130. #endif /* __ASM_ARCH_REGS_CLOCK_H */
    131.