exynos_dp.txt 2.4 KB

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  1. The Exynos display port interface should be configured based on
  2. the type of panel connected to it.
  3. We use two nodes:
  4. -dp-controller node
  5. -dptx-phy node(defined inside dp-controller node)
  6. For the DP-PHY initialization, we use the dptx-phy node.
  7. Required properties for dptx-phy: deprecated, use phys and phy-names
  8. -reg: deprecated
  9. Base address of DP PHY register.
  10. -samsung,enable-mask: deprecated
  11. The bit-mask used to enable/disable DP PHY.
  12. For the Panel initialization, we read data from dp-controller node.
  13. Required properties for dp-controller:
  14. -compatible:
  15. should be "samsung,exynos5-dp".
  16. -reg:
  17. physical base address of the controller and length
  18. of memory mapped region.
  19. -interrupts:
  20. interrupt combiner values.
  21. -clocks:
  22. from common clock binding: handle to dp clock.
  23. -clock-names:
  24. from common clock binding: Shall be "dp".
  25. -interrupt-parent:
  26. phandle to Interrupt combiner node.
  27. -phys:
  28. from general PHY binding: the phandle for the PHY device.
  29. -phy-names:
  30. from general PHY binding: Should be "dp".
  31. -samsung,color-space:
  32. input video data format.
  33. COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
  34. -samsung,dynamic-range:
  35. dynamic range for input video data.
  36. VESA = 0, CEA = 1
  37. -samsung,ycbcr-coeff:
  38. YCbCr co-efficients for input video.
  39. COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
  40. -samsung,color-depth:
  41. number of bits per colour component.
  42. COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
  43. -samsung,link-rate:
  44. link rate supported by the panel.
  45. LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
  46. -samsung,lane-count:
  47. number of lanes supported by the panel.
  48. LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
  49. Optional properties for dp-controller:
  50. -interlaced:
  51. interlace scan mode.
  52. Progressive if defined, Interlaced if not defined
  53. -vsync-active-high:
  54. VSYNC polarity configuration.
  55. High if defined, Low if not defined
  56. -hsync-active-high:
  57. HSYNC polarity configuration.
  58. High if defined, Low if not defined
  59. Example:
  60. SOC specific portion:
  61. dp-controller {
  62. compatible = "samsung,exynos5-dp";
  63. reg = <0x145b0000 0x10000>;
  64. interrupts = <10 3>;
  65. interrupt-parent = <&combiner>;
  66. clocks = <&clock 342>;
  67. clock-names = "dp";
  68. phys = <&dp_phy>;
  69. phy-names = "dp";
  70. };
  71. Board Specific portion:
  72. dp-controller {
  73. samsung,color-space = <0>;
  74. samsung,dynamic-range = <0>;
  75. samsung,ycbcr-coeff = <0>;
  76. samsung,color-depth = <1>;
  77. samsung,link-rate = <0x0a>;
  78. samsung,lane-count = <4>;
  79. };