spear320.dtsi 2.9 KB

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  1. /*
  2. * DTS file for SPEAr320 SoC
  3. *
  4. * Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
  5. *
  6. * The code contained herein is licensed under the GNU General Public
  7. * License. You may obtain a copy of the GNU General Public License
  8. * Version 2 or later at the following locations:
  9. *
  10. * http://www.opensource.org/licenses/gpl-license.html
  11. * http://www.gnu.org/copyleft/gpl.html
  12. */
  13. /include/ "spear3xx.dtsi"
  14. / {
  15. ahb {
  16. #address-cells = <1>;
  17. #size-cells = <1>;
  18. compatible = "simple-bus";
  19. ranges = <0x40000000 0x40000000 0x80000000
  20. 0xd0000000 0xd0000000 0x30000000>;
  21. pinmux: pinmux@b3000000 {
  22. compatible = "st,spear320-pinmux";
  23. reg = <0xb3000000 0x1000>;
  24. #gpio-range-cells = <2>;
  25. };
  26. clcd@90000000 {
  27. compatible = "arm,pl110", "arm,primecell";
  28. reg = <0x90000000 0x1000>;
  29. interrupts = <33>;
  30. status = "disabled";
  31. };
  32. fsmc: flash@4c000000 {
  33. compatible = "st,spear600-fsmc-nand";
  34. #address-cells = <1>;
  35. #size-cells = <1>;
  36. reg = <0x4c000000 0x1000 /* FSMC Register */
  37. 0x50000000 0x0010>; /* NAND Base */
  38. reg-names = "fsmc_regs", "nand_data";
  39. st,ale-off = <0x20000>;
  40. st,cle-off = <0x10000>;
  41. status = "disabled";
  42. };
  43. sdhci@70000000 {
  44. compatible = "st,sdhci-spear";
  45. reg = <0x70000000 0x100>;
  46. interrupts = <29>;
  47. status = "disabled";
  48. };
  49. spi1: spi@a5000000 {
  50. compatible = "arm,pl022", "arm,primecell";
  51. reg = <0xa5000000 0x1000>;
  52. #address-cells = <1>;
  53. #size-cells = <0>;
  54. status = "disabled";
  55. };
  56. spi2: spi@a6000000 {
  57. compatible = "arm,pl022", "arm,primecell";
  58. reg = <0xa6000000 0x1000>;
  59. #address-cells = <1>;
  60. #size-cells = <0>;
  61. status = "disabled";
  62. };
  63. pwm: pwm@a8000000 {
  64. compatible ="st,spear-pwm";
  65. reg = <0xa8000000 0x1000>;
  66. #pwm-cells = <2>;
  67. status = "disabled";
  68. };
  69. apb {
  70. #address-cells = <1>;
  71. #size-cells = <1>;
  72. compatible = "simple-bus";
  73. ranges = <0xa0000000 0xa0000000 0x20000000
  74. 0xd0000000 0xd0000000 0x30000000>;
  75. i2c1: i2c@a7000000 {
  76. #address-cells = <1>;
  77. #size-cells = <0>;
  78. compatible = "snps,designware-i2c";
  79. reg = <0xa7000000 0x1000>;
  80. status = "disabled";
  81. };
  82. serial@a3000000 {
  83. compatible = "arm,pl011", "arm,primecell";
  84. reg = <0xa3000000 0x1000>;
  85. status = "disabled";
  86. };
  87. serial@a4000000 {
  88. compatible = "arm,pl011", "arm,primecell";
  89. reg = <0xa4000000 0x1000>;
  90. status = "disabled";
  91. };
  92. gpiopinctrl: gpio@b3000000 {
  93. compatible = "st,spear-plgpio";
  94. reg = <0xb3000000 0x1000>;
  95. #interrupt-cells = <1>;
  96. interrupt-controller;
  97. gpio-controller;
  98. #gpio-cells = <2>;
  99. gpio-ranges = <&pinmux 0 102>;
  100. status = "disabled";
  101. st-plgpio,ngpio = <102>;
  102. st-plgpio,enb-reg = <0x24>;
  103. st-plgpio,wdata-reg = <0x34>;
  104. st-plgpio,dir-reg = <0x44>;
  105. st-plgpio,ie-reg = <0x64>;
  106. st-plgpio,rdata-reg = <0x54>;
  107. st-plgpio,mis-reg = <0x84>;
  108. st-plgpio,eit-reg = <0x94>;
  109. };
  110. };
  111. };
  112. };