omap-mcpdm.c 14 KB

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  1. /*
  2. * omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port
  3. *
  4. * Copyright (C) 2009 - 2011 Texas Instruments
  5. *
  6. * Author: Misael Lopez Cruz <misael.lopez@ti.com>
  7. * Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
  8. * Margarita Olaya <magi.olaya@ti.com>
  9. * Peter Ujfalusi <peter.ujfalusi@ti.com>
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License
  13. * version 2 as published by the Free Software Foundation.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  23. * 02110-1301 USA
  24. *
  25. */
  26. #include <linux/init.h>
  27. #include <linux/module.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/err.h>
  31. #include <linux/io.h>
  32. #include <linux/irq.h>
  33. #include <linux/slab.h>
  34. #include <linux/pm_runtime.h>
  35. #include <linux/of_device.h>
  36. #include <sound/core.h>
  37. #include <sound/pcm.h>
  38. #include <sound/pcm_params.h>
  39. #include <sound/soc.h>
  40. #include "omap-mcpdm.h"
  41. #include "omap-pcm.h"
  42. #define OMAP44XX_MCPDM_L3_BASE 0x49032000
  43. struct mcpdm_link_config {
  44. u32 link_mask; /* channel mask for the direction */
  45. u32 threshold; /* FIFO threshold */
  46. };
  47. struct omap_mcpdm {
  48. struct device *dev;
  49. unsigned long phys_base;
  50. void __iomem *io_base;
  51. int irq;
  52. struct mutex mutex;
  53. /* Playback/Capture configuration */
  54. struct mcpdm_link_config config[2];
  55. /* McPDM dn offsets for rx1, and 2 channels */
  56. u32 dn_rx_offset;
  57. /* McPDM needs to be restarted due to runtime reconfiguration */
  58. bool restart;
  59. };
  60. /*
  61. * Stream DMA parameters
  62. */
  63. static struct omap_pcm_dma_data omap_mcpdm_dai_dma_params[] = {
  64. {
  65. .name = "Audio playback",
  66. },
  67. {
  68. .name = "Audio capture",
  69. },
  70. };
  71. static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
  72. {
  73. __raw_writel(val, mcpdm->io_base + reg);
  74. }
  75. static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
  76. {
  77. return __raw_readl(mcpdm->io_base + reg);
  78. }
  79. #ifdef DEBUG
  80. static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
  81. {
  82. dev_dbg(mcpdm->dev, "***********************\n");
  83. dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n",
  84. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
  85. dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
  86. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
  87. dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n",
  88. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
  89. dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n",
  90. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
  91. dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
  92. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
  93. dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
  94. omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
  95. dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n",
  96. omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
  97. dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
  98. omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
  99. dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n",
  100. omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
  101. dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n",
  102. omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
  103. dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
  104. omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
  105. dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
  106. omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
  107. dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n",
  108. omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
  109. dev_dbg(mcpdm->dev, "***********************\n");
  110. }
  111. #else
  112. static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
  113. #endif
  114. /*
  115. * Enables the transfer through the PDM interface to/from the Phoenix
  116. * codec by enabling the corresponding UP or DN channels.
  117. */
  118. static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
  119. {
  120. u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
  121. u32 link_mask = mcpdm->config[0].link_mask | mcpdm->config[1].link_mask;
  122. ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
  123. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  124. ctrl |= link_mask;
  125. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  126. ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
  127. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  128. }
  129. /*
  130. * Disables the transfer through the PDM interface to/from the Phoenix
  131. * codec by disabling the corresponding UP or DN channels.
  132. */
  133. static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
  134. {
  135. u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
  136. u32 link_mask = MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK;
  137. ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
  138. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  139. ctrl &= ~(link_mask);
  140. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  141. ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
  142. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  143. }
  144. /*
  145. * Is the physical McPDM interface active.
  146. */
  147. static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
  148. {
  149. return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
  150. (MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK);
  151. }
  152. /*
  153. * Configures McPDM uplink, and downlink for audio.
  154. * This function should be called before omap_mcpdm_start.
  155. */
  156. static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
  157. {
  158. omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
  159. MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL |
  160. MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
  161. /* Enable DN RX1/2 offset cancellation feature, if configured */
  162. if (mcpdm->dn_rx_offset) {
  163. u32 dn_offset = mcpdm->dn_rx_offset;
  164. omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
  165. dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN);
  166. omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
  167. }
  168. omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN,
  169. mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold);
  170. omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP,
  171. mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold);
  172. omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
  173. MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
  174. }
  175. /*
  176. * Cleans McPDM uplink, and downlink configuration.
  177. * This function should be called when the stream is closed.
  178. */
  179. static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
  180. {
  181. /* Disable irq request generation for downlink */
  182. omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
  183. MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL);
  184. /* Disable DMA request generation for downlink */
  185. omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);
  186. /* Disable irq request generation for uplink */
  187. omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
  188. MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
  189. /* Disable DMA request generation for uplink */
  190. omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
  191. /* Disable RX1/2 offset cancellation */
  192. if (mcpdm->dn_rx_offset)
  193. omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
  194. }
  195. static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
  196. {
  197. struct omap_mcpdm *mcpdm = dev_id;
  198. int irq_status;
  199. irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);
  200. /* Acknowledge irq event */
  201. omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);
  202. if (irq_status & MCPDM_DN_IRQ_FULL)
  203. dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");
  204. if (irq_status & MCPDM_DN_IRQ_EMPTY)
  205. dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");
  206. if (irq_status & MCPDM_DN_IRQ)
  207. dev_dbg(mcpdm->dev, "DN (playback) write request\n");
  208. if (irq_status & MCPDM_UP_IRQ_FULL)
  209. dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");
  210. if (irq_status & MCPDM_UP_IRQ_EMPTY)
  211. dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");
  212. if (irq_status & MCPDM_UP_IRQ)
  213. dev_dbg(mcpdm->dev, "UP (capture) write request\n");
  214. return IRQ_HANDLED;
  215. }
  216. static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
  217. struct snd_soc_dai *dai)
  218. {
  219. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  220. mutex_lock(&mcpdm->mutex);
  221. if (!dai->active) {
  222. u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
  223. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl | MCPDM_WD_EN);
  224. omap_mcpdm_open_streams(mcpdm);
  225. }
  226. mutex_unlock(&mcpdm->mutex);
  227. snd_soc_dai_set_dma_data(dai, substream,
  228. &omap_mcpdm_dai_dma_params[substream->stream]);
  229. return 0;
  230. }
  231. static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
  232. struct snd_soc_dai *dai)
  233. {
  234. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  235. mutex_lock(&mcpdm->mutex);
  236. if (!dai->active) {
  237. if (omap_mcpdm_active(mcpdm)) {
  238. omap_mcpdm_stop(mcpdm);
  239. omap_mcpdm_close_streams(mcpdm);
  240. mcpdm->config[0].link_mask = 0;
  241. mcpdm->config[1].link_mask = 0;
  242. }
  243. }
  244. mutex_unlock(&mcpdm->mutex);
  245. }
  246. static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
  247. struct snd_pcm_hw_params *params,
  248. struct snd_soc_dai *dai)
  249. {
  250. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  251. int stream = substream->stream;
  252. struct omap_pcm_dma_data *dma_data;
  253. u32 threshold;
  254. int channels;
  255. int link_mask = 0;
  256. channels = params_channels(params);
  257. switch (channels) {
  258. case 5:
  259. if (stream == SNDRV_PCM_STREAM_CAPTURE)
  260. /* up to 3 channels for capture */
  261. return -EINVAL;
  262. link_mask |= 1 << 4;
  263. case 4:
  264. if (stream == SNDRV_PCM_STREAM_CAPTURE)
  265. /* up to 3 channels for capture */
  266. return -EINVAL;
  267. link_mask |= 1 << 3;
  268. case 3:
  269. link_mask |= 1 << 2;
  270. case 2:
  271. link_mask |= 1 << 1;
  272. case 1:
  273. link_mask |= 1 << 0;
  274. break;
  275. default:
  276. /* unsupported number of channels */
  277. return -EINVAL;
  278. }
  279. dma_data = snd_soc_dai_get_dma_data(dai, substream);
  280. threshold = mcpdm->config[stream].threshold;
  281. /* Configure McPDM channels, and DMA packet size */
  282. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  283. link_mask <<= 3;
  284. /* If capture is not running assume a stereo stream to come */
  285. if (!mcpdm->config[!stream].link_mask)
  286. mcpdm->config[!stream].link_mask = 0x3;
  287. dma_data->packet_size =
  288. (MCPDM_DN_THRES_MAX - threshold) * channels;
  289. } else {
  290. /* If playback is not running assume a stereo stream to come */
  291. if (!mcpdm->config[!stream].link_mask)
  292. mcpdm->config[!stream].link_mask = (0x3 << 3);
  293. dma_data->packet_size = threshold * channels;
  294. }
  295. /* Check if we need to restart McPDM with this stream */
  296. if (mcpdm->config[stream].link_mask &&
  297. mcpdm->config[stream].link_mask != link_mask)
  298. mcpdm->restart = true;
  299. mcpdm->config[stream].link_mask = link_mask;
  300. return 0;
  301. }
  302. static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
  303. struct snd_soc_dai *dai)
  304. {
  305. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  306. if (!omap_mcpdm_active(mcpdm)) {
  307. omap_mcpdm_start(mcpdm);
  308. omap_mcpdm_reg_dump(mcpdm);
  309. } else if (mcpdm->restart) {
  310. omap_mcpdm_stop(mcpdm);
  311. omap_mcpdm_start(mcpdm);
  312. mcpdm->restart = false;
  313. omap_mcpdm_reg_dump(mcpdm);
  314. }
  315. return 0;
  316. }
  317. static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
  318. .startup = omap_mcpdm_dai_startup,
  319. .shutdown = omap_mcpdm_dai_shutdown,
  320. .hw_params = omap_mcpdm_dai_hw_params,
  321. .prepare = omap_mcpdm_prepare,
  322. };
  323. static int omap_mcpdm_probe(struct snd_soc_dai *dai)
  324. {
  325. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  326. int ret;
  327. pm_runtime_enable(mcpdm->dev);
  328. /* Disable lines while request is ongoing */
  329. pm_runtime_get_sync(mcpdm->dev);
  330. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
  331. ret = devm_request_irq(mcpdm->dev, mcpdm->irq, omap_mcpdm_irq_handler,
  332. 0, "McPDM", (void *)mcpdm);
  333. pm_runtime_put_sync(mcpdm->dev);
  334. if (ret) {
  335. dev_err(mcpdm->dev, "Request for IRQ failed\n");
  336. pm_runtime_disable(mcpdm->dev);
  337. }
  338. /* Configure McPDM threshold values */
  339. mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold = 2;
  340. mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold =
  341. MCPDM_UP_THRES_MAX - 3;
  342. return ret;
  343. }
  344. static int omap_mcpdm_remove(struct snd_soc_dai *dai)
  345. {
  346. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  347. pm_runtime_disable(mcpdm->dev);
  348. return 0;
  349. }
  350. #define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
  351. #define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE
  352. static struct snd_soc_dai_driver omap_mcpdm_dai = {
  353. .probe = omap_mcpdm_probe,
  354. .remove = omap_mcpdm_remove,
  355. .probe_order = SND_SOC_COMP_ORDER_LATE,
  356. .remove_order = SND_SOC_COMP_ORDER_EARLY,
  357. .playback = {
  358. .channels_min = 1,
  359. .channels_max = 5,
  360. .rates = OMAP_MCPDM_RATES,
  361. .formats = OMAP_MCPDM_FORMATS,
  362. .sig_bits = 24,
  363. },
  364. .capture = {
  365. .channels_min = 1,
  366. .channels_max = 3,
  367. .rates = OMAP_MCPDM_RATES,
  368. .formats = OMAP_MCPDM_FORMATS,
  369. .sig_bits = 24,
  370. },
  371. .ops = &omap_mcpdm_dai_ops,
  372. };
  373. void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
  374. u8 rx1, u8 rx2)
  375. {
  376. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
  377. mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2);
  378. }
  379. EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);
  380. static int asoc_mcpdm_probe(struct platform_device *pdev)
  381. {
  382. struct omap_mcpdm *mcpdm;
  383. struct resource *res;
  384. mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
  385. if (!mcpdm)
  386. return -ENOMEM;
  387. platform_set_drvdata(pdev, mcpdm);
  388. mutex_init(&mcpdm->mutex);
  389. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
  390. if (res == NULL)
  391. return -ENOMEM;
  392. omap_mcpdm_dai_dma_params[0].port_addr = res->start + MCPDM_REG_DN_DATA;
  393. omap_mcpdm_dai_dma_params[1].port_addr = res->start + MCPDM_REG_UP_DATA;
  394. res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "dn_link");
  395. if (!res)
  396. return -ENODEV;
  397. omap_mcpdm_dai_dma_params[0].dma_req = res->start;
  398. res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "up_link");
  399. if (!res)
  400. return -ENODEV;
  401. omap_mcpdm_dai_dma_params[1].dma_req = res->start;
  402. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
  403. if (res == NULL)
  404. return -ENOMEM;
  405. mcpdm->io_base = devm_ioremap_resource(&pdev->dev, res);
  406. if (IS_ERR(mcpdm->io_base))
  407. return PTR_ERR(mcpdm->io_base);
  408. mcpdm->irq = platform_get_irq(pdev, 0);
  409. if (mcpdm->irq < 0)
  410. return mcpdm->irq;
  411. mcpdm->dev = &pdev->dev;
  412. return snd_soc_register_dai(&pdev->dev, &omap_mcpdm_dai);
  413. }
  414. static int asoc_mcpdm_remove(struct platform_device *pdev)
  415. {
  416. snd_soc_unregister_dai(&pdev->dev);
  417. return 0;
  418. }
  419. static const struct of_device_id omap_mcpdm_of_match[] = {
  420. { .compatible = "ti,omap4-mcpdm", },
  421. { }
  422. };
  423. MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);
  424. static struct platform_driver asoc_mcpdm_driver = {
  425. .driver = {
  426. .name = "omap-mcpdm",
  427. .owner = THIS_MODULE,
  428. .of_match_table = omap_mcpdm_of_match,
  429. },
  430. .probe = asoc_mcpdm_probe,
  431. .remove = asoc_mcpdm_remove,
  432. };
  433. module_platform_driver(asoc_mcpdm_driver);
  434. MODULE_ALIAS("platform:omap-mcpdm");
  435. MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
  436. MODULE_DESCRIPTION("OMAP PDM SoC Interface");
  437. MODULE_LICENSE("GPL");