iwl3945-base.c 236 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/version.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <linux/dma-mapping.h>
  35. #include <linux/delay.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/wireless.h>
  39. #include <linux/firmware.h>
  40. #include <linux/etherdevice.h>
  41. #include <linux/if_arp.h>
  42. #include <net/ieee80211_radiotap.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #include "iwl-3945-core.h"
  46. #include "iwl-3945.h"
  47. #include "iwl-helpers.h"
  48. #ifdef CONFIG_IWL3945_DEBUG
  49. u32 iwl3945_debug_level;
  50. #endif
  51. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  52. struct iwl3945_tx_queue *txq);
  53. /******************************************************************************
  54. *
  55. * module boiler plate
  56. *
  57. ******************************************************************************/
  58. /* module parameters */
  59. static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
  60. static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */
  61. static int iwl3945_param_disable; /* def: 0 = enable radio */
  62. static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
  63. int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
  64. static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */
  65. int iwl3945_param_queues_num = IWL39_MAX_NUM_QUEUES; /* def: 8 Tx queues */
  66. /*
  67. * module name, copyright, version, etc.
  68. * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
  69. */
  70. #define DRV_DESCRIPTION \
  71. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  72. #ifdef CONFIG_IWL3945_DEBUG
  73. #define VD "d"
  74. #else
  75. #define VD
  76. #endif
  77. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  78. #define VS "s"
  79. #else
  80. #define VS
  81. #endif
  82. #define IWLWIFI_VERSION "1.2.26k" VD VS
  83. #define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
  84. #define DRV_VERSION IWLWIFI_VERSION
  85. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  86. MODULE_VERSION(DRV_VERSION);
  87. MODULE_AUTHOR(DRV_COPYRIGHT);
  88. MODULE_LICENSE("GPL");
  89. static const struct ieee80211_supported_band *iwl3945_get_band(
  90. struct iwl3945_priv *priv, enum ieee80211_band band)
  91. {
  92. return priv->hw->wiphy->bands[band];
  93. }
  94. static int iwl3945_is_empty_essid(const char *essid, int essid_len)
  95. {
  96. /* Single white space is for Linksys APs */
  97. if (essid_len == 1 && essid[0] == ' ')
  98. return 1;
  99. /* Otherwise, if the entire essid is 0, we assume it is hidden */
  100. while (essid_len) {
  101. essid_len--;
  102. if (essid[essid_len] != '\0')
  103. return 0;
  104. }
  105. return 1;
  106. }
  107. static const char *iwl3945_escape_essid(const char *essid, u8 essid_len)
  108. {
  109. static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
  110. const char *s = essid;
  111. char *d = escaped;
  112. if (iwl3945_is_empty_essid(essid, essid_len)) {
  113. memcpy(escaped, "<hidden>", sizeof("<hidden>"));
  114. return escaped;
  115. }
  116. essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
  117. while (essid_len--) {
  118. if (*s == '\0') {
  119. *d++ = '\\';
  120. *d++ = '0';
  121. s++;
  122. } else
  123. *d++ = *s++;
  124. }
  125. *d = '\0';
  126. return escaped;
  127. }
  128. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  129. * DMA services
  130. *
  131. * Theory of operation
  132. *
  133. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  134. * of buffer descriptors, each of which points to one or more data buffers for
  135. * the device to read from or fill. Driver and device exchange status of each
  136. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  137. * entries in each circular buffer, to protect against confusing empty and full
  138. * queue states.
  139. *
  140. * The device reads or writes the data in the queues via the device's several
  141. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  142. *
  143. * For Tx queue, there are low mark and high mark limits. If, after queuing
  144. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  145. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  146. * Tx queue resumed.
  147. *
  148. * The 3945 operates with six queues: One receive queue, one transmit queue
  149. * (#4) for sending commands to the device firmware, and four transmit queues
  150. * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
  151. ***************************************************/
  152. int iwl3945_queue_space(const struct iwl3945_queue *q)
  153. {
  154. int s = q->read_ptr - q->write_ptr;
  155. if (q->read_ptr > q->write_ptr)
  156. s -= q->n_bd;
  157. if (s <= 0)
  158. s += q->n_window;
  159. /* keep some reserve to not confuse empty and full situations */
  160. s -= 2;
  161. if (s < 0)
  162. s = 0;
  163. return s;
  164. }
  165. int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i)
  166. {
  167. return q->write_ptr > q->read_ptr ?
  168. (i >= q->read_ptr && i < q->write_ptr) :
  169. !(i < q->read_ptr && i >= q->write_ptr);
  170. }
  171. static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
  172. {
  173. /* This is for scan command, the big buffer at end of command array */
  174. if (is_huge)
  175. return q->n_window; /* must be power of 2 */
  176. /* Otherwise, use normal size buffers */
  177. return index & (q->n_window - 1);
  178. }
  179. /**
  180. * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
  181. */
  182. static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
  183. int count, int slots_num, u32 id)
  184. {
  185. q->n_bd = count;
  186. q->n_window = slots_num;
  187. q->id = id;
  188. /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
  189. * and iwl_queue_dec_wrap are broken. */
  190. BUG_ON(!is_power_of_2(count));
  191. /* slots_num must be power-of-two size, otherwise
  192. * get_cmd_index is broken. */
  193. BUG_ON(!is_power_of_2(slots_num));
  194. q->low_mark = q->n_window / 4;
  195. if (q->low_mark < 4)
  196. q->low_mark = 4;
  197. q->high_mark = q->n_window / 8;
  198. if (q->high_mark < 2)
  199. q->high_mark = 2;
  200. q->write_ptr = q->read_ptr = 0;
  201. return 0;
  202. }
  203. /**
  204. * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  205. */
  206. static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
  207. struct iwl3945_tx_queue *txq, u32 id)
  208. {
  209. struct pci_dev *dev = priv->pci_dev;
  210. /* Driver private data, only for Tx (not command) queues,
  211. * not shared with device. */
  212. if (id != IWL_CMD_QUEUE_NUM) {
  213. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  214. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  215. if (!txq->txb) {
  216. IWL_ERROR("kmalloc for auxiliary BD "
  217. "structures failed\n");
  218. goto error;
  219. }
  220. } else
  221. txq->txb = NULL;
  222. /* Circular buffer of transmit frame descriptors (TFDs),
  223. * shared with device */
  224. txq->bd = pci_alloc_consistent(dev,
  225. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
  226. &txq->q.dma_addr);
  227. if (!txq->bd) {
  228. IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
  229. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
  230. goto error;
  231. }
  232. txq->q.id = id;
  233. return 0;
  234. error:
  235. if (txq->txb) {
  236. kfree(txq->txb);
  237. txq->txb = NULL;
  238. }
  239. return -ENOMEM;
  240. }
  241. /**
  242. * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
  243. */
  244. int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
  245. struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
  246. {
  247. struct pci_dev *dev = priv->pci_dev;
  248. int len;
  249. int rc = 0;
  250. /*
  251. * Alloc buffer array for commands (Tx or other types of commands).
  252. * For the command queue (#4), allocate command space + one big
  253. * command for scan, since scan command is very huge; the system will
  254. * not have two scans at the same time, so only one is needed.
  255. * For data Tx queues (all other queues), no super-size command
  256. * space is needed.
  257. */
  258. len = sizeof(struct iwl3945_cmd) * slots_num;
  259. if (txq_id == IWL_CMD_QUEUE_NUM)
  260. len += IWL_MAX_SCAN_SIZE;
  261. txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
  262. if (!txq->cmd)
  263. return -ENOMEM;
  264. /* Alloc driver data array and TFD circular buffer */
  265. rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
  266. if (rc) {
  267. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  268. return -ENOMEM;
  269. }
  270. txq->need_update = 0;
  271. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  272. * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
  273. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  274. /* Initialize queue high/low-water, head/tail indexes */
  275. iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  276. /* Tell device where to find queue, enable DMA channel. */
  277. iwl3945_hw_tx_queue_init(priv, txq);
  278. return 0;
  279. }
  280. /**
  281. * iwl3945_tx_queue_free - Deallocate DMA queue.
  282. * @txq: Transmit queue to deallocate.
  283. *
  284. * Empty queue by removing and destroying all BD's.
  285. * Free all buffers.
  286. * 0-fill, but do not free "txq" descriptor structure.
  287. */
  288. void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
  289. {
  290. struct iwl3945_queue *q = &txq->q;
  291. struct pci_dev *dev = priv->pci_dev;
  292. int len;
  293. if (q->n_bd == 0)
  294. return;
  295. /* first, empty all BD's */
  296. for (; q->write_ptr != q->read_ptr;
  297. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
  298. iwl3945_hw_txq_free_tfd(priv, txq);
  299. len = sizeof(struct iwl3945_cmd) * q->n_window;
  300. if (q->id == IWL_CMD_QUEUE_NUM)
  301. len += IWL_MAX_SCAN_SIZE;
  302. /* De-alloc array of command/tx buffers */
  303. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  304. /* De-alloc circular buffer of TFDs */
  305. if (txq->q.n_bd)
  306. pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
  307. txq->q.n_bd, txq->bd, txq->q.dma_addr);
  308. /* De-alloc array of per-TFD driver data */
  309. if (txq->txb) {
  310. kfree(txq->txb);
  311. txq->txb = NULL;
  312. }
  313. /* 0-fill queue descriptor structure */
  314. memset(txq, 0, sizeof(*txq));
  315. }
  316. const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  317. /*************** STATION TABLE MANAGEMENT ****
  318. * mac80211 should be examined to determine if sta_info is duplicating
  319. * the functionality provided here
  320. */
  321. /**************************************************************/
  322. #if 0 /* temporary disable till we add real remove station */
  323. /**
  324. * iwl3945_remove_station - Remove driver's knowledge of station.
  325. *
  326. * NOTE: This does not remove station from device's station table.
  327. */
  328. static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
  329. {
  330. int index = IWL_INVALID_STATION;
  331. int i;
  332. unsigned long flags;
  333. spin_lock_irqsave(&priv->sta_lock, flags);
  334. if (is_ap)
  335. index = IWL_AP_ID;
  336. else if (is_broadcast_ether_addr(addr))
  337. index = priv->hw_setting.bcast_sta_id;
  338. else
  339. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
  340. if (priv->stations[i].used &&
  341. !compare_ether_addr(priv->stations[i].sta.sta.addr,
  342. addr)) {
  343. index = i;
  344. break;
  345. }
  346. if (unlikely(index == IWL_INVALID_STATION))
  347. goto out;
  348. if (priv->stations[index].used) {
  349. priv->stations[index].used = 0;
  350. priv->num_stations--;
  351. }
  352. BUG_ON(priv->num_stations < 0);
  353. out:
  354. spin_unlock_irqrestore(&priv->sta_lock, flags);
  355. return 0;
  356. }
  357. #endif
  358. /**
  359. * iwl3945_clear_stations_table - Clear the driver's station table
  360. *
  361. * NOTE: This does not clear or otherwise alter the device's station table.
  362. */
  363. static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
  364. {
  365. unsigned long flags;
  366. spin_lock_irqsave(&priv->sta_lock, flags);
  367. priv->num_stations = 0;
  368. memset(priv->stations, 0, sizeof(priv->stations));
  369. spin_unlock_irqrestore(&priv->sta_lock, flags);
  370. }
  371. /**
  372. * iwl3945_add_station - Add station to station tables in driver and device
  373. */
  374. u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
  375. {
  376. int i;
  377. int index = IWL_INVALID_STATION;
  378. struct iwl3945_station_entry *station;
  379. unsigned long flags_spin;
  380. DECLARE_MAC_BUF(mac);
  381. u8 rate;
  382. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  383. if (is_ap)
  384. index = IWL_AP_ID;
  385. else if (is_broadcast_ether_addr(addr))
  386. index = priv->hw_setting.bcast_sta_id;
  387. else
  388. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
  389. if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
  390. addr)) {
  391. index = i;
  392. break;
  393. }
  394. if (!priv->stations[i].used &&
  395. index == IWL_INVALID_STATION)
  396. index = i;
  397. }
  398. /* These two conditions has the same outcome but keep them separate
  399. since they have different meaning */
  400. if (unlikely(index == IWL_INVALID_STATION)) {
  401. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  402. return index;
  403. }
  404. if (priv->stations[index].used &&
  405. !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
  406. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  407. return index;
  408. }
  409. IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
  410. station = &priv->stations[index];
  411. station->used = 1;
  412. priv->num_stations++;
  413. /* Set up the REPLY_ADD_STA command to send to device */
  414. memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
  415. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  416. station->sta.mode = 0;
  417. station->sta.sta.sta_id = index;
  418. station->sta.station_flags = 0;
  419. if (priv->band == IEEE80211_BAND_5GHZ)
  420. rate = IWL_RATE_6M_PLCP;
  421. else
  422. rate = IWL_RATE_1M_PLCP;
  423. /* Turn on both antennas for the station... */
  424. station->sta.rate_n_flags =
  425. iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
  426. station->current_rate.rate_n_flags =
  427. le16_to_cpu(station->sta.rate_n_flags);
  428. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  429. /* Add station to device's station table */
  430. iwl3945_send_add_station(priv, &station->sta, flags);
  431. return index;
  432. }
  433. /*************** DRIVER STATUS FUNCTIONS *****/
  434. static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
  435. {
  436. /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
  437. * set but EXIT_PENDING is not */
  438. return test_bit(STATUS_READY, &priv->status) &&
  439. test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
  440. !test_bit(STATUS_EXIT_PENDING, &priv->status);
  441. }
  442. static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
  443. {
  444. return test_bit(STATUS_ALIVE, &priv->status);
  445. }
  446. static inline int iwl3945_is_init(struct iwl3945_priv *priv)
  447. {
  448. return test_bit(STATUS_INIT, &priv->status);
  449. }
  450. static inline int iwl3945_is_rfkill_sw(struct iwl3945_priv *priv)
  451. {
  452. return test_bit(STATUS_RF_KILL_SW, &priv->status);
  453. }
  454. static inline int iwl3945_is_rfkill_hw(struct iwl3945_priv *priv)
  455. {
  456. return test_bit(STATUS_RF_KILL_HW, &priv->status);
  457. }
  458. static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
  459. {
  460. return iwl3945_is_rfkill_hw(priv) ||
  461. iwl3945_is_rfkill_sw(priv);
  462. }
  463. static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
  464. {
  465. if (iwl3945_is_rfkill(priv))
  466. return 0;
  467. return iwl3945_is_ready(priv);
  468. }
  469. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  470. #define IWL_CMD(x) case x : return #x
  471. static const char *get_cmd_string(u8 cmd)
  472. {
  473. switch (cmd) {
  474. IWL_CMD(REPLY_ALIVE);
  475. IWL_CMD(REPLY_ERROR);
  476. IWL_CMD(REPLY_RXON);
  477. IWL_CMD(REPLY_RXON_ASSOC);
  478. IWL_CMD(REPLY_QOS_PARAM);
  479. IWL_CMD(REPLY_RXON_TIMING);
  480. IWL_CMD(REPLY_ADD_STA);
  481. IWL_CMD(REPLY_REMOVE_STA);
  482. IWL_CMD(REPLY_REMOVE_ALL_STA);
  483. IWL_CMD(REPLY_3945_RX);
  484. IWL_CMD(REPLY_TX);
  485. IWL_CMD(REPLY_RATE_SCALE);
  486. IWL_CMD(REPLY_LEDS_CMD);
  487. IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
  488. IWL_CMD(RADAR_NOTIFICATION);
  489. IWL_CMD(REPLY_QUIET_CMD);
  490. IWL_CMD(REPLY_CHANNEL_SWITCH);
  491. IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
  492. IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
  493. IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
  494. IWL_CMD(POWER_TABLE_CMD);
  495. IWL_CMD(PM_SLEEP_NOTIFICATION);
  496. IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
  497. IWL_CMD(REPLY_SCAN_CMD);
  498. IWL_CMD(REPLY_SCAN_ABORT_CMD);
  499. IWL_CMD(SCAN_START_NOTIFICATION);
  500. IWL_CMD(SCAN_RESULTS_NOTIFICATION);
  501. IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
  502. IWL_CMD(BEACON_NOTIFICATION);
  503. IWL_CMD(REPLY_TX_BEACON);
  504. IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
  505. IWL_CMD(QUIET_NOTIFICATION);
  506. IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
  507. IWL_CMD(MEASURE_ABORT_NOTIFICATION);
  508. IWL_CMD(REPLY_BT_CONFIG);
  509. IWL_CMD(REPLY_STATISTICS_CMD);
  510. IWL_CMD(STATISTICS_NOTIFICATION);
  511. IWL_CMD(REPLY_CARD_STATE_CMD);
  512. IWL_CMD(CARD_STATE_NOTIFICATION);
  513. IWL_CMD(MISSED_BEACONS_NOTIFICATION);
  514. default:
  515. return "UNKNOWN";
  516. }
  517. }
  518. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  519. /**
  520. * iwl3945_enqueue_hcmd - enqueue a uCode command
  521. * @priv: device private data point
  522. * @cmd: a point to the ucode command structure
  523. *
  524. * The function returns < 0 values to indicate the operation is
  525. * failed. On success, it turns the index (> 0) of command in the
  526. * command queue.
  527. */
  528. static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  529. {
  530. struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
  531. struct iwl3945_queue *q = &txq->q;
  532. struct iwl3945_tfd_frame *tfd;
  533. u32 *control_flags;
  534. struct iwl3945_cmd *out_cmd;
  535. u32 idx;
  536. u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  537. dma_addr_t phys_addr;
  538. int pad;
  539. u16 count;
  540. int ret;
  541. unsigned long flags;
  542. /* If any of the command structures end up being larger than
  543. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  544. * we will need to increase the size of the TFD entries */
  545. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  546. !(cmd->meta.flags & CMD_SIZE_HUGE));
  547. if (iwl3945_is_rfkill(priv)) {
  548. IWL_DEBUG_INFO("Not sending command - RF KILL");
  549. return -EIO;
  550. }
  551. if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
  552. IWL_ERROR("No space for Tx\n");
  553. return -ENOSPC;
  554. }
  555. spin_lock_irqsave(&priv->hcmd_lock, flags);
  556. tfd = &txq->bd[q->write_ptr];
  557. memset(tfd, 0, sizeof(*tfd));
  558. control_flags = (u32 *) tfd;
  559. idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
  560. out_cmd = &txq->cmd[idx];
  561. out_cmd->hdr.cmd = cmd->id;
  562. memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
  563. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  564. /* At this point, the out_cmd now has all of the incoming cmd
  565. * information */
  566. out_cmd->hdr.flags = 0;
  567. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
  568. INDEX_TO_SEQ(q->write_ptr));
  569. if (out_cmd->meta.flags & CMD_SIZE_HUGE)
  570. out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
  571. phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
  572. offsetof(struct iwl3945_cmd, hdr);
  573. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
  574. pad = U32_PAD(cmd->len);
  575. count = TFD_CTL_COUNT_GET(*control_flags);
  576. *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
  577. IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
  578. "%d bytes at %d[%d]:%d\n",
  579. get_cmd_string(out_cmd->hdr.cmd),
  580. out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
  581. fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
  582. txq->need_update = 1;
  583. /* Increment and update queue's write index */
  584. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  585. ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
  586. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  587. return ret ? ret : idx;
  588. }
  589. static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  590. {
  591. int ret;
  592. BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
  593. /* An asynchronous command can not expect an SKB to be set. */
  594. BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
  595. /* An asynchronous command MUST have a callback. */
  596. BUG_ON(!cmd->meta.u.callback);
  597. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  598. return -EBUSY;
  599. ret = iwl3945_enqueue_hcmd(priv, cmd);
  600. if (ret < 0) {
  601. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  602. get_cmd_string(cmd->id), ret);
  603. return ret;
  604. }
  605. return 0;
  606. }
  607. static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  608. {
  609. int cmd_idx;
  610. int ret;
  611. BUG_ON(cmd->meta.flags & CMD_ASYNC);
  612. /* A synchronous command can not have a callback set. */
  613. BUG_ON(cmd->meta.u.callback != NULL);
  614. if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
  615. IWL_ERROR("Error sending %s: Already sending a host command\n",
  616. get_cmd_string(cmd->id));
  617. ret = -EBUSY;
  618. goto out;
  619. }
  620. set_bit(STATUS_HCMD_ACTIVE, &priv->status);
  621. if (cmd->meta.flags & CMD_WANT_SKB)
  622. cmd->meta.source = &cmd->meta;
  623. cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
  624. if (cmd_idx < 0) {
  625. ret = cmd_idx;
  626. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  627. get_cmd_string(cmd->id), ret);
  628. goto out;
  629. }
  630. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  631. !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
  632. HOST_COMPLETE_TIMEOUT);
  633. if (!ret) {
  634. if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
  635. IWL_ERROR("Error sending %s: time out after %dms.\n",
  636. get_cmd_string(cmd->id),
  637. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  638. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  639. ret = -ETIMEDOUT;
  640. goto cancel;
  641. }
  642. }
  643. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  644. IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
  645. get_cmd_string(cmd->id));
  646. ret = -ECANCELED;
  647. goto fail;
  648. }
  649. if (test_bit(STATUS_FW_ERROR, &priv->status)) {
  650. IWL_DEBUG_INFO("Command %s failed: FW Error\n",
  651. get_cmd_string(cmd->id));
  652. ret = -EIO;
  653. goto fail;
  654. }
  655. if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
  656. IWL_ERROR("Error: Response NULL in '%s'\n",
  657. get_cmd_string(cmd->id));
  658. ret = -EIO;
  659. goto out;
  660. }
  661. ret = 0;
  662. goto out;
  663. cancel:
  664. if (cmd->meta.flags & CMD_WANT_SKB) {
  665. struct iwl3945_cmd *qcmd;
  666. /* Cancel the CMD_WANT_SKB flag for the cmd in the
  667. * TX cmd queue. Otherwise in case the cmd comes
  668. * in later, it will possibly set an invalid
  669. * address (cmd->meta.source). */
  670. qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
  671. qcmd->meta.flags &= ~CMD_WANT_SKB;
  672. }
  673. fail:
  674. if (cmd->meta.u.skb) {
  675. dev_kfree_skb_any(cmd->meta.u.skb);
  676. cmd->meta.u.skb = NULL;
  677. }
  678. out:
  679. clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
  680. return ret;
  681. }
  682. int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  683. {
  684. if (cmd->meta.flags & CMD_ASYNC)
  685. return iwl3945_send_cmd_async(priv, cmd);
  686. return iwl3945_send_cmd_sync(priv, cmd);
  687. }
  688. int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
  689. {
  690. struct iwl3945_host_cmd cmd = {
  691. .id = id,
  692. .len = len,
  693. .data = data,
  694. };
  695. return iwl3945_send_cmd_sync(priv, &cmd);
  696. }
  697. static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
  698. {
  699. struct iwl3945_host_cmd cmd = {
  700. .id = id,
  701. .len = sizeof(val),
  702. .data = &val,
  703. };
  704. return iwl3945_send_cmd_sync(priv, &cmd);
  705. }
  706. int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
  707. {
  708. return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
  709. }
  710. /**
  711. * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
  712. * @band: 2.4 or 5 GHz band
  713. * @channel: Any channel valid for the requested band
  714. * In addition to setting the staging RXON, priv->band is also set.
  715. *
  716. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  717. * in the staging RXON flag structure based on the band
  718. */
  719. static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
  720. enum ieee80211_band band,
  721. u16 channel)
  722. {
  723. if (!iwl3945_get_channel_info(priv, band, channel)) {
  724. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  725. channel, band);
  726. return -EINVAL;
  727. }
  728. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  729. (priv->band == band))
  730. return 0;
  731. priv->staging_rxon.channel = cpu_to_le16(channel);
  732. if (band == IEEE80211_BAND_5GHZ)
  733. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  734. else
  735. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  736. priv->band = band;
  737. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
  738. return 0;
  739. }
  740. /**
  741. * iwl3945_check_rxon_cmd - validate RXON structure is valid
  742. *
  743. * NOTE: This is really only useful during development and can eventually
  744. * be #ifdef'd out once the driver is stable and folks aren't actively
  745. * making changes
  746. */
  747. static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
  748. {
  749. int error = 0;
  750. int counter = 1;
  751. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  752. error |= le32_to_cpu(rxon->flags &
  753. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  754. RXON_FLG_RADAR_DETECT_MSK));
  755. if (error)
  756. IWL_WARNING("check 24G fields %d | %d\n",
  757. counter++, error);
  758. } else {
  759. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  760. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  761. if (error)
  762. IWL_WARNING("check 52 fields %d | %d\n",
  763. counter++, error);
  764. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  765. if (error)
  766. IWL_WARNING("check 52 CCK %d | %d\n",
  767. counter++, error);
  768. }
  769. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  770. if (error)
  771. IWL_WARNING("check mac addr %d | %d\n", counter++, error);
  772. /* make sure basic rates 6Mbps and 1Mbps are supported */
  773. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  774. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  775. if (error)
  776. IWL_WARNING("check basic rate %d | %d\n", counter++, error);
  777. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  778. if (error)
  779. IWL_WARNING("check assoc id %d | %d\n", counter++, error);
  780. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  781. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  782. if (error)
  783. IWL_WARNING("check CCK and short slot %d | %d\n",
  784. counter++, error);
  785. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  786. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  787. if (error)
  788. IWL_WARNING("check CCK & auto detect %d | %d\n",
  789. counter++, error);
  790. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  791. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  792. if (error)
  793. IWL_WARNING("check TGG and auto detect %d | %d\n",
  794. counter++, error);
  795. if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
  796. error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
  797. RXON_FLG_ANT_A_MSK)) == 0);
  798. if (error)
  799. IWL_WARNING("check antenna %d %d\n", counter++, error);
  800. if (error)
  801. IWL_WARNING("Tuning to channel %d\n",
  802. le16_to_cpu(rxon->channel));
  803. if (error) {
  804. IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
  805. return -1;
  806. }
  807. return 0;
  808. }
  809. /**
  810. * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  811. * @priv: staging_rxon is compared to active_rxon
  812. *
  813. * If the RXON structure is changing enough to require a new tune,
  814. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  815. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  816. */
  817. static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
  818. {
  819. /* These items are only settable from the full RXON command */
  820. if (!(iwl3945_is_associated(priv)) ||
  821. compare_ether_addr(priv->staging_rxon.bssid_addr,
  822. priv->active_rxon.bssid_addr) ||
  823. compare_ether_addr(priv->staging_rxon.node_addr,
  824. priv->active_rxon.node_addr) ||
  825. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  826. priv->active_rxon.wlap_bssid_addr) ||
  827. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  828. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  829. (priv->staging_rxon.air_propagation !=
  830. priv->active_rxon.air_propagation) ||
  831. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  832. return 1;
  833. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  834. * be updated with the RXON_ASSOC command -- however only some
  835. * flag transitions are allowed using RXON_ASSOC */
  836. /* Check if we are not switching bands */
  837. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  838. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  839. return 1;
  840. /* Check if we are switching association toggle */
  841. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  842. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  843. return 1;
  844. return 0;
  845. }
  846. static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
  847. {
  848. int rc = 0;
  849. struct iwl3945_rx_packet *res = NULL;
  850. struct iwl3945_rxon_assoc_cmd rxon_assoc;
  851. struct iwl3945_host_cmd cmd = {
  852. .id = REPLY_RXON_ASSOC,
  853. .len = sizeof(rxon_assoc),
  854. .meta.flags = CMD_WANT_SKB,
  855. .data = &rxon_assoc,
  856. };
  857. const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
  858. const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
  859. if ((rxon1->flags == rxon2->flags) &&
  860. (rxon1->filter_flags == rxon2->filter_flags) &&
  861. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  862. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  863. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  864. return 0;
  865. }
  866. rxon_assoc.flags = priv->staging_rxon.flags;
  867. rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
  868. rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
  869. rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
  870. rxon_assoc.reserved = 0;
  871. rc = iwl3945_send_cmd_sync(priv, &cmd);
  872. if (rc)
  873. return rc;
  874. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  875. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  876. IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
  877. rc = -EIO;
  878. }
  879. priv->alloc_rxb_skb--;
  880. dev_kfree_skb_any(cmd.meta.u.skb);
  881. return rc;
  882. }
  883. /**
  884. * iwl3945_commit_rxon - commit staging_rxon to hardware
  885. *
  886. * The RXON command in staging_rxon is committed to the hardware and
  887. * the active_rxon structure is updated with the new data. This
  888. * function correctly transitions out of the RXON_ASSOC_MSK state if
  889. * a HW tune is required based on the RXON structure changes.
  890. */
  891. static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
  892. {
  893. /* cast away the const for active_rxon in this function */
  894. struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  895. int rc = 0;
  896. DECLARE_MAC_BUF(mac);
  897. if (!iwl3945_is_alive(priv))
  898. return -1;
  899. /* always get timestamp with Rx frame */
  900. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  901. /* select antenna */
  902. priv->staging_rxon.flags &=
  903. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  904. priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
  905. rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
  906. if (rc) {
  907. IWL_ERROR("Invalid RXON configuration. Not committing.\n");
  908. return -EINVAL;
  909. }
  910. /* If we don't need to send a full RXON, we can use
  911. * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
  912. * and other flags for the current radio configuration. */
  913. if (!iwl3945_full_rxon_required(priv)) {
  914. rc = iwl3945_send_rxon_assoc(priv);
  915. if (rc) {
  916. IWL_ERROR("Error setting RXON_ASSOC "
  917. "configuration (%d).\n", rc);
  918. return rc;
  919. }
  920. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  921. return 0;
  922. }
  923. /* If we are currently associated and the new config requires
  924. * an RXON_ASSOC and the new config wants the associated mask enabled,
  925. * we must clear the associated from the active configuration
  926. * before we apply the new config */
  927. if (iwl3945_is_associated(priv) &&
  928. (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  929. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  930. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  931. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  932. sizeof(struct iwl3945_rxon_cmd),
  933. &priv->active_rxon);
  934. /* If the mask clearing failed then we set
  935. * active_rxon back to what it was previously */
  936. if (rc) {
  937. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  938. IWL_ERROR("Error clearing ASSOC_MSK on current "
  939. "configuration (%d).\n", rc);
  940. return rc;
  941. }
  942. }
  943. IWL_DEBUG_INFO("Sending RXON\n"
  944. "* with%s RXON_FILTER_ASSOC_MSK\n"
  945. "* channel = %d\n"
  946. "* bssid = %s\n",
  947. ((priv->staging_rxon.filter_flags &
  948. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  949. le16_to_cpu(priv->staging_rxon.channel),
  950. print_mac(mac, priv->staging_rxon.bssid_addr));
  951. /* Apply the new configuration */
  952. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  953. sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
  954. if (rc) {
  955. IWL_ERROR("Error setting new configuration (%d).\n", rc);
  956. return rc;
  957. }
  958. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  959. iwl3945_clear_stations_table(priv);
  960. /* If we issue a new RXON command which required a tune then we must
  961. * send a new TXPOWER command or we won't be able to Tx any frames */
  962. rc = iwl3945_hw_reg_send_txpower(priv);
  963. if (rc) {
  964. IWL_ERROR("Error setting Tx power (%d).\n", rc);
  965. return rc;
  966. }
  967. /* Add the broadcast address so we can send broadcast frames */
  968. if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
  969. IWL_INVALID_STATION) {
  970. IWL_ERROR("Error adding BROADCAST address for transmit.\n");
  971. return -EIO;
  972. }
  973. /* If we have set the ASSOC_MSK and we are in BSS mode then
  974. * add the IWL_AP_ID to the station rate table */
  975. if (iwl3945_is_associated(priv) &&
  976. (priv->iw_mode == IEEE80211_IF_TYPE_STA))
  977. if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
  978. == IWL_INVALID_STATION) {
  979. IWL_ERROR("Error adding AP address for transmit.\n");
  980. return -EIO;
  981. }
  982. /* Init the hardware's rate fallback order based on the band */
  983. rc = iwl3945_init_hw_rate_table(priv);
  984. if (rc) {
  985. IWL_ERROR("Error setting HW rate table: %02X\n", rc);
  986. return -EIO;
  987. }
  988. return 0;
  989. }
  990. static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
  991. {
  992. struct iwl3945_bt_cmd bt_cmd = {
  993. .flags = 3,
  994. .lead_time = 0xAA,
  995. .max_kill = 1,
  996. .kill_ack_mask = 0,
  997. .kill_cts_mask = 0,
  998. };
  999. return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  1000. sizeof(struct iwl3945_bt_cmd), &bt_cmd);
  1001. }
  1002. static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
  1003. {
  1004. int rc = 0;
  1005. struct iwl3945_rx_packet *res;
  1006. struct iwl3945_host_cmd cmd = {
  1007. .id = REPLY_SCAN_ABORT_CMD,
  1008. .meta.flags = CMD_WANT_SKB,
  1009. };
  1010. /* If there isn't a scan actively going on in the hardware
  1011. * then we are in between scan bands and not actually
  1012. * actively scanning, so don't send the abort command */
  1013. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1014. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1015. return 0;
  1016. }
  1017. rc = iwl3945_send_cmd_sync(priv, &cmd);
  1018. if (rc) {
  1019. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1020. return rc;
  1021. }
  1022. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1023. if (res->u.status != CAN_ABORT_STATUS) {
  1024. /* The scan abort will return 1 for success or
  1025. * 2 for "failure". A failure condition can be
  1026. * due to simply not being in an active scan which
  1027. * can occur if we send the scan abort before we
  1028. * the microcode has notified us that a scan is
  1029. * completed. */
  1030. IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
  1031. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1032. clear_bit(STATUS_SCAN_HW, &priv->status);
  1033. }
  1034. dev_kfree_skb_any(cmd.meta.u.skb);
  1035. return rc;
  1036. }
  1037. static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
  1038. struct iwl3945_cmd *cmd,
  1039. struct sk_buff *skb)
  1040. {
  1041. return 1;
  1042. }
  1043. /*
  1044. * CARD_STATE_CMD
  1045. *
  1046. * Use: Sets the device's internal card state to enable, disable, or halt
  1047. *
  1048. * When in the 'enable' state the card operates as normal.
  1049. * When in the 'disable' state, the card enters into a low power mode.
  1050. * When in the 'halt' state, the card is shut down and must be fully
  1051. * restarted to come back on.
  1052. */
  1053. static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
  1054. {
  1055. struct iwl3945_host_cmd cmd = {
  1056. .id = REPLY_CARD_STATE_CMD,
  1057. .len = sizeof(u32),
  1058. .data = &flags,
  1059. .meta.flags = meta_flag,
  1060. };
  1061. if (meta_flag & CMD_ASYNC)
  1062. cmd.meta.u.callback = iwl3945_card_state_sync_callback;
  1063. return iwl3945_send_cmd(priv, &cmd);
  1064. }
  1065. static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
  1066. struct iwl3945_cmd *cmd, struct sk_buff *skb)
  1067. {
  1068. struct iwl3945_rx_packet *res = NULL;
  1069. if (!skb) {
  1070. IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
  1071. return 1;
  1072. }
  1073. res = (struct iwl3945_rx_packet *)skb->data;
  1074. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1075. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1076. res->hdr.flags);
  1077. return 1;
  1078. }
  1079. switch (res->u.add_sta.status) {
  1080. case ADD_STA_SUCCESS_MSK:
  1081. break;
  1082. default:
  1083. break;
  1084. }
  1085. /* We didn't cache the SKB; let the caller free it */
  1086. return 1;
  1087. }
  1088. int iwl3945_send_add_station(struct iwl3945_priv *priv,
  1089. struct iwl3945_addsta_cmd *sta, u8 flags)
  1090. {
  1091. struct iwl3945_rx_packet *res = NULL;
  1092. int rc = 0;
  1093. struct iwl3945_host_cmd cmd = {
  1094. .id = REPLY_ADD_STA,
  1095. .len = sizeof(struct iwl3945_addsta_cmd),
  1096. .meta.flags = flags,
  1097. .data = sta,
  1098. };
  1099. if (flags & CMD_ASYNC)
  1100. cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
  1101. else
  1102. cmd.meta.flags |= CMD_WANT_SKB;
  1103. rc = iwl3945_send_cmd(priv, &cmd);
  1104. if (rc || (flags & CMD_ASYNC))
  1105. return rc;
  1106. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1107. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1108. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1109. res->hdr.flags);
  1110. rc = -EIO;
  1111. }
  1112. if (rc == 0) {
  1113. switch (res->u.add_sta.status) {
  1114. case ADD_STA_SUCCESS_MSK:
  1115. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  1116. break;
  1117. default:
  1118. rc = -EIO;
  1119. IWL_WARNING("REPLY_ADD_STA failed\n");
  1120. break;
  1121. }
  1122. }
  1123. priv->alloc_rxb_skb--;
  1124. dev_kfree_skb_any(cmd.meta.u.skb);
  1125. return rc;
  1126. }
  1127. static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
  1128. struct ieee80211_key_conf *keyconf,
  1129. u8 sta_id)
  1130. {
  1131. unsigned long flags;
  1132. __le16 key_flags = 0;
  1133. switch (keyconf->alg) {
  1134. case ALG_CCMP:
  1135. key_flags |= STA_KEY_FLG_CCMP;
  1136. key_flags |= cpu_to_le16(
  1137. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  1138. key_flags &= ~STA_KEY_FLG_INVALID;
  1139. break;
  1140. case ALG_TKIP:
  1141. case ALG_WEP:
  1142. default:
  1143. return -EINVAL;
  1144. }
  1145. spin_lock_irqsave(&priv->sta_lock, flags);
  1146. priv->stations[sta_id].keyinfo.alg = keyconf->alg;
  1147. priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  1148. memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
  1149. keyconf->keylen);
  1150. memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
  1151. keyconf->keylen);
  1152. priv->stations[sta_id].sta.key.key_flags = key_flags;
  1153. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1154. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1155. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1156. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  1157. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1158. return 0;
  1159. }
  1160. static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
  1161. {
  1162. unsigned long flags;
  1163. spin_lock_irqsave(&priv->sta_lock, flags);
  1164. memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
  1165. memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
  1166. priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  1167. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1168. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1169. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1170. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  1171. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1172. return 0;
  1173. }
  1174. static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
  1175. {
  1176. struct list_head *element;
  1177. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  1178. priv->frames_count);
  1179. while (!list_empty(&priv->free_frames)) {
  1180. element = priv->free_frames.next;
  1181. list_del(element);
  1182. kfree(list_entry(element, struct iwl3945_frame, list));
  1183. priv->frames_count--;
  1184. }
  1185. if (priv->frames_count) {
  1186. IWL_WARNING("%d frames still in use. Did we lose one?\n",
  1187. priv->frames_count);
  1188. priv->frames_count = 0;
  1189. }
  1190. }
  1191. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
  1192. {
  1193. struct iwl3945_frame *frame;
  1194. struct list_head *element;
  1195. if (list_empty(&priv->free_frames)) {
  1196. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  1197. if (!frame) {
  1198. IWL_ERROR("Could not allocate frame!\n");
  1199. return NULL;
  1200. }
  1201. priv->frames_count++;
  1202. return frame;
  1203. }
  1204. element = priv->free_frames.next;
  1205. list_del(element);
  1206. return list_entry(element, struct iwl3945_frame, list);
  1207. }
  1208. static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
  1209. {
  1210. memset(frame, 0, sizeof(*frame));
  1211. list_add(&frame->list, &priv->free_frames);
  1212. }
  1213. unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
  1214. struct ieee80211_hdr *hdr,
  1215. const u8 *dest, int left)
  1216. {
  1217. if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
  1218. ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) &&
  1219. (priv->iw_mode != IEEE80211_IF_TYPE_AP)))
  1220. return 0;
  1221. if (priv->ibss_beacon->len > left)
  1222. return 0;
  1223. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  1224. return priv->ibss_beacon->len;
  1225. }
  1226. static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
  1227. {
  1228. u8 i;
  1229. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  1230. i = iwl3945_rates[i].next_ieee) {
  1231. if (rate_mask & (1 << i))
  1232. return iwl3945_rates[i].plcp;
  1233. }
  1234. return IWL_RATE_INVALID;
  1235. }
  1236. static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
  1237. {
  1238. struct iwl3945_frame *frame;
  1239. unsigned int frame_size;
  1240. int rc;
  1241. u8 rate;
  1242. frame = iwl3945_get_free_frame(priv);
  1243. if (!frame) {
  1244. IWL_ERROR("Could not obtain free frame buffer for beacon "
  1245. "command.\n");
  1246. return -ENOMEM;
  1247. }
  1248. if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
  1249. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
  1250. 0xFF0);
  1251. if (rate == IWL_INVALID_RATE)
  1252. rate = IWL_RATE_6M_PLCP;
  1253. } else {
  1254. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
  1255. if (rate == IWL_INVALID_RATE)
  1256. rate = IWL_RATE_1M_PLCP;
  1257. }
  1258. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  1259. rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  1260. &frame->u.cmd[0]);
  1261. iwl3945_free_frame(priv, frame);
  1262. return rc;
  1263. }
  1264. /******************************************************************************
  1265. *
  1266. * EEPROM related functions
  1267. *
  1268. ******************************************************************************/
  1269. static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
  1270. {
  1271. memcpy(mac, priv->eeprom.mac_address, 6);
  1272. }
  1273. /*
  1274. * Clear the OWNER_MSK, to establish driver (instead of uCode running on
  1275. * embedded controller) as EEPROM reader; each read is a series of pulses
  1276. * to/from the EEPROM chip, not a single event, so even reads could conflict
  1277. * if they weren't arbitrated by some ownership mechanism. Here, the driver
  1278. * simply claims ownership, which should be safe when this function is called
  1279. * (i.e. before loading uCode!).
  1280. */
  1281. static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
  1282. {
  1283. _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
  1284. return 0;
  1285. }
  1286. /**
  1287. * iwl3945_eeprom_init - read EEPROM contents
  1288. *
  1289. * Load the EEPROM contents from adapter into priv->eeprom
  1290. *
  1291. * NOTE: This routine uses the non-debug IO access functions.
  1292. */
  1293. int iwl3945_eeprom_init(struct iwl3945_priv *priv)
  1294. {
  1295. u16 *e = (u16 *)&priv->eeprom;
  1296. u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
  1297. u32 r;
  1298. int sz = sizeof(priv->eeprom);
  1299. int rc;
  1300. int i;
  1301. u16 addr;
  1302. /* The EEPROM structure has several padding buffers within it
  1303. * and when adding new EEPROM maps is subject to programmer errors
  1304. * which may be very difficult to identify without explicitly
  1305. * checking the resulting size of the eeprom map. */
  1306. BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
  1307. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  1308. IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
  1309. return -ENOENT;
  1310. }
  1311. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  1312. rc = iwl3945_eeprom_acquire_semaphore(priv);
  1313. if (rc < 0) {
  1314. IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
  1315. return -ENOENT;
  1316. }
  1317. /* eeprom is an array of 16bit values */
  1318. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  1319. _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
  1320. _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  1321. for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
  1322. i += IWL_EEPROM_ACCESS_DELAY) {
  1323. r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
  1324. if (r & CSR_EEPROM_REG_READ_VALID_MSK)
  1325. break;
  1326. udelay(IWL_EEPROM_ACCESS_DELAY);
  1327. }
  1328. if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
  1329. IWL_ERROR("Time out reading EEPROM[%d]", addr);
  1330. return -ETIMEDOUT;
  1331. }
  1332. e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
  1333. }
  1334. return 0;
  1335. }
  1336. static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
  1337. {
  1338. if (priv->hw_setting.shared_virt)
  1339. pci_free_consistent(priv->pci_dev,
  1340. sizeof(struct iwl3945_shared),
  1341. priv->hw_setting.shared_virt,
  1342. priv->hw_setting.shared_phys);
  1343. }
  1344. /**
  1345. * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
  1346. *
  1347. * return : set the bit for each supported rate insert in ie
  1348. */
  1349. static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
  1350. u16 basic_rate, int *left)
  1351. {
  1352. u16 ret_rates = 0, bit;
  1353. int i;
  1354. u8 *cnt = ie;
  1355. u8 *rates = ie + 1;
  1356. for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
  1357. if (bit & supported_rate) {
  1358. ret_rates |= bit;
  1359. rates[*cnt] = iwl3945_rates[i].ieee |
  1360. ((bit & basic_rate) ? 0x80 : 0x00);
  1361. (*cnt)++;
  1362. (*left)--;
  1363. if ((*left <= 0) ||
  1364. (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
  1365. break;
  1366. }
  1367. }
  1368. return ret_rates;
  1369. }
  1370. /**
  1371. * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
  1372. */
  1373. static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
  1374. struct ieee80211_mgmt *frame,
  1375. int left, int is_direct)
  1376. {
  1377. int len = 0;
  1378. u8 *pos = NULL;
  1379. u16 active_rates, ret_rates, cck_rates;
  1380. /* Make sure there is enough space for the probe request,
  1381. * two mandatory IEs and the data */
  1382. left -= 24;
  1383. if (left < 0)
  1384. return 0;
  1385. len += 24;
  1386. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1387. memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
  1388. memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
  1389. memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
  1390. frame->seq_ctrl = 0;
  1391. /* fill in our indirect SSID IE */
  1392. /* ...next IE... */
  1393. left -= 2;
  1394. if (left < 0)
  1395. return 0;
  1396. len += 2;
  1397. pos = &(frame->u.probe_req.variable[0]);
  1398. *pos++ = WLAN_EID_SSID;
  1399. *pos++ = 0;
  1400. /* fill in our direct SSID IE... */
  1401. if (is_direct) {
  1402. /* ...next IE... */
  1403. left -= 2 + priv->essid_len;
  1404. if (left < 0)
  1405. return 0;
  1406. /* ... fill it in... */
  1407. *pos++ = WLAN_EID_SSID;
  1408. *pos++ = priv->essid_len;
  1409. memcpy(pos, priv->essid, priv->essid_len);
  1410. pos += priv->essid_len;
  1411. len += 2 + priv->essid_len;
  1412. }
  1413. /* fill in supported rate */
  1414. /* ...next IE... */
  1415. left -= 2;
  1416. if (left < 0)
  1417. return 0;
  1418. /* ... fill it in... */
  1419. *pos++ = WLAN_EID_SUPP_RATES;
  1420. *pos = 0;
  1421. priv->active_rate = priv->rates_mask;
  1422. active_rates = priv->active_rate;
  1423. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1424. cck_rates = IWL_CCK_RATES_MASK & active_rates;
  1425. ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
  1426. priv->active_rate_basic, &left);
  1427. active_rates &= ~ret_rates;
  1428. ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
  1429. priv->active_rate_basic, &left);
  1430. active_rates &= ~ret_rates;
  1431. len += 2 + *pos;
  1432. pos += (*pos) + 1;
  1433. if (active_rates == 0)
  1434. goto fill_end;
  1435. /* fill in supported extended rate */
  1436. /* ...next IE... */
  1437. left -= 2;
  1438. if (left < 0)
  1439. return 0;
  1440. /* ... fill it in... */
  1441. *pos++ = WLAN_EID_EXT_SUPP_RATES;
  1442. *pos = 0;
  1443. iwl3945_supported_rate_to_ie(pos, active_rates,
  1444. priv->active_rate_basic, &left);
  1445. if (*pos > 0)
  1446. len += 2 + *pos;
  1447. fill_end:
  1448. return (u16)len;
  1449. }
  1450. /*
  1451. * QoS support
  1452. */
  1453. static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
  1454. struct iwl3945_qosparam_cmd *qos)
  1455. {
  1456. return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  1457. sizeof(struct iwl3945_qosparam_cmd), qos);
  1458. }
  1459. static void iwl3945_reset_qos(struct iwl3945_priv *priv)
  1460. {
  1461. u16 cw_min = 15;
  1462. u16 cw_max = 1023;
  1463. u8 aifs = 2;
  1464. u8 is_legacy = 0;
  1465. unsigned long flags;
  1466. int i;
  1467. spin_lock_irqsave(&priv->lock, flags);
  1468. priv->qos_data.qos_active = 0;
  1469. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
  1470. if (priv->qos_data.qos_enable)
  1471. priv->qos_data.qos_active = 1;
  1472. if (!(priv->active_rate & 0xfff0)) {
  1473. cw_min = 31;
  1474. is_legacy = 1;
  1475. }
  1476. } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  1477. if (priv->qos_data.qos_enable)
  1478. priv->qos_data.qos_active = 1;
  1479. } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
  1480. cw_min = 31;
  1481. is_legacy = 1;
  1482. }
  1483. if (priv->qos_data.qos_active)
  1484. aifs = 3;
  1485. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  1486. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  1487. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  1488. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  1489. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  1490. if (priv->qos_data.qos_active) {
  1491. i = 1;
  1492. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  1493. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  1494. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  1495. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1496. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1497. i = 2;
  1498. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1499. cpu_to_le16((cw_min + 1) / 2 - 1);
  1500. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1501. cpu_to_le16(cw_max);
  1502. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1503. if (is_legacy)
  1504. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1505. cpu_to_le16(6016);
  1506. else
  1507. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1508. cpu_to_le16(3008);
  1509. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1510. i = 3;
  1511. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1512. cpu_to_le16((cw_min + 1) / 4 - 1);
  1513. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1514. cpu_to_le16((cw_max + 1) / 2 - 1);
  1515. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1516. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1517. if (is_legacy)
  1518. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1519. cpu_to_le16(3264);
  1520. else
  1521. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1522. cpu_to_le16(1504);
  1523. } else {
  1524. for (i = 1; i < 4; i++) {
  1525. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1526. cpu_to_le16(cw_min);
  1527. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1528. cpu_to_le16(cw_max);
  1529. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  1530. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1531. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1532. }
  1533. }
  1534. IWL_DEBUG_QOS("set QoS to default \n");
  1535. spin_unlock_irqrestore(&priv->lock, flags);
  1536. }
  1537. static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
  1538. {
  1539. unsigned long flags;
  1540. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1541. return;
  1542. if (!priv->qos_data.qos_enable)
  1543. return;
  1544. spin_lock_irqsave(&priv->lock, flags);
  1545. priv->qos_data.def_qos_parm.qos_flags = 0;
  1546. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  1547. !priv->qos_data.qos_cap.q_AP.txop_request)
  1548. priv->qos_data.def_qos_parm.qos_flags |=
  1549. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  1550. if (priv->qos_data.qos_active)
  1551. priv->qos_data.def_qos_parm.qos_flags |=
  1552. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  1553. spin_unlock_irqrestore(&priv->lock, flags);
  1554. if (force || iwl3945_is_associated(priv)) {
  1555. IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n",
  1556. priv->qos_data.qos_active);
  1557. iwl3945_send_qos_params_command(priv,
  1558. &(priv->qos_data.def_qos_parm));
  1559. }
  1560. }
  1561. /*
  1562. * Power management (not Tx power!) functions
  1563. */
  1564. #define MSEC_TO_USEC 1024
  1565. #define NOSLP __constant_cpu_to_le32(0)
  1566. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
  1567. #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
  1568. #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
  1569. __constant_cpu_to_le32(X1), \
  1570. __constant_cpu_to_le32(X2), \
  1571. __constant_cpu_to_le32(X3), \
  1572. __constant_cpu_to_le32(X4)}
  1573. /* default power management (not Tx power) table values */
  1574. /* for tim 0-10 */
  1575. static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
  1576. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1577. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  1578. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  1579. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  1580. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  1581. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  1582. };
  1583. /* for tim > 10 */
  1584. static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
  1585. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1586. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
  1587. SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  1588. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
  1589. SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  1590. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
  1591. SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  1592. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  1593. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
  1594. SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  1595. };
  1596. int iwl3945_power_init_handle(struct iwl3945_priv *priv)
  1597. {
  1598. int rc = 0, i;
  1599. struct iwl3945_power_mgr *pow_data;
  1600. int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
  1601. u16 pci_pm;
  1602. IWL_DEBUG_POWER("Initialize power \n");
  1603. pow_data = &(priv->power_data);
  1604. memset(pow_data, 0, sizeof(*pow_data));
  1605. pow_data->active_index = IWL_POWER_RANGE_0;
  1606. pow_data->dtim_val = 0xffff;
  1607. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1608. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1609. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1610. if (rc != 0)
  1611. return 0;
  1612. else {
  1613. struct iwl3945_powertable_cmd *cmd;
  1614. IWL_DEBUG_POWER("adjust power command flags\n");
  1615. for (i = 0; i < IWL_POWER_AC; i++) {
  1616. cmd = &pow_data->pwr_range_0[i].cmd;
  1617. if (pci_pm & 0x1)
  1618. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1619. else
  1620. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1621. }
  1622. }
  1623. return rc;
  1624. }
  1625. static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
  1626. struct iwl3945_powertable_cmd *cmd, u32 mode)
  1627. {
  1628. int rc = 0, i;
  1629. u8 skip;
  1630. u32 max_sleep = 0;
  1631. struct iwl3945_power_vec_entry *range;
  1632. u8 period = 0;
  1633. struct iwl3945_power_mgr *pow_data;
  1634. if (mode > IWL_POWER_INDEX_5) {
  1635. IWL_DEBUG_POWER("Error invalid power mode \n");
  1636. return -1;
  1637. }
  1638. pow_data = &(priv->power_data);
  1639. if (pow_data->active_index == IWL_POWER_RANGE_0)
  1640. range = &pow_data->pwr_range_0[0];
  1641. else
  1642. range = &pow_data->pwr_range_1[1];
  1643. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
  1644. #ifdef IWL_MAC80211_DISABLE
  1645. if (priv->assoc_network != NULL) {
  1646. unsigned long flags;
  1647. period = priv->assoc_network->tim.tim_period;
  1648. }
  1649. #endif /*IWL_MAC80211_DISABLE */
  1650. skip = range[mode].no_dtim;
  1651. if (period == 0) {
  1652. period = 1;
  1653. skip = 0;
  1654. }
  1655. if (skip == 0) {
  1656. max_sleep = period;
  1657. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1658. } else {
  1659. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1660. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1661. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1662. }
  1663. for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
  1664. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1665. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1666. }
  1667. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1668. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1669. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1670. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1671. le32_to_cpu(cmd->sleep_interval[0]),
  1672. le32_to_cpu(cmd->sleep_interval[1]),
  1673. le32_to_cpu(cmd->sleep_interval[2]),
  1674. le32_to_cpu(cmd->sleep_interval[3]),
  1675. le32_to_cpu(cmd->sleep_interval[4]));
  1676. return rc;
  1677. }
  1678. static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
  1679. {
  1680. u32 uninitialized_var(final_mode);
  1681. int rc;
  1682. struct iwl3945_powertable_cmd cmd;
  1683. /* If on battery, set to 3,
  1684. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1685. * else user level */
  1686. switch (mode) {
  1687. case IWL_POWER_BATTERY:
  1688. final_mode = IWL_POWER_INDEX_3;
  1689. break;
  1690. case IWL_POWER_AC:
  1691. final_mode = IWL_POWER_MODE_CAM;
  1692. break;
  1693. default:
  1694. final_mode = mode;
  1695. break;
  1696. }
  1697. iwl3945_update_power_cmd(priv, &cmd, final_mode);
  1698. rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
  1699. if (final_mode == IWL_POWER_MODE_CAM)
  1700. clear_bit(STATUS_POWER_PMI, &priv->status);
  1701. else
  1702. set_bit(STATUS_POWER_PMI, &priv->status);
  1703. return rc;
  1704. }
  1705. int iwl3945_is_network_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
  1706. {
  1707. /* Filter incoming packets to determine if they are targeted toward
  1708. * this network, discarding packets coming from ourselves */
  1709. switch (priv->iw_mode) {
  1710. case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
  1711. /* packets from our adapter are dropped (echo) */
  1712. if (!compare_ether_addr(header->addr2, priv->mac_addr))
  1713. return 0;
  1714. /* {broad,multi}cast packets to our IBSS go through */
  1715. if (is_multicast_ether_addr(header->addr1))
  1716. return !compare_ether_addr(header->addr3, priv->bssid);
  1717. /* packets to our adapter go through */
  1718. return !compare_ether_addr(header->addr1, priv->mac_addr);
  1719. case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
  1720. /* packets from our adapter are dropped (echo) */
  1721. if (!compare_ether_addr(header->addr3, priv->mac_addr))
  1722. return 0;
  1723. /* {broad,multi}cast packets to our BSS go through */
  1724. if (is_multicast_ether_addr(header->addr1))
  1725. return !compare_ether_addr(header->addr2, priv->bssid);
  1726. /* packets to our adapter go through */
  1727. return !compare_ether_addr(header->addr1, priv->mac_addr);
  1728. default:
  1729. return 1;
  1730. }
  1731. return 1;
  1732. }
  1733. /**
  1734. * iwl3945_scan_cancel - Cancel any currently executing HW scan
  1735. *
  1736. * NOTE: priv->mutex is not required before calling this function
  1737. */
  1738. static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
  1739. {
  1740. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1741. clear_bit(STATUS_SCANNING, &priv->status);
  1742. return 0;
  1743. }
  1744. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1745. if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1746. IWL_DEBUG_SCAN("Queuing scan abort.\n");
  1747. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  1748. queue_work(priv->workqueue, &priv->abort_scan);
  1749. } else
  1750. IWL_DEBUG_SCAN("Scan abort already in progress.\n");
  1751. return test_bit(STATUS_SCANNING, &priv->status);
  1752. }
  1753. return 0;
  1754. }
  1755. /**
  1756. * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
  1757. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1758. *
  1759. * NOTE: priv->mutex must be held before calling this function
  1760. */
  1761. static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
  1762. {
  1763. unsigned long now = jiffies;
  1764. int ret;
  1765. ret = iwl3945_scan_cancel(priv);
  1766. if (ret && ms) {
  1767. mutex_unlock(&priv->mutex);
  1768. while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
  1769. test_bit(STATUS_SCANNING, &priv->status))
  1770. msleep(1);
  1771. mutex_lock(&priv->mutex);
  1772. return test_bit(STATUS_SCANNING, &priv->status);
  1773. }
  1774. return ret;
  1775. }
  1776. static void iwl3945_sequence_reset(struct iwl3945_priv *priv)
  1777. {
  1778. /* Reset ieee stats */
  1779. /* We don't reset the net_device_stats (ieee->stats) on
  1780. * re-association */
  1781. priv->last_seq_num = -1;
  1782. priv->last_frag_num = -1;
  1783. priv->last_packet_time = 0;
  1784. iwl3945_scan_cancel(priv);
  1785. }
  1786. #define MAX_UCODE_BEACON_INTERVAL 1024
  1787. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  1788. static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
  1789. {
  1790. u16 new_val = 0;
  1791. u16 beacon_factor = 0;
  1792. beacon_factor =
  1793. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  1794. / MAX_UCODE_BEACON_INTERVAL;
  1795. new_val = beacon_val / beacon_factor;
  1796. return cpu_to_le16(new_val);
  1797. }
  1798. static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
  1799. {
  1800. u64 interval_tm_unit;
  1801. u64 tsf, result;
  1802. unsigned long flags;
  1803. struct ieee80211_conf *conf = NULL;
  1804. u16 beacon_int = 0;
  1805. conf = ieee80211_get_hw_conf(priv->hw);
  1806. spin_lock_irqsave(&priv->lock, flags);
  1807. priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
  1808. priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
  1809. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  1810. tsf = priv->timestamp1;
  1811. tsf = ((tsf << 32) | priv->timestamp0);
  1812. beacon_int = priv->beacon_int;
  1813. spin_unlock_irqrestore(&priv->lock, flags);
  1814. if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
  1815. if (beacon_int == 0) {
  1816. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  1817. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  1818. } else {
  1819. priv->rxon_timing.beacon_interval =
  1820. cpu_to_le16(beacon_int);
  1821. priv->rxon_timing.beacon_interval =
  1822. iwl3945_adjust_beacon_interval(
  1823. le16_to_cpu(priv->rxon_timing.beacon_interval));
  1824. }
  1825. priv->rxon_timing.atim_window = 0;
  1826. } else {
  1827. priv->rxon_timing.beacon_interval =
  1828. iwl3945_adjust_beacon_interval(conf->beacon_int);
  1829. /* TODO: we need to get atim_window from upper stack
  1830. * for now we set to 0 */
  1831. priv->rxon_timing.atim_window = 0;
  1832. }
  1833. interval_tm_unit =
  1834. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  1835. result = do_div(tsf, interval_tm_unit);
  1836. priv->rxon_timing.beacon_init_val =
  1837. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  1838. IWL_DEBUG_ASSOC
  1839. ("beacon interval %d beacon timer %d beacon tim %d\n",
  1840. le16_to_cpu(priv->rxon_timing.beacon_interval),
  1841. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  1842. le16_to_cpu(priv->rxon_timing.atim_window));
  1843. }
  1844. static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
  1845. {
  1846. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  1847. IWL_ERROR("APs don't scan.\n");
  1848. return 0;
  1849. }
  1850. if (!iwl3945_is_ready_rf(priv)) {
  1851. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  1852. return -EIO;
  1853. }
  1854. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1855. IWL_DEBUG_SCAN("Scan already in progress.\n");
  1856. return -EAGAIN;
  1857. }
  1858. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1859. IWL_DEBUG_SCAN("Scan request while abort pending. "
  1860. "Queuing.\n");
  1861. return -EAGAIN;
  1862. }
  1863. IWL_DEBUG_INFO("Starting scan...\n");
  1864. if (priv->cfg->sku & IWL_SKU_G)
  1865. priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
  1866. if (priv->cfg->sku & IWL_SKU_A)
  1867. priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
  1868. set_bit(STATUS_SCANNING, &priv->status);
  1869. priv->scan_start = jiffies;
  1870. priv->scan_pass_start = priv->scan_start;
  1871. queue_work(priv->workqueue, &priv->request_scan);
  1872. return 0;
  1873. }
  1874. static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
  1875. {
  1876. struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
  1877. if (hw_decrypt)
  1878. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  1879. else
  1880. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  1881. return 0;
  1882. }
  1883. static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
  1884. enum ieee80211_band band)
  1885. {
  1886. if (band == IEEE80211_BAND_5GHZ) {
  1887. priv->staging_rxon.flags &=
  1888. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  1889. | RXON_FLG_CCK_MSK);
  1890. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1891. } else {
  1892. /* Copied from iwl3945_bg_post_associate() */
  1893. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1894. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1895. else
  1896. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1897. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  1898. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1899. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  1900. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  1901. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  1902. }
  1903. }
  1904. /*
  1905. * initialize rxon structure with default values from eeprom
  1906. */
  1907. static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
  1908. {
  1909. const struct iwl3945_channel_info *ch_info;
  1910. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  1911. switch (priv->iw_mode) {
  1912. case IEEE80211_IF_TYPE_AP:
  1913. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  1914. break;
  1915. case IEEE80211_IF_TYPE_STA:
  1916. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1917. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1918. break;
  1919. case IEEE80211_IF_TYPE_IBSS:
  1920. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1921. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1922. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1923. RXON_FILTER_ACCEPT_GRP_MSK;
  1924. break;
  1925. case IEEE80211_IF_TYPE_MNTR:
  1926. priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  1927. priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  1928. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  1929. break;
  1930. default:
  1931. IWL_ERROR("Unsupported interface type %d\n", priv->iw_mode);
  1932. break;
  1933. }
  1934. #if 0
  1935. /* TODO: Figure out when short_preamble would be set and cache from
  1936. * that */
  1937. if (!hw_to_local(priv->hw)->short_preamble)
  1938. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1939. else
  1940. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1941. #endif
  1942. ch_info = iwl3945_get_channel_info(priv, priv->band,
  1943. le16_to_cpu(priv->active_rxon.channel));
  1944. if (!ch_info)
  1945. ch_info = &priv->channel_info[0];
  1946. /*
  1947. * in some case A channels are all non IBSS
  1948. * in this case force B/G channel
  1949. */
  1950. if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
  1951. !(is_channel_ibss(ch_info)))
  1952. ch_info = &priv->channel_info[0];
  1953. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  1954. if (is_channel_a_band(ch_info))
  1955. priv->band = IEEE80211_BAND_5GHZ;
  1956. else
  1957. priv->band = IEEE80211_BAND_2GHZ;
  1958. iwl3945_set_flags_for_phymode(priv, priv->band);
  1959. priv->staging_rxon.ofdm_basic_rates =
  1960. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1961. priv->staging_rxon.cck_basic_rates =
  1962. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1963. }
  1964. static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
  1965. {
  1966. if (mode == IEEE80211_IF_TYPE_IBSS) {
  1967. const struct iwl3945_channel_info *ch_info;
  1968. ch_info = iwl3945_get_channel_info(priv,
  1969. priv->band,
  1970. le16_to_cpu(priv->staging_rxon.channel));
  1971. if (!ch_info || !is_channel_ibss(ch_info)) {
  1972. IWL_ERROR("channel %d not IBSS channel\n",
  1973. le16_to_cpu(priv->staging_rxon.channel));
  1974. return -EINVAL;
  1975. }
  1976. }
  1977. priv->iw_mode = mode;
  1978. iwl3945_connection_init_rx_config(priv);
  1979. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1980. iwl3945_clear_stations_table(priv);
  1981. /* dont commit rxon if rf-kill is on*/
  1982. if (!iwl3945_is_ready_rf(priv))
  1983. return -EAGAIN;
  1984. cancel_delayed_work(&priv->scan_check);
  1985. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  1986. IWL_WARNING("Aborted scan still in progress after 100ms\n");
  1987. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  1988. return -EAGAIN;
  1989. }
  1990. iwl3945_commit_rxon(priv);
  1991. return 0;
  1992. }
  1993. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
  1994. struct ieee80211_tx_info *info,
  1995. struct iwl3945_cmd *cmd,
  1996. struct sk_buff *skb_frag,
  1997. int last_frag)
  1998. {
  1999. struct iwl3945_hw_key *keyinfo =
  2000. &priv->stations[info->control.hw_key->hw_key_idx].keyinfo;
  2001. switch (keyinfo->alg) {
  2002. case ALG_CCMP:
  2003. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
  2004. memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
  2005. IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
  2006. break;
  2007. case ALG_TKIP:
  2008. #if 0
  2009. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
  2010. if (last_frag)
  2011. memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
  2012. 8);
  2013. else
  2014. memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
  2015. #endif
  2016. break;
  2017. case ALG_WEP:
  2018. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
  2019. (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  2020. if (keyinfo->keylen == 13)
  2021. cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
  2022. memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
  2023. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  2024. "with key %d\n", info->control.hw_key->hw_key_idx);
  2025. break;
  2026. default:
  2027. printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
  2028. break;
  2029. }
  2030. }
  2031. /*
  2032. * handle build REPLY_TX command notification.
  2033. */
  2034. static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
  2035. struct iwl3945_cmd *cmd,
  2036. struct ieee80211_tx_info *info,
  2037. struct ieee80211_hdr *hdr,
  2038. int is_unicast, u8 std_id)
  2039. {
  2040. __le16 fc = hdr->frame_control;
  2041. __le32 tx_flags = cmd->cmd.tx.tx_flags;
  2042. cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2043. if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  2044. tx_flags |= TX_CMD_FLG_ACK_MSK;
  2045. if (ieee80211_is_mgmt(fc))
  2046. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2047. if (ieee80211_is_probe_resp(fc) &&
  2048. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  2049. tx_flags |= TX_CMD_FLG_TSF_MSK;
  2050. } else {
  2051. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  2052. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2053. }
  2054. cmd->cmd.tx.sta_id = std_id;
  2055. if (ieee80211_has_morefrags(fc))
  2056. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  2057. if (ieee80211_is_data_qos(fc)) {
  2058. u8 *qc = ieee80211_get_qos_ctl(hdr);
  2059. cmd->cmd.tx.tid_tspec = qc[0] & 0xf;
  2060. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  2061. } else {
  2062. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2063. }
  2064. if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) {
  2065. tx_flags |= TX_CMD_FLG_RTS_MSK;
  2066. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  2067. } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
  2068. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  2069. tx_flags |= TX_CMD_FLG_CTS_MSK;
  2070. }
  2071. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  2072. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  2073. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  2074. if (ieee80211_is_mgmt(fc)) {
  2075. if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
  2076. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
  2077. else
  2078. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
  2079. } else {
  2080. cmd->cmd.tx.timeout.pm_frame_timeout = 0;
  2081. #ifdef CONFIG_IWL3945_LEDS
  2082. priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
  2083. #endif
  2084. }
  2085. cmd->cmd.tx.driver_txop = 0;
  2086. cmd->cmd.tx.tx_flags = tx_flags;
  2087. cmd->cmd.tx.next_frame_len = 0;
  2088. }
  2089. /**
  2090. * iwl3945_get_sta_id - Find station's index within station table
  2091. */
  2092. static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
  2093. {
  2094. int sta_id;
  2095. u16 fc = le16_to_cpu(hdr->frame_control);
  2096. /* If this frame is broadcast or management, use broadcast station id */
  2097. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  2098. is_multicast_ether_addr(hdr->addr1))
  2099. return priv->hw_setting.bcast_sta_id;
  2100. switch (priv->iw_mode) {
  2101. /* If we are a client station in a BSS network, use the special
  2102. * AP station entry (that's the only station we communicate with) */
  2103. case IEEE80211_IF_TYPE_STA:
  2104. return IWL_AP_ID;
  2105. /* If we are an AP, then find the station, or use BCAST */
  2106. case IEEE80211_IF_TYPE_AP:
  2107. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2108. if (sta_id != IWL_INVALID_STATION)
  2109. return sta_id;
  2110. return priv->hw_setting.bcast_sta_id;
  2111. /* If this frame is going out to an IBSS network, find the station,
  2112. * or create a new station table entry */
  2113. case IEEE80211_IF_TYPE_IBSS: {
  2114. DECLARE_MAC_BUF(mac);
  2115. /* Create new station table entry */
  2116. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2117. if (sta_id != IWL_INVALID_STATION)
  2118. return sta_id;
  2119. sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
  2120. if (sta_id != IWL_INVALID_STATION)
  2121. return sta_id;
  2122. IWL_DEBUG_DROP("Station %s not in station map. "
  2123. "Defaulting to broadcast...\n",
  2124. print_mac(mac, hdr->addr1));
  2125. iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  2126. return priv->hw_setting.bcast_sta_id;
  2127. }
  2128. /* If we are in monitor mode, use BCAST. This is required for
  2129. * packet injection. */
  2130. case IEEE80211_IF_TYPE_MNTR:
  2131. return priv->hw_setting.bcast_sta_id;
  2132. default:
  2133. IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
  2134. return priv->hw_setting.bcast_sta_id;
  2135. }
  2136. }
  2137. /*
  2138. * start REPLY_TX command process
  2139. */
  2140. static int iwl3945_tx_skb(struct iwl3945_priv *priv, struct sk_buff *skb)
  2141. {
  2142. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  2143. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  2144. struct iwl3945_tfd_frame *tfd;
  2145. u32 *control_flags;
  2146. int txq_id = skb_get_queue_mapping(skb);
  2147. struct iwl3945_tx_queue *txq = NULL;
  2148. struct iwl3945_queue *q = NULL;
  2149. dma_addr_t phys_addr;
  2150. dma_addr_t txcmd_phys;
  2151. struct iwl3945_cmd *out_cmd = NULL;
  2152. u16 len, idx, len_org, hdr_len;
  2153. u8 id;
  2154. u8 unicast;
  2155. u8 sta_id;
  2156. u8 tid = 0;
  2157. u16 seq_number = 0;
  2158. __le16 fc;
  2159. u8 wait_write_ptr = 0;
  2160. u8 *qc = NULL;
  2161. unsigned long flags;
  2162. int rc;
  2163. spin_lock_irqsave(&priv->lock, flags);
  2164. if (iwl3945_is_rfkill(priv)) {
  2165. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  2166. goto drop_unlock;
  2167. }
  2168. if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
  2169. IWL_ERROR("ERROR: No TX rate available.\n");
  2170. goto drop_unlock;
  2171. }
  2172. unicast = !is_multicast_ether_addr(hdr->addr1);
  2173. id = 0;
  2174. fc = hdr->frame_control;
  2175. #ifdef CONFIG_IWL3945_DEBUG
  2176. if (ieee80211_is_auth(fc))
  2177. IWL_DEBUG_TX("Sending AUTH frame\n");
  2178. else if (ieee80211_is_assoc_req(fc))
  2179. IWL_DEBUG_TX("Sending ASSOC frame\n");
  2180. else if (ieee80211_is_reassoc_req(fc))
  2181. IWL_DEBUG_TX("Sending REASSOC frame\n");
  2182. #endif
  2183. /* drop all data frame if we are not associated */
  2184. if (ieee80211_is_data(fc) &&
  2185. (priv->iw_mode != IEEE80211_IF_TYPE_MNTR) && /* packet injection */
  2186. (!iwl3945_is_associated(priv) ||
  2187. ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id))) {
  2188. IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
  2189. goto drop_unlock;
  2190. }
  2191. spin_unlock_irqrestore(&priv->lock, flags);
  2192. hdr_len = ieee80211_get_hdrlen(le16_to_cpu(fc));
  2193. /* Find (or create) index into station table for destination station */
  2194. sta_id = iwl3945_get_sta_id(priv, hdr);
  2195. if (sta_id == IWL_INVALID_STATION) {
  2196. DECLARE_MAC_BUF(mac);
  2197. IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
  2198. print_mac(mac, hdr->addr1));
  2199. goto drop;
  2200. }
  2201. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  2202. if (ieee80211_is_data_qos(fc)) {
  2203. qc = ieee80211_get_qos_ctl(hdr);
  2204. tid = qc[0] & 0xf;
  2205. seq_number = priv->stations[sta_id].tid[tid].seq_number &
  2206. IEEE80211_SCTL_SEQ;
  2207. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  2208. (hdr->seq_ctrl &
  2209. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  2210. seq_number += 0x10;
  2211. }
  2212. /* Descriptor for chosen Tx queue */
  2213. txq = &priv->txq[txq_id];
  2214. q = &txq->q;
  2215. spin_lock_irqsave(&priv->lock, flags);
  2216. /* Set up first empty TFD within this queue's circular TFD buffer */
  2217. tfd = &txq->bd[q->write_ptr];
  2218. memset(tfd, 0, sizeof(*tfd));
  2219. control_flags = (u32 *) tfd;
  2220. idx = get_cmd_index(q, q->write_ptr, 0);
  2221. /* Set up driver data for this TFD */
  2222. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
  2223. txq->txb[q->write_ptr].skb[0] = skb;
  2224. /* Init first empty entry in queue's array of Tx/cmd buffers */
  2225. out_cmd = &txq->cmd[idx];
  2226. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  2227. memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
  2228. /*
  2229. * Set up the Tx-command (not MAC!) header.
  2230. * Store the chosen Tx queue and TFD index within the sequence field;
  2231. * after Tx, uCode's Tx response will return this value so driver can
  2232. * locate the frame within the tx queue and do post-tx processing.
  2233. */
  2234. out_cmd->hdr.cmd = REPLY_TX;
  2235. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  2236. INDEX_TO_SEQ(q->write_ptr)));
  2237. /* Copy MAC header from skb into command buffer */
  2238. memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
  2239. /*
  2240. * Use the first empty entry in this queue's command buffer array
  2241. * to contain the Tx command and MAC header concatenated together
  2242. * (payload data will be in another buffer).
  2243. * Size of this varies, due to varying MAC header length.
  2244. * If end is not dword aligned, we'll have 2 extra bytes at the end
  2245. * of the MAC header (device reads on dword boundaries).
  2246. * We'll tell device about this padding later.
  2247. */
  2248. len = priv->hw_setting.tx_cmd_len +
  2249. sizeof(struct iwl3945_cmd_header) + hdr_len;
  2250. len_org = len;
  2251. len = (len + 3) & ~3;
  2252. if (len_org != len)
  2253. len_org = 1;
  2254. else
  2255. len_org = 0;
  2256. /* Physical address of this Tx command's header (not MAC header!),
  2257. * within command buffer array. */
  2258. txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
  2259. offsetof(struct iwl3945_cmd, hdr);
  2260. /* Add buffer containing Tx command and MAC(!) header to TFD's
  2261. * first entry */
  2262. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
  2263. if (!(info->flags & IEEE80211_TX_CTL_DO_NOT_ENCRYPT))
  2264. iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
  2265. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  2266. * if any (802.11 null frames have no payload). */
  2267. len = skb->len - hdr_len;
  2268. if (len) {
  2269. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  2270. len, PCI_DMA_TODEVICE);
  2271. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
  2272. }
  2273. if (!len)
  2274. /* If there is no payload, then we use only one Tx buffer */
  2275. *control_flags = TFD_CTL_COUNT_SET(1);
  2276. else
  2277. /* Else use 2 buffers.
  2278. * Tell 3945 about any padding after MAC header */
  2279. *control_flags = TFD_CTL_COUNT_SET(2) |
  2280. TFD_CTL_PAD_SET(U32_PAD(len));
  2281. /* Total # bytes to be transmitted */
  2282. len = (u16)skb->len;
  2283. out_cmd->cmd.tx.len = cpu_to_le16(len);
  2284. /* TODO need this for burst mode later on */
  2285. iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id);
  2286. /* set is_hcca to 0; it probably will never be implemented */
  2287. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
  2288. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  2289. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  2290. if (!ieee80211_has_morefrags(hdr->frame_control)) {
  2291. txq->need_update = 1;
  2292. if (qc) {
  2293. priv->stations[sta_id].tid[tid].seq_number = seq_number;
  2294. }
  2295. } else {
  2296. wait_write_ptr = 1;
  2297. txq->need_update = 0;
  2298. }
  2299. iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
  2300. sizeof(out_cmd->cmd.tx));
  2301. iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
  2302. ieee80211_get_hdrlen(le16_to_cpu(fc)));
  2303. /* Tell device the write index *just past* this latest filled TFD */
  2304. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  2305. rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
  2306. spin_unlock_irqrestore(&priv->lock, flags);
  2307. if (rc)
  2308. return rc;
  2309. if ((iwl3945_queue_space(q) < q->high_mark)
  2310. && priv->mac80211_registered) {
  2311. if (wait_write_ptr) {
  2312. spin_lock_irqsave(&priv->lock, flags);
  2313. txq->need_update = 1;
  2314. iwl3945_tx_queue_update_write_ptr(priv, txq);
  2315. spin_unlock_irqrestore(&priv->lock, flags);
  2316. }
  2317. ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
  2318. }
  2319. return 0;
  2320. drop_unlock:
  2321. spin_unlock_irqrestore(&priv->lock, flags);
  2322. drop:
  2323. return -1;
  2324. }
  2325. static void iwl3945_set_rate(struct iwl3945_priv *priv)
  2326. {
  2327. const struct ieee80211_supported_band *sband = NULL;
  2328. struct ieee80211_rate *rate;
  2329. int i;
  2330. sband = iwl3945_get_band(priv, priv->band);
  2331. if (!sband) {
  2332. IWL_ERROR("Failed to set rate: unable to get hw mode\n");
  2333. return;
  2334. }
  2335. priv->active_rate = 0;
  2336. priv->active_rate_basic = 0;
  2337. IWL_DEBUG_RATE("Setting rates for %s GHz\n",
  2338. sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
  2339. for (i = 0; i < sband->n_bitrates; i++) {
  2340. rate = &sband->bitrates[i];
  2341. if ((rate->hw_value < IWL_RATE_COUNT) &&
  2342. !(rate->flags & IEEE80211_CHAN_DISABLED)) {
  2343. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
  2344. rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
  2345. priv->active_rate |= (1 << rate->hw_value);
  2346. }
  2347. }
  2348. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  2349. priv->active_rate, priv->active_rate_basic);
  2350. /*
  2351. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  2352. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  2353. * OFDM
  2354. */
  2355. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  2356. priv->staging_rxon.cck_basic_rates =
  2357. ((priv->active_rate_basic &
  2358. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  2359. else
  2360. priv->staging_rxon.cck_basic_rates =
  2361. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2362. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  2363. priv->staging_rxon.ofdm_basic_rates =
  2364. ((priv->active_rate_basic &
  2365. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  2366. IWL_FIRST_OFDM_RATE) & 0xFF;
  2367. else
  2368. priv->staging_rxon.ofdm_basic_rates =
  2369. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2370. }
  2371. static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
  2372. {
  2373. unsigned long flags;
  2374. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  2375. return;
  2376. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  2377. disable_radio ? "OFF" : "ON");
  2378. if (disable_radio) {
  2379. iwl3945_scan_cancel(priv);
  2380. /* FIXME: This is a workaround for AP */
  2381. if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
  2382. spin_lock_irqsave(&priv->lock, flags);
  2383. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2384. CSR_UCODE_SW_BIT_RFKILL);
  2385. spin_unlock_irqrestore(&priv->lock, flags);
  2386. iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  2387. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2388. }
  2389. return;
  2390. }
  2391. spin_lock_irqsave(&priv->lock, flags);
  2392. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2393. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2394. spin_unlock_irqrestore(&priv->lock, flags);
  2395. /* wake up ucode */
  2396. msleep(10);
  2397. spin_lock_irqsave(&priv->lock, flags);
  2398. iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  2399. if (!iwl3945_grab_nic_access(priv))
  2400. iwl3945_release_nic_access(priv);
  2401. spin_unlock_irqrestore(&priv->lock, flags);
  2402. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  2403. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  2404. "disabled by HW switch\n");
  2405. return;
  2406. }
  2407. if (priv->is_open)
  2408. queue_work(priv->workqueue, &priv->restart);
  2409. return;
  2410. }
  2411. void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
  2412. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2413. {
  2414. u16 fc =
  2415. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  2416. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2417. return;
  2418. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2419. return;
  2420. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2421. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2422. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2423. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2424. RX_RES_STATUS_BAD_ICV_MIC)
  2425. stats->flag |= RX_FLAG_MMIC_ERROR;
  2426. case RX_RES_STATUS_SEC_TYPE_WEP:
  2427. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2428. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2429. RX_RES_STATUS_DECRYPT_OK) {
  2430. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2431. stats->flag |= RX_FLAG_DECRYPTED;
  2432. }
  2433. break;
  2434. default:
  2435. break;
  2436. }
  2437. }
  2438. #define IWL_PACKET_RETRY_TIME HZ
  2439. int iwl3945_is_duplicate_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
  2440. {
  2441. u16 sc = le16_to_cpu(header->seq_ctrl);
  2442. u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4;
  2443. u16 frag = sc & IEEE80211_SCTL_FRAG;
  2444. u16 *last_seq, *last_frag;
  2445. unsigned long *last_time;
  2446. switch (priv->iw_mode) {
  2447. case IEEE80211_IF_TYPE_IBSS:{
  2448. struct list_head *p;
  2449. struct iwl3945_ibss_seq *entry = NULL;
  2450. u8 *mac = header->addr2;
  2451. int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1);
  2452. __list_for_each(p, &priv->ibss_mac_hash[index]) {
  2453. entry = list_entry(p, struct iwl3945_ibss_seq, list);
  2454. if (!compare_ether_addr(entry->mac, mac))
  2455. break;
  2456. }
  2457. if (p == &priv->ibss_mac_hash[index]) {
  2458. entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
  2459. if (!entry) {
  2460. IWL_ERROR("Cannot malloc new mac entry\n");
  2461. return 0;
  2462. }
  2463. memcpy(entry->mac, mac, ETH_ALEN);
  2464. entry->seq_num = seq;
  2465. entry->frag_num = frag;
  2466. entry->packet_time = jiffies;
  2467. list_add(&entry->list, &priv->ibss_mac_hash[index]);
  2468. return 0;
  2469. }
  2470. last_seq = &entry->seq_num;
  2471. last_frag = &entry->frag_num;
  2472. last_time = &entry->packet_time;
  2473. break;
  2474. }
  2475. case IEEE80211_IF_TYPE_STA:
  2476. last_seq = &priv->last_seq_num;
  2477. last_frag = &priv->last_frag_num;
  2478. last_time = &priv->last_packet_time;
  2479. break;
  2480. default:
  2481. return 0;
  2482. }
  2483. if ((*last_seq == seq) &&
  2484. time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) {
  2485. if (*last_frag == frag)
  2486. goto drop;
  2487. if (*last_frag + 1 != frag)
  2488. /* out-of-order fragment */
  2489. goto drop;
  2490. } else
  2491. *last_seq = seq;
  2492. *last_frag = frag;
  2493. *last_time = jiffies;
  2494. return 0;
  2495. drop:
  2496. return 1;
  2497. }
  2498. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2499. #include "iwl-spectrum.h"
  2500. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  2501. #define BEACON_TIME_MASK_HIGH 0xFF000000
  2502. #define TIME_UNIT 1024
  2503. /*
  2504. * extended beacon time format
  2505. * time in usec will be changed into a 32-bit value in 8:24 format
  2506. * the high 1 byte is the beacon counts
  2507. * the lower 3 bytes is the time in usec within one beacon interval
  2508. */
  2509. static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
  2510. {
  2511. u32 quot;
  2512. u32 rem;
  2513. u32 interval = beacon_interval * 1024;
  2514. if (!interval || !usec)
  2515. return 0;
  2516. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  2517. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  2518. return (quot << 24) + rem;
  2519. }
  2520. /* base is usually what we get from ucode with each received frame,
  2521. * the same as HW timer counter counting down
  2522. */
  2523. static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  2524. {
  2525. u32 base_low = base & BEACON_TIME_MASK_LOW;
  2526. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  2527. u32 interval = beacon_interval * TIME_UNIT;
  2528. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  2529. (addon & BEACON_TIME_MASK_HIGH);
  2530. if (base_low > addon_low)
  2531. res += base_low - addon_low;
  2532. else if (base_low < addon_low) {
  2533. res += interval + base_low - addon_low;
  2534. res += (1 << 24);
  2535. } else
  2536. res += (1 << 24);
  2537. return cpu_to_le32(res);
  2538. }
  2539. static int iwl3945_get_measurement(struct iwl3945_priv *priv,
  2540. struct ieee80211_measurement_params *params,
  2541. u8 type)
  2542. {
  2543. struct iwl3945_spectrum_cmd spectrum;
  2544. struct iwl3945_rx_packet *res;
  2545. struct iwl3945_host_cmd cmd = {
  2546. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  2547. .data = (void *)&spectrum,
  2548. .meta.flags = CMD_WANT_SKB,
  2549. };
  2550. u32 add_time = le64_to_cpu(params->start_time);
  2551. int rc;
  2552. int spectrum_resp_status;
  2553. int duration = le16_to_cpu(params->duration);
  2554. if (iwl3945_is_associated(priv))
  2555. add_time =
  2556. iwl3945_usecs_to_beacons(
  2557. le64_to_cpu(params->start_time) - priv->last_tsf,
  2558. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2559. memset(&spectrum, 0, sizeof(spectrum));
  2560. spectrum.channel_count = cpu_to_le16(1);
  2561. spectrum.flags =
  2562. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  2563. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  2564. cmd.len = sizeof(spectrum);
  2565. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  2566. if (iwl3945_is_associated(priv))
  2567. spectrum.start_time =
  2568. iwl3945_add_beacon_time(priv->last_beacon_time,
  2569. add_time,
  2570. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2571. else
  2572. spectrum.start_time = 0;
  2573. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  2574. spectrum.channels[0].channel = params->channel;
  2575. spectrum.channels[0].type = type;
  2576. if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
  2577. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  2578. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  2579. rc = iwl3945_send_cmd_sync(priv, &cmd);
  2580. if (rc)
  2581. return rc;
  2582. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  2583. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  2584. IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
  2585. rc = -EIO;
  2586. }
  2587. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  2588. switch (spectrum_resp_status) {
  2589. case 0: /* Command will be handled */
  2590. if (res->u.spectrum.id != 0xff) {
  2591. IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
  2592. res->u.spectrum.id);
  2593. priv->measurement_status &= ~MEASUREMENT_READY;
  2594. }
  2595. priv->measurement_status |= MEASUREMENT_ACTIVE;
  2596. rc = 0;
  2597. break;
  2598. case 1: /* Command will not be handled */
  2599. rc = -EAGAIN;
  2600. break;
  2601. }
  2602. dev_kfree_skb_any(cmd.meta.u.skb);
  2603. return rc;
  2604. }
  2605. #endif
  2606. static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
  2607. struct iwl3945_rx_mem_buffer *rxb)
  2608. {
  2609. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2610. struct iwl3945_alive_resp *palive;
  2611. struct delayed_work *pwork;
  2612. palive = &pkt->u.alive_frame;
  2613. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  2614. "0x%01X 0x%01X\n",
  2615. palive->is_valid, palive->ver_type,
  2616. palive->ver_subtype);
  2617. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  2618. IWL_DEBUG_INFO("Initialization Alive received.\n");
  2619. memcpy(&priv->card_alive_init,
  2620. &pkt->u.alive_frame,
  2621. sizeof(struct iwl3945_init_alive_resp));
  2622. pwork = &priv->init_alive_start;
  2623. } else {
  2624. IWL_DEBUG_INFO("Runtime Alive received.\n");
  2625. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  2626. sizeof(struct iwl3945_alive_resp));
  2627. pwork = &priv->alive_start;
  2628. iwl3945_disable_events(priv);
  2629. }
  2630. /* We delay the ALIVE response by 5ms to
  2631. * give the HW RF Kill time to activate... */
  2632. if (palive->is_valid == UCODE_VALID_OK)
  2633. queue_delayed_work(priv->workqueue, pwork,
  2634. msecs_to_jiffies(5));
  2635. else
  2636. IWL_WARNING("uCode did not respond OK.\n");
  2637. }
  2638. static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
  2639. struct iwl3945_rx_mem_buffer *rxb)
  2640. {
  2641. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2642. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  2643. return;
  2644. }
  2645. static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
  2646. struct iwl3945_rx_mem_buffer *rxb)
  2647. {
  2648. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2649. IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
  2650. "seq 0x%04X ser 0x%08X\n",
  2651. le32_to_cpu(pkt->u.err_resp.error_type),
  2652. get_cmd_string(pkt->u.err_resp.cmd_id),
  2653. pkt->u.err_resp.cmd_id,
  2654. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  2655. le32_to_cpu(pkt->u.err_resp.error_info));
  2656. }
  2657. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  2658. static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
  2659. {
  2660. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2661. struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
  2662. struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
  2663. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  2664. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  2665. rxon->channel = csa->channel;
  2666. priv->staging_rxon.channel = csa->channel;
  2667. }
  2668. static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
  2669. struct iwl3945_rx_mem_buffer *rxb)
  2670. {
  2671. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2672. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2673. struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2674. if (!report->state) {
  2675. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  2676. "Spectrum Measure Notification: Start\n");
  2677. return;
  2678. }
  2679. memcpy(&priv->measure_report, report, sizeof(*report));
  2680. priv->measurement_status |= MEASUREMENT_READY;
  2681. #endif
  2682. }
  2683. static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
  2684. struct iwl3945_rx_mem_buffer *rxb)
  2685. {
  2686. #ifdef CONFIG_IWL3945_DEBUG
  2687. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2688. struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
  2689. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  2690. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  2691. #endif
  2692. }
  2693. static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
  2694. struct iwl3945_rx_mem_buffer *rxb)
  2695. {
  2696. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2697. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  2698. "notification for %s:\n",
  2699. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  2700. iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
  2701. }
  2702. static void iwl3945_bg_beacon_update(struct work_struct *work)
  2703. {
  2704. struct iwl3945_priv *priv =
  2705. container_of(work, struct iwl3945_priv, beacon_update);
  2706. struct sk_buff *beacon;
  2707. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  2708. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  2709. if (!beacon) {
  2710. IWL_ERROR("update beacon failed\n");
  2711. return;
  2712. }
  2713. mutex_lock(&priv->mutex);
  2714. /* new beacon skb is allocated every time; dispose previous.*/
  2715. if (priv->ibss_beacon)
  2716. dev_kfree_skb(priv->ibss_beacon);
  2717. priv->ibss_beacon = beacon;
  2718. mutex_unlock(&priv->mutex);
  2719. iwl3945_send_beacon_cmd(priv);
  2720. }
  2721. static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
  2722. struct iwl3945_rx_mem_buffer *rxb)
  2723. {
  2724. #ifdef CONFIG_IWL3945_DEBUG
  2725. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2726. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  2727. u8 rate = beacon->beacon_notify_hdr.rate;
  2728. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  2729. "tsf %d %d rate %d\n",
  2730. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  2731. beacon->beacon_notify_hdr.failure_frame,
  2732. le32_to_cpu(beacon->ibss_mgr_status),
  2733. le32_to_cpu(beacon->high_tsf),
  2734. le32_to_cpu(beacon->low_tsf), rate);
  2735. #endif
  2736. if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
  2737. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  2738. queue_work(priv->workqueue, &priv->beacon_update);
  2739. }
  2740. /* Service response to REPLY_SCAN_CMD (0x80) */
  2741. static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
  2742. struct iwl3945_rx_mem_buffer *rxb)
  2743. {
  2744. #ifdef CONFIG_IWL3945_DEBUG
  2745. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2746. struct iwl3945_scanreq_notification *notif =
  2747. (struct iwl3945_scanreq_notification *)pkt->u.raw;
  2748. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  2749. #endif
  2750. }
  2751. /* Service SCAN_START_NOTIFICATION (0x82) */
  2752. static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
  2753. struct iwl3945_rx_mem_buffer *rxb)
  2754. {
  2755. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2756. struct iwl3945_scanstart_notification *notif =
  2757. (struct iwl3945_scanstart_notification *)pkt->u.raw;
  2758. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  2759. IWL_DEBUG_SCAN("Scan start: "
  2760. "%d [802.11%s] "
  2761. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  2762. notif->channel,
  2763. notif->band ? "bg" : "a",
  2764. notif->tsf_high,
  2765. notif->tsf_low, notif->status, notif->beacon_timer);
  2766. }
  2767. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  2768. static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
  2769. struct iwl3945_rx_mem_buffer *rxb)
  2770. {
  2771. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2772. struct iwl3945_scanresults_notification *notif =
  2773. (struct iwl3945_scanresults_notification *)pkt->u.raw;
  2774. IWL_DEBUG_SCAN("Scan ch.res: "
  2775. "%d [802.11%s] "
  2776. "(TSF: 0x%08X:%08X) - %d "
  2777. "elapsed=%lu usec (%dms since last)\n",
  2778. notif->channel,
  2779. notif->band ? "bg" : "a",
  2780. le32_to_cpu(notif->tsf_high),
  2781. le32_to_cpu(notif->tsf_low),
  2782. le32_to_cpu(notif->statistics[0]),
  2783. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  2784. jiffies_to_msecs(elapsed_jiffies
  2785. (priv->last_scan_jiffies, jiffies)));
  2786. priv->last_scan_jiffies = jiffies;
  2787. priv->next_scan_jiffies = 0;
  2788. }
  2789. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  2790. static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
  2791. struct iwl3945_rx_mem_buffer *rxb)
  2792. {
  2793. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2794. struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  2795. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  2796. scan_notif->scanned_channels,
  2797. scan_notif->tsf_low,
  2798. scan_notif->tsf_high, scan_notif->status);
  2799. /* The HW is no longer scanning */
  2800. clear_bit(STATUS_SCAN_HW, &priv->status);
  2801. /* The scan completion notification came in, so kill that timer... */
  2802. cancel_delayed_work(&priv->scan_check);
  2803. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  2804. (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
  2805. "2.4" : "5.2",
  2806. jiffies_to_msecs(elapsed_jiffies
  2807. (priv->scan_pass_start, jiffies)));
  2808. /* Remove this scanned band from the list of pending
  2809. * bands to scan, band G precedes A in order of scanning
  2810. * as seen in iwl3945_bg_request_scan */
  2811. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
  2812. priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
  2813. else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
  2814. priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
  2815. /* If a request to abort was given, or the scan did not succeed
  2816. * then we reset the scan state machine and terminate,
  2817. * re-queuing another scan if one has been requested */
  2818. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2819. IWL_DEBUG_INFO("Aborted scan completed.\n");
  2820. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  2821. } else {
  2822. /* If there are more bands on this scan pass reschedule */
  2823. if (priv->scan_bands > 0)
  2824. goto reschedule;
  2825. }
  2826. priv->last_scan_jiffies = jiffies;
  2827. priv->next_scan_jiffies = 0;
  2828. IWL_DEBUG_INFO("Setting scan to off\n");
  2829. clear_bit(STATUS_SCANNING, &priv->status);
  2830. IWL_DEBUG_INFO("Scan took %dms\n",
  2831. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  2832. queue_work(priv->workqueue, &priv->scan_completed);
  2833. return;
  2834. reschedule:
  2835. priv->scan_pass_start = jiffies;
  2836. queue_work(priv->workqueue, &priv->request_scan);
  2837. }
  2838. /* Handle notification from uCode that card's power state is changing
  2839. * due to software, hardware, or critical temperature RFKILL */
  2840. static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
  2841. struct iwl3945_rx_mem_buffer *rxb)
  2842. {
  2843. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2844. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  2845. unsigned long status = priv->status;
  2846. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  2847. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  2848. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  2849. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2850. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2851. if (flags & HW_CARD_DISABLED)
  2852. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2853. else
  2854. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2855. if (flags & SW_CARD_DISABLED)
  2856. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2857. else
  2858. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2859. iwl3945_scan_cancel(priv);
  2860. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  2861. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  2862. (test_bit(STATUS_RF_KILL_SW, &status) !=
  2863. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  2864. queue_work(priv->workqueue, &priv->rf_kill);
  2865. else
  2866. wake_up_interruptible(&priv->wait_command_queue);
  2867. }
  2868. /**
  2869. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  2870. *
  2871. * Setup the RX handlers for each of the reply types sent from the uCode
  2872. * to the host.
  2873. *
  2874. * This function chains into the hardware specific files for them to setup
  2875. * any hardware specific handlers as well.
  2876. */
  2877. static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
  2878. {
  2879. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  2880. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  2881. priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
  2882. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
  2883. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  2884. iwl3945_rx_spectrum_measure_notif;
  2885. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
  2886. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  2887. iwl3945_rx_pm_debug_statistics_notif;
  2888. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  2889. /*
  2890. * The same handler is used for both the REPLY to a discrete
  2891. * statistics request from the host as well as for the periodic
  2892. * statistics notifications (after received beacons) from the uCode.
  2893. */
  2894. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
  2895. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  2896. priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
  2897. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
  2898. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  2899. iwl3945_rx_scan_results_notif;
  2900. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  2901. iwl3945_rx_scan_complete_notif;
  2902. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  2903. /* Set up hardware specific Rx handlers */
  2904. iwl3945_hw_rx_handler_setup(priv);
  2905. }
  2906. /**
  2907. * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
  2908. * When FW advances 'R' index, all entries between old and new 'R' index
  2909. * need to be reclaimed.
  2910. */
  2911. static void iwl3945_cmd_queue_reclaim(struct iwl3945_priv *priv,
  2912. int txq_id, int index)
  2913. {
  2914. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  2915. struct iwl3945_queue *q = &txq->q;
  2916. int nfreed = 0;
  2917. if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
  2918. IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
  2919. "is out of range [0-%d] %d %d.\n", txq_id,
  2920. index, q->n_bd, q->write_ptr, q->read_ptr);
  2921. return;
  2922. }
  2923. for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
  2924. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2925. if (nfreed > 1) {
  2926. IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
  2927. q->write_ptr, q->read_ptr);
  2928. queue_work(priv->workqueue, &priv->restart);
  2929. break;
  2930. }
  2931. nfreed++;
  2932. }
  2933. }
  2934. /**
  2935. * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  2936. * @rxb: Rx buffer to reclaim
  2937. *
  2938. * If an Rx buffer has an async callback associated with it the callback
  2939. * will be executed. The attached skb (if present) will only be freed
  2940. * if the callback returns 1
  2941. */
  2942. static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
  2943. struct iwl3945_rx_mem_buffer *rxb)
  2944. {
  2945. struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  2946. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2947. int txq_id = SEQ_TO_QUEUE(sequence);
  2948. int index = SEQ_TO_INDEX(sequence);
  2949. int huge = sequence & SEQ_HUGE_FRAME;
  2950. int cmd_index;
  2951. struct iwl3945_cmd *cmd;
  2952. BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
  2953. cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
  2954. cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  2955. /* Input error checking is done when commands are added to queue. */
  2956. if (cmd->meta.flags & CMD_WANT_SKB) {
  2957. cmd->meta.source->u.skb = rxb->skb;
  2958. rxb->skb = NULL;
  2959. } else if (cmd->meta.u.callback &&
  2960. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  2961. rxb->skb = NULL;
  2962. iwl3945_cmd_queue_reclaim(priv, txq_id, index);
  2963. if (!(cmd->meta.flags & CMD_ASYNC)) {
  2964. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  2965. wake_up_interruptible(&priv->wait_command_queue);
  2966. }
  2967. }
  2968. /************************** RX-FUNCTIONS ****************************/
  2969. /*
  2970. * Rx theory of operation
  2971. *
  2972. * The host allocates 32 DMA target addresses and passes the host address
  2973. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  2974. * 0 to 31
  2975. *
  2976. * Rx Queue Indexes
  2977. * The host/firmware share two index registers for managing the Rx buffers.
  2978. *
  2979. * The READ index maps to the first position that the firmware may be writing
  2980. * to -- the driver can read up to (but not including) this position and get
  2981. * good data.
  2982. * The READ index is managed by the firmware once the card is enabled.
  2983. *
  2984. * The WRITE index maps to the last position the driver has read from -- the
  2985. * position preceding WRITE is the last slot the firmware can place a packet.
  2986. *
  2987. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  2988. * WRITE = READ.
  2989. *
  2990. * During initialization, the host sets up the READ queue position to the first
  2991. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  2992. *
  2993. * When the firmware places a packet in a buffer, it will advance the READ index
  2994. * and fire the RX interrupt. The driver can then query the READ index and
  2995. * process as many packets as possible, moving the WRITE index forward as it
  2996. * resets the Rx queue buffers with new memory.
  2997. *
  2998. * The management in the driver is as follows:
  2999. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  3000. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  3001. * to replenish the iwl->rxq->rx_free.
  3002. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  3003. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  3004. * 'processed' and 'read' driver indexes as well)
  3005. * + A received packet is processed and handed to the kernel network stack,
  3006. * detached from the iwl->rxq. The driver 'processed' index is updated.
  3007. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  3008. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  3009. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  3010. * were enough free buffers and RX_STALLED is set it is cleared.
  3011. *
  3012. *
  3013. * Driver sequence:
  3014. *
  3015. * iwl3945_rx_queue_alloc() Allocates rx_free
  3016. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  3017. * iwl3945_rx_queue_restock
  3018. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  3019. * queue, updates firmware pointers, and updates
  3020. * the WRITE index. If insufficient rx_free buffers
  3021. * are available, schedules iwl3945_rx_replenish
  3022. *
  3023. * -- enable interrupts --
  3024. * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
  3025. * READ INDEX, detaching the SKB from the pool.
  3026. * Moves the packet buffer from queue to rx_used.
  3027. * Calls iwl3945_rx_queue_restock to refill any empty
  3028. * slots.
  3029. * ...
  3030. *
  3031. */
  3032. /**
  3033. * iwl3945_rx_queue_space - Return number of free slots available in queue.
  3034. */
  3035. static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
  3036. {
  3037. int s = q->read - q->write;
  3038. if (s <= 0)
  3039. s += RX_QUEUE_SIZE;
  3040. /* keep some buffer to not confuse full and empty queue */
  3041. s -= 2;
  3042. if (s < 0)
  3043. s = 0;
  3044. return s;
  3045. }
  3046. /**
  3047. * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  3048. */
  3049. int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
  3050. {
  3051. u32 reg = 0;
  3052. int rc = 0;
  3053. unsigned long flags;
  3054. spin_lock_irqsave(&q->lock, flags);
  3055. if (q->need_update == 0)
  3056. goto exit_unlock;
  3057. /* If power-saving is in use, make sure device is awake */
  3058. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3059. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3060. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3061. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3062. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3063. goto exit_unlock;
  3064. }
  3065. rc = iwl3945_grab_nic_access(priv);
  3066. if (rc)
  3067. goto exit_unlock;
  3068. /* Device expects a multiple of 8 */
  3069. iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
  3070. q->write & ~0x7);
  3071. iwl3945_release_nic_access(priv);
  3072. /* Else device is assumed to be awake */
  3073. } else
  3074. /* Device expects a multiple of 8 */
  3075. iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  3076. q->need_update = 0;
  3077. exit_unlock:
  3078. spin_unlock_irqrestore(&q->lock, flags);
  3079. return rc;
  3080. }
  3081. /**
  3082. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  3083. */
  3084. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
  3085. dma_addr_t dma_addr)
  3086. {
  3087. return cpu_to_le32((u32)dma_addr);
  3088. }
  3089. /**
  3090. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  3091. *
  3092. * If there are slots in the RX queue that need to be restocked,
  3093. * and we have free pre-allocated buffers, fill the ranks as much
  3094. * as we can, pulling from rx_free.
  3095. *
  3096. * This moves the 'write' index forward to catch up with 'processed', and
  3097. * also updates the memory address in the firmware to reference the new
  3098. * target buffer.
  3099. */
  3100. static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
  3101. {
  3102. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3103. struct list_head *element;
  3104. struct iwl3945_rx_mem_buffer *rxb;
  3105. unsigned long flags;
  3106. int write, rc;
  3107. spin_lock_irqsave(&rxq->lock, flags);
  3108. write = rxq->write & ~0x7;
  3109. while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  3110. /* Get next free Rx buffer, remove from free list */
  3111. element = rxq->rx_free.next;
  3112. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3113. list_del(element);
  3114. /* Point to Rx buffer via next RBD in circular buffer */
  3115. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
  3116. rxq->queue[rxq->write] = rxb;
  3117. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  3118. rxq->free_count--;
  3119. }
  3120. spin_unlock_irqrestore(&rxq->lock, flags);
  3121. /* If the pre-allocated buffer pool is dropping low, schedule to
  3122. * refill it */
  3123. if (rxq->free_count <= RX_LOW_WATERMARK)
  3124. queue_work(priv->workqueue, &priv->rx_replenish);
  3125. /* If we've added more space for the firmware to place data, tell it.
  3126. * Increment device's write pointer in multiples of 8. */
  3127. if ((write != (rxq->write & ~0x7))
  3128. || (abs(rxq->write - rxq->read) > 7)) {
  3129. spin_lock_irqsave(&rxq->lock, flags);
  3130. rxq->need_update = 1;
  3131. spin_unlock_irqrestore(&rxq->lock, flags);
  3132. rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
  3133. if (rc)
  3134. return rc;
  3135. }
  3136. return 0;
  3137. }
  3138. /**
  3139. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  3140. *
  3141. * When moving to rx_free an SKB is allocated for the slot.
  3142. *
  3143. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  3144. * This is called as a scheduled work item (except for during initialization)
  3145. */
  3146. static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
  3147. {
  3148. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3149. struct list_head *element;
  3150. struct iwl3945_rx_mem_buffer *rxb;
  3151. unsigned long flags;
  3152. spin_lock_irqsave(&rxq->lock, flags);
  3153. while (!list_empty(&rxq->rx_used)) {
  3154. element = rxq->rx_used.next;
  3155. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3156. /* Alloc a new receive buffer */
  3157. rxb->skb =
  3158. alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
  3159. if (!rxb->skb) {
  3160. if (net_ratelimit())
  3161. printk(KERN_CRIT DRV_NAME
  3162. ": Can not allocate SKB buffers\n");
  3163. /* We don't reschedule replenish work here -- we will
  3164. * call the restock method and if it still needs
  3165. * more buffers it will schedule replenish */
  3166. break;
  3167. }
  3168. /* If radiotap head is required, reserve some headroom here.
  3169. * The physical head count is a variable rx_stats->phy_count.
  3170. * We reserve 4 bytes here. Plus these extra bytes, the
  3171. * headroom of the physical head should be enough for the
  3172. * radiotap head that iwl3945 supported. See iwl3945_rt.
  3173. */
  3174. skb_reserve(rxb->skb, 4);
  3175. priv->alloc_rxb_skb++;
  3176. list_del(element);
  3177. /* Get physical address of RB/SKB */
  3178. rxb->dma_addr =
  3179. pci_map_single(priv->pci_dev, rxb->skb->data,
  3180. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3181. list_add_tail(&rxb->list, &rxq->rx_free);
  3182. rxq->free_count++;
  3183. }
  3184. spin_unlock_irqrestore(&rxq->lock, flags);
  3185. }
  3186. /*
  3187. * this should be called while priv->lock is locked
  3188. */
  3189. static void __iwl3945_rx_replenish(void *data)
  3190. {
  3191. struct iwl3945_priv *priv = data;
  3192. iwl3945_rx_allocate(priv);
  3193. iwl3945_rx_queue_restock(priv);
  3194. }
  3195. void iwl3945_rx_replenish(void *data)
  3196. {
  3197. struct iwl3945_priv *priv = data;
  3198. unsigned long flags;
  3199. iwl3945_rx_allocate(priv);
  3200. spin_lock_irqsave(&priv->lock, flags);
  3201. iwl3945_rx_queue_restock(priv);
  3202. spin_unlock_irqrestore(&priv->lock, flags);
  3203. }
  3204. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  3205. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  3206. * This free routine walks the list of POOL entries and if SKB is set to
  3207. * non NULL it is unmapped and freed
  3208. */
  3209. static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3210. {
  3211. int i;
  3212. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  3213. if (rxq->pool[i].skb != NULL) {
  3214. pci_unmap_single(priv->pci_dev,
  3215. rxq->pool[i].dma_addr,
  3216. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3217. dev_kfree_skb(rxq->pool[i].skb);
  3218. }
  3219. }
  3220. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  3221. rxq->dma_addr);
  3222. rxq->bd = NULL;
  3223. }
  3224. int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
  3225. {
  3226. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3227. struct pci_dev *dev = priv->pci_dev;
  3228. int i;
  3229. spin_lock_init(&rxq->lock);
  3230. INIT_LIST_HEAD(&rxq->rx_free);
  3231. INIT_LIST_HEAD(&rxq->rx_used);
  3232. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  3233. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  3234. if (!rxq->bd)
  3235. return -ENOMEM;
  3236. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3237. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  3238. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3239. /* Set us so that we have processed and used all buffers, but have
  3240. * not restocked the Rx queue with fresh buffers */
  3241. rxq->read = rxq->write = 0;
  3242. rxq->free_count = 0;
  3243. rxq->need_update = 0;
  3244. return 0;
  3245. }
  3246. void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3247. {
  3248. unsigned long flags;
  3249. int i;
  3250. spin_lock_irqsave(&rxq->lock, flags);
  3251. INIT_LIST_HEAD(&rxq->rx_free);
  3252. INIT_LIST_HEAD(&rxq->rx_used);
  3253. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3254. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  3255. /* In the reset function, these buffers may have been allocated
  3256. * to an SKB, so we need to unmap and free potential storage */
  3257. if (rxq->pool[i].skb != NULL) {
  3258. pci_unmap_single(priv->pci_dev,
  3259. rxq->pool[i].dma_addr,
  3260. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3261. priv->alloc_rxb_skb--;
  3262. dev_kfree_skb(rxq->pool[i].skb);
  3263. rxq->pool[i].skb = NULL;
  3264. }
  3265. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3266. }
  3267. /* Set us so that we have processed and used all buffers, but have
  3268. * not restocked the Rx queue with fresh buffers */
  3269. rxq->read = rxq->write = 0;
  3270. rxq->free_count = 0;
  3271. spin_unlock_irqrestore(&rxq->lock, flags);
  3272. }
  3273. /* Convert linear signal-to-noise ratio into dB */
  3274. static u8 ratio2dB[100] = {
  3275. /* 0 1 2 3 4 5 6 7 8 9 */
  3276. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  3277. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  3278. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  3279. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  3280. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  3281. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  3282. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  3283. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  3284. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  3285. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  3286. };
  3287. /* Calculates a relative dB value from a ratio of linear
  3288. * (i.e. not dB) signal levels.
  3289. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  3290. int iwl3945_calc_db_from_ratio(int sig_ratio)
  3291. {
  3292. /* 1000:1 or higher just report as 60 dB */
  3293. if (sig_ratio >= 1000)
  3294. return 60;
  3295. /* 100:1 or higher, divide by 10 and use table,
  3296. * add 20 dB to make up for divide by 10 */
  3297. if (sig_ratio >= 100)
  3298. return (20 + (int)ratio2dB[sig_ratio/10]);
  3299. /* We shouldn't see this */
  3300. if (sig_ratio < 1)
  3301. return 0;
  3302. /* Use table for ratios 1:1 - 99:1 */
  3303. return (int)ratio2dB[sig_ratio];
  3304. }
  3305. #define PERFECT_RSSI (-20) /* dBm */
  3306. #define WORST_RSSI (-95) /* dBm */
  3307. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  3308. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  3309. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  3310. * about formulas used below. */
  3311. int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
  3312. {
  3313. int sig_qual;
  3314. int degradation = PERFECT_RSSI - rssi_dbm;
  3315. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  3316. * as indicator; formula is (signal dbm - noise dbm).
  3317. * SNR at or above 40 is a great signal (100%).
  3318. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  3319. * Weakest usable signal is usually 10 - 15 dB SNR. */
  3320. if (noise_dbm) {
  3321. if (rssi_dbm - noise_dbm >= 40)
  3322. return 100;
  3323. else if (rssi_dbm < noise_dbm)
  3324. return 0;
  3325. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  3326. /* Else use just the signal level.
  3327. * This formula is a least squares fit of data points collected and
  3328. * compared with a reference system that had a percentage (%) display
  3329. * for signal quality. */
  3330. } else
  3331. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  3332. (15 * RSSI_RANGE + 62 * degradation)) /
  3333. (RSSI_RANGE * RSSI_RANGE);
  3334. if (sig_qual > 100)
  3335. sig_qual = 100;
  3336. else if (sig_qual < 1)
  3337. sig_qual = 0;
  3338. return sig_qual;
  3339. }
  3340. /**
  3341. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  3342. *
  3343. * Uses the priv->rx_handlers callback function array to invoke
  3344. * the appropriate handlers, including command responses,
  3345. * frame-received notifications, and other notifications.
  3346. */
  3347. static void iwl3945_rx_handle(struct iwl3945_priv *priv)
  3348. {
  3349. struct iwl3945_rx_mem_buffer *rxb;
  3350. struct iwl3945_rx_packet *pkt;
  3351. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3352. u32 r, i;
  3353. int reclaim;
  3354. unsigned long flags;
  3355. u8 fill_rx = 0;
  3356. u32 count = 8;
  3357. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  3358. * buffer that the driver may process (last buffer filled by ucode). */
  3359. r = iwl3945_hw_get_rx_read(priv);
  3360. i = rxq->read;
  3361. if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  3362. fill_rx = 1;
  3363. /* Rx interrupt, but nothing sent from uCode */
  3364. if (i == r)
  3365. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  3366. while (i != r) {
  3367. rxb = rxq->queue[i];
  3368. /* If an RXB doesn't have a Rx queue slot associated with it,
  3369. * then a bug has been introduced in the queue refilling
  3370. * routines -- catch it here */
  3371. BUG_ON(rxb == NULL);
  3372. rxq->queue[i] = NULL;
  3373. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
  3374. IWL_RX_BUF_SIZE,
  3375. PCI_DMA_FROMDEVICE);
  3376. pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  3377. /* Reclaim a command buffer only if this packet is a response
  3378. * to a (driver-originated) command.
  3379. * If the packet (e.g. Rx frame) originated from uCode,
  3380. * there is no command buffer to reclaim.
  3381. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  3382. * but apparently a few don't get set; catch them here. */
  3383. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  3384. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  3385. (pkt->hdr.cmd != REPLY_TX);
  3386. /* Based on type of command response or notification,
  3387. * handle those that need handling via function in
  3388. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  3389. if (priv->rx_handlers[pkt->hdr.cmd]) {
  3390. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3391. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  3392. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  3393. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  3394. } else {
  3395. /* No handling needed */
  3396. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3397. "r %d i %d No handler needed for %s, 0x%02x\n",
  3398. r, i, get_cmd_string(pkt->hdr.cmd),
  3399. pkt->hdr.cmd);
  3400. }
  3401. if (reclaim) {
  3402. /* Invoke any callbacks, transfer the skb to caller, and
  3403. * fire off the (possibly) blocking iwl3945_send_cmd()
  3404. * as we reclaim the driver command queue */
  3405. if (rxb && rxb->skb)
  3406. iwl3945_tx_cmd_complete(priv, rxb);
  3407. else
  3408. IWL_WARNING("Claim null rxb?\n");
  3409. }
  3410. /* For now we just don't re-use anything. We can tweak this
  3411. * later to try and re-use notification packets and SKBs that
  3412. * fail to Rx correctly */
  3413. if (rxb->skb != NULL) {
  3414. priv->alloc_rxb_skb--;
  3415. dev_kfree_skb_any(rxb->skb);
  3416. rxb->skb = NULL;
  3417. }
  3418. pci_unmap_single(priv->pci_dev, rxb->dma_addr,
  3419. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3420. spin_lock_irqsave(&rxq->lock, flags);
  3421. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  3422. spin_unlock_irqrestore(&rxq->lock, flags);
  3423. i = (i + 1) & RX_QUEUE_MASK;
  3424. /* If there are a lot of unused frames,
  3425. * restock the Rx queue so ucode won't assert. */
  3426. if (fill_rx) {
  3427. count++;
  3428. if (count >= 8) {
  3429. priv->rxq.read = i;
  3430. __iwl3945_rx_replenish(priv);
  3431. count = 0;
  3432. }
  3433. }
  3434. }
  3435. /* Backtrack one entry */
  3436. priv->rxq.read = i;
  3437. iwl3945_rx_queue_restock(priv);
  3438. }
  3439. /**
  3440. * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
  3441. */
  3442. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  3443. struct iwl3945_tx_queue *txq)
  3444. {
  3445. u32 reg = 0;
  3446. int rc = 0;
  3447. int txq_id = txq->q.id;
  3448. if (txq->need_update == 0)
  3449. return rc;
  3450. /* if we're trying to save power */
  3451. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3452. /* wake up nic if it's powered down ...
  3453. * uCode will wake up, and interrupt us again, so next
  3454. * time we'll skip this part. */
  3455. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3456. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3457. IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
  3458. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3459. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3460. return rc;
  3461. }
  3462. /* restore this queue's parameters in nic hardware. */
  3463. rc = iwl3945_grab_nic_access(priv);
  3464. if (rc)
  3465. return rc;
  3466. iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
  3467. txq->q.write_ptr | (txq_id << 8));
  3468. iwl3945_release_nic_access(priv);
  3469. /* else not in power-save mode, uCode will never sleep when we're
  3470. * trying to tx (during RFKILL, we're not trying to tx). */
  3471. } else
  3472. iwl3945_write32(priv, HBUS_TARG_WRPTR,
  3473. txq->q.write_ptr | (txq_id << 8));
  3474. txq->need_update = 0;
  3475. return rc;
  3476. }
  3477. #ifdef CONFIG_IWL3945_DEBUG
  3478. static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
  3479. {
  3480. DECLARE_MAC_BUF(mac);
  3481. IWL_DEBUG_RADIO("RX CONFIG:\n");
  3482. iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3483. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3484. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3485. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  3486. le32_to_cpu(rxon->filter_flags));
  3487. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3488. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  3489. rxon->ofdm_basic_rates);
  3490. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3491. IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
  3492. print_mac(mac, rxon->node_addr));
  3493. IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
  3494. print_mac(mac, rxon->bssid_addr));
  3495. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3496. }
  3497. #endif
  3498. static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
  3499. {
  3500. IWL_DEBUG_ISR("Enabling interrupts\n");
  3501. set_bit(STATUS_INT_ENABLED, &priv->status);
  3502. iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  3503. }
  3504. /* call this function to flush any scheduled tasklet */
  3505. static inline void iwl_synchronize_irq(struct iwl3945_priv *priv)
  3506. {
  3507. /* wait to make sure we flush pedding tasklet*/
  3508. synchronize_irq(priv->pci_dev->irq);
  3509. tasklet_kill(&priv->irq_tasklet);
  3510. }
  3511. static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
  3512. {
  3513. clear_bit(STATUS_INT_ENABLED, &priv->status);
  3514. /* disable interrupts from uCode/NIC to host */
  3515. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3516. /* acknowledge/clear/reset any interrupts still pending
  3517. * from uCode or flow handler (Rx/Tx DMA) */
  3518. iwl3945_write32(priv, CSR_INT, 0xffffffff);
  3519. iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  3520. IWL_DEBUG_ISR("Disabled interrupts\n");
  3521. }
  3522. static const char *desc_lookup(int i)
  3523. {
  3524. switch (i) {
  3525. case 1:
  3526. return "FAIL";
  3527. case 2:
  3528. return "BAD_PARAM";
  3529. case 3:
  3530. return "BAD_CHECKSUM";
  3531. case 4:
  3532. return "NMI_INTERRUPT";
  3533. case 5:
  3534. return "SYSASSERT";
  3535. case 6:
  3536. return "FATAL_ERROR";
  3537. }
  3538. return "UNKNOWN";
  3539. }
  3540. #define ERROR_START_OFFSET (1 * sizeof(u32))
  3541. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  3542. static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
  3543. {
  3544. u32 i;
  3545. u32 desc, time, count, base, data1;
  3546. u32 blink1, blink2, ilink1, ilink2;
  3547. int rc;
  3548. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  3549. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3550. IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
  3551. return;
  3552. }
  3553. rc = iwl3945_grab_nic_access(priv);
  3554. if (rc) {
  3555. IWL_WARNING("Can not read from adapter at this time.\n");
  3556. return;
  3557. }
  3558. count = iwl3945_read_targ_mem(priv, base);
  3559. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  3560. IWL_ERROR("Start IWL Error Log Dump:\n");
  3561. IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
  3562. }
  3563. IWL_ERROR("Desc Time asrtPC blink2 "
  3564. "ilink1 nmiPC Line\n");
  3565. for (i = ERROR_START_OFFSET;
  3566. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  3567. i += ERROR_ELEM_SIZE) {
  3568. desc = iwl3945_read_targ_mem(priv, base + i);
  3569. time =
  3570. iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  3571. blink1 =
  3572. iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  3573. blink2 =
  3574. iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  3575. ilink1 =
  3576. iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  3577. ilink2 =
  3578. iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  3579. data1 =
  3580. iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  3581. IWL_ERROR
  3582. ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  3583. desc_lookup(desc), desc, time, blink1, blink2,
  3584. ilink1, ilink2, data1);
  3585. }
  3586. iwl3945_release_nic_access(priv);
  3587. }
  3588. #define EVENT_START_OFFSET (6 * sizeof(u32))
  3589. /**
  3590. * iwl3945_print_event_log - Dump error event log to syslog
  3591. *
  3592. * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
  3593. */
  3594. static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
  3595. u32 num_events, u32 mode)
  3596. {
  3597. u32 i;
  3598. u32 base; /* SRAM byte address of event log header */
  3599. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  3600. u32 ptr; /* SRAM byte address of log data */
  3601. u32 ev, time, data; /* event log data */
  3602. if (num_events == 0)
  3603. return;
  3604. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3605. if (mode == 0)
  3606. event_size = 2 * sizeof(u32);
  3607. else
  3608. event_size = 3 * sizeof(u32);
  3609. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  3610. /* "time" is actually "data" for mode 0 (no timestamp).
  3611. * place event id # at far right for easier visual parsing. */
  3612. for (i = 0; i < num_events; i++) {
  3613. ev = iwl3945_read_targ_mem(priv, ptr);
  3614. ptr += sizeof(u32);
  3615. time = iwl3945_read_targ_mem(priv, ptr);
  3616. ptr += sizeof(u32);
  3617. if (mode == 0)
  3618. IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
  3619. else {
  3620. data = iwl3945_read_targ_mem(priv, ptr);
  3621. ptr += sizeof(u32);
  3622. IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
  3623. }
  3624. }
  3625. }
  3626. static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
  3627. {
  3628. int rc;
  3629. u32 base; /* SRAM byte address of event log header */
  3630. u32 capacity; /* event log capacity in # entries */
  3631. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  3632. u32 num_wraps; /* # times uCode wrapped to top of log */
  3633. u32 next_entry; /* index of next entry to be written by uCode */
  3634. u32 size; /* # entries that we'll print */
  3635. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3636. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3637. IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
  3638. return;
  3639. }
  3640. rc = iwl3945_grab_nic_access(priv);
  3641. if (rc) {
  3642. IWL_WARNING("Can not read from adapter at this time.\n");
  3643. return;
  3644. }
  3645. /* event log header */
  3646. capacity = iwl3945_read_targ_mem(priv, base);
  3647. mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
  3648. num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
  3649. next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
  3650. size = num_wraps ? capacity : next_entry;
  3651. /* bail out if nothing in log */
  3652. if (size == 0) {
  3653. IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
  3654. iwl3945_release_nic_access(priv);
  3655. return;
  3656. }
  3657. IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
  3658. size, num_wraps);
  3659. /* if uCode has wrapped back to top of log, start at the oldest entry,
  3660. * i.e the next one that uCode would fill. */
  3661. if (num_wraps)
  3662. iwl3945_print_event_log(priv, next_entry,
  3663. capacity - next_entry, mode);
  3664. /* (then/else) start at top of log */
  3665. iwl3945_print_event_log(priv, 0, next_entry, mode);
  3666. iwl3945_release_nic_access(priv);
  3667. }
  3668. /**
  3669. * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
  3670. */
  3671. static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
  3672. {
  3673. /* Set the FW error flag -- cleared on iwl3945_down */
  3674. set_bit(STATUS_FW_ERROR, &priv->status);
  3675. /* Cancel currently queued command. */
  3676. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3677. #ifdef CONFIG_IWL3945_DEBUG
  3678. if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
  3679. iwl3945_dump_nic_error_log(priv);
  3680. iwl3945_dump_nic_event_log(priv);
  3681. iwl3945_print_rx_config_cmd(&priv->staging_rxon);
  3682. }
  3683. #endif
  3684. wake_up_interruptible(&priv->wait_command_queue);
  3685. /* Keep the restart process from trying to send host
  3686. * commands by clearing the INIT status bit */
  3687. clear_bit(STATUS_READY, &priv->status);
  3688. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3689. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  3690. "Restarting adapter due to uCode error.\n");
  3691. if (iwl3945_is_associated(priv)) {
  3692. memcpy(&priv->recovery_rxon, &priv->active_rxon,
  3693. sizeof(priv->recovery_rxon));
  3694. priv->error_recovering = 1;
  3695. }
  3696. queue_work(priv->workqueue, &priv->restart);
  3697. }
  3698. }
  3699. static void iwl3945_error_recovery(struct iwl3945_priv *priv)
  3700. {
  3701. unsigned long flags;
  3702. memcpy(&priv->staging_rxon, &priv->recovery_rxon,
  3703. sizeof(priv->staging_rxon));
  3704. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  3705. iwl3945_commit_rxon(priv);
  3706. iwl3945_add_station(priv, priv->bssid, 1, 0);
  3707. spin_lock_irqsave(&priv->lock, flags);
  3708. priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
  3709. priv->error_recovering = 0;
  3710. spin_unlock_irqrestore(&priv->lock, flags);
  3711. }
  3712. static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
  3713. {
  3714. u32 inta, handled = 0;
  3715. u32 inta_fh;
  3716. unsigned long flags;
  3717. #ifdef CONFIG_IWL3945_DEBUG
  3718. u32 inta_mask;
  3719. #endif
  3720. spin_lock_irqsave(&priv->lock, flags);
  3721. /* Ack/clear/reset pending uCode interrupts.
  3722. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  3723. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  3724. inta = iwl3945_read32(priv, CSR_INT);
  3725. iwl3945_write32(priv, CSR_INT, inta);
  3726. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  3727. * Any new interrupts that happen after this, either while we're
  3728. * in this tasklet, or later, will show up in next ISR/tasklet. */
  3729. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3730. iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  3731. #ifdef CONFIG_IWL3945_DEBUG
  3732. if (iwl3945_debug_level & IWL_DL_ISR) {
  3733. /* just for debug */
  3734. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3735. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3736. inta, inta_mask, inta_fh);
  3737. }
  3738. #endif
  3739. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  3740. * atomic, make sure that inta covers all the interrupts that
  3741. * we've discovered, even if FH interrupt came in just after
  3742. * reading CSR_INT. */
  3743. if (inta_fh & CSR39_FH_INT_RX_MASK)
  3744. inta |= CSR_INT_BIT_FH_RX;
  3745. if (inta_fh & CSR39_FH_INT_TX_MASK)
  3746. inta |= CSR_INT_BIT_FH_TX;
  3747. /* Now service all interrupt bits discovered above. */
  3748. if (inta & CSR_INT_BIT_HW_ERR) {
  3749. IWL_ERROR("Microcode HW error detected. Restarting.\n");
  3750. /* Tell the device to stop sending interrupts */
  3751. iwl3945_disable_interrupts(priv);
  3752. iwl3945_irq_handle_error(priv);
  3753. handled |= CSR_INT_BIT_HW_ERR;
  3754. spin_unlock_irqrestore(&priv->lock, flags);
  3755. return;
  3756. }
  3757. #ifdef CONFIG_IWL3945_DEBUG
  3758. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  3759. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  3760. if (inta & CSR_INT_BIT_SCD)
  3761. IWL_DEBUG_ISR("Scheduler finished to transmit "
  3762. "the frame/frames.\n");
  3763. /* Alive notification via Rx interrupt will do the real work */
  3764. if (inta & CSR_INT_BIT_ALIVE)
  3765. IWL_DEBUG_ISR("Alive interrupt\n");
  3766. }
  3767. #endif
  3768. /* Safely ignore these bits for debug checks below */
  3769. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  3770. /* HW RF KILL switch toggled (4965 only) */
  3771. if (inta & CSR_INT_BIT_RF_KILL) {
  3772. int hw_rf_kill = 0;
  3773. if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
  3774. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  3775. hw_rf_kill = 1;
  3776. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
  3777. "RF_KILL bit toggled to %s.\n",
  3778. hw_rf_kill ? "disable radio":"enable radio");
  3779. /* Queue restart only if RF_KILL switch was set to "kill"
  3780. * when we loaded driver, and is now set to "enable".
  3781. * After we're Alive, RF_KILL gets handled by
  3782. * iwl3945_rx_card_state_notif() */
  3783. if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
  3784. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3785. queue_work(priv->workqueue, &priv->restart);
  3786. }
  3787. handled |= CSR_INT_BIT_RF_KILL;
  3788. }
  3789. /* Chip got too hot and stopped itself (4965 only) */
  3790. if (inta & CSR_INT_BIT_CT_KILL) {
  3791. IWL_ERROR("Microcode CT kill error detected.\n");
  3792. handled |= CSR_INT_BIT_CT_KILL;
  3793. }
  3794. /* Error detected by uCode */
  3795. if (inta & CSR_INT_BIT_SW_ERR) {
  3796. IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
  3797. inta);
  3798. iwl3945_irq_handle_error(priv);
  3799. handled |= CSR_INT_BIT_SW_ERR;
  3800. }
  3801. /* uCode wakes up after power-down sleep */
  3802. if (inta & CSR_INT_BIT_WAKEUP) {
  3803. IWL_DEBUG_ISR("Wakeup interrupt\n");
  3804. iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
  3805. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
  3806. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
  3807. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
  3808. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
  3809. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
  3810. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
  3811. handled |= CSR_INT_BIT_WAKEUP;
  3812. }
  3813. /* All uCode command responses, including Tx command responses,
  3814. * Rx "responses" (frame-received notification), and other
  3815. * notifications from uCode come through here*/
  3816. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  3817. iwl3945_rx_handle(priv);
  3818. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  3819. }
  3820. if (inta & CSR_INT_BIT_FH_TX) {
  3821. IWL_DEBUG_ISR("Tx interrupt\n");
  3822. iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  3823. if (!iwl3945_grab_nic_access(priv)) {
  3824. iwl3945_write_direct32(priv,
  3825. FH_TCSR_CREDIT
  3826. (ALM_FH_SRVC_CHNL), 0x0);
  3827. iwl3945_release_nic_access(priv);
  3828. }
  3829. handled |= CSR_INT_BIT_FH_TX;
  3830. }
  3831. if (inta & ~handled)
  3832. IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
  3833. if (inta & ~CSR_INI_SET_MASK) {
  3834. IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
  3835. inta & ~CSR_INI_SET_MASK);
  3836. IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
  3837. }
  3838. /* Re-enable all interrupts */
  3839. /* only Re-enable if disabled by irq */
  3840. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3841. iwl3945_enable_interrupts(priv);
  3842. #ifdef CONFIG_IWL3945_DEBUG
  3843. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  3844. inta = iwl3945_read32(priv, CSR_INT);
  3845. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3846. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3847. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  3848. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  3849. }
  3850. #endif
  3851. spin_unlock_irqrestore(&priv->lock, flags);
  3852. }
  3853. static irqreturn_t iwl3945_isr(int irq, void *data)
  3854. {
  3855. struct iwl3945_priv *priv = data;
  3856. u32 inta, inta_mask;
  3857. u32 inta_fh;
  3858. if (!priv)
  3859. return IRQ_NONE;
  3860. spin_lock(&priv->lock);
  3861. /* Disable (but don't clear!) interrupts here to avoid
  3862. * back-to-back ISRs and sporadic interrupts from our NIC.
  3863. * If we have something to service, the tasklet will re-enable ints.
  3864. * If we *don't* have something, we'll re-enable before leaving here. */
  3865. inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
  3866. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3867. /* Discover which interrupts are active/pending */
  3868. inta = iwl3945_read32(priv, CSR_INT);
  3869. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3870. /* Ignore interrupt if there's nothing in NIC to service.
  3871. * This may be due to IRQ shared with another device,
  3872. * or due to sporadic interrupts thrown from our NIC. */
  3873. if (!inta && !inta_fh) {
  3874. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  3875. goto none;
  3876. }
  3877. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  3878. /* Hardware disappeared */
  3879. IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
  3880. goto unplugged;
  3881. }
  3882. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3883. inta, inta_mask, inta_fh);
  3884. inta &= ~CSR_INT_BIT_SCD;
  3885. /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
  3886. if (likely(inta || inta_fh))
  3887. tasklet_schedule(&priv->irq_tasklet);
  3888. unplugged:
  3889. spin_unlock(&priv->lock);
  3890. return IRQ_HANDLED;
  3891. none:
  3892. /* re-enable interrupts here since we don't have anything to service. */
  3893. /* only Re-enable if disabled by irq */
  3894. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3895. iwl3945_enable_interrupts(priv);
  3896. spin_unlock(&priv->lock);
  3897. return IRQ_NONE;
  3898. }
  3899. /************************** EEPROM BANDS ****************************
  3900. *
  3901. * The iwl3945_eeprom_band definitions below provide the mapping from the
  3902. * EEPROM contents to the specific channel number supported for each
  3903. * band.
  3904. *
  3905. * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
  3906. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  3907. * The specific geography and calibration information for that channel
  3908. * is contained in the eeprom map itself.
  3909. *
  3910. * During init, we copy the eeprom information and channel map
  3911. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  3912. *
  3913. * channel_map_24/52 provides the index in the channel_info array for a
  3914. * given channel. We have to have two separate maps as there is channel
  3915. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  3916. * band_2
  3917. *
  3918. * A value of 0xff stored in the channel_map indicates that the channel
  3919. * is not supported by the hardware at all.
  3920. *
  3921. * A value of 0xfe in the channel_map indicates that the channel is not
  3922. * valid for Tx with the current hardware. This means that
  3923. * while the system can tune and receive on a given channel, it may not
  3924. * be able to associate or transmit any frames on that
  3925. * channel. There is no corresponding channel information for that
  3926. * entry.
  3927. *
  3928. *********************************************************************/
  3929. /* 2.4 GHz */
  3930. static const u8 iwl3945_eeprom_band_1[14] = {
  3931. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  3932. };
  3933. /* 5.2 GHz bands */
  3934. static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
  3935. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  3936. };
  3937. static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
  3938. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  3939. };
  3940. static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
  3941. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  3942. };
  3943. static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
  3944. 145, 149, 153, 157, 161, 165
  3945. };
  3946. static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
  3947. int *eeprom_ch_count,
  3948. const struct iwl3945_eeprom_channel
  3949. **eeprom_ch_info,
  3950. const u8 **eeprom_ch_index)
  3951. {
  3952. switch (band) {
  3953. case 1: /* 2.4GHz band */
  3954. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
  3955. *eeprom_ch_info = priv->eeprom.band_1_channels;
  3956. *eeprom_ch_index = iwl3945_eeprom_band_1;
  3957. break;
  3958. case 2: /* 4.9GHz band */
  3959. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
  3960. *eeprom_ch_info = priv->eeprom.band_2_channels;
  3961. *eeprom_ch_index = iwl3945_eeprom_band_2;
  3962. break;
  3963. case 3: /* 5.2GHz band */
  3964. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
  3965. *eeprom_ch_info = priv->eeprom.band_3_channels;
  3966. *eeprom_ch_index = iwl3945_eeprom_band_3;
  3967. break;
  3968. case 4: /* 5.5GHz band */
  3969. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
  3970. *eeprom_ch_info = priv->eeprom.band_4_channels;
  3971. *eeprom_ch_index = iwl3945_eeprom_band_4;
  3972. break;
  3973. case 5: /* 5.7GHz band */
  3974. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
  3975. *eeprom_ch_info = priv->eeprom.band_5_channels;
  3976. *eeprom_ch_index = iwl3945_eeprom_band_5;
  3977. break;
  3978. default:
  3979. BUG();
  3980. return;
  3981. }
  3982. }
  3983. /**
  3984. * iwl3945_get_channel_info - Find driver's private channel info
  3985. *
  3986. * Based on band and channel number.
  3987. */
  3988. const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
  3989. enum ieee80211_band band, u16 channel)
  3990. {
  3991. int i;
  3992. switch (band) {
  3993. case IEEE80211_BAND_5GHZ:
  3994. for (i = 14; i < priv->channel_count; i++) {
  3995. if (priv->channel_info[i].channel == channel)
  3996. return &priv->channel_info[i];
  3997. }
  3998. break;
  3999. case IEEE80211_BAND_2GHZ:
  4000. if (channel >= 1 && channel <= 14)
  4001. return &priv->channel_info[channel - 1];
  4002. break;
  4003. case IEEE80211_NUM_BANDS:
  4004. WARN_ON(1);
  4005. }
  4006. return NULL;
  4007. }
  4008. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  4009. ? # x " " : "")
  4010. /**
  4011. * iwl3945_init_channel_map - Set up driver's info for all possible channels
  4012. */
  4013. static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
  4014. {
  4015. int eeprom_ch_count = 0;
  4016. const u8 *eeprom_ch_index = NULL;
  4017. const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
  4018. int band, ch;
  4019. struct iwl3945_channel_info *ch_info;
  4020. if (priv->channel_count) {
  4021. IWL_DEBUG_INFO("Channel map already initialized.\n");
  4022. return 0;
  4023. }
  4024. if (priv->eeprom.version < 0x2f) {
  4025. IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
  4026. priv->eeprom.version);
  4027. return -EINVAL;
  4028. }
  4029. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  4030. priv->channel_count =
  4031. ARRAY_SIZE(iwl3945_eeprom_band_1) +
  4032. ARRAY_SIZE(iwl3945_eeprom_band_2) +
  4033. ARRAY_SIZE(iwl3945_eeprom_band_3) +
  4034. ARRAY_SIZE(iwl3945_eeprom_band_4) +
  4035. ARRAY_SIZE(iwl3945_eeprom_band_5);
  4036. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  4037. priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
  4038. priv->channel_count, GFP_KERNEL);
  4039. if (!priv->channel_info) {
  4040. IWL_ERROR("Could not allocate channel_info\n");
  4041. priv->channel_count = 0;
  4042. return -ENOMEM;
  4043. }
  4044. ch_info = priv->channel_info;
  4045. /* Loop through the 5 EEPROM bands adding them in order to the
  4046. * channel map we maintain (that contains additional information than
  4047. * what just in the EEPROM) */
  4048. for (band = 1; band <= 5; band++) {
  4049. iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
  4050. &eeprom_ch_info, &eeprom_ch_index);
  4051. /* Loop through each band adding each of the channels */
  4052. for (ch = 0; ch < eeprom_ch_count; ch++) {
  4053. ch_info->channel = eeprom_ch_index[ch];
  4054. ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
  4055. IEEE80211_BAND_5GHZ;
  4056. /* permanently store EEPROM's channel regulatory flags
  4057. * and max power in channel info database. */
  4058. ch_info->eeprom = eeprom_ch_info[ch];
  4059. /* Copy the run-time flags so they are there even on
  4060. * invalid channels */
  4061. ch_info->flags = eeprom_ch_info[ch].flags;
  4062. if (!(is_channel_valid(ch_info))) {
  4063. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  4064. "No traffic\n",
  4065. ch_info->channel,
  4066. ch_info->flags,
  4067. is_channel_a_band(ch_info) ?
  4068. "5.2" : "2.4");
  4069. ch_info++;
  4070. continue;
  4071. }
  4072. /* Initialize regulatory-based run-time data */
  4073. ch_info->max_power_avg = ch_info->curr_txpow =
  4074. eeprom_ch_info[ch].max_power_avg;
  4075. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  4076. ch_info->min_power = 0;
  4077. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  4078. " %ddBm): Ad-Hoc %ssupported\n",
  4079. ch_info->channel,
  4080. is_channel_a_band(ch_info) ?
  4081. "5.2" : "2.4",
  4082. CHECK_AND_PRINT(VALID),
  4083. CHECK_AND_PRINT(IBSS),
  4084. CHECK_AND_PRINT(ACTIVE),
  4085. CHECK_AND_PRINT(RADAR),
  4086. CHECK_AND_PRINT(WIDE),
  4087. CHECK_AND_PRINT(DFS),
  4088. eeprom_ch_info[ch].flags,
  4089. eeprom_ch_info[ch].max_power_avg,
  4090. ((eeprom_ch_info[ch].
  4091. flags & EEPROM_CHANNEL_IBSS)
  4092. && !(eeprom_ch_info[ch].
  4093. flags & EEPROM_CHANNEL_RADAR))
  4094. ? "" : "not ");
  4095. /* Set the user_txpower_limit to the highest power
  4096. * supported by any channel */
  4097. if (eeprom_ch_info[ch].max_power_avg >
  4098. priv->user_txpower_limit)
  4099. priv->user_txpower_limit =
  4100. eeprom_ch_info[ch].max_power_avg;
  4101. ch_info++;
  4102. }
  4103. }
  4104. /* Set up txpower settings in driver for all channels */
  4105. if (iwl3945_txpower_set_from_eeprom(priv))
  4106. return -EIO;
  4107. return 0;
  4108. }
  4109. /*
  4110. * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
  4111. */
  4112. static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
  4113. {
  4114. kfree(priv->channel_info);
  4115. priv->channel_count = 0;
  4116. }
  4117. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  4118. * sending probe req. This should be set long enough to hear probe responses
  4119. * from more than one AP. */
  4120. #define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */
  4121. #define IWL_ACTIVE_DWELL_TIME_52 (10)
  4122. /* For faster active scanning, scan will move to the next channel if fewer than
  4123. * PLCP_QUIET_THRESH packets are heard on this channel within
  4124. * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
  4125. * time if it's a quiet channel (nothing responded to our probe, and there's
  4126. * no other traffic).
  4127. * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
  4128. #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
  4129. #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */
  4130. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  4131. * Must be set longer than active dwell time.
  4132. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  4133. #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  4134. #define IWL_PASSIVE_DWELL_TIME_52 (10)
  4135. #define IWL_PASSIVE_DWELL_BASE (100)
  4136. #define IWL_CHANNEL_TUNE_TIME 5
  4137. static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
  4138. enum ieee80211_band band)
  4139. {
  4140. if (band == IEEE80211_BAND_5GHZ)
  4141. return IWL_ACTIVE_DWELL_TIME_52;
  4142. else
  4143. return IWL_ACTIVE_DWELL_TIME_24;
  4144. }
  4145. static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
  4146. enum ieee80211_band band)
  4147. {
  4148. u16 active = iwl3945_get_active_dwell_time(priv, band);
  4149. u16 passive = (band == IEEE80211_BAND_2GHZ) ?
  4150. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
  4151. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
  4152. if (iwl3945_is_associated(priv)) {
  4153. /* If we're associated, we clamp the maximum passive
  4154. * dwell time to be 98% of the beacon interval (minus
  4155. * 2 * channel tune time) */
  4156. passive = priv->beacon_int;
  4157. if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
  4158. passive = IWL_PASSIVE_DWELL_BASE;
  4159. passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
  4160. }
  4161. if (passive <= active)
  4162. passive = active + 1;
  4163. return passive;
  4164. }
  4165. static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
  4166. enum ieee80211_band band,
  4167. u8 is_active, u8 direct_mask,
  4168. struct iwl3945_scan_channel *scan_ch)
  4169. {
  4170. const struct ieee80211_channel *channels = NULL;
  4171. const struct ieee80211_supported_band *sband;
  4172. const struct iwl3945_channel_info *ch_info;
  4173. u16 passive_dwell = 0;
  4174. u16 active_dwell = 0;
  4175. int added, i;
  4176. sband = iwl3945_get_band(priv, band);
  4177. if (!sband)
  4178. return 0;
  4179. channels = sband->channels;
  4180. active_dwell = iwl3945_get_active_dwell_time(priv, band);
  4181. passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
  4182. for (i = 0, added = 0; i < sband->n_channels; i++) {
  4183. if (channels[i].flags & IEEE80211_CHAN_DISABLED)
  4184. continue;
  4185. scan_ch->channel = channels[i].hw_value;
  4186. ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
  4187. if (!is_channel_valid(ch_info)) {
  4188. IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
  4189. scan_ch->channel);
  4190. continue;
  4191. }
  4192. if (!is_active || is_channel_passive(ch_info) ||
  4193. (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
  4194. scan_ch->type = 0; /* passive */
  4195. else
  4196. scan_ch->type = 1; /* active */
  4197. if (scan_ch->type & 1)
  4198. scan_ch->type |= (direct_mask << 1);
  4199. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  4200. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  4201. /* Set txpower levels to defaults */
  4202. scan_ch->tpc.dsp_atten = 110;
  4203. /* scan_pwr_info->tpc.dsp_atten; */
  4204. /*scan_pwr_info->tpc.tx_gain; */
  4205. if (band == IEEE80211_BAND_5GHZ)
  4206. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  4207. else {
  4208. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  4209. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  4210. * power level:
  4211. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  4212. */
  4213. }
  4214. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  4215. scan_ch->channel,
  4216. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  4217. (scan_ch->type & 1) ?
  4218. active_dwell : passive_dwell);
  4219. scan_ch++;
  4220. added++;
  4221. }
  4222. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  4223. return added;
  4224. }
  4225. static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
  4226. struct ieee80211_rate *rates)
  4227. {
  4228. int i;
  4229. for (i = 0; i < IWL_RATE_COUNT; i++) {
  4230. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  4231. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  4232. rates[i].hw_value_short = i;
  4233. rates[i].flags = 0;
  4234. if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  4235. /*
  4236. * If CCK != 1M then set short preamble rate flag.
  4237. */
  4238. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  4239. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  4240. }
  4241. }
  4242. }
  4243. /**
  4244. * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
  4245. */
  4246. static int iwl3945_init_geos(struct iwl3945_priv *priv)
  4247. {
  4248. struct iwl3945_channel_info *ch;
  4249. struct ieee80211_supported_band *sband;
  4250. struct ieee80211_channel *channels;
  4251. struct ieee80211_channel *geo_ch;
  4252. struct ieee80211_rate *rates;
  4253. int i = 0;
  4254. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  4255. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  4256. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  4257. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4258. return 0;
  4259. }
  4260. channels = kzalloc(sizeof(struct ieee80211_channel) *
  4261. priv->channel_count, GFP_KERNEL);
  4262. if (!channels)
  4263. return -ENOMEM;
  4264. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
  4265. GFP_KERNEL);
  4266. if (!rates) {
  4267. kfree(channels);
  4268. return -ENOMEM;
  4269. }
  4270. /* 5.2GHz channels start after the 2.4GHz channels */
  4271. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4272. sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
  4273. /* just OFDM */
  4274. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  4275. sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
  4276. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4277. sband->channels = channels;
  4278. /* OFDM & CCK */
  4279. sband->bitrates = rates;
  4280. sband->n_bitrates = IWL_RATE_COUNT;
  4281. priv->ieee_channels = channels;
  4282. priv->ieee_rates = rates;
  4283. iwl3945_init_hw_rates(priv, rates);
  4284. for (i = 0; i < priv->channel_count; i++) {
  4285. ch = &priv->channel_info[i];
  4286. /* FIXME: might be removed if scan is OK*/
  4287. if (!is_channel_valid(ch))
  4288. continue;
  4289. if (is_channel_a_band(ch))
  4290. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4291. else
  4292. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4293. geo_ch = &sband->channels[sband->n_channels++];
  4294. geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
  4295. geo_ch->max_power = ch->max_power_avg;
  4296. geo_ch->max_antenna_gain = 0xff;
  4297. geo_ch->hw_value = ch->channel;
  4298. if (is_channel_valid(ch)) {
  4299. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  4300. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  4301. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  4302. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  4303. if (ch->flags & EEPROM_CHANNEL_RADAR)
  4304. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  4305. if (ch->max_power_avg > priv->max_channel_txpower_limit)
  4306. priv->max_channel_txpower_limit =
  4307. ch->max_power_avg;
  4308. } else {
  4309. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  4310. }
  4311. /* Save flags for reg domain usage */
  4312. geo_ch->orig_flags = geo_ch->flags;
  4313. IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
  4314. ch->channel, geo_ch->center_freq,
  4315. is_channel_a_band(ch) ? "5.2" : "2.4",
  4316. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  4317. "restricted" : "valid",
  4318. geo_ch->flags);
  4319. }
  4320. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  4321. priv->cfg->sku & IWL_SKU_A) {
  4322. printk(KERN_INFO DRV_NAME
  4323. ": Incorrectly detected BG card as ABG. Please send "
  4324. "your PCI ID 0x%04X:0x%04X to maintainer.\n",
  4325. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  4326. priv->cfg->sku &= ~IWL_SKU_A;
  4327. }
  4328. printk(KERN_INFO DRV_NAME
  4329. ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  4330. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  4331. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  4332. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  4333. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  4334. &priv->bands[IEEE80211_BAND_2GHZ];
  4335. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  4336. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  4337. &priv->bands[IEEE80211_BAND_5GHZ];
  4338. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4339. return 0;
  4340. }
  4341. /*
  4342. * iwl3945_free_geos - undo allocations in iwl3945_init_geos
  4343. */
  4344. static void iwl3945_free_geos(struct iwl3945_priv *priv)
  4345. {
  4346. kfree(priv->ieee_channels);
  4347. kfree(priv->ieee_rates);
  4348. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4349. }
  4350. /******************************************************************************
  4351. *
  4352. * uCode download functions
  4353. *
  4354. ******************************************************************************/
  4355. static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
  4356. {
  4357. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  4358. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  4359. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4360. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  4361. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4362. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4363. }
  4364. /**
  4365. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  4366. * looking at all data.
  4367. */
  4368. static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 * image, u32 len)
  4369. {
  4370. u32 val;
  4371. u32 save_len = len;
  4372. int rc = 0;
  4373. u32 errcnt;
  4374. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4375. rc = iwl3945_grab_nic_access(priv);
  4376. if (rc)
  4377. return rc;
  4378. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
  4379. errcnt = 0;
  4380. for (; len > 0; len -= sizeof(u32), image++) {
  4381. /* read data comes through single port, auto-incr addr */
  4382. /* NOTE: Use the debugless read so we don't flood kernel log
  4383. * if IWL_DL_IO is set */
  4384. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4385. if (val != le32_to_cpu(*image)) {
  4386. IWL_ERROR("uCode INST section is invalid at "
  4387. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4388. save_len - len, val, le32_to_cpu(*image));
  4389. rc = -EIO;
  4390. errcnt++;
  4391. if (errcnt >= 20)
  4392. break;
  4393. }
  4394. }
  4395. iwl3945_release_nic_access(priv);
  4396. if (!errcnt)
  4397. IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
  4398. return rc;
  4399. }
  4400. /**
  4401. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  4402. * using sample data 100 bytes apart. If these sample points are good,
  4403. * it's a pretty good bet that everything between them is good, too.
  4404. */
  4405. static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
  4406. {
  4407. u32 val;
  4408. int rc = 0;
  4409. u32 errcnt = 0;
  4410. u32 i;
  4411. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4412. rc = iwl3945_grab_nic_access(priv);
  4413. if (rc)
  4414. return rc;
  4415. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  4416. /* read data comes through single port, auto-incr addr */
  4417. /* NOTE: Use the debugless read so we don't flood kernel log
  4418. * if IWL_DL_IO is set */
  4419. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4420. i + RTC_INST_LOWER_BOUND);
  4421. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4422. if (val != le32_to_cpu(*image)) {
  4423. #if 0 /* Enable this if you want to see details */
  4424. IWL_ERROR("uCode INST section is invalid at "
  4425. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4426. i, val, *image);
  4427. #endif
  4428. rc = -EIO;
  4429. errcnt++;
  4430. if (errcnt >= 3)
  4431. break;
  4432. }
  4433. }
  4434. iwl3945_release_nic_access(priv);
  4435. return rc;
  4436. }
  4437. /**
  4438. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  4439. * and verify its contents
  4440. */
  4441. static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
  4442. {
  4443. __le32 *image;
  4444. u32 len;
  4445. int rc = 0;
  4446. /* Try bootstrap */
  4447. image = (__le32 *)priv->ucode_boot.v_addr;
  4448. len = priv->ucode_boot.len;
  4449. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4450. if (rc == 0) {
  4451. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  4452. return 0;
  4453. }
  4454. /* Try initialize */
  4455. image = (__le32 *)priv->ucode_init.v_addr;
  4456. len = priv->ucode_init.len;
  4457. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4458. if (rc == 0) {
  4459. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  4460. return 0;
  4461. }
  4462. /* Try runtime/protocol */
  4463. image = (__le32 *)priv->ucode_code.v_addr;
  4464. len = priv->ucode_code.len;
  4465. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4466. if (rc == 0) {
  4467. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  4468. return 0;
  4469. }
  4470. IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  4471. /* Since nothing seems to match, show first several data entries in
  4472. * instruction SRAM, so maybe visual inspection will give a clue.
  4473. * Selection of bootstrap image (vs. other images) is arbitrary. */
  4474. image = (__le32 *)priv->ucode_boot.v_addr;
  4475. len = priv->ucode_boot.len;
  4476. rc = iwl3945_verify_inst_full(priv, image, len);
  4477. return rc;
  4478. }
  4479. /* check contents of special bootstrap uCode SRAM */
  4480. static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
  4481. {
  4482. __le32 *image = priv->ucode_boot.v_addr;
  4483. u32 len = priv->ucode_boot.len;
  4484. u32 reg;
  4485. u32 val;
  4486. IWL_DEBUG_INFO("Begin verify bsm\n");
  4487. /* verify BSM SRAM contents */
  4488. val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
  4489. for (reg = BSM_SRAM_LOWER_BOUND;
  4490. reg < BSM_SRAM_LOWER_BOUND + len;
  4491. reg += sizeof(u32), image ++) {
  4492. val = iwl3945_read_prph(priv, reg);
  4493. if (val != le32_to_cpu(*image)) {
  4494. IWL_ERROR("BSM uCode verification failed at "
  4495. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  4496. BSM_SRAM_LOWER_BOUND,
  4497. reg - BSM_SRAM_LOWER_BOUND, len,
  4498. val, le32_to_cpu(*image));
  4499. return -EIO;
  4500. }
  4501. }
  4502. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  4503. return 0;
  4504. }
  4505. /**
  4506. * iwl3945_load_bsm - Load bootstrap instructions
  4507. *
  4508. * BSM operation:
  4509. *
  4510. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  4511. * in special SRAM that does not power down during RFKILL. When powering back
  4512. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  4513. * the bootstrap program into the on-board processor, and starts it.
  4514. *
  4515. * The bootstrap program loads (via DMA) instructions and data for a new
  4516. * program from host DRAM locations indicated by the host driver in the
  4517. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  4518. * automatically.
  4519. *
  4520. * When initializing the NIC, the host driver points the BSM to the
  4521. * "initialize" uCode image. This uCode sets up some internal data, then
  4522. * notifies host via "initialize alive" that it is complete.
  4523. *
  4524. * The host then replaces the BSM_DRAM_* pointer values to point to the
  4525. * normal runtime uCode instructions and a backup uCode data cache buffer
  4526. * (filled initially with starting data values for the on-board processor),
  4527. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  4528. * which begins normal operation.
  4529. *
  4530. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  4531. * the backup data cache in DRAM before SRAM is powered down.
  4532. *
  4533. * When powering back up, the BSM loads the bootstrap program. This reloads
  4534. * the runtime uCode instructions and the backup data cache into SRAM,
  4535. * and re-launches the runtime uCode from where it left off.
  4536. */
  4537. static int iwl3945_load_bsm(struct iwl3945_priv *priv)
  4538. {
  4539. __le32 *image = priv->ucode_boot.v_addr;
  4540. u32 len = priv->ucode_boot.len;
  4541. dma_addr_t pinst;
  4542. dma_addr_t pdata;
  4543. u32 inst_len;
  4544. u32 data_len;
  4545. int rc;
  4546. int i;
  4547. u32 done;
  4548. u32 reg_offset;
  4549. IWL_DEBUG_INFO("Begin load bsm\n");
  4550. /* make sure bootstrap program is no larger than BSM's SRAM size */
  4551. if (len > IWL_MAX_BSM_SIZE)
  4552. return -EINVAL;
  4553. /* Tell bootstrap uCode where to find the "Initialize" uCode
  4554. * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
  4555. * NOTE: iwl3945_initialize_alive_start() will replace these values,
  4556. * after the "initialize" uCode has run, to point to
  4557. * runtime/protocol instructions and backup data cache. */
  4558. pinst = priv->ucode_init.p_addr;
  4559. pdata = priv->ucode_init_data.p_addr;
  4560. inst_len = priv->ucode_init.len;
  4561. data_len = priv->ucode_init_data.len;
  4562. rc = iwl3945_grab_nic_access(priv);
  4563. if (rc)
  4564. return rc;
  4565. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4566. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4567. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  4568. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  4569. /* Fill BSM memory with bootstrap instructions */
  4570. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  4571. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  4572. reg_offset += sizeof(u32), image++)
  4573. _iwl3945_write_prph(priv, reg_offset,
  4574. le32_to_cpu(*image));
  4575. rc = iwl3945_verify_bsm(priv);
  4576. if (rc) {
  4577. iwl3945_release_nic_access(priv);
  4578. return rc;
  4579. }
  4580. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  4581. iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  4582. iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
  4583. RTC_INST_LOWER_BOUND);
  4584. iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  4585. /* Load bootstrap code into instruction SRAM now,
  4586. * to prepare to load "initialize" uCode */
  4587. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4588. BSM_WR_CTRL_REG_BIT_START);
  4589. /* Wait for load of bootstrap uCode to finish */
  4590. for (i = 0; i < 100; i++) {
  4591. done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
  4592. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  4593. break;
  4594. udelay(10);
  4595. }
  4596. if (i < 100)
  4597. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  4598. else {
  4599. IWL_ERROR("BSM write did not complete!\n");
  4600. return -EIO;
  4601. }
  4602. /* Enable future boot loads whenever power management unit triggers it
  4603. * (e.g. when powering back up after power-save shutdown) */
  4604. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4605. BSM_WR_CTRL_REG_BIT_START_EN);
  4606. iwl3945_release_nic_access(priv);
  4607. return 0;
  4608. }
  4609. static void iwl3945_nic_start(struct iwl3945_priv *priv)
  4610. {
  4611. /* Remove all resets to allow NIC to operate */
  4612. iwl3945_write32(priv, CSR_RESET, 0);
  4613. }
  4614. /**
  4615. * iwl3945_read_ucode - Read uCode images from disk file.
  4616. *
  4617. * Copy into buffers for card to fetch via bus-mastering
  4618. */
  4619. static int iwl3945_read_ucode(struct iwl3945_priv *priv)
  4620. {
  4621. struct iwl3945_ucode *ucode;
  4622. int ret = 0;
  4623. const struct firmware *ucode_raw;
  4624. /* firmware file name contains uCode/driver compatibility version */
  4625. const char *name = priv->cfg->fw_name;
  4626. u8 *src;
  4627. size_t len;
  4628. u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
  4629. /* Ask kernel firmware_class module to get the boot firmware off disk.
  4630. * request_firmware() is synchronous, file is in memory on return. */
  4631. ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
  4632. if (ret < 0) {
  4633. IWL_ERROR("%s firmware file req failed: Reason %d\n",
  4634. name, ret);
  4635. goto error;
  4636. }
  4637. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  4638. name, ucode_raw->size);
  4639. /* Make sure that we got at least our header! */
  4640. if (ucode_raw->size < sizeof(*ucode)) {
  4641. IWL_ERROR("File size way too small!\n");
  4642. ret = -EINVAL;
  4643. goto err_release;
  4644. }
  4645. /* Data from ucode file: header followed by uCode images */
  4646. ucode = (void *)ucode_raw->data;
  4647. ver = le32_to_cpu(ucode->ver);
  4648. inst_size = le32_to_cpu(ucode->inst_size);
  4649. data_size = le32_to_cpu(ucode->data_size);
  4650. init_size = le32_to_cpu(ucode->init_size);
  4651. init_data_size = le32_to_cpu(ucode->init_data_size);
  4652. boot_size = le32_to_cpu(ucode->boot_size);
  4653. IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
  4654. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
  4655. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
  4656. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
  4657. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
  4658. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
  4659. /* Verify size of file vs. image size info in file's header */
  4660. if (ucode_raw->size < sizeof(*ucode) +
  4661. inst_size + data_size + init_size +
  4662. init_data_size + boot_size) {
  4663. IWL_DEBUG_INFO("uCode file size %d too small\n",
  4664. (int)ucode_raw->size);
  4665. ret = -EINVAL;
  4666. goto err_release;
  4667. }
  4668. /* Verify that uCode images will fit in card's SRAM */
  4669. if (inst_size > IWL_MAX_INST_SIZE) {
  4670. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  4671. inst_size);
  4672. ret = -EINVAL;
  4673. goto err_release;
  4674. }
  4675. if (data_size > IWL_MAX_DATA_SIZE) {
  4676. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  4677. data_size);
  4678. ret = -EINVAL;
  4679. goto err_release;
  4680. }
  4681. if (init_size > IWL_MAX_INST_SIZE) {
  4682. IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
  4683. init_size);
  4684. ret = -EINVAL;
  4685. goto err_release;
  4686. }
  4687. if (init_data_size > IWL_MAX_DATA_SIZE) {
  4688. IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
  4689. init_data_size);
  4690. ret = -EINVAL;
  4691. goto err_release;
  4692. }
  4693. if (boot_size > IWL_MAX_BSM_SIZE) {
  4694. IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
  4695. boot_size);
  4696. ret = -EINVAL;
  4697. goto err_release;
  4698. }
  4699. /* Allocate ucode buffers for card's bus-master loading ... */
  4700. /* Runtime instructions and 2 copies of data:
  4701. * 1) unmodified from disk
  4702. * 2) backup cache for save/restore during power-downs */
  4703. priv->ucode_code.len = inst_size;
  4704. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  4705. priv->ucode_data.len = data_size;
  4706. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  4707. priv->ucode_data_backup.len = data_size;
  4708. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4709. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  4710. !priv->ucode_data_backup.v_addr)
  4711. goto err_pci_alloc;
  4712. /* Initialization instructions and data */
  4713. if (init_size && init_data_size) {
  4714. priv->ucode_init.len = init_size;
  4715. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  4716. priv->ucode_init_data.len = init_data_size;
  4717. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4718. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  4719. goto err_pci_alloc;
  4720. }
  4721. /* Bootstrap (instructions only, no data) */
  4722. if (boot_size) {
  4723. priv->ucode_boot.len = boot_size;
  4724. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4725. if (!priv->ucode_boot.v_addr)
  4726. goto err_pci_alloc;
  4727. }
  4728. /* Copy images into buffers for card's bus-master reads ... */
  4729. /* Runtime instructions (first block of data in file) */
  4730. src = &ucode->data[0];
  4731. len = priv->ucode_code.len;
  4732. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  4733. memcpy(priv->ucode_code.v_addr, src, len);
  4734. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  4735. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  4736. /* Runtime data (2nd block)
  4737. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  4738. src = &ucode->data[inst_size];
  4739. len = priv->ucode_data.len;
  4740. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  4741. memcpy(priv->ucode_data.v_addr, src, len);
  4742. memcpy(priv->ucode_data_backup.v_addr, src, len);
  4743. /* Initialization instructions (3rd block) */
  4744. if (init_size) {
  4745. src = &ucode->data[inst_size + data_size];
  4746. len = priv->ucode_init.len;
  4747. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  4748. len);
  4749. memcpy(priv->ucode_init.v_addr, src, len);
  4750. }
  4751. /* Initialization data (4th block) */
  4752. if (init_data_size) {
  4753. src = &ucode->data[inst_size + data_size + init_size];
  4754. len = priv->ucode_init_data.len;
  4755. IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
  4756. (int)len);
  4757. memcpy(priv->ucode_init_data.v_addr, src, len);
  4758. }
  4759. /* Bootstrap instructions (5th block) */
  4760. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  4761. len = priv->ucode_boot.len;
  4762. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
  4763. (int)len);
  4764. memcpy(priv->ucode_boot.v_addr, src, len);
  4765. /* We have our copies now, allow OS release its copies */
  4766. release_firmware(ucode_raw);
  4767. return 0;
  4768. err_pci_alloc:
  4769. IWL_ERROR("failed to allocate pci memory\n");
  4770. ret = -ENOMEM;
  4771. iwl3945_dealloc_ucode_pci(priv);
  4772. err_release:
  4773. release_firmware(ucode_raw);
  4774. error:
  4775. return ret;
  4776. }
  4777. /**
  4778. * iwl3945_set_ucode_ptrs - Set uCode address location
  4779. *
  4780. * Tell initialization uCode where to find runtime uCode.
  4781. *
  4782. * BSM registers initially contain pointers to initialization uCode.
  4783. * We need to replace them to load runtime uCode inst and data,
  4784. * and to save runtime data when powering down.
  4785. */
  4786. static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
  4787. {
  4788. dma_addr_t pinst;
  4789. dma_addr_t pdata;
  4790. int rc = 0;
  4791. unsigned long flags;
  4792. /* bits 31:0 for 3945 */
  4793. pinst = priv->ucode_code.p_addr;
  4794. pdata = priv->ucode_data_backup.p_addr;
  4795. spin_lock_irqsave(&priv->lock, flags);
  4796. rc = iwl3945_grab_nic_access(priv);
  4797. if (rc) {
  4798. spin_unlock_irqrestore(&priv->lock, flags);
  4799. return rc;
  4800. }
  4801. /* Tell bootstrap uCode where to find image to load */
  4802. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4803. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4804. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  4805. priv->ucode_data.len);
  4806. /* Inst bytecount must be last to set up, bit 31 signals uCode
  4807. * that all new ptr/size info is in place */
  4808. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  4809. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  4810. iwl3945_release_nic_access(priv);
  4811. spin_unlock_irqrestore(&priv->lock, flags);
  4812. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  4813. return rc;
  4814. }
  4815. /**
  4816. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  4817. *
  4818. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  4819. *
  4820. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  4821. */
  4822. static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
  4823. {
  4824. /* Check alive response for "valid" sign from uCode */
  4825. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  4826. /* We had an error bringing up the hardware, so take it
  4827. * all the way back down so we can try again */
  4828. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  4829. goto restart;
  4830. }
  4831. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  4832. * This is a paranoid check, because we would not have gotten the
  4833. * "initialize" alive if code weren't properly loaded. */
  4834. if (iwl3945_verify_ucode(priv)) {
  4835. /* Runtime instruction load was bad;
  4836. * take it all the way back down so we can try again */
  4837. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  4838. goto restart;
  4839. }
  4840. /* Send pointers to protocol/runtime uCode image ... init code will
  4841. * load and launch runtime uCode, which will send us another "Alive"
  4842. * notification. */
  4843. IWL_DEBUG_INFO("Initialization Alive received.\n");
  4844. if (iwl3945_set_ucode_ptrs(priv)) {
  4845. /* Runtime instruction load won't happen;
  4846. * take it all the way back down so we can try again */
  4847. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  4848. goto restart;
  4849. }
  4850. return;
  4851. restart:
  4852. queue_work(priv->workqueue, &priv->restart);
  4853. }
  4854. /**
  4855. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  4856. * from protocol/runtime uCode (initialization uCode's
  4857. * Alive gets handled by iwl3945_init_alive_start()).
  4858. */
  4859. static void iwl3945_alive_start(struct iwl3945_priv *priv)
  4860. {
  4861. int rc = 0;
  4862. int thermal_spin = 0;
  4863. u32 rfkill;
  4864. IWL_DEBUG_INFO("Runtime Alive received.\n");
  4865. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  4866. /* We had an error bringing up the hardware, so take it
  4867. * all the way back down so we can try again */
  4868. IWL_DEBUG_INFO("Alive failed.\n");
  4869. goto restart;
  4870. }
  4871. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  4872. * This is a paranoid check, because we would not have gotten the
  4873. * "runtime" alive if code weren't properly loaded. */
  4874. if (iwl3945_verify_ucode(priv)) {
  4875. /* Runtime instruction load was bad;
  4876. * take it all the way back down so we can try again */
  4877. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  4878. goto restart;
  4879. }
  4880. iwl3945_clear_stations_table(priv);
  4881. rc = iwl3945_grab_nic_access(priv);
  4882. if (rc) {
  4883. IWL_WARNING("Can not read rfkill status from adapter\n");
  4884. return;
  4885. }
  4886. rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
  4887. IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
  4888. iwl3945_release_nic_access(priv);
  4889. if (rfkill & 0x1) {
  4890. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4891. /* if rfkill is not on, then wait for thermal
  4892. * sensor in adapter to kick in */
  4893. while (iwl3945_hw_get_temperature(priv) == 0) {
  4894. thermal_spin++;
  4895. udelay(10);
  4896. }
  4897. if (thermal_spin)
  4898. IWL_DEBUG_INFO("Thermal calibration took %dus\n",
  4899. thermal_spin * 10);
  4900. } else
  4901. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4902. /* After the ALIVE response, we can send commands to 3945 uCode */
  4903. set_bit(STATUS_ALIVE, &priv->status);
  4904. /* Clear out the uCode error bit if it is set */
  4905. clear_bit(STATUS_FW_ERROR, &priv->status);
  4906. if (iwl3945_is_rfkill(priv))
  4907. return;
  4908. ieee80211_wake_queues(priv->hw);
  4909. priv->active_rate = priv->rates_mask;
  4910. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  4911. iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  4912. if (iwl3945_is_associated(priv)) {
  4913. struct iwl3945_rxon_cmd *active_rxon =
  4914. (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
  4915. memcpy(&priv->staging_rxon, &priv->active_rxon,
  4916. sizeof(priv->staging_rxon));
  4917. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4918. } else {
  4919. /* Initialize our rx_config data */
  4920. iwl3945_connection_init_rx_config(priv);
  4921. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  4922. }
  4923. /* Configure Bluetooth device coexistence support */
  4924. iwl3945_send_bt_config(priv);
  4925. /* Configure the adapter for unassociated operation */
  4926. iwl3945_commit_rxon(priv);
  4927. iwl3945_reg_txpower_periodic(priv);
  4928. iwl3945_led_register(priv);
  4929. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  4930. set_bit(STATUS_READY, &priv->status);
  4931. wake_up_interruptible(&priv->wait_command_queue);
  4932. if (priv->error_recovering)
  4933. iwl3945_error_recovery(priv);
  4934. ieee80211_notify_mac(priv->hw, IEEE80211_NOTIFY_RE_ASSOC);
  4935. return;
  4936. restart:
  4937. queue_work(priv->workqueue, &priv->restart);
  4938. }
  4939. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
  4940. static void __iwl3945_down(struct iwl3945_priv *priv)
  4941. {
  4942. unsigned long flags;
  4943. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  4944. struct ieee80211_conf *conf = NULL;
  4945. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  4946. conf = ieee80211_get_hw_conf(priv->hw);
  4947. if (!exit_pending)
  4948. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4949. iwl3945_led_unregister(priv);
  4950. iwl3945_clear_stations_table(priv);
  4951. /* Unblock any waiting calls */
  4952. wake_up_interruptible_all(&priv->wait_command_queue);
  4953. /* Wipe out the EXIT_PENDING status bit if we are not actually
  4954. * exiting the module */
  4955. if (!exit_pending)
  4956. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4957. /* stop and reset the on-board processor */
  4958. iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  4959. /* tell the device to stop sending interrupts */
  4960. spin_lock_irqsave(&priv->lock, flags);
  4961. iwl3945_disable_interrupts(priv);
  4962. spin_unlock_irqrestore(&priv->lock, flags);
  4963. iwl_synchronize_irq(priv);
  4964. if (priv->mac80211_registered)
  4965. ieee80211_stop_queues(priv->hw);
  4966. /* If we have not previously called iwl3945_init() then
  4967. * clear all bits but the RF Kill and SUSPEND bits and return */
  4968. if (!iwl3945_is_init(priv)) {
  4969. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4970. STATUS_RF_KILL_HW |
  4971. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4972. STATUS_RF_KILL_SW |
  4973. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4974. STATUS_GEO_CONFIGURED |
  4975. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4976. STATUS_IN_SUSPEND |
  4977. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4978. STATUS_EXIT_PENDING;
  4979. goto exit;
  4980. }
  4981. /* ...otherwise clear out all the status bits but the RF Kill and
  4982. * SUSPEND bits and continue taking the NIC down. */
  4983. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4984. STATUS_RF_KILL_HW |
  4985. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4986. STATUS_RF_KILL_SW |
  4987. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4988. STATUS_GEO_CONFIGURED |
  4989. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4990. STATUS_IN_SUSPEND |
  4991. test_bit(STATUS_FW_ERROR, &priv->status) <<
  4992. STATUS_FW_ERROR |
  4993. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4994. STATUS_EXIT_PENDING;
  4995. spin_lock_irqsave(&priv->lock, flags);
  4996. iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  4997. spin_unlock_irqrestore(&priv->lock, flags);
  4998. iwl3945_hw_txq_ctx_stop(priv);
  4999. iwl3945_hw_rxq_stop(priv);
  5000. spin_lock_irqsave(&priv->lock, flags);
  5001. if (!iwl3945_grab_nic_access(priv)) {
  5002. iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
  5003. APMG_CLK_VAL_DMA_CLK_RQT);
  5004. iwl3945_release_nic_access(priv);
  5005. }
  5006. spin_unlock_irqrestore(&priv->lock, flags);
  5007. udelay(5);
  5008. iwl3945_hw_nic_stop_master(priv);
  5009. iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  5010. iwl3945_hw_nic_reset(priv);
  5011. exit:
  5012. memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
  5013. if (priv->ibss_beacon)
  5014. dev_kfree_skb(priv->ibss_beacon);
  5015. priv->ibss_beacon = NULL;
  5016. /* clear out any free frames */
  5017. iwl3945_clear_free_frames(priv);
  5018. }
  5019. static void iwl3945_down(struct iwl3945_priv *priv)
  5020. {
  5021. mutex_lock(&priv->mutex);
  5022. __iwl3945_down(priv);
  5023. mutex_unlock(&priv->mutex);
  5024. iwl3945_cancel_deferred_work(priv);
  5025. }
  5026. #define MAX_HW_RESTARTS 5
  5027. static int __iwl3945_up(struct iwl3945_priv *priv)
  5028. {
  5029. int rc, i;
  5030. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5031. IWL_WARNING("Exit pending; will not bring the NIC up\n");
  5032. return -EIO;
  5033. }
  5034. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  5035. IWL_WARNING("Radio disabled by SW RF kill (module "
  5036. "parameter)\n");
  5037. return -ENODEV;
  5038. }
  5039. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  5040. IWL_ERROR("ucode not available for device bringup\n");
  5041. return -EIO;
  5042. }
  5043. /* If platform's RF_KILL switch is NOT set to KILL */
  5044. if (iwl3945_read32(priv, CSR_GP_CNTRL) &
  5045. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  5046. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  5047. else {
  5048. set_bit(STATUS_RF_KILL_HW, &priv->status);
  5049. if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
  5050. IWL_WARNING("Radio disabled by HW RF Kill switch\n");
  5051. return -ENODEV;
  5052. }
  5053. }
  5054. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  5055. rc = iwl3945_hw_nic_init(priv);
  5056. if (rc) {
  5057. IWL_ERROR("Unable to int nic\n");
  5058. return rc;
  5059. }
  5060. /* make sure rfkill handshake bits are cleared */
  5061. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5062. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  5063. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  5064. /* clear (again), then enable host interrupts */
  5065. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  5066. iwl3945_enable_interrupts(priv);
  5067. /* really make sure rfkill handshake bits are cleared */
  5068. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5069. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5070. /* Copy original ucode data image from disk into backup cache.
  5071. * This will be used to initialize the on-board processor's
  5072. * data SRAM for a clean start when the runtime program first loads. */
  5073. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  5074. priv->ucode_data.len);
  5075. /* We return success when we resume from suspend and rf_kill is on. */
  5076. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  5077. return 0;
  5078. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  5079. iwl3945_clear_stations_table(priv);
  5080. /* load bootstrap state machine,
  5081. * load bootstrap program into processor's memory,
  5082. * prepare to load the "initialize" uCode */
  5083. rc = iwl3945_load_bsm(priv);
  5084. if (rc) {
  5085. IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
  5086. continue;
  5087. }
  5088. /* start card; "initialize" will load runtime ucode */
  5089. iwl3945_nic_start(priv);
  5090. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  5091. return 0;
  5092. }
  5093. set_bit(STATUS_EXIT_PENDING, &priv->status);
  5094. __iwl3945_down(priv);
  5095. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  5096. /* tried to restart and config the device for as long as our
  5097. * patience could withstand */
  5098. IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
  5099. return -EIO;
  5100. }
  5101. /*****************************************************************************
  5102. *
  5103. * Workqueue callbacks
  5104. *
  5105. *****************************************************************************/
  5106. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  5107. {
  5108. struct iwl3945_priv *priv =
  5109. container_of(data, struct iwl3945_priv, init_alive_start.work);
  5110. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5111. return;
  5112. mutex_lock(&priv->mutex);
  5113. iwl3945_init_alive_start(priv);
  5114. mutex_unlock(&priv->mutex);
  5115. }
  5116. static void iwl3945_bg_alive_start(struct work_struct *data)
  5117. {
  5118. struct iwl3945_priv *priv =
  5119. container_of(data, struct iwl3945_priv, alive_start.work);
  5120. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5121. return;
  5122. mutex_lock(&priv->mutex);
  5123. iwl3945_alive_start(priv);
  5124. mutex_unlock(&priv->mutex);
  5125. }
  5126. static void iwl3945_bg_rf_kill(struct work_struct *work)
  5127. {
  5128. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
  5129. wake_up_interruptible(&priv->wait_command_queue);
  5130. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5131. return;
  5132. mutex_lock(&priv->mutex);
  5133. if (!iwl3945_is_rfkill(priv)) {
  5134. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
  5135. "HW and/or SW RF Kill no longer active, restarting "
  5136. "device\n");
  5137. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5138. queue_work(priv->workqueue, &priv->restart);
  5139. } else {
  5140. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  5141. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  5142. "disabled by SW switch\n");
  5143. else
  5144. IWL_WARNING("Radio Frequency Kill Switch is On:\n"
  5145. "Kill switch must be turned off for "
  5146. "wireless networking to work.\n");
  5147. }
  5148. mutex_unlock(&priv->mutex);
  5149. iwl3945_rfkill_set_hw_state(priv);
  5150. }
  5151. static void iwl3945_bg_set_monitor(struct work_struct *work)
  5152. {
  5153. struct iwl3945_priv *priv = container_of(work,
  5154. struct iwl3945_priv, set_monitor);
  5155. IWL_DEBUG(IWL_DL_STATE, "setting monitor mode\n");
  5156. mutex_lock(&priv->mutex);
  5157. if (!iwl3945_is_ready(priv))
  5158. IWL_DEBUG(IWL_DL_STATE, "leave - not ready\n");
  5159. else
  5160. if (iwl3945_set_mode(priv, IEEE80211_IF_TYPE_MNTR) != 0)
  5161. IWL_ERROR("iwl3945_set_mode() failed\n");
  5162. mutex_unlock(&priv->mutex);
  5163. }
  5164. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  5165. static void iwl3945_bg_scan_check(struct work_struct *data)
  5166. {
  5167. struct iwl3945_priv *priv =
  5168. container_of(data, struct iwl3945_priv, scan_check.work);
  5169. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5170. return;
  5171. mutex_lock(&priv->mutex);
  5172. if (test_bit(STATUS_SCANNING, &priv->status) ||
  5173. test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5174. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
  5175. "Scan completion watchdog resetting adapter (%dms)\n",
  5176. jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
  5177. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5178. iwl3945_send_scan_abort(priv);
  5179. }
  5180. mutex_unlock(&priv->mutex);
  5181. }
  5182. static void iwl3945_bg_request_scan(struct work_struct *data)
  5183. {
  5184. struct iwl3945_priv *priv =
  5185. container_of(data, struct iwl3945_priv, request_scan);
  5186. struct iwl3945_host_cmd cmd = {
  5187. .id = REPLY_SCAN_CMD,
  5188. .len = sizeof(struct iwl3945_scan_cmd),
  5189. .meta.flags = CMD_SIZE_HUGE,
  5190. };
  5191. int rc = 0;
  5192. struct iwl3945_scan_cmd *scan;
  5193. struct ieee80211_conf *conf = NULL;
  5194. u8 direct_mask;
  5195. enum ieee80211_band band;
  5196. conf = ieee80211_get_hw_conf(priv->hw);
  5197. mutex_lock(&priv->mutex);
  5198. if (!iwl3945_is_ready(priv)) {
  5199. IWL_WARNING("request scan called when driver not ready.\n");
  5200. goto done;
  5201. }
  5202. /* Make sure the scan wasn't cancelled before this queued work
  5203. * was given the chance to run... */
  5204. if (!test_bit(STATUS_SCANNING, &priv->status))
  5205. goto done;
  5206. /* This should never be called or scheduled if there is currently
  5207. * a scan active in the hardware. */
  5208. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  5209. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  5210. "Ignoring second request.\n");
  5211. rc = -EIO;
  5212. goto done;
  5213. }
  5214. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5215. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  5216. goto done;
  5217. }
  5218. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5219. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  5220. goto done;
  5221. }
  5222. if (iwl3945_is_rfkill(priv)) {
  5223. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  5224. goto done;
  5225. }
  5226. if (!test_bit(STATUS_READY, &priv->status)) {
  5227. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  5228. goto done;
  5229. }
  5230. if (!priv->scan_bands) {
  5231. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  5232. goto done;
  5233. }
  5234. if (!priv->scan) {
  5235. priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  5236. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  5237. if (!priv->scan) {
  5238. rc = -ENOMEM;
  5239. goto done;
  5240. }
  5241. }
  5242. scan = priv->scan;
  5243. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  5244. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  5245. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  5246. if (iwl3945_is_associated(priv)) {
  5247. u16 interval = 0;
  5248. u32 extra;
  5249. u32 suspend_time = 100;
  5250. u32 scan_suspend_time = 100;
  5251. unsigned long flags;
  5252. IWL_DEBUG_INFO("Scanning while associated...\n");
  5253. spin_lock_irqsave(&priv->lock, flags);
  5254. interval = priv->beacon_int;
  5255. spin_unlock_irqrestore(&priv->lock, flags);
  5256. scan->suspend_time = 0;
  5257. scan->max_out_time = cpu_to_le32(200 * 1024);
  5258. if (!interval)
  5259. interval = suspend_time;
  5260. /*
  5261. * suspend time format:
  5262. * 0-19: beacon interval in usec (time before exec.)
  5263. * 20-23: 0
  5264. * 24-31: number of beacons (suspend between channels)
  5265. */
  5266. extra = (suspend_time / interval) << 24;
  5267. scan_suspend_time = 0xFF0FFFFF &
  5268. (extra | ((suspend_time % interval) * 1024));
  5269. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  5270. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  5271. scan_suspend_time, interval);
  5272. }
  5273. /* We should add the ability for user to lock to PASSIVE ONLY */
  5274. if (priv->one_direct_scan) {
  5275. IWL_DEBUG_SCAN
  5276. ("Kicking off one direct scan for '%s'\n",
  5277. iwl3945_escape_essid(priv->direct_ssid,
  5278. priv->direct_ssid_len));
  5279. scan->direct_scan[0].id = WLAN_EID_SSID;
  5280. scan->direct_scan[0].len = priv->direct_ssid_len;
  5281. memcpy(scan->direct_scan[0].ssid,
  5282. priv->direct_ssid, priv->direct_ssid_len);
  5283. direct_mask = 1;
  5284. } else if (!iwl3945_is_associated(priv) && priv->essid_len) {
  5285. IWL_DEBUG_SCAN
  5286. ("Kicking off one direct scan for '%s' when not associated\n",
  5287. iwl3945_escape_essid(priv->essid, priv->essid_len));
  5288. scan->direct_scan[0].id = WLAN_EID_SSID;
  5289. scan->direct_scan[0].len = priv->essid_len;
  5290. memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
  5291. direct_mask = 1;
  5292. } else {
  5293. IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
  5294. direct_mask = 0;
  5295. }
  5296. /* We don't build a direct scan probe request; the uCode will do
  5297. * that based on the direct_mask added to each channel entry */
  5298. scan->tx_cmd.len = cpu_to_le16(
  5299. iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
  5300. IWL_MAX_SCAN_SIZE - sizeof(*scan), 0));
  5301. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  5302. scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
  5303. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  5304. /* flags + rate selection */
  5305. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
  5306. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  5307. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  5308. scan->good_CRC_th = 0;
  5309. band = IEEE80211_BAND_2GHZ;
  5310. } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
  5311. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  5312. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  5313. band = IEEE80211_BAND_5GHZ;
  5314. } else {
  5315. IWL_WARNING("Invalid scan band count\n");
  5316. goto done;
  5317. }
  5318. /* select Rx antennas */
  5319. scan->flags |= iwl3945_get_antenna_flags(priv);
  5320. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
  5321. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  5322. if (direct_mask)
  5323. scan->channel_count =
  5324. iwl3945_get_channels_for_scan(
  5325. priv, band, 1, /* active */
  5326. direct_mask,
  5327. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  5328. else
  5329. scan->channel_count =
  5330. iwl3945_get_channels_for_scan(
  5331. priv, band, 0, /* passive */
  5332. direct_mask,
  5333. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  5334. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  5335. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  5336. cmd.data = scan;
  5337. scan->len = cpu_to_le16(cmd.len);
  5338. set_bit(STATUS_SCAN_HW, &priv->status);
  5339. rc = iwl3945_send_cmd_sync(priv, &cmd);
  5340. if (rc)
  5341. goto done;
  5342. queue_delayed_work(priv->workqueue, &priv->scan_check,
  5343. IWL_SCAN_CHECK_WATCHDOG);
  5344. mutex_unlock(&priv->mutex);
  5345. return;
  5346. done:
  5347. /* inform mac80211 scan aborted */
  5348. queue_work(priv->workqueue, &priv->scan_completed);
  5349. mutex_unlock(&priv->mutex);
  5350. }
  5351. static void iwl3945_bg_up(struct work_struct *data)
  5352. {
  5353. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
  5354. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5355. return;
  5356. mutex_lock(&priv->mutex);
  5357. __iwl3945_up(priv);
  5358. mutex_unlock(&priv->mutex);
  5359. iwl3945_rfkill_set_hw_state(priv);
  5360. }
  5361. static void iwl3945_bg_restart(struct work_struct *data)
  5362. {
  5363. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
  5364. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5365. return;
  5366. iwl3945_down(priv);
  5367. queue_work(priv->workqueue, &priv->up);
  5368. }
  5369. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  5370. {
  5371. struct iwl3945_priv *priv =
  5372. container_of(data, struct iwl3945_priv, rx_replenish);
  5373. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5374. return;
  5375. mutex_lock(&priv->mutex);
  5376. iwl3945_rx_replenish(priv);
  5377. mutex_unlock(&priv->mutex);
  5378. }
  5379. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  5380. static void iwl3945_bg_post_associate(struct work_struct *data)
  5381. {
  5382. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv,
  5383. post_associate.work);
  5384. int rc = 0;
  5385. struct ieee80211_conf *conf = NULL;
  5386. DECLARE_MAC_BUF(mac);
  5387. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  5388. IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__);
  5389. return;
  5390. }
  5391. IWL_DEBUG_ASSOC("Associated as %d to: %s\n",
  5392. priv->assoc_id,
  5393. print_mac(mac, priv->active_rxon.bssid_addr));
  5394. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5395. return;
  5396. mutex_lock(&priv->mutex);
  5397. if (!priv->vif || !priv->is_open) {
  5398. mutex_unlock(&priv->mutex);
  5399. return;
  5400. }
  5401. iwl3945_scan_cancel_timeout(priv, 200);
  5402. conf = ieee80211_get_hw_conf(priv->hw);
  5403. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5404. iwl3945_commit_rxon(priv);
  5405. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5406. iwl3945_setup_rxon_timing(priv);
  5407. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5408. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5409. if (rc)
  5410. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5411. "Attempting to continue.\n");
  5412. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5413. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5414. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  5415. priv->assoc_id, priv->beacon_int);
  5416. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5417. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5418. else
  5419. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5420. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5421. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5422. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  5423. else
  5424. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5425. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  5426. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5427. }
  5428. iwl3945_commit_rxon(priv);
  5429. switch (priv->iw_mode) {
  5430. case IEEE80211_IF_TYPE_STA:
  5431. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  5432. break;
  5433. case IEEE80211_IF_TYPE_IBSS:
  5434. /* clear out the station table */
  5435. iwl3945_clear_stations_table(priv);
  5436. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5437. iwl3945_add_station(priv, priv->bssid, 0, 0);
  5438. iwl3945_sync_sta(priv, IWL_STA_ID,
  5439. (priv->band == IEEE80211_BAND_5GHZ) ?
  5440. IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
  5441. CMD_ASYNC);
  5442. iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
  5443. iwl3945_send_beacon_cmd(priv);
  5444. break;
  5445. default:
  5446. IWL_ERROR("%s Should not be called in %d mode\n",
  5447. __FUNCTION__, priv->iw_mode);
  5448. break;
  5449. }
  5450. iwl3945_sequence_reset(priv);
  5451. iwl3945_activate_qos(priv, 0);
  5452. /* we have just associated, don't start scan too early */
  5453. priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
  5454. mutex_unlock(&priv->mutex);
  5455. }
  5456. static void iwl3945_bg_abort_scan(struct work_struct *work)
  5457. {
  5458. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
  5459. if (!iwl3945_is_ready(priv))
  5460. return;
  5461. mutex_lock(&priv->mutex);
  5462. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  5463. iwl3945_send_scan_abort(priv);
  5464. mutex_unlock(&priv->mutex);
  5465. }
  5466. static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf);
  5467. static void iwl3945_bg_scan_completed(struct work_struct *work)
  5468. {
  5469. struct iwl3945_priv *priv =
  5470. container_of(work, struct iwl3945_priv, scan_completed);
  5471. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
  5472. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5473. return;
  5474. if (test_bit(STATUS_CONF_PENDING, &priv->status))
  5475. iwl3945_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw));
  5476. ieee80211_scan_completed(priv->hw);
  5477. /* Since setting the TXPOWER may have been deferred while
  5478. * performing the scan, fire one off */
  5479. mutex_lock(&priv->mutex);
  5480. iwl3945_hw_reg_send_txpower(priv);
  5481. mutex_unlock(&priv->mutex);
  5482. }
  5483. /*****************************************************************************
  5484. *
  5485. * mac80211 entry point functions
  5486. *
  5487. *****************************************************************************/
  5488. #define UCODE_READY_TIMEOUT (2 * HZ)
  5489. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  5490. {
  5491. struct iwl3945_priv *priv = hw->priv;
  5492. int ret;
  5493. IWL_DEBUG_MAC80211("enter\n");
  5494. if (pci_enable_device(priv->pci_dev)) {
  5495. IWL_ERROR("Fail to pci_enable_device\n");
  5496. return -ENODEV;
  5497. }
  5498. pci_restore_state(priv->pci_dev);
  5499. pci_enable_msi(priv->pci_dev);
  5500. ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
  5501. DRV_NAME, priv);
  5502. if (ret) {
  5503. IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
  5504. goto out_disable_msi;
  5505. }
  5506. /* we should be verifying the device is ready to be opened */
  5507. mutex_lock(&priv->mutex);
  5508. memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
  5509. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  5510. * ucode filename and max sizes are card-specific. */
  5511. if (!priv->ucode_code.len) {
  5512. ret = iwl3945_read_ucode(priv);
  5513. if (ret) {
  5514. IWL_ERROR("Could not read microcode: %d\n", ret);
  5515. mutex_unlock(&priv->mutex);
  5516. goto out_release_irq;
  5517. }
  5518. }
  5519. ret = __iwl3945_up(priv);
  5520. mutex_unlock(&priv->mutex);
  5521. iwl3945_rfkill_set_hw_state(priv);
  5522. if (ret)
  5523. goto out_release_irq;
  5524. IWL_DEBUG_INFO("Start UP work.\n");
  5525. if (test_bit(STATUS_IN_SUSPEND, &priv->status))
  5526. return 0;
  5527. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  5528. * mac80211 will not be run successfully. */
  5529. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  5530. test_bit(STATUS_READY, &priv->status),
  5531. UCODE_READY_TIMEOUT);
  5532. if (!ret) {
  5533. if (!test_bit(STATUS_READY, &priv->status)) {
  5534. IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
  5535. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  5536. ret = -ETIMEDOUT;
  5537. goto out_release_irq;
  5538. }
  5539. }
  5540. priv->is_open = 1;
  5541. IWL_DEBUG_MAC80211("leave\n");
  5542. return 0;
  5543. out_release_irq:
  5544. free_irq(priv->pci_dev->irq, priv);
  5545. out_disable_msi:
  5546. pci_disable_msi(priv->pci_dev);
  5547. pci_disable_device(priv->pci_dev);
  5548. priv->is_open = 0;
  5549. IWL_DEBUG_MAC80211("leave - failed\n");
  5550. return ret;
  5551. }
  5552. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  5553. {
  5554. struct iwl3945_priv *priv = hw->priv;
  5555. IWL_DEBUG_MAC80211("enter\n");
  5556. if (!priv->is_open) {
  5557. IWL_DEBUG_MAC80211("leave - skip\n");
  5558. return;
  5559. }
  5560. priv->is_open = 0;
  5561. if (iwl3945_is_ready_rf(priv)) {
  5562. /* stop mac, cancel any scan request and clear
  5563. * RXON_FILTER_ASSOC_MSK BIT
  5564. */
  5565. mutex_lock(&priv->mutex);
  5566. iwl3945_scan_cancel_timeout(priv, 100);
  5567. cancel_delayed_work(&priv->post_associate);
  5568. mutex_unlock(&priv->mutex);
  5569. }
  5570. iwl3945_down(priv);
  5571. flush_workqueue(priv->workqueue);
  5572. free_irq(priv->pci_dev->irq, priv);
  5573. pci_disable_msi(priv->pci_dev);
  5574. pci_save_state(priv->pci_dev);
  5575. pci_disable_device(priv->pci_dev);
  5576. IWL_DEBUG_MAC80211("leave\n");
  5577. }
  5578. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  5579. {
  5580. struct iwl3945_priv *priv = hw->priv;
  5581. IWL_DEBUG_MAC80211("enter\n");
  5582. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
  5583. IWL_DEBUG_MAC80211("leave - monitor\n");
  5584. dev_kfree_skb_any(skb);
  5585. return 0;
  5586. }
  5587. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  5588. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  5589. if (iwl3945_tx_skb(priv, skb))
  5590. dev_kfree_skb_any(skb);
  5591. IWL_DEBUG_MAC80211("leave\n");
  5592. return 0;
  5593. }
  5594. static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
  5595. struct ieee80211_if_init_conf *conf)
  5596. {
  5597. struct iwl3945_priv *priv = hw->priv;
  5598. unsigned long flags;
  5599. DECLARE_MAC_BUF(mac);
  5600. IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
  5601. if (priv->vif) {
  5602. IWL_DEBUG_MAC80211("leave - vif != NULL\n");
  5603. return -EOPNOTSUPP;
  5604. }
  5605. spin_lock_irqsave(&priv->lock, flags);
  5606. priv->vif = conf->vif;
  5607. spin_unlock_irqrestore(&priv->lock, flags);
  5608. mutex_lock(&priv->mutex);
  5609. if (conf->mac_addr) {
  5610. IWL_DEBUG_MAC80211("Set: %s\n", print_mac(mac, conf->mac_addr));
  5611. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  5612. }
  5613. if (iwl3945_is_ready(priv))
  5614. iwl3945_set_mode(priv, conf->type);
  5615. mutex_unlock(&priv->mutex);
  5616. IWL_DEBUG_MAC80211("leave\n");
  5617. return 0;
  5618. }
  5619. /**
  5620. * iwl3945_mac_config - mac80211 config callback
  5621. *
  5622. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  5623. * be set inappropriately and the driver currently sets the hardware up to
  5624. * use it whenever needed.
  5625. */
  5626. static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
  5627. {
  5628. struct iwl3945_priv *priv = hw->priv;
  5629. const struct iwl3945_channel_info *ch_info;
  5630. unsigned long flags;
  5631. int ret = 0;
  5632. mutex_lock(&priv->mutex);
  5633. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
  5634. priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
  5635. if (!iwl3945_is_ready(priv)) {
  5636. IWL_DEBUG_MAC80211("leave - not ready\n");
  5637. ret = -EIO;
  5638. goto out;
  5639. }
  5640. if (unlikely(!iwl3945_param_disable_hw_scan &&
  5641. test_bit(STATUS_SCANNING, &priv->status))) {
  5642. IWL_DEBUG_MAC80211("leave - scanning\n");
  5643. set_bit(STATUS_CONF_PENDING, &priv->status);
  5644. mutex_unlock(&priv->mutex);
  5645. return 0;
  5646. }
  5647. spin_lock_irqsave(&priv->lock, flags);
  5648. ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
  5649. conf->channel->hw_value);
  5650. if (!is_channel_valid(ch_info)) {
  5651. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
  5652. conf->channel->hw_value, conf->channel->band);
  5653. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  5654. spin_unlock_irqrestore(&priv->lock, flags);
  5655. ret = -EINVAL;
  5656. goto out;
  5657. }
  5658. iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
  5659. iwl3945_set_flags_for_phymode(priv, conf->channel->band);
  5660. /* The list of supported rates and rate mask can be different
  5661. * for each phymode; since the phymode may have changed, reset
  5662. * the rate mask to what mac80211 lists */
  5663. iwl3945_set_rate(priv);
  5664. spin_unlock_irqrestore(&priv->lock, flags);
  5665. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  5666. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  5667. iwl3945_hw_channel_switch(priv, conf->channel);
  5668. goto out;
  5669. }
  5670. #endif
  5671. iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
  5672. if (!conf->radio_enabled) {
  5673. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  5674. goto out;
  5675. }
  5676. if (iwl3945_is_rfkill(priv)) {
  5677. IWL_DEBUG_MAC80211("leave - RF kill\n");
  5678. ret = -EIO;
  5679. goto out;
  5680. }
  5681. iwl3945_set_rate(priv);
  5682. if (memcmp(&priv->active_rxon,
  5683. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  5684. iwl3945_commit_rxon(priv);
  5685. else
  5686. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  5687. IWL_DEBUG_MAC80211("leave\n");
  5688. out:
  5689. clear_bit(STATUS_CONF_PENDING, &priv->status);
  5690. mutex_unlock(&priv->mutex);
  5691. return ret;
  5692. }
  5693. static void iwl3945_config_ap(struct iwl3945_priv *priv)
  5694. {
  5695. int rc = 0;
  5696. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5697. return;
  5698. /* The following should be done only at AP bring up */
  5699. if (!(iwl3945_is_associated(priv))) {
  5700. /* RXON - unassoc (to set timing command) */
  5701. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5702. iwl3945_commit_rxon(priv);
  5703. /* RXON Timing */
  5704. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5705. iwl3945_setup_rxon_timing(priv);
  5706. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5707. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5708. if (rc)
  5709. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5710. "Attempting to continue.\n");
  5711. /* FIXME: what should be the assoc_id for AP? */
  5712. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5713. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5714. priv->staging_rxon.flags |=
  5715. RXON_FLG_SHORT_PREAMBLE_MSK;
  5716. else
  5717. priv->staging_rxon.flags &=
  5718. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5719. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5720. if (priv->assoc_capability &
  5721. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5722. priv->staging_rxon.flags |=
  5723. RXON_FLG_SHORT_SLOT_MSK;
  5724. else
  5725. priv->staging_rxon.flags &=
  5726. ~RXON_FLG_SHORT_SLOT_MSK;
  5727. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  5728. priv->staging_rxon.flags &=
  5729. ~RXON_FLG_SHORT_SLOT_MSK;
  5730. }
  5731. /* restore RXON assoc */
  5732. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5733. iwl3945_commit_rxon(priv);
  5734. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5735. }
  5736. iwl3945_send_beacon_cmd(priv);
  5737. /* FIXME - we need to add code here to detect a totally new
  5738. * configuration, reset the AP, unassoc, rxon timing, assoc,
  5739. * clear sta table, add BCAST sta... */
  5740. }
  5741. static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
  5742. struct ieee80211_vif *vif,
  5743. struct ieee80211_if_conf *conf)
  5744. {
  5745. struct iwl3945_priv *priv = hw->priv;
  5746. DECLARE_MAC_BUF(mac);
  5747. unsigned long flags;
  5748. int rc;
  5749. if (conf == NULL)
  5750. return -EIO;
  5751. if (priv->vif != vif) {
  5752. IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
  5753. return 0;
  5754. }
  5755. /* XXX: this MUST use conf->mac_addr */
  5756. if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
  5757. (!conf->beacon || !conf->ssid_len)) {
  5758. IWL_DEBUG_MAC80211
  5759. ("Leaving in AP mode because HostAPD is not ready.\n");
  5760. return 0;
  5761. }
  5762. if (!iwl3945_is_alive(priv))
  5763. return -EAGAIN;
  5764. mutex_lock(&priv->mutex);
  5765. if (conf->bssid)
  5766. IWL_DEBUG_MAC80211("bssid: %s\n",
  5767. print_mac(mac, conf->bssid));
  5768. /*
  5769. * very dubious code was here; the probe filtering flag is never set:
  5770. *
  5771. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  5772. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  5773. */
  5774. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  5775. if (!conf->bssid) {
  5776. conf->bssid = priv->mac_addr;
  5777. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  5778. IWL_DEBUG_MAC80211("bssid was set to: %s\n",
  5779. print_mac(mac, conf->bssid));
  5780. }
  5781. if (priv->ibss_beacon)
  5782. dev_kfree_skb(priv->ibss_beacon);
  5783. priv->ibss_beacon = conf->beacon;
  5784. }
  5785. if (iwl3945_is_rfkill(priv))
  5786. goto done;
  5787. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  5788. !is_multicast_ether_addr(conf->bssid)) {
  5789. /* If there is currently a HW scan going on in the background
  5790. * then we need to cancel it else the RXON below will fail. */
  5791. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  5792. IWL_WARNING("Aborted scan still in progress "
  5793. "after 100ms\n");
  5794. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  5795. mutex_unlock(&priv->mutex);
  5796. return -EAGAIN;
  5797. }
  5798. memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  5799. /* TODO: Audit driver for usage of these members and see
  5800. * if mac80211 deprecates them (priv->bssid looks like it
  5801. * shouldn't be there, but I haven't scanned the IBSS code
  5802. * to verify) - jpk */
  5803. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  5804. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  5805. iwl3945_config_ap(priv);
  5806. else {
  5807. rc = iwl3945_commit_rxon(priv);
  5808. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc)
  5809. iwl3945_add_station(priv,
  5810. priv->active_rxon.bssid_addr, 1, 0);
  5811. }
  5812. } else {
  5813. iwl3945_scan_cancel_timeout(priv, 100);
  5814. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5815. iwl3945_commit_rxon(priv);
  5816. }
  5817. done:
  5818. spin_lock_irqsave(&priv->lock, flags);
  5819. if (!conf->ssid_len)
  5820. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  5821. else
  5822. memcpy(priv->essid, conf->ssid, conf->ssid_len);
  5823. priv->essid_len = conf->ssid_len;
  5824. spin_unlock_irqrestore(&priv->lock, flags);
  5825. IWL_DEBUG_MAC80211("leave\n");
  5826. mutex_unlock(&priv->mutex);
  5827. return 0;
  5828. }
  5829. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  5830. unsigned int changed_flags,
  5831. unsigned int *total_flags,
  5832. int mc_count, struct dev_addr_list *mc_list)
  5833. {
  5834. struct iwl3945_priv *priv = hw->priv;
  5835. if (changed_flags & (*total_flags) & FIF_OTHER_BSS) {
  5836. IWL_DEBUG_MAC80211("Enter: type %d (0x%x, 0x%x)\n",
  5837. IEEE80211_IF_TYPE_MNTR,
  5838. changed_flags, *total_flags);
  5839. /* queue work 'cuz mac80211 is holding a lock which
  5840. * prevents us from issuing (synchronous) f/w cmds */
  5841. queue_work(priv->workqueue, &priv->set_monitor);
  5842. }
  5843. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI |
  5844. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  5845. }
  5846. static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
  5847. struct ieee80211_if_init_conf *conf)
  5848. {
  5849. struct iwl3945_priv *priv = hw->priv;
  5850. IWL_DEBUG_MAC80211("enter\n");
  5851. mutex_lock(&priv->mutex);
  5852. if (iwl3945_is_ready_rf(priv)) {
  5853. iwl3945_scan_cancel_timeout(priv, 100);
  5854. cancel_delayed_work(&priv->post_associate);
  5855. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5856. iwl3945_commit_rxon(priv);
  5857. }
  5858. if (priv->vif == conf->vif) {
  5859. priv->vif = NULL;
  5860. memset(priv->bssid, 0, ETH_ALEN);
  5861. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  5862. priv->essid_len = 0;
  5863. }
  5864. mutex_unlock(&priv->mutex);
  5865. IWL_DEBUG_MAC80211("leave\n");
  5866. }
  5867. static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  5868. {
  5869. int rc = 0;
  5870. unsigned long flags;
  5871. struct iwl3945_priv *priv = hw->priv;
  5872. IWL_DEBUG_MAC80211("enter\n");
  5873. mutex_lock(&priv->mutex);
  5874. spin_lock_irqsave(&priv->lock, flags);
  5875. if (!iwl3945_is_ready_rf(priv)) {
  5876. rc = -EIO;
  5877. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  5878. goto out_unlock;
  5879. }
  5880. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */
  5881. rc = -EIO;
  5882. IWL_ERROR("ERROR: APs don't scan\n");
  5883. goto out_unlock;
  5884. }
  5885. /* we don't schedule scan within next_scan_jiffies period */
  5886. if (priv->next_scan_jiffies &&
  5887. time_after(priv->next_scan_jiffies, jiffies)) {
  5888. rc = -EAGAIN;
  5889. goto out_unlock;
  5890. }
  5891. /* if we just finished scan ask for delay for a broadcast scan */
  5892. if ((len == 0) && priv->last_scan_jiffies &&
  5893. time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
  5894. jiffies)) {
  5895. rc = -EAGAIN;
  5896. goto out_unlock;
  5897. }
  5898. if (len) {
  5899. IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
  5900. iwl3945_escape_essid(ssid, len), (int)len);
  5901. priv->one_direct_scan = 1;
  5902. priv->direct_ssid_len = (u8)
  5903. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  5904. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  5905. } else
  5906. priv->one_direct_scan = 0;
  5907. rc = iwl3945_scan_initiate(priv);
  5908. IWL_DEBUG_MAC80211("leave\n");
  5909. out_unlock:
  5910. spin_unlock_irqrestore(&priv->lock, flags);
  5911. mutex_unlock(&priv->mutex);
  5912. return rc;
  5913. }
  5914. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  5915. const u8 *local_addr, const u8 *addr,
  5916. struct ieee80211_key_conf *key)
  5917. {
  5918. struct iwl3945_priv *priv = hw->priv;
  5919. int rc = 0;
  5920. u8 sta_id;
  5921. IWL_DEBUG_MAC80211("enter\n");
  5922. if (!iwl3945_param_hwcrypto) {
  5923. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  5924. return -EOPNOTSUPP;
  5925. }
  5926. if (is_zero_ether_addr(addr))
  5927. /* only support pairwise keys */
  5928. return -EOPNOTSUPP;
  5929. sta_id = iwl3945_hw_find_station(priv, addr);
  5930. if (sta_id == IWL_INVALID_STATION) {
  5931. DECLARE_MAC_BUF(mac);
  5932. IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
  5933. print_mac(mac, addr));
  5934. return -EINVAL;
  5935. }
  5936. mutex_lock(&priv->mutex);
  5937. iwl3945_scan_cancel_timeout(priv, 100);
  5938. switch (cmd) {
  5939. case SET_KEY:
  5940. rc = iwl3945_update_sta_key_info(priv, key, sta_id);
  5941. if (!rc) {
  5942. iwl3945_set_rxon_hwcrypto(priv, 1);
  5943. iwl3945_commit_rxon(priv);
  5944. key->hw_key_idx = sta_id;
  5945. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  5946. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  5947. }
  5948. break;
  5949. case DISABLE_KEY:
  5950. rc = iwl3945_clear_sta_key_info(priv, sta_id);
  5951. if (!rc) {
  5952. iwl3945_set_rxon_hwcrypto(priv, 0);
  5953. iwl3945_commit_rxon(priv);
  5954. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  5955. }
  5956. break;
  5957. default:
  5958. rc = -EINVAL;
  5959. }
  5960. IWL_DEBUG_MAC80211("leave\n");
  5961. mutex_unlock(&priv->mutex);
  5962. return rc;
  5963. }
  5964. static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  5965. const struct ieee80211_tx_queue_params *params)
  5966. {
  5967. struct iwl3945_priv *priv = hw->priv;
  5968. unsigned long flags;
  5969. int q;
  5970. IWL_DEBUG_MAC80211("enter\n");
  5971. if (!iwl3945_is_ready_rf(priv)) {
  5972. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5973. return -EIO;
  5974. }
  5975. if (queue >= AC_NUM) {
  5976. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  5977. return 0;
  5978. }
  5979. if (!priv->qos_data.qos_enable) {
  5980. priv->qos_data.qos_active = 0;
  5981. IWL_DEBUG_MAC80211("leave - qos not enabled\n");
  5982. return 0;
  5983. }
  5984. q = AC_NUM - 1 - queue;
  5985. spin_lock_irqsave(&priv->lock, flags);
  5986. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  5987. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  5988. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  5989. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  5990. cpu_to_le16((params->txop * 32));
  5991. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  5992. priv->qos_data.qos_active = 1;
  5993. spin_unlock_irqrestore(&priv->lock, flags);
  5994. mutex_lock(&priv->mutex);
  5995. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  5996. iwl3945_activate_qos(priv, 1);
  5997. else if (priv->assoc_id && iwl3945_is_associated(priv))
  5998. iwl3945_activate_qos(priv, 0);
  5999. mutex_unlock(&priv->mutex);
  6000. IWL_DEBUG_MAC80211("leave\n");
  6001. return 0;
  6002. }
  6003. static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
  6004. struct ieee80211_tx_queue_stats *stats)
  6005. {
  6006. struct iwl3945_priv *priv = hw->priv;
  6007. int i, avail;
  6008. struct iwl3945_tx_queue *txq;
  6009. struct iwl3945_queue *q;
  6010. unsigned long flags;
  6011. IWL_DEBUG_MAC80211("enter\n");
  6012. if (!iwl3945_is_ready_rf(priv)) {
  6013. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6014. return -EIO;
  6015. }
  6016. spin_lock_irqsave(&priv->lock, flags);
  6017. for (i = 0; i < AC_NUM; i++) {
  6018. txq = &priv->txq[i];
  6019. q = &txq->q;
  6020. avail = iwl3945_queue_space(q);
  6021. stats[i].len = q->n_window - avail;
  6022. stats[i].limit = q->n_window - q->high_mark;
  6023. stats[i].count = q->n_window;
  6024. }
  6025. spin_unlock_irqrestore(&priv->lock, flags);
  6026. IWL_DEBUG_MAC80211("leave\n");
  6027. return 0;
  6028. }
  6029. static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
  6030. struct ieee80211_low_level_stats *stats)
  6031. {
  6032. IWL_DEBUG_MAC80211("enter\n");
  6033. IWL_DEBUG_MAC80211("leave\n");
  6034. return 0;
  6035. }
  6036. static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw)
  6037. {
  6038. IWL_DEBUG_MAC80211("enter\n");
  6039. IWL_DEBUG_MAC80211("leave\n");
  6040. return 0;
  6041. }
  6042. static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
  6043. {
  6044. struct iwl3945_priv *priv = hw->priv;
  6045. unsigned long flags;
  6046. mutex_lock(&priv->mutex);
  6047. IWL_DEBUG_MAC80211("enter\n");
  6048. iwl3945_reset_qos(priv);
  6049. cancel_delayed_work(&priv->post_associate);
  6050. spin_lock_irqsave(&priv->lock, flags);
  6051. priv->assoc_id = 0;
  6052. priv->assoc_capability = 0;
  6053. priv->call_post_assoc_from_beacon = 0;
  6054. /* new association get rid of ibss beacon skb */
  6055. if (priv->ibss_beacon)
  6056. dev_kfree_skb(priv->ibss_beacon);
  6057. priv->ibss_beacon = NULL;
  6058. priv->beacon_int = priv->hw->conf.beacon_int;
  6059. priv->timestamp1 = 0;
  6060. priv->timestamp0 = 0;
  6061. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA))
  6062. priv->beacon_int = 0;
  6063. spin_unlock_irqrestore(&priv->lock, flags);
  6064. if (!iwl3945_is_ready_rf(priv)) {
  6065. IWL_DEBUG_MAC80211("leave - not ready\n");
  6066. mutex_unlock(&priv->mutex);
  6067. return;
  6068. }
  6069. /* we are restarting association process
  6070. * clear RXON_FILTER_ASSOC_MSK bit
  6071. */
  6072. if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
  6073. iwl3945_scan_cancel_timeout(priv, 100);
  6074. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  6075. iwl3945_commit_rxon(priv);
  6076. }
  6077. /* Per mac80211.h: This is only used in IBSS mode... */
  6078. if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
  6079. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  6080. mutex_unlock(&priv->mutex);
  6081. return;
  6082. }
  6083. iwl3945_set_rate(priv);
  6084. mutex_unlock(&priv->mutex);
  6085. IWL_DEBUG_MAC80211("leave\n");
  6086. }
  6087. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
  6088. {
  6089. struct iwl3945_priv *priv = hw->priv;
  6090. unsigned long flags;
  6091. mutex_lock(&priv->mutex);
  6092. IWL_DEBUG_MAC80211("enter\n");
  6093. if (!iwl3945_is_ready_rf(priv)) {
  6094. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6095. mutex_unlock(&priv->mutex);
  6096. return -EIO;
  6097. }
  6098. if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
  6099. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  6100. mutex_unlock(&priv->mutex);
  6101. return -EIO;
  6102. }
  6103. spin_lock_irqsave(&priv->lock, flags);
  6104. if (priv->ibss_beacon)
  6105. dev_kfree_skb(priv->ibss_beacon);
  6106. priv->ibss_beacon = skb;
  6107. priv->assoc_id = 0;
  6108. IWL_DEBUG_MAC80211("leave\n");
  6109. spin_unlock_irqrestore(&priv->lock, flags);
  6110. iwl3945_reset_qos(priv);
  6111. queue_work(priv->workqueue, &priv->post_associate.work);
  6112. mutex_unlock(&priv->mutex);
  6113. return 0;
  6114. }
  6115. /*****************************************************************************
  6116. *
  6117. * sysfs attributes
  6118. *
  6119. *****************************************************************************/
  6120. #ifdef CONFIG_IWL3945_DEBUG
  6121. /*
  6122. * The following adds a new attribute to the sysfs representation
  6123. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  6124. * used for controlling the debug level.
  6125. *
  6126. * See the level definitions in iwl for details.
  6127. */
  6128. static ssize_t show_debug_level(struct device_driver *d, char *buf)
  6129. {
  6130. return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
  6131. }
  6132. static ssize_t store_debug_level(struct device_driver *d,
  6133. const char *buf, size_t count)
  6134. {
  6135. char *p = (char *)buf;
  6136. u32 val;
  6137. val = simple_strtoul(p, &p, 0);
  6138. if (p == buf)
  6139. printk(KERN_INFO DRV_NAME
  6140. ": %s is not in hex or decimal form.\n", buf);
  6141. else
  6142. iwl3945_debug_level = val;
  6143. return strnlen(buf, count);
  6144. }
  6145. static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
  6146. show_debug_level, store_debug_level);
  6147. #endif /* CONFIG_IWL3945_DEBUG */
  6148. static ssize_t show_temperature(struct device *d,
  6149. struct device_attribute *attr, char *buf)
  6150. {
  6151. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6152. if (!iwl3945_is_alive(priv))
  6153. return -EAGAIN;
  6154. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  6155. }
  6156. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  6157. static ssize_t show_rs_window(struct device *d,
  6158. struct device_attribute *attr,
  6159. char *buf)
  6160. {
  6161. struct iwl3945_priv *priv = d->driver_data;
  6162. return iwl3945_fill_rs_info(priv->hw, buf, IWL_AP_ID);
  6163. }
  6164. static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL);
  6165. static ssize_t show_tx_power(struct device *d,
  6166. struct device_attribute *attr, char *buf)
  6167. {
  6168. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6169. return sprintf(buf, "%d\n", priv->user_txpower_limit);
  6170. }
  6171. static ssize_t store_tx_power(struct device *d,
  6172. struct device_attribute *attr,
  6173. const char *buf, size_t count)
  6174. {
  6175. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6176. char *p = (char *)buf;
  6177. u32 val;
  6178. val = simple_strtoul(p, &p, 10);
  6179. if (p == buf)
  6180. printk(KERN_INFO DRV_NAME
  6181. ": %s is not in decimal form.\n", buf);
  6182. else
  6183. iwl3945_hw_reg_set_txpower(priv, val);
  6184. return count;
  6185. }
  6186. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  6187. static ssize_t show_flags(struct device *d,
  6188. struct device_attribute *attr, char *buf)
  6189. {
  6190. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6191. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  6192. }
  6193. static ssize_t store_flags(struct device *d,
  6194. struct device_attribute *attr,
  6195. const char *buf, size_t count)
  6196. {
  6197. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6198. u32 flags = simple_strtoul(buf, NULL, 0);
  6199. mutex_lock(&priv->mutex);
  6200. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  6201. /* Cancel any currently running scans... */
  6202. if (iwl3945_scan_cancel_timeout(priv, 100))
  6203. IWL_WARNING("Could not cancel scan.\n");
  6204. else {
  6205. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  6206. flags);
  6207. priv->staging_rxon.flags = cpu_to_le32(flags);
  6208. iwl3945_commit_rxon(priv);
  6209. }
  6210. }
  6211. mutex_unlock(&priv->mutex);
  6212. return count;
  6213. }
  6214. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  6215. static ssize_t show_filter_flags(struct device *d,
  6216. struct device_attribute *attr, char *buf)
  6217. {
  6218. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6219. return sprintf(buf, "0x%04X\n",
  6220. le32_to_cpu(priv->active_rxon.filter_flags));
  6221. }
  6222. static ssize_t store_filter_flags(struct device *d,
  6223. struct device_attribute *attr,
  6224. const char *buf, size_t count)
  6225. {
  6226. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6227. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  6228. mutex_lock(&priv->mutex);
  6229. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  6230. /* Cancel any currently running scans... */
  6231. if (iwl3945_scan_cancel_timeout(priv, 100))
  6232. IWL_WARNING("Could not cancel scan.\n");
  6233. else {
  6234. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  6235. "0x%04X\n", filter_flags);
  6236. priv->staging_rxon.filter_flags =
  6237. cpu_to_le32(filter_flags);
  6238. iwl3945_commit_rxon(priv);
  6239. }
  6240. }
  6241. mutex_unlock(&priv->mutex);
  6242. return count;
  6243. }
  6244. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  6245. store_filter_flags);
  6246. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6247. static ssize_t show_measurement(struct device *d,
  6248. struct device_attribute *attr, char *buf)
  6249. {
  6250. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6251. struct iwl3945_spectrum_notification measure_report;
  6252. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  6253. u8 *data = (u8 *) & measure_report;
  6254. unsigned long flags;
  6255. spin_lock_irqsave(&priv->lock, flags);
  6256. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  6257. spin_unlock_irqrestore(&priv->lock, flags);
  6258. return 0;
  6259. }
  6260. memcpy(&measure_report, &priv->measure_report, size);
  6261. priv->measurement_status = 0;
  6262. spin_unlock_irqrestore(&priv->lock, flags);
  6263. while (size && (PAGE_SIZE - len)) {
  6264. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6265. PAGE_SIZE - len, 1);
  6266. len = strlen(buf);
  6267. if (PAGE_SIZE - len)
  6268. buf[len++] = '\n';
  6269. ofs += 16;
  6270. size -= min(size, 16U);
  6271. }
  6272. return len;
  6273. }
  6274. static ssize_t store_measurement(struct device *d,
  6275. struct device_attribute *attr,
  6276. const char *buf, size_t count)
  6277. {
  6278. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6279. struct ieee80211_measurement_params params = {
  6280. .channel = le16_to_cpu(priv->active_rxon.channel),
  6281. .start_time = cpu_to_le64(priv->last_tsf),
  6282. .duration = cpu_to_le16(1),
  6283. };
  6284. u8 type = IWL_MEASURE_BASIC;
  6285. u8 buffer[32];
  6286. u8 channel;
  6287. if (count) {
  6288. char *p = buffer;
  6289. strncpy(buffer, buf, min(sizeof(buffer), count));
  6290. channel = simple_strtoul(p, NULL, 0);
  6291. if (channel)
  6292. params.channel = channel;
  6293. p = buffer;
  6294. while (*p && *p != ' ')
  6295. p++;
  6296. if (*p)
  6297. type = simple_strtoul(p + 1, NULL, 0);
  6298. }
  6299. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  6300. "channel %d (for '%s')\n", type, params.channel, buf);
  6301. iwl3945_get_measurement(priv, &params, type);
  6302. return count;
  6303. }
  6304. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  6305. show_measurement, store_measurement);
  6306. #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
  6307. static ssize_t store_retry_rate(struct device *d,
  6308. struct device_attribute *attr,
  6309. const char *buf, size_t count)
  6310. {
  6311. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6312. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  6313. if (priv->retry_rate <= 0)
  6314. priv->retry_rate = 1;
  6315. return count;
  6316. }
  6317. static ssize_t show_retry_rate(struct device *d,
  6318. struct device_attribute *attr, char *buf)
  6319. {
  6320. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6321. return sprintf(buf, "%d", priv->retry_rate);
  6322. }
  6323. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  6324. store_retry_rate);
  6325. static ssize_t store_power_level(struct device *d,
  6326. struct device_attribute *attr,
  6327. const char *buf, size_t count)
  6328. {
  6329. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6330. int rc;
  6331. int mode;
  6332. mode = simple_strtoul(buf, NULL, 0);
  6333. mutex_lock(&priv->mutex);
  6334. if (!iwl3945_is_ready(priv)) {
  6335. rc = -EAGAIN;
  6336. goto out;
  6337. }
  6338. if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
  6339. mode = IWL_POWER_AC;
  6340. else
  6341. mode |= IWL_POWER_ENABLED;
  6342. if (mode != priv->power_mode) {
  6343. rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  6344. if (rc) {
  6345. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  6346. goto out;
  6347. }
  6348. priv->power_mode = mode;
  6349. }
  6350. rc = count;
  6351. out:
  6352. mutex_unlock(&priv->mutex);
  6353. return rc;
  6354. }
  6355. #define MAX_WX_STRING 80
  6356. /* Values are in microsecond */
  6357. static const s32 timeout_duration[] = {
  6358. 350000,
  6359. 250000,
  6360. 75000,
  6361. 37000,
  6362. 25000,
  6363. };
  6364. static const s32 period_duration[] = {
  6365. 400000,
  6366. 700000,
  6367. 1000000,
  6368. 1000000,
  6369. 1000000
  6370. };
  6371. static ssize_t show_power_level(struct device *d,
  6372. struct device_attribute *attr, char *buf)
  6373. {
  6374. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6375. int level = IWL_POWER_LEVEL(priv->power_mode);
  6376. char *p = buf;
  6377. p += sprintf(p, "%d ", level);
  6378. switch (level) {
  6379. case IWL_POWER_MODE_CAM:
  6380. case IWL_POWER_AC:
  6381. p += sprintf(p, "(AC)");
  6382. break;
  6383. case IWL_POWER_BATTERY:
  6384. p += sprintf(p, "(BATTERY)");
  6385. break;
  6386. default:
  6387. p += sprintf(p,
  6388. "(Timeout %dms, Period %dms)",
  6389. timeout_duration[level - 1] / 1000,
  6390. period_duration[level - 1] / 1000);
  6391. }
  6392. if (!(priv->power_mode & IWL_POWER_ENABLED))
  6393. p += sprintf(p, " OFF\n");
  6394. else
  6395. p += sprintf(p, " \n");
  6396. return (p - buf + 1);
  6397. }
  6398. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  6399. store_power_level);
  6400. static ssize_t show_channels(struct device *d,
  6401. struct device_attribute *attr, char *buf)
  6402. {
  6403. /* all this shit doesn't belong into sysfs anyway */
  6404. return 0;
  6405. }
  6406. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  6407. static ssize_t show_statistics(struct device *d,
  6408. struct device_attribute *attr, char *buf)
  6409. {
  6410. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6411. u32 size = sizeof(struct iwl3945_notif_statistics);
  6412. u32 len = 0, ofs = 0;
  6413. u8 *data = (u8 *) & priv->statistics;
  6414. int rc = 0;
  6415. if (!iwl3945_is_alive(priv))
  6416. return -EAGAIN;
  6417. mutex_lock(&priv->mutex);
  6418. rc = iwl3945_send_statistics_request(priv);
  6419. mutex_unlock(&priv->mutex);
  6420. if (rc) {
  6421. len = sprintf(buf,
  6422. "Error sending statistics request: 0x%08X\n", rc);
  6423. return len;
  6424. }
  6425. while (size && (PAGE_SIZE - len)) {
  6426. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6427. PAGE_SIZE - len, 1);
  6428. len = strlen(buf);
  6429. if (PAGE_SIZE - len)
  6430. buf[len++] = '\n';
  6431. ofs += 16;
  6432. size -= min(size, 16U);
  6433. }
  6434. return len;
  6435. }
  6436. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  6437. static ssize_t show_antenna(struct device *d,
  6438. struct device_attribute *attr, char *buf)
  6439. {
  6440. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6441. if (!iwl3945_is_alive(priv))
  6442. return -EAGAIN;
  6443. return sprintf(buf, "%d\n", priv->antenna);
  6444. }
  6445. static ssize_t store_antenna(struct device *d,
  6446. struct device_attribute *attr,
  6447. const char *buf, size_t count)
  6448. {
  6449. int ant;
  6450. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6451. if (count == 0)
  6452. return 0;
  6453. if (sscanf(buf, "%1i", &ant) != 1) {
  6454. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  6455. return count;
  6456. }
  6457. if ((ant >= 0) && (ant <= 2)) {
  6458. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  6459. priv->antenna = (enum iwl3945_antenna)ant;
  6460. } else
  6461. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  6462. return count;
  6463. }
  6464. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  6465. static ssize_t show_status(struct device *d,
  6466. struct device_attribute *attr, char *buf)
  6467. {
  6468. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6469. if (!iwl3945_is_alive(priv))
  6470. return -EAGAIN;
  6471. return sprintf(buf, "0x%08x\n", (int)priv->status);
  6472. }
  6473. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  6474. static ssize_t dump_error_log(struct device *d,
  6475. struct device_attribute *attr,
  6476. const char *buf, size_t count)
  6477. {
  6478. char *p = (char *)buf;
  6479. if (p[0] == '1')
  6480. iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
  6481. return strnlen(buf, count);
  6482. }
  6483. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  6484. static ssize_t dump_event_log(struct device *d,
  6485. struct device_attribute *attr,
  6486. const char *buf, size_t count)
  6487. {
  6488. char *p = (char *)buf;
  6489. if (p[0] == '1')
  6490. iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
  6491. return strnlen(buf, count);
  6492. }
  6493. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  6494. /*****************************************************************************
  6495. *
  6496. * driver setup and teardown
  6497. *
  6498. *****************************************************************************/
  6499. static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
  6500. {
  6501. priv->workqueue = create_workqueue(DRV_NAME);
  6502. init_waitqueue_head(&priv->wait_command_queue);
  6503. INIT_WORK(&priv->up, iwl3945_bg_up);
  6504. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  6505. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  6506. INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
  6507. INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
  6508. INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
  6509. INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
  6510. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  6511. INIT_WORK(&priv->set_monitor, iwl3945_bg_set_monitor);
  6512. INIT_DELAYED_WORK(&priv->post_associate, iwl3945_bg_post_associate);
  6513. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  6514. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  6515. INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
  6516. iwl3945_hw_setup_deferred_work(priv);
  6517. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  6518. iwl3945_irq_tasklet, (unsigned long)priv);
  6519. }
  6520. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
  6521. {
  6522. iwl3945_hw_cancel_deferred_work(priv);
  6523. cancel_delayed_work_sync(&priv->init_alive_start);
  6524. cancel_delayed_work(&priv->scan_check);
  6525. cancel_delayed_work(&priv->alive_start);
  6526. cancel_delayed_work(&priv->post_associate);
  6527. cancel_work_sync(&priv->beacon_update);
  6528. }
  6529. static struct attribute *iwl3945_sysfs_entries[] = {
  6530. &dev_attr_antenna.attr,
  6531. &dev_attr_channels.attr,
  6532. &dev_attr_dump_errors.attr,
  6533. &dev_attr_dump_events.attr,
  6534. &dev_attr_flags.attr,
  6535. &dev_attr_filter_flags.attr,
  6536. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6537. &dev_attr_measurement.attr,
  6538. #endif
  6539. &dev_attr_power_level.attr,
  6540. &dev_attr_retry_rate.attr,
  6541. &dev_attr_rs_window.attr,
  6542. &dev_attr_statistics.attr,
  6543. &dev_attr_status.attr,
  6544. &dev_attr_temperature.attr,
  6545. &dev_attr_tx_power.attr,
  6546. NULL
  6547. };
  6548. static struct attribute_group iwl3945_attribute_group = {
  6549. .name = NULL, /* put in device directory */
  6550. .attrs = iwl3945_sysfs_entries,
  6551. };
  6552. static struct ieee80211_ops iwl3945_hw_ops = {
  6553. .tx = iwl3945_mac_tx,
  6554. .start = iwl3945_mac_start,
  6555. .stop = iwl3945_mac_stop,
  6556. .add_interface = iwl3945_mac_add_interface,
  6557. .remove_interface = iwl3945_mac_remove_interface,
  6558. .config = iwl3945_mac_config,
  6559. .config_interface = iwl3945_mac_config_interface,
  6560. .configure_filter = iwl3945_configure_filter,
  6561. .set_key = iwl3945_mac_set_key,
  6562. .get_stats = iwl3945_mac_get_stats,
  6563. .get_tx_stats = iwl3945_mac_get_tx_stats,
  6564. .conf_tx = iwl3945_mac_conf_tx,
  6565. .get_tsf = iwl3945_mac_get_tsf,
  6566. .reset_tsf = iwl3945_mac_reset_tsf,
  6567. .beacon_update = iwl3945_mac_beacon_update,
  6568. .hw_scan = iwl3945_mac_hw_scan
  6569. };
  6570. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  6571. {
  6572. int err = 0;
  6573. struct iwl3945_priv *priv;
  6574. struct ieee80211_hw *hw;
  6575. struct iwl_3945_cfg *cfg = (struct iwl_3945_cfg *)(ent->driver_data);
  6576. int i;
  6577. unsigned long flags;
  6578. DECLARE_MAC_BUF(mac);
  6579. /* Disabling hardware scan means that mac80211 will perform scans
  6580. * "the hard way", rather than using device's scan. */
  6581. if (iwl3945_param_disable_hw_scan) {
  6582. IWL_DEBUG_INFO("Disabling hw_scan\n");
  6583. iwl3945_hw_ops.hw_scan = NULL;
  6584. }
  6585. if ((iwl3945_param_queues_num > IWL39_MAX_NUM_QUEUES) ||
  6586. (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
  6587. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  6588. IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
  6589. err = -EINVAL;
  6590. goto out;
  6591. }
  6592. /* mac80211 allocates memory for this device instance, including
  6593. * space for this driver's private structure */
  6594. hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
  6595. if (hw == NULL) {
  6596. IWL_ERROR("Can not allocate network device\n");
  6597. err = -ENOMEM;
  6598. goto out;
  6599. }
  6600. SET_IEEE80211_DEV(hw, &pdev->dev);
  6601. hw->rate_control_algorithm = "iwl-3945-rs";
  6602. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  6603. priv = hw->priv;
  6604. priv->hw = hw;
  6605. priv->pci_dev = pdev;
  6606. priv->cfg = cfg;
  6607. /* Select antenna (may be helpful if only one antenna is connected) */
  6608. priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
  6609. #ifdef CONFIG_IWL3945_DEBUG
  6610. iwl3945_debug_level = iwl3945_param_debug;
  6611. atomic_set(&priv->restrict_refcnt, 0);
  6612. #endif
  6613. priv->retry_rate = 1;
  6614. priv->ibss_beacon = NULL;
  6615. /* Tell mac80211 our characteristics */
  6616. hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
  6617. IEEE80211_HW_SIGNAL_DBM |
  6618. IEEE80211_HW_NOISE_DBM;
  6619. /* 4 EDCA QOS priorities */
  6620. hw->queues = 4;
  6621. spin_lock_init(&priv->lock);
  6622. spin_lock_init(&priv->power_data.lock);
  6623. spin_lock_init(&priv->sta_lock);
  6624. spin_lock_init(&priv->hcmd_lock);
  6625. for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
  6626. INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
  6627. INIT_LIST_HEAD(&priv->free_frames);
  6628. mutex_init(&priv->mutex);
  6629. if (pci_enable_device(pdev)) {
  6630. err = -ENODEV;
  6631. goto out_ieee80211_free_hw;
  6632. }
  6633. pci_set_master(pdev);
  6634. /* Clear the driver's (not device's) station table */
  6635. iwl3945_clear_stations_table(priv);
  6636. priv->data_retry_limit = -1;
  6637. priv->ieee_channels = NULL;
  6638. priv->ieee_rates = NULL;
  6639. priv->band = IEEE80211_BAND_2GHZ;
  6640. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  6641. if (!err)
  6642. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  6643. if (err) {
  6644. printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
  6645. goto out_pci_disable_device;
  6646. }
  6647. pci_set_drvdata(pdev, priv);
  6648. err = pci_request_regions(pdev, DRV_NAME);
  6649. if (err)
  6650. goto out_pci_disable_device;
  6651. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  6652. * PCI Tx retries from interfering with C3 CPU state */
  6653. pci_write_config_byte(pdev, 0x41, 0x00);
  6654. priv->hw_base = pci_iomap(pdev, 0, 0);
  6655. if (!priv->hw_base) {
  6656. err = -ENODEV;
  6657. goto out_pci_release_regions;
  6658. }
  6659. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  6660. (unsigned long long) pci_resource_len(pdev, 0));
  6661. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  6662. /* Initialize module parameter values here */
  6663. /* Disable radio (SW RF KILL) via parameter when loading driver */
  6664. if (iwl3945_param_disable) {
  6665. set_bit(STATUS_RF_KILL_SW, &priv->status);
  6666. IWL_DEBUG_INFO("Radio disabled.\n");
  6667. }
  6668. priv->iw_mode = IEEE80211_IF_TYPE_STA;
  6669. printk(KERN_INFO DRV_NAME
  6670. ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name);
  6671. /* Device-specific setup */
  6672. if (iwl3945_hw_set_hw_setting(priv)) {
  6673. IWL_ERROR("failed to set hw settings\n");
  6674. goto out_iounmap;
  6675. }
  6676. if (iwl3945_param_qos_enable)
  6677. priv->qos_data.qos_enable = 1;
  6678. iwl3945_reset_qos(priv);
  6679. priv->qos_data.qos_active = 0;
  6680. priv->qos_data.qos_cap.val = 0;
  6681. iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
  6682. iwl3945_setup_deferred_work(priv);
  6683. iwl3945_setup_rx_handlers(priv);
  6684. priv->rates_mask = IWL_RATES_MASK;
  6685. /* If power management is turned on, default to AC mode */
  6686. priv->power_mode = IWL_POWER_AC;
  6687. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  6688. spin_lock_irqsave(&priv->lock, flags);
  6689. iwl3945_disable_interrupts(priv);
  6690. spin_unlock_irqrestore(&priv->lock, flags);
  6691. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6692. if (err) {
  6693. IWL_ERROR("failed to create sysfs device attributes\n");
  6694. goto out_release_irq;
  6695. }
  6696. /* nic init */
  6697. iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  6698. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  6699. iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  6700. err = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
  6701. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  6702. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  6703. if (err < 0) {
  6704. IWL_DEBUG_INFO("Failed to init the card\n");
  6705. goto out_remove_sysfs;
  6706. }
  6707. /* Read the EEPROM */
  6708. err = iwl3945_eeprom_init(priv);
  6709. if (err) {
  6710. IWL_ERROR("Unable to init EEPROM\n");
  6711. goto out_remove_sysfs;
  6712. }
  6713. /* MAC Address location in EEPROM same for 3945/4965 */
  6714. get_eeprom_mac(priv, priv->mac_addr);
  6715. IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr));
  6716. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  6717. err = iwl3945_init_channel_map(priv);
  6718. if (err) {
  6719. IWL_ERROR("initializing regulatory failed: %d\n", err);
  6720. goto out_remove_sysfs;
  6721. }
  6722. err = iwl3945_init_geos(priv);
  6723. if (err) {
  6724. IWL_ERROR("initializing geos failed: %d\n", err);
  6725. goto out_free_channel_map;
  6726. }
  6727. err = ieee80211_register_hw(priv->hw);
  6728. if (err) {
  6729. IWL_ERROR("Failed to register network device (error %d)\n", err);
  6730. goto out_free_geos;
  6731. }
  6732. priv->hw->conf.beacon_int = 100;
  6733. priv->mac80211_registered = 1;
  6734. pci_save_state(pdev);
  6735. pci_disable_device(pdev);
  6736. err = iwl3945_rfkill_init(priv);
  6737. if (err)
  6738. IWL_ERROR("Unable to initialize RFKILL system. "
  6739. "Ignoring error: %d\n", err);
  6740. return 0;
  6741. out_free_geos:
  6742. iwl3945_free_geos(priv);
  6743. out_free_channel_map:
  6744. iwl3945_free_channel_map(priv);
  6745. out_remove_sysfs:
  6746. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6747. out_release_irq:
  6748. destroy_workqueue(priv->workqueue);
  6749. priv->workqueue = NULL;
  6750. iwl3945_unset_hw_setting(priv);
  6751. out_iounmap:
  6752. pci_iounmap(pdev, priv->hw_base);
  6753. out_pci_release_regions:
  6754. pci_release_regions(pdev);
  6755. out_pci_disable_device:
  6756. pci_disable_device(pdev);
  6757. pci_set_drvdata(pdev, NULL);
  6758. out_ieee80211_free_hw:
  6759. ieee80211_free_hw(priv->hw);
  6760. out:
  6761. return err;
  6762. }
  6763. static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
  6764. {
  6765. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6766. struct list_head *p, *q;
  6767. int i;
  6768. unsigned long flags;
  6769. if (!priv)
  6770. return;
  6771. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  6772. set_bit(STATUS_EXIT_PENDING, &priv->status);
  6773. iwl3945_down(priv);
  6774. /* make sure we flush any pending irq or
  6775. * tasklet for the driver
  6776. */
  6777. spin_lock_irqsave(&priv->lock, flags);
  6778. iwl3945_disable_interrupts(priv);
  6779. spin_unlock_irqrestore(&priv->lock, flags);
  6780. iwl_synchronize_irq(priv);
  6781. /* Free MAC hash list for ADHOC */
  6782. for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) {
  6783. list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) {
  6784. list_del(p);
  6785. kfree(list_entry(p, struct iwl3945_ibss_seq, list));
  6786. }
  6787. }
  6788. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6789. iwl3945_rfkill_unregister(priv);
  6790. iwl3945_dealloc_ucode_pci(priv);
  6791. if (priv->rxq.bd)
  6792. iwl3945_rx_queue_free(priv, &priv->rxq);
  6793. iwl3945_hw_txq_ctx_free(priv);
  6794. iwl3945_unset_hw_setting(priv);
  6795. iwl3945_clear_stations_table(priv);
  6796. if (priv->mac80211_registered) {
  6797. ieee80211_unregister_hw(priv->hw);
  6798. }
  6799. /*netif_stop_queue(dev); */
  6800. flush_workqueue(priv->workqueue);
  6801. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  6802. * priv->workqueue... so we can't take down the workqueue
  6803. * until now... */
  6804. destroy_workqueue(priv->workqueue);
  6805. priv->workqueue = NULL;
  6806. pci_iounmap(pdev, priv->hw_base);
  6807. pci_release_regions(pdev);
  6808. pci_disable_device(pdev);
  6809. pci_set_drvdata(pdev, NULL);
  6810. iwl3945_free_channel_map(priv);
  6811. iwl3945_free_geos(priv);
  6812. kfree(priv->scan);
  6813. if (priv->ibss_beacon)
  6814. dev_kfree_skb(priv->ibss_beacon);
  6815. ieee80211_free_hw(priv->hw);
  6816. }
  6817. #ifdef CONFIG_PM
  6818. static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  6819. {
  6820. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6821. if (priv->is_open) {
  6822. set_bit(STATUS_IN_SUSPEND, &priv->status);
  6823. iwl3945_mac_stop(priv->hw);
  6824. priv->is_open = 1;
  6825. }
  6826. pci_set_power_state(pdev, PCI_D3hot);
  6827. return 0;
  6828. }
  6829. static int iwl3945_pci_resume(struct pci_dev *pdev)
  6830. {
  6831. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6832. pci_set_power_state(pdev, PCI_D0);
  6833. if (priv->is_open)
  6834. iwl3945_mac_start(priv->hw);
  6835. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  6836. return 0;
  6837. }
  6838. #endif /* CONFIG_PM */
  6839. /*************** RFKILL FUNCTIONS **********/
  6840. #ifdef CONFIG_IWL3945_RFKILL
  6841. /* software rf-kill from user */
  6842. static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
  6843. {
  6844. struct iwl3945_priv *priv = data;
  6845. int err = 0;
  6846. if (!priv->rfkill)
  6847. return 0;
  6848. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  6849. return 0;
  6850. IWL_DEBUG_RF_KILL("we recieved soft RFKILL set to state %d\n", state);
  6851. mutex_lock(&priv->mutex);
  6852. switch (state) {
  6853. case RFKILL_STATE_UNBLOCKED:
  6854. if (iwl3945_is_rfkill_hw(priv)) {
  6855. err = -EBUSY;
  6856. goto out_unlock;
  6857. }
  6858. iwl3945_radio_kill_sw(priv, 0);
  6859. break;
  6860. case RFKILL_STATE_SOFT_BLOCKED:
  6861. iwl3945_radio_kill_sw(priv, 1);
  6862. break;
  6863. default:
  6864. IWL_WARNING("we recieved unexpected RFKILL state %d\n", state);
  6865. break;
  6866. }
  6867. out_unlock:
  6868. mutex_unlock(&priv->mutex);
  6869. return err;
  6870. }
  6871. int iwl3945_rfkill_init(struct iwl3945_priv *priv)
  6872. {
  6873. struct device *device = wiphy_dev(priv->hw->wiphy);
  6874. int ret = 0;
  6875. BUG_ON(device == NULL);
  6876. IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
  6877. priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
  6878. if (!priv->rfkill) {
  6879. IWL_ERROR("Unable to allocate rfkill device.\n");
  6880. ret = -ENOMEM;
  6881. goto error;
  6882. }
  6883. priv->rfkill->name = priv->cfg->name;
  6884. priv->rfkill->data = priv;
  6885. priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
  6886. priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
  6887. priv->rfkill->user_claim_unsupported = 1;
  6888. priv->rfkill->dev.class->suspend = NULL;
  6889. priv->rfkill->dev.class->resume = NULL;
  6890. ret = rfkill_register(priv->rfkill);
  6891. if (ret) {
  6892. IWL_ERROR("Unable to register rfkill: %d\n", ret);
  6893. goto freed_rfkill;
  6894. }
  6895. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6896. return ret;
  6897. freed_rfkill:
  6898. if (priv->rfkill != NULL)
  6899. rfkill_free(priv->rfkill);
  6900. priv->rfkill = NULL;
  6901. error:
  6902. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6903. return ret;
  6904. }
  6905. void iwl3945_rfkill_unregister(struct iwl3945_priv *priv)
  6906. {
  6907. if (priv->rfkill)
  6908. rfkill_unregister(priv->rfkill);
  6909. priv->rfkill = NULL;
  6910. }
  6911. /* set rf-kill to the right state. */
  6912. void iwl3945_rfkill_set_hw_state(struct iwl3945_priv *priv)
  6913. {
  6914. if (!priv->rfkill)
  6915. return;
  6916. if (iwl3945_is_rfkill_hw(priv)) {
  6917. rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
  6918. return;
  6919. }
  6920. if (!iwl3945_is_rfkill_sw(priv))
  6921. rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
  6922. else
  6923. rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
  6924. }
  6925. #endif
  6926. /*****************************************************************************
  6927. *
  6928. * driver and module entry point
  6929. *
  6930. *****************************************************************************/
  6931. static struct pci_driver iwl3945_driver = {
  6932. .name = DRV_NAME,
  6933. .id_table = iwl3945_hw_card_ids,
  6934. .probe = iwl3945_pci_probe,
  6935. .remove = __devexit_p(iwl3945_pci_remove),
  6936. #ifdef CONFIG_PM
  6937. .suspend = iwl3945_pci_suspend,
  6938. .resume = iwl3945_pci_resume,
  6939. #endif
  6940. };
  6941. static int __init iwl3945_init(void)
  6942. {
  6943. int ret;
  6944. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  6945. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  6946. ret = iwl3945_rate_control_register();
  6947. if (ret) {
  6948. IWL_ERROR("Unable to register rate control algorithm: %d\n", ret);
  6949. return ret;
  6950. }
  6951. ret = pci_register_driver(&iwl3945_driver);
  6952. if (ret) {
  6953. IWL_ERROR("Unable to initialize PCI module\n");
  6954. goto error_register;
  6955. }
  6956. #ifdef CONFIG_IWL3945_DEBUG
  6957. ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  6958. if (ret) {
  6959. IWL_ERROR("Unable to create driver sysfs file\n");
  6960. goto error_debug;
  6961. }
  6962. #endif
  6963. return ret;
  6964. #ifdef CONFIG_IWL3945_DEBUG
  6965. error_debug:
  6966. pci_unregister_driver(&iwl3945_driver);
  6967. #endif
  6968. error_register:
  6969. iwl3945_rate_control_unregister();
  6970. return ret;
  6971. }
  6972. static void __exit iwl3945_exit(void)
  6973. {
  6974. #ifdef CONFIG_IWL3945_DEBUG
  6975. driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  6976. #endif
  6977. pci_unregister_driver(&iwl3945_driver);
  6978. iwl3945_rate_control_unregister();
  6979. }
  6980. module_param_named(antenna, iwl3945_param_antenna, int, 0444);
  6981. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  6982. module_param_named(disable, iwl3945_param_disable, int, 0444);
  6983. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  6984. module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
  6985. MODULE_PARM_DESC(hwcrypto,
  6986. "using hardware crypto engine (default 0 [software])\n");
  6987. module_param_named(debug, iwl3945_param_debug, int, 0444);
  6988. MODULE_PARM_DESC(debug, "debug output mask");
  6989. module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
  6990. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  6991. module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
  6992. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  6993. /* QoS */
  6994. module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444);
  6995. MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
  6996. module_exit(iwl3945_exit);
  6997. module_init(iwl3945_init);