mb86a20s.c 53 KB

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  1. /*
  2. * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver
  3. *
  4. * Copyright (C) 2010-2013 Mauro Carvalho Chehab <mchehab@redhat.com>
  5. * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation version 2.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. */
  16. #include <linux/kernel.h>
  17. #include <asm/div64.h>
  18. #include "dvb_frontend.h"
  19. #include "mb86a20s.h"
  20. static int debug = 1;
  21. module_param(debug, int, 0644);
  22. MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
  23. enum mb86a20s_bandwidth {
  24. MB86A20S_13SEG = 0,
  25. MB86A20S_13SEG_PARTIAL = 1,
  26. MB86A20S_1SEG = 2,
  27. MB86A20S_3SEG = 3,
  28. };
  29. u8 mb86a20s_subchannel[] = {
  30. 0xb0, 0xc0, 0xd0, 0xe0,
  31. 0xf0, 0x00, 0x10, 0x20,
  32. };
  33. struct mb86a20s_state {
  34. struct i2c_adapter *i2c;
  35. const struct mb86a20s_config *config;
  36. u32 last_frequency;
  37. struct dvb_frontend frontend;
  38. u32 if_freq;
  39. enum mb86a20s_bandwidth bw;
  40. bool inversion;
  41. u32 subchannel;
  42. u32 estimated_rate[3];
  43. unsigned long get_strength_time;
  44. bool need_init;
  45. };
  46. struct regdata {
  47. u8 reg;
  48. u8 data;
  49. };
  50. #define BER_SAMPLING_RATE 1 /* Seconds */
  51. /*
  52. * Initialization sequence: Use whatevere default values that PV SBTVD
  53. * does on its initialisation, obtained via USB snoop
  54. */
  55. static struct regdata mb86a20s_init1[] = {
  56. { 0x70, 0x0f },
  57. { 0x70, 0xff },
  58. { 0x08, 0x01 },
  59. { 0x50, 0xd1 }, { 0x51, 0x20 },
  60. };
  61. static struct regdata mb86a20s_init2[] = {
  62. { 0x28, 0x22 }, { 0x29, 0x00 }, { 0x2a, 0x1f }, { 0x2b, 0xf0 },
  63. { 0x3b, 0x21 },
  64. { 0x3c, 0x38 },
  65. { 0x01, 0x0d },
  66. { 0x04, 0x08 }, { 0x05, 0x03 },
  67. { 0x04, 0x0e }, { 0x05, 0x00 },
  68. { 0x04, 0x0f }, { 0x05, 0x37 },
  69. { 0x04, 0x0b }, { 0x05, 0x78 },
  70. { 0x04, 0x00 }, { 0x05, 0x00 },
  71. { 0x04, 0x01 }, { 0x05, 0x1e },
  72. { 0x04, 0x02 }, { 0x05, 0x07 },
  73. { 0x04, 0x03 }, { 0x05, 0xd0 },
  74. { 0x04, 0x09 }, { 0x05, 0x00 },
  75. { 0x04, 0x0a }, { 0x05, 0xff },
  76. { 0x04, 0x27 }, { 0x05, 0x00 },
  77. { 0x04, 0x28 }, { 0x05, 0x00 },
  78. { 0x04, 0x1e }, { 0x05, 0x00 },
  79. { 0x04, 0x29 }, { 0x05, 0x64 },
  80. { 0x04, 0x32 }, { 0x05, 0x02 },
  81. { 0x04, 0x14 }, { 0x05, 0x02 },
  82. { 0x04, 0x04 }, { 0x05, 0x00 },
  83. { 0x04, 0x05 }, { 0x05, 0x22 },
  84. { 0x04, 0x06 }, { 0x05, 0x0e },
  85. { 0x04, 0x07 }, { 0x05, 0xd8 },
  86. { 0x04, 0x12 }, { 0x05, 0x00 },
  87. { 0x04, 0x13 }, { 0x05, 0xff },
  88. { 0x04, 0x15 }, { 0x05, 0x4e },
  89. { 0x04, 0x16 }, { 0x05, 0x20 },
  90. /*
  91. * On this demod, when the bit count reaches the count below,
  92. * it collects the bit error count. The bit counters are initialized
  93. * to 65535 here. This warrants that all of them will be quickly
  94. * calculated when device gets locked. As TMCC is parsed, the values
  95. * will be adjusted later in the driver's code.
  96. */
  97. { 0x52, 0x01 }, /* Turn on BER before Viterbi */
  98. { 0x50, 0xa7 }, { 0x51, 0x00 },
  99. { 0x50, 0xa8 }, { 0x51, 0xff },
  100. { 0x50, 0xa9 }, { 0x51, 0xff },
  101. { 0x50, 0xaa }, { 0x51, 0x00 },
  102. { 0x50, 0xab }, { 0x51, 0xff },
  103. { 0x50, 0xac }, { 0x51, 0xff },
  104. { 0x50, 0xad }, { 0x51, 0x00 },
  105. { 0x50, 0xae }, { 0x51, 0xff },
  106. { 0x50, 0xaf }, { 0x51, 0xff },
  107. /*
  108. * On this demod, post BER counts blocks. When the count reaches the
  109. * value below, it collects the block error count. The block counters
  110. * are initialized to 127 here. This warrants that all of them will be
  111. * quickly calculated when device gets locked. As TMCC is parsed, the
  112. * values will be adjusted later in the driver's code.
  113. */
  114. { 0x5e, 0x07 }, /* Turn on BER after Viterbi */
  115. { 0x50, 0xdc }, { 0x51, 0x00 },
  116. { 0x50, 0xdd }, { 0x51, 0x7f },
  117. { 0x50, 0xde }, { 0x51, 0x00 },
  118. { 0x50, 0xdf }, { 0x51, 0x7f },
  119. { 0x50, 0xe0 }, { 0x51, 0x00 },
  120. { 0x50, 0xe1 }, { 0x51, 0x7f },
  121. /*
  122. * On this demod, when the block count reaches the count below,
  123. * it collects the block error count. The block counters are initialized
  124. * to 127 here. This warrants that all of them will be quickly
  125. * calculated when device gets locked. As TMCC is parsed, the values
  126. * will be adjusted later in the driver's code.
  127. */
  128. { 0x50, 0xb0 }, { 0x51, 0x07 }, /* Enable PER */
  129. { 0x50, 0xb2 }, { 0x51, 0x00 },
  130. { 0x50, 0xb3 }, { 0x51, 0x7f },
  131. { 0x50, 0xb4 }, { 0x51, 0x00 },
  132. { 0x50, 0xb5 }, { 0x51, 0x7f },
  133. { 0x50, 0xb6 }, { 0x51, 0x00 },
  134. { 0x50, 0xb7 }, { 0x51, 0x7f },
  135. { 0x50, 0x50 }, { 0x51, 0x02 }, /* MER manual mode */
  136. { 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */
  137. { 0x45, 0x04 }, /* CN symbol 4 */
  138. { 0x48, 0x04 }, /* CN manual mode */
  139. { 0x50, 0xd5 }, { 0x51, 0x01 }, /* Serial */
  140. { 0x50, 0xd6 }, { 0x51, 0x1f },
  141. { 0x50, 0xd2 }, { 0x51, 0x03 },
  142. { 0x50, 0xd7 }, { 0x51, 0xbf },
  143. { 0x28, 0x74 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0xff },
  144. { 0x28, 0x46 }, { 0x29, 0x00 }, { 0x2a, 0x1a }, { 0x2b, 0x0c },
  145. { 0x04, 0x40 }, { 0x05, 0x00 },
  146. { 0x28, 0x00 }, { 0x2b, 0x08 },
  147. { 0x28, 0x05 }, { 0x2b, 0x00 },
  148. { 0x1c, 0x01 },
  149. { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x1f },
  150. { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x18 },
  151. { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x12 },
  152. { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x30 },
  153. { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x37 },
  154. { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 },
  155. { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x09 },
  156. { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x06 },
  157. { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x7b },
  158. { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x76 },
  159. { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x7d },
  160. { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x08 },
  161. { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0b },
  162. { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 },
  163. { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xf2 },
  164. { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xf3 },
  165. { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x05 },
  166. { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 },
  167. { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f },
  168. { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xef },
  169. { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xd8 },
  170. { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xf1 },
  171. { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x3d },
  172. { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x94 },
  173. { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0xba },
  174. { 0x50, 0x1e }, { 0x51, 0x5d },
  175. { 0x50, 0x22 }, { 0x51, 0x00 },
  176. { 0x50, 0x23 }, { 0x51, 0xc8 },
  177. { 0x50, 0x24 }, { 0x51, 0x00 },
  178. { 0x50, 0x25 }, { 0x51, 0xf0 },
  179. { 0x50, 0x26 }, { 0x51, 0x00 },
  180. { 0x50, 0x27 }, { 0x51, 0xc3 },
  181. { 0x50, 0x39 }, { 0x51, 0x02 },
  182. { 0xec, 0x0f },
  183. { 0xeb, 0x1f },
  184. { 0x28, 0x6a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 },
  185. { 0xd0, 0x00 },
  186. };
  187. static struct regdata mb86a20s_reset_reception[] = {
  188. { 0x70, 0xf0 },
  189. { 0x70, 0xff },
  190. { 0x08, 0x01 },
  191. { 0x08, 0x00 },
  192. };
  193. static struct regdata mb86a20s_per_ber_reset[] = {
  194. { 0x53, 0x00 }, /* pre BER Counter reset */
  195. { 0x53, 0x07 },
  196. { 0x5f, 0x00 }, /* post BER Counter reset */
  197. { 0x5f, 0x07 },
  198. { 0x50, 0xb1 }, /* PER Counter reset */
  199. { 0x51, 0x07 },
  200. { 0x51, 0x00 },
  201. };
  202. /*
  203. * I2C read/write functions and macros
  204. */
  205. static int mb86a20s_i2c_writereg(struct mb86a20s_state *state,
  206. u8 i2c_addr, u8 reg, u8 data)
  207. {
  208. u8 buf[] = { reg, data };
  209. struct i2c_msg msg = {
  210. .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
  211. };
  212. int rc;
  213. rc = i2c_transfer(state->i2c, &msg, 1);
  214. if (rc != 1) {
  215. dev_err(&state->i2c->dev,
  216. "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n",
  217. __func__, rc, reg, data);
  218. return rc;
  219. }
  220. return 0;
  221. }
  222. static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state,
  223. u8 i2c_addr, struct regdata *rd, int size)
  224. {
  225. int i, rc;
  226. for (i = 0; i < size; i++) {
  227. rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg,
  228. rd[i].data);
  229. if (rc < 0)
  230. return rc;
  231. }
  232. return 0;
  233. }
  234. static int mb86a20s_i2c_readreg(struct mb86a20s_state *state,
  235. u8 i2c_addr, u8 reg)
  236. {
  237. u8 val;
  238. int rc;
  239. struct i2c_msg msg[] = {
  240. { .addr = i2c_addr, .flags = 0, .buf = &reg, .len = 1 },
  241. { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 }
  242. };
  243. rc = i2c_transfer(state->i2c, msg, 2);
  244. if (rc != 2) {
  245. dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n",
  246. __func__, reg, rc);
  247. return (rc < 0) ? rc : -EIO;
  248. }
  249. return val;
  250. }
  251. #define mb86a20s_readreg(state, reg) \
  252. mb86a20s_i2c_readreg(state, state->config->demod_address, reg)
  253. #define mb86a20s_writereg(state, reg, val) \
  254. mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val)
  255. #define mb86a20s_writeregdata(state, regdata) \
  256. mb86a20s_i2c_writeregdata(state, state->config->demod_address, \
  257. regdata, ARRAY_SIZE(regdata))
  258. /*
  259. * Ancillary internal routines (likely compiled inlined)
  260. *
  261. * The functions below assume that gateway lock has already obtained
  262. */
  263. static int mb86a20s_read_status(struct dvb_frontend *fe, fe_status_t *status)
  264. {
  265. struct mb86a20s_state *state = fe->demodulator_priv;
  266. int val;
  267. *status = 0;
  268. val = mb86a20s_readreg(state, 0x0a) & 0xf;
  269. if (val < 0)
  270. return val;
  271. if (val >= 2)
  272. *status |= FE_HAS_SIGNAL;
  273. if (val >= 4)
  274. *status |= FE_HAS_CARRIER;
  275. if (val >= 5)
  276. *status |= FE_HAS_VITERBI;
  277. if (val >= 7)
  278. *status |= FE_HAS_SYNC;
  279. if (val >= 8) /* Maybe 9? */
  280. *status |= FE_HAS_LOCK;
  281. dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n",
  282. __func__, *status, val);
  283. return val;
  284. }
  285. static int mb86a20s_read_signal_strength(struct dvb_frontend *fe)
  286. {
  287. struct mb86a20s_state *state = fe->demodulator_priv;
  288. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  289. int rc;
  290. unsigned rf_max, rf_min, rf;
  291. if (state->get_strength_time &&
  292. (!time_after(jiffies, state->get_strength_time)))
  293. return c->strength.stat[0].uvalue;
  294. /* Reset its value if an error happen */
  295. c->strength.stat[0].uvalue = 0;
  296. /* Does a binary search to get RF strength */
  297. rf_max = 0xfff;
  298. rf_min = 0;
  299. do {
  300. rf = (rf_max + rf_min) / 2;
  301. rc = mb86a20s_writereg(state, 0x04, 0x1f);
  302. if (rc < 0)
  303. return rc;
  304. rc = mb86a20s_writereg(state, 0x05, rf >> 8);
  305. if (rc < 0)
  306. return rc;
  307. rc = mb86a20s_writereg(state, 0x04, 0x20);
  308. if (rc < 0)
  309. return rc;
  310. rc = mb86a20s_writereg(state, 0x05, rf);
  311. if (rc < 0)
  312. return rc;
  313. rc = mb86a20s_readreg(state, 0x02);
  314. if (rc < 0)
  315. return rc;
  316. if (rc & 0x08)
  317. rf_min = (rf_max + rf_min) / 2;
  318. else
  319. rf_max = (rf_max + rf_min) / 2;
  320. if (rf_max - rf_min < 4) {
  321. rf = (rf_max + rf_min) / 2;
  322. /* Rescale it from 2^12 (4096) to 2^16 */
  323. rf = rf << (16 - 12);
  324. if (rf)
  325. rf |= (1 << 12) - 1;
  326. dev_dbg(&state->i2c->dev,
  327. "%s: signal strength = %d (%d < RF=%d < %d)\n",
  328. __func__, rf, rf_min, rf >> 4, rf_max);
  329. c->strength.stat[0].uvalue = rf;
  330. state->get_strength_time = jiffies +
  331. msecs_to_jiffies(1000);
  332. return 0;
  333. }
  334. } while (1);
  335. }
  336. static int mb86a20s_get_modulation(struct mb86a20s_state *state,
  337. unsigned layer)
  338. {
  339. int rc;
  340. static unsigned char reg[] = {
  341. [0] = 0x86, /* Layer A */
  342. [1] = 0x8a, /* Layer B */
  343. [2] = 0x8e, /* Layer C */
  344. };
  345. if (layer >= ARRAY_SIZE(reg))
  346. return -EINVAL;
  347. rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
  348. if (rc < 0)
  349. return rc;
  350. rc = mb86a20s_readreg(state, 0x6e);
  351. if (rc < 0)
  352. return rc;
  353. switch ((rc >> 4) & 0x07) {
  354. case 0:
  355. return DQPSK;
  356. case 1:
  357. return QPSK;
  358. case 2:
  359. return QAM_16;
  360. case 3:
  361. return QAM_64;
  362. default:
  363. return QAM_AUTO;
  364. }
  365. }
  366. static int mb86a20s_get_fec(struct mb86a20s_state *state,
  367. unsigned layer)
  368. {
  369. int rc;
  370. static unsigned char reg[] = {
  371. [0] = 0x87, /* Layer A */
  372. [1] = 0x8b, /* Layer B */
  373. [2] = 0x8f, /* Layer C */
  374. };
  375. if (layer >= ARRAY_SIZE(reg))
  376. return -EINVAL;
  377. rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
  378. if (rc < 0)
  379. return rc;
  380. rc = mb86a20s_readreg(state, 0x6e);
  381. if (rc < 0)
  382. return rc;
  383. switch ((rc >> 4) & 0x07) {
  384. case 0:
  385. return FEC_1_2;
  386. case 1:
  387. return FEC_2_3;
  388. case 2:
  389. return FEC_3_4;
  390. case 3:
  391. return FEC_5_6;
  392. case 4:
  393. return FEC_7_8;
  394. default:
  395. return FEC_AUTO;
  396. }
  397. }
  398. static int mb86a20s_get_interleaving(struct mb86a20s_state *state,
  399. unsigned layer)
  400. {
  401. int rc;
  402. static unsigned char reg[] = {
  403. [0] = 0x88, /* Layer A */
  404. [1] = 0x8c, /* Layer B */
  405. [2] = 0x90, /* Layer C */
  406. };
  407. if (layer >= ARRAY_SIZE(reg))
  408. return -EINVAL;
  409. rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
  410. if (rc < 0)
  411. return rc;
  412. rc = mb86a20s_readreg(state, 0x6e);
  413. if (rc < 0)
  414. return rc;
  415. switch ((rc >> 4) & 0x07) {
  416. case 1:
  417. return GUARD_INTERVAL_1_4;
  418. case 2:
  419. return GUARD_INTERVAL_1_8;
  420. case 3:
  421. return GUARD_INTERVAL_1_16;
  422. case 4:
  423. return GUARD_INTERVAL_1_32;
  424. default:
  425. case 0:
  426. return GUARD_INTERVAL_AUTO;
  427. }
  428. }
  429. static int mb86a20s_get_segment_count(struct mb86a20s_state *state,
  430. unsigned layer)
  431. {
  432. int rc, count;
  433. static unsigned char reg[] = {
  434. [0] = 0x89, /* Layer A */
  435. [1] = 0x8d, /* Layer B */
  436. [2] = 0x91, /* Layer C */
  437. };
  438. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  439. if (layer >= ARRAY_SIZE(reg))
  440. return -EINVAL;
  441. rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
  442. if (rc < 0)
  443. return rc;
  444. rc = mb86a20s_readreg(state, 0x6e);
  445. if (rc < 0)
  446. return rc;
  447. count = (rc >> 4) & 0x0f;
  448. dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count);
  449. return count;
  450. }
  451. static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe)
  452. {
  453. struct mb86a20s_state *state = fe->demodulator_priv;
  454. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  455. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  456. /* Fixed parameters */
  457. c->delivery_system = SYS_ISDBT;
  458. c->bandwidth_hz = 6000000;
  459. /* Initialize values that will be later autodetected */
  460. c->isdbt_layer_enabled = 0;
  461. c->transmission_mode = TRANSMISSION_MODE_AUTO;
  462. c->guard_interval = GUARD_INTERVAL_AUTO;
  463. c->isdbt_sb_mode = 0;
  464. c->isdbt_sb_segment_count = 0;
  465. }
  466. /*
  467. * Estimates the bit rate using the per-segment bit rate given by
  468. * ABNT/NBR 15601 spec (table 4).
  469. */
  470. static u32 isdbt_rate[3][5][4] = {
  471. { /* DQPSK/QPSK */
  472. { 280850, 312060, 330420, 340430 }, /* 1/2 */
  473. { 374470, 416080, 440560, 453910 }, /* 2/3 */
  474. { 421280, 468090, 495630, 510650 }, /* 3/4 */
  475. { 468090, 520100, 550700, 567390 }, /* 5/6 */
  476. { 491500, 546110, 578230, 595760 }, /* 7/8 */
  477. }, { /* QAM16 */
  478. { 561710, 624130, 660840, 680870 }, /* 1/2 */
  479. { 748950, 832170, 881120, 907820 }, /* 2/3 */
  480. { 842570, 936190, 991260, 1021300 }, /* 3/4 */
  481. { 936190, 1040210, 1101400, 1134780 }, /* 5/6 */
  482. { 983000, 1092220, 1156470, 1191520 }, /* 7/8 */
  483. }, { /* QAM64 */
  484. { 842570, 936190, 991260, 1021300 }, /* 1/2 */
  485. { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */
  486. { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */
  487. { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */
  488. { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */
  489. }
  490. };
  491. static void mb86a20s_layer_bitrate(struct dvb_frontend *fe, u32 layer,
  492. u32 modulation, u32 fec, u32 interleaving,
  493. u32 segment)
  494. {
  495. struct mb86a20s_state *state = fe->demodulator_priv;
  496. u32 rate;
  497. int m, f, i;
  498. /*
  499. * If modulation/fec/interleaving is not detected, the default is
  500. * to consider the lowest bit rate, to avoid taking too long time
  501. * to get BER.
  502. */
  503. switch (modulation) {
  504. case DQPSK:
  505. case QPSK:
  506. default:
  507. m = 0;
  508. break;
  509. case QAM_16:
  510. m = 1;
  511. break;
  512. case QAM_64:
  513. m = 2;
  514. break;
  515. }
  516. switch (fec) {
  517. default:
  518. case FEC_1_2:
  519. case FEC_AUTO:
  520. f = 0;
  521. break;
  522. case FEC_2_3:
  523. f = 1;
  524. break;
  525. case FEC_3_4:
  526. f = 2;
  527. break;
  528. case FEC_5_6:
  529. f = 3;
  530. break;
  531. case FEC_7_8:
  532. f = 4;
  533. break;
  534. }
  535. switch (interleaving) {
  536. default:
  537. case GUARD_INTERVAL_1_4:
  538. i = 0;
  539. break;
  540. case GUARD_INTERVAL_1_8:
  541. i = 1;
  542. break;
  543. case GUARD_INTERVAL_1_16:
  544. i = 2;
  545. break;
  546. case GUARD_INTERVAL_1_32:
  547. i = 3;
  548. break;
  549. }
  550. /* Samples BER at BER_SAMPLING_RATE seconds */
  551. rate = isdbt_rate[m][f][i] * segment * BER_SAMPLING_RATE;
  552. /* Avoids sampling too quickly or to overflow the register */
  553. if (rate < 256)
  554. rate = 256;
  555. else if (rate > (1 << 24) - 1)
  556. rate = (1 << 24) - 1;
  557. dev_dbg(&state->i2c->dev,
  558. "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n",
  559. __func__, 'A' + layer, segment * isdbt_rate[m][f][i]/1000,
  560. rate, rate);
  561. state->estimated_rate[i] = rate;
  562. }
  563. static int mb86a20s_get_frontend(struct dvb_frontend *fe)
  564. {
  565. struct mb86a20s_state *state = fe->demodulator_priv;
  566. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  567. int i, rc;
  568. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  569. /* Reset frontend cache to default values */
  570. mb86a20s_reset_frontend_cache(fe);
  571. /* Check for partial reception */
  572. rc = mb86a20s_writereg(state, 0x6d, 0x85);
  573. if (rc < 0)
  574. return rc;
  575. rc = mb86a20s_readreg(state, 0x6e);
  576. if (rc < 0)
  577. return rc;
  578. c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0;
  579. /* Get per-layer data */
  580. for (i = 0; i < 3; i++) {
  581. dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n",
  582. __func__, 'A' + i);
  583. rc = mb86a20s_get_segment_count(state, i);
  584. if (rc < 0)
  585. goto noperlayer_error;
  586. if (rc >= 0 && rc < 14) {
  587. c->layer[i].segment_count = rc;
  588. } else {
  589. c->layer[i].segment_count = 0;
  590. state->estimated_rate[i] = 0;
  591. continue;
  592. }
  593. c->isdbt_layer_enabled |= 1 << i;
  594. rc = mb86a20s_get_modulation(state, i);
  595. if (rc < 0)
  596. goto noperlayer_error;
  597. dev_dbg(&state->i2c->dev, "%s: modulation %d.\n",
  598. __func__, rc);
  599. c->layer[i].modulation = rc;
  600. rc = mb86a20s_get_fec(state, i);
  601. if (rc < 0)
  602. goto noperlayer_error;
  603. dev_dbg(&state->i2c->dev, "%s: FEC %d.\n",
  604. __func__, rc);
  605. c->layer[i].fec = rc;
  606. rc = mb86a20s_get_interleaving(state, i);
  607. if (rc < 0)
  608. goto noperlayer_error;
  609. dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n",
  610. __func__, rc);
  611. c->layer[i].interleaving = rc;
  612. mb86a20s_layer_bitrate(fe, i, c->layer[i].modulation,
  613. c->layer[i].fec,
  614. c->layer[i].interleaving,
  615. c->layer[i].segment_count);
  616. }
  617. rc = mb86a20s_writereg(state, 0x6d, 0x84);
  618. if (rc < 0)
  619. return rc;
  620. if ((rc & 0x60) == 0x20) {
  621. c->isdbt_sb_mode = 1;
  622. /* At least, one segment should exist */
  623. if (!c->isdbt_sb_segment_count)
  624. c->isdbt_sb_segment_count = 1;
  625. }
  626. /* Get transmission mode and guard interval */
  627. rc = mb86a20s_readreg(state, 0x07);
  628. if (rc < 0)
  629. return rc;
  630. if ((rc & 0x60) == 0x20) {
  631. switch (rc & 0x0c >> 2) {
  632. case 0:
  633. c->transmission_mode = TRANSMISSION_MODE_2K;
  634. break;
  635. case 1:
  636. c->transmission_mode = TRANSMISSION_MODE_4K;
  637. break;
  638. case 2:
  639. c->transmission_mode = TRANSMISSION_MODE_8K;
  640. break;
  641. }
  642. }
  643. if (!(rc & 0x10)) {
  644. switch (rc & 0x3) {
  645. case 0:
  646. c->guard_interval = GUARD_INTERVAL_1_4;
  647. break;
  648. case 1:
  649. c->guard_interval = GUARD_INTERVAL_1_8;
  650. break;
  651. case 2:
  652. c->guard_interval = GUARD_INTERVAL_1_16;
  653. break;
  654. }
  655. }
  656. return 0;
  657. noperlayer_error:
  658. /* per-layer info is incomplete; discard all per-layer */
  659. c->isdbt_layer_enabled = 0;
  660. return rc;
  661. }
  662. static int mb86a20s_reset_counters(struct dvb_frontend *fe)
  663. {
  664. struct mb86a20s_state *state = fe->demodulator_priv;
  665. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  666. int rc, val;
  667. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  668. /* Reset the counters, if the channel changed */
  669. if (state->last_frequency != c->frequency) {
  670. memset(&c->cnr, 0, sizeof(c->cnr));
  671. memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error));
  672. memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count));
  673. memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
  674. memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
  675. memset(&c->block_error, 0, sizeof(c->block_error));
  676. memset(&c->block_count, 0, sizeof(c->block_count));
  677. state->last_frequency = c->frequency;
  678. }
  679. /* Clear status for most stats */
  680. /* BER/PER counter reset */
  681. rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset);
  682. if (rc < 0)
  683. goto err;
  684. /* CNR counter reset */
  685. rc = mb86a20s_readreg(state, 0x45);
  686. if (rc < 0)
  687. goto err;
  688. val = rc;
  689. rc = mb86a20s_writereg(state, 0x45, val | 0x10);
  690. if (rc < 0)
  691. goto err;
  692. rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
  693. if (rc < 0)
  694. goto err;
  695. /* MER counter reset */
  696. rc = mb86a20s_writereg(state, 0x50, 0x50);
  697. if (rc < 0)
  698. goto err;
  699. rc = mb86a20s_readreg(state, 0x51);
  700. if (rc < 0)
  701. goto err;
  702. val = rc;
  703. rc = mb86a20s_writereg(state, 0x51, val | 0x01);
  704. if (rc < 0)
  705. goto err;
  706. rc = mb86a20s_writereg(state, 0x51, val & 0x06);
  707. if (rc < 0)
  708. goto err;
  709. goto ok;
  710. err:
  711. dev_err(&state->i2c->dev,
  712. "%s: Can't reset FE statistics (error %d).\n",
  713. __func__, rc);
  714. ok:
  715. return rc;
  716. }
  717. static int mb86a20s_get_pre_ber(struct dvb_frontend *fe,
  718. unsigned layer,
  719. u32 *error, u32 *count)
  720. {
  721. struct mb86a20s_state *state = fe->demodulator_priv;
  722. int rc, val;
  723. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  724. if (layer >= 3)
  725. return -EINVAL;
  726. /* Check if the BER measures are already available */
  727. rc = mb86a20s_readreg(state, 0x54);
  728. if (rc < 0)
  729. return rc;
  730. /* Check if data is available for that layer */
  731. if (!(rc & (1 << layer))) {
  732. dev_dbg(&state->i2c->dev,
  733. "%s: preBER for layer %c is not available yet.\n",
  734. __func__, 'A' + layer);
  735. return -EBUSY;
  736. }
  737. /* Read Bit Error Count */
  738. rc = mb86a20s_readreg(state, 0x55 + layer * 3);
  739. if (rc < 0)
  740. return rc;
  741. *error = rc << 16;
  742. rc = mb86a20s_readreg(state, 0x56 + layer * 3);
  743. if (rc < 0)
  744. return rc;
  745. *error |= rc << 8;
  746. rc = mb86a20s_readreg(state, 0x57 + layer * 3);
  747. if (rc < 0)
  748. return rc;
  749. *error |= rc;
  750. dev_dbg(&state->i2c->dev,
  751. "%s: bit error before Viterbi for layer %c: %d.\n",
  752. __func__, 'A' + layer, *error);
  753. /* Read Bit Count */
  754. rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
  755. if (rc < 0)
  756. return rc;
  757. rc = mb86a20s_readreg(state, 0x51);
  758. if (rc < 0)
  759. return rc;
  760. *count = rc << 16;
  761. rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
  762. if (rc < 0)
  763. return rc;
  764. rc = mb86a20s_readreg(state, 0x51);
  765. if (rc < 0)
  766. return rc;
  767. *count |= rc << 8;
  768. rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
  769. if (rc < 0)
  770. return rc;
  771. rc = mb86a20s_readreg(state, 0x51);
  772. if (rc < 0)
  773. return rc;
  774. *count |= rc;
  775. dev_dbg(&state->i2c->dev,
  776. "%s: bit count before Viterbi for layer %c: %d.\n",
  777. __func__, 'A' + layer, *count);
  778. /*
  779. * As we get TMCC data from the frontend, we can better estimate the
  780. * BER bit counters, in order to do the BER measure during a longer
  781. * time. Use those data, if available, to update the bit count
  782. * measure.
  783. */
  784. if (state->estimated_rate[layer]
  785. && state->estimated_rate[layer] != *count) {
  786. dev_dbg(&state->i2c->dev,
  787. "%s: updating layer %c preBER counter to %d.\n",
  788. __func__, 'A' + layer, state->estimated_rate[layer]);
  789. /* Turn off BER before Viterbi */
  790. rc = mb86a20s_writereg(state, 0x52, 0x00);
  791. /* Update counter for this layer */
  792. rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
  793. if (rc < 0)
  794. return rc;
  795. rc = mb86a20s_writereg(state, 0x51,
  796. state->estimated_rate[layer] >> 16);
  797. if (rc < 0)
  798. return rc;
  799. rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
  800. if (rc < 0)
  801. return rc;
  802. rc = mb86a20s_writereg(state, 0x51,
  803. state->estimated_rate[layer] >> 8);
  804. if (rc < 0)
  805. return rc;
  806. rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
  807. if (rc < 0)
  808. return rc;
  809. rc = mb86a20s_writereg(state, 0x51,
  810. state->estimated_rate[layer]);
  811. if (rc < 0)
  812. return rc;
  813. /* Turn on BER before Viterbi */
  814. rc = mb86a20s_writereg(state, 0x52, 0x01);
  815. /* Reset all preBER counters */
  816. rc = mb86a20s_writereg(state, 0x53, 0x00);
  817. if (rc < 0)
  818. return rc;
  819. rc = mb86a20s_writereg(state, 0x53, 0x07);
  820. } else {
  821. /* Reset counter to collect new data */
  822. rc = mb86a20s_readreg(state, 0x53);
  823. if (rc < 0)
  824. return rc;
  825. val = rc;
  826. rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer));
  827. if (rc < 0)
  828. return rc;
  829. rc = mb86a20s_writereg(state, 0x53, val | (1 << layer));
  830. }
  831. return rc;
  832. }
  833. static int mb86a20s_get_post_ber(struct dvb_frontend *fe,
  834. unsigned layer,
  835. u32 *error, u32 *count)
  836. {
  837. struct mb86a20s_state *state = fe->demodulator_priv;
  838. u32 counter, collect_rate;
  839. int rc, val;
  840. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  841. if (layer >= 3)
  842. return -EINVAL;
  843. /* Check if the BER measures are already available */
  844. rc = mb86a20s_readreg(state, 0x60);
  845. if (rc < 0)
  846. return rc;
  847. /* Check if data is available for that layer */
  848. if (!(rc & (1 << layer))) {
  849. dev_dbg(&state->i2c->dev,
  850. "%s: post BER for layer %c is not available yet.\n",
  851. __func__, 'A' + layer);
  852. return -EBUSY;
  853. }
  854. /* Read Bit Error Count */
  855. rc = mb86a20s_readreg(state, 0x64 + layer * 3);
  856. if (rc < 0)
  857. return rc;
  858. *error = rc << 16;
  859. rc = mb86a20s_readreg(state, 0x65 + layer * 3);
  860. if (rc < 0)
  861. return rc;
  862. *error |= rc << 8;
  863. rc = mb86a20s_readreg(state, 0x66 + layer * 3);
  864. if (rc < 0)
  865. return rc;
  866. *error |= rc;
  867. dev_dbg(&state->i2c->dev,
  868. "%s: post bit error for layer %c: %d.\n",
  869. __func__, 'A' + layer, *error);
  870. /* Read Bit Count */
  871. rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
  872. if (rc < 0)
  873. return rc;
  874. rc = mb86a20s_readreg(state, 0x51);
  875. if (rc < 0)
  876. return rc;
  877. counter = rc << 8;
  878. rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
  879. if (rc < 0)
  880. return rc;
  881. rc = mb86a20s_readreg(state, 0x51);
  882. if (rc < 0)
  883. return rc;
  884. counter |= rc;
  885. *count = counter * 204 * 8;
  886. dev_dbg(&state->i2c->dev,
  887. "%s: post bit count for layer %c: %d.\n",
  888. __func__, 'A' + layer, *count);
  889. /*
  890. * As we get TMCC data from the frontend, we can better estimate the
  891. * BER bit counters, in order to do the BER measure during a longer
  892. * time. Use those data, if available, to update the bit count
  893. * measure.
  894. */
  895. if (!state->estimated_rate[layer])
  896. goto reset_measurement;
  897. collect_rate = state->estimated_rate[layer] / 204 / 8;
  898. if (collect_rate < 32)
  899. collect_rate = 32;
  900. if (collect_rate > 65535)
  901. collect_rate = 65535;
  902. if (collect_rate != counter) {
  903. dev_dbg(&state->i2c->dev,
  904. "%s: updating postBER counter on layer %c to %d.\n",
  905. __func__, 'A' + layer, collect_rate);
  906. /* Turn off BER after Viterbi */
  907. rc = mb86a20s_writereg(state, 0x5e, 0x00);
  908. /* Update counter for this layer */
  909. rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
  910. if (rc < 0)
  911. return rc;
  912. rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
  913. if (rc < 0)
  914. return rc;
  915. rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
  916. if (rc < 0)
  917. return rc;
  918. rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
  919. if (rc < 0)
  920. return rc;
  921. /* Turn on BER after Viterbi */
  922. rc = mb86a20s_writereg(state, 0x5e, 0x07);
  923. /* Reset all preBER counters */
  924. rc = mb86a20s_writereg(state, 0x5f, 0x00);
  925. if (rc < 0)
  926. return rc;
  927. rc = mb86a20s_writereg(state, 0x5f, 0x07);
  928. return rc;
  929. }
  930. reset_measurement:
  931. /* Reset counter to collect new data */
  932. rc = mb86a20s_readreg(state, 0x5f);
  933. if (rc < 0)
  934. return rc;
  935. val = rc;
  936. rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer));
  937. if (rc < 0)
  938. return rc;
  939. rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer));
  940. return rc;
  941. }
  942. static int mb86a20s_get_blk_error(struct dvb_frontend *fe,
  943. unsigned layer,
  944. u32 *error, u32 *count)
  945. {
  946. struct mb86a20s_state *state = fe->demodulator_priv;
  947. int rc, val;
  948. u32 collect_rate;
  949. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  950. if (layer >= 3)
  951. return -EINVAL;
  952. /* Check if the PER measures are already available */
  953. rc = mb86a20s_writereg(state, 0x50, 0xb8);
  954. if (rc < 0)
  955. return rc;
  956. rc = mb86a20s_readreg(state, 0x51);
  957. if (rc < 0)
  958. return rc;
  959. /* Check if data is available for that layer */
  960. if (!(rc & (1 << layer))) {
  961. dev_dbg(&state->i2c->dev,
  962. "%s: block counts for layer %c aren't available yet.\n",
  963. __func__, 'A' + layer);
  964. return -EBUSY;
  965. }
  966. /* Read Packet error Count */
  967. rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2);
  968. if (rc < 0)
  969. return rc;
  970. rc = mb86a20s_readreg(state, 0x51);
  971. if (rc < 0)
  972. return rc;
  973. *error = rc << 8;
  974. rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2);
  975. if (rc < 0)
  976. return rc;
  977. rc = mb86a20s_readreg(state, 0x51);
  978. if (rc < 0)
  979. return rc;
  980. *error |= rc;
  981. dev_dbg(&state->i2c->dev, "%s: block error for layer %c: %d.\n",
  982. __func__, 'A' + layer, *error);
  983. /* Read Bit Count */
  984. rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
  985. if (rc < 0)
  986. return rc;
  987. rc = mb86a20s_readreg(state, 0x51);
  988. if (rc < 0)
  989. return rc;
  990. *count = rc << 8;
  991. rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
  992. if (rc < 0)
  993. return rc;
  994. rc = mb86a20s_readreg(state, 0x51);
  995. if (rc < 0)
  996. return rc;
  997. *count |= rc;
  998. dev_dbg(&state->i2c->dev,
  999. "%s: block count for layer %c: %d.\n",
  1000. __func__, 'A' + layer, *count);
  1001. /*
  1002. * As we get TMCC data from the frontend, we can better estimate the
  1003. * BER bit counters, in order to do the BER measure during a longer
  1004. * time. Use those data, if available, to update the bit count
  1005. * measure.
  1006. */
  1007. if (!state->estimated_rate[layer])
  1008. goto reset_measurement;
  1009. collect_rate = state->estimated_rate[layer] / 204 / 8;
  1010. if (collect_rate < 32)
  1011. collect_rate = 32;
  1012. if (collect_rate > 65535)
  1013. collect_rate = 65535;
  1014. if (collect_rate != *count) {
  1015. dev_dbg(&state->i2c->dev,
  1016. "%s: updating PER counter on layer %c to %d.\n",
  1017. __func__, 'A' + layer, collect_rate);
  1018. /* Stop PER measurement */
  1019. rc = mb86a20s_writereg(state, 0x50, 0xb0);
  1020. if (rc < 0)
  1021. return rc;
  1022. rc = mb86a20s_writereg(state, 0x51, 0x00);
  1023. if (rc < 0)
  1024. return rc;
  1025. /* Update this layer's counter */
  1026. rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
  1027. if (rc < 0)
  1028. return rc;
  1029. rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
  1030. if (rc < 0)
  1031. return rc;
  1032. rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
  1033. if (rc < 0)
  1034. return rc;
  1035. rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
  1036. if (rc < 0)
  1037. return rc;
  1038. /* start PER measurement */
  1039. rc = mb86a20s_writereg(state, 0x50, 0xb0);
  1040. if (rc < 0)
  1041. return rc;
  1042. rc = mb86a20s_writereg(state, 0x51, 0x07);
  1043. if (rc < 0)
  1044. return rc;
  1045. /* Reset all counters to collect new data */
  1046. rc = mb86a20s_writereg(state, 0x50, 0xb1);
  1047. if (rc < 0)
  1048. return rc;
  1049. rc = mb86a20s_writereg(state, 0x51, 0x07);
  1050. if (rc < 0)
  1051. return rc;
  1052. rc = mb86a20s_writereg(state, 0x51, 0x00);
  1053. return rc;
  1054. }
  1055. reset_measurement:
  1056. /* Reset counter to collect new data */
  1057. rc = mb86a20s_writereg(state, 0x50, 0xb1);
  1058. if (rc < 0)
  1059. return rc;
  1060. rc = mb86a20s_readreg(state, 0x51);
  1061. if (rc < 0)
  1062. return rc;
  1063. val = rc;
  1064. rc = mb86a20s_writereg(state, 0x51, val | (1 << layer));
  1065. if (rc < 0)
  1066. return rc;
  1067. rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer));
  1068. return rc;
  1069. }
  1070. struct linear_segments {
  1071. unsigned x, y;
  1072. };
  1073. /*
  1074. * All tables below return a dB/1000 measurement
  1075. */
  1076. static struct linear_segments cnr_to_db_table[] = {
  1077. { 19648, 0},
  1078. { 18187, 1000},
  1079. { 16534, 2000},
  1080. { 14823, 3000},
  1081. { 13161, 4000},
  1082. { 11622, 5000},
  1083. { 10279, 6000},
  1084. { 9089, 7000},
  1085. { 8042, 8000},
  1086. { 7137, 9000},
  1087. { 6342, 10000},
  1088. { 5641, 11000},
  1089. { 5030, 12000},
  1090. { 4474, 13000},
  1091. { 3988, 14000},
  1092. { 3556, 15000},
  1093. { 3180, 16000},
  1094. { 2841, 17000},
  1095. { 2541, 18000},
  1096. { 2276, 19000},
  1097. { 2038, 20000},
  1098. { 1800, 21000},
  1099. { 1625, 22000},
  1100. { 1462, 23000},
  1101. { 1324, 24000},
  1102. { 1175, 25000},
  1103. { 1063, 26000},
  1104. { 980, 27000},
  1105. { 907, 28000},
  1106. { 840, 29000},
  1107. { 788, 30000},
  1108. };
  1109. static struct linear_segments cnr_64qam_table[] = {
  1110. { 3922688, 0},
  1111. { 3920384, 1000},
  1112. { 3902720, 2000},
  1113. { 3894784, 3000},
  1114. { 3882496, 4000},
  1115. { 3872768, 5000},
  1116. { 3858944, 6000},
  1117. { 3851520, 7000},
  1118. { 3838976, 8000},
  1119. { 3829248, 9000},
  1120. { 3818240, 10000},
  1121. { 3806976, 11000},
  1122. { 3791872, 12000},
  1123. { 3767040, 13000},
  1124. { 3720960, 14000},
  1125. { 3637504, 15000},
  1126. { 3498496, 16000},
  1127. { 3296000, 17000},
  1128. { 3031040, 18000},
  1129. { 2715392, 19000},
  1130. { 2362624, 20000},
  1131. { 1963264, 21000},
  1132. { 1649664, 22000},
  1133. { 1366784, 23000},
  1134. { 1120768, 24000},
  1135. { 890880, 25000},
  1136. { 723456, 26000},
  1137. { 612096, 27000},
  1138. { 518912, 28000},
  1139. { 448256, 29000},
  1140. { 388864, 30000},
  1141. };
  1142. static struct linear_segments cnr_16qam_table[] = {
  1143. { 5314816, 0},
  1144. { 5219072, 1000},
  1145. { 5118720, 2000},
  1146. { 4998912, 3000},
  1147. { 4875520, 4000},
  1148. { 4736000, 5000},
  1149. { 4604160, 6000},
  1150. { 4458752, 7000},
  1151. { 4300288, 8000},
  1152. { 4092928, 9000},
  1153. { 3836160, 10000},
  1154. { 3521024, 11000},
  1155. { 3155968, 12000},
  1156. { 2756864, 13000},
  1157. { 2347008, 14000},
  1158. { 1955072, 15000},
  1159. { 1593600, 16000},
  1160. { 1297920, 17000},
  1161. { 1043968, 18000},
  1162. { 839680, 19000},
  1163. { 672256, 20000},
  1164. { 523008, 21000},
  1165. { 424704, 22000},
  1166. { 345088, 23000},
  1167. { 280064, 24000},
  1168. { 221440, 25000},
  1169. { 179712, 26000},
  1170. { 151040, 27000},
  1171. { 128512, 28000},
  1172. { 110080, 29000},
  1173. { 95744, 30000},
  1174. };
  1175. struct linear_segments cnr_qpsk_table[] = {
  1176. { 2834176, 0},
  1177. { 2683648, 1000},
  1178. { 2536960, 2000},
  1179. { 2391808, 3000},
  1180. { 2133248, 4000},
  1181. { 1906176, 5000},
  1182. { 1666560, 6000},
  1183. { 1422080, 7000},
  1184. { 1189632, 8000},
  1185. { 976384, 9000},
  1186. { 790272, 10000},
  1187. { 633344, 11000},
  1188. { 505600, 12000},
  1189. { 402944, 13000},
  1190. { 320768, 14000},
  1191. { 255488, 15000},
  1192. { 204032, 16000},
  1193. { 163072, 17000},
  1194. { 130304, 18000},
  1195. { 105216, 19000},
  1196. { 83456, 20000},
  1197. { 65024, 21000},
  1198. { 52480, 22000},
  1199. { 42752, 23000},
  1200. { 34560, 24000},
  1201. { 27136, 25000},
  1202. { 22016, 26000},
  1203. { 18432, 27000},
  1204. { 15616, 28000},
  1205. { 13312, 29000},
  1206. { 11520, 30000},
  1207. };
  1208. static u32 interpolate_value(u32 value, struct linear_segments *segments,
  1209. unsigned len)
  1210. {
  1211. u64 tmp64;
  1212. u32 dx, dy;
  1213. int i, ret;
  1214. if (value >= segments[0].x)
  1215. return segments[0].y;
  1216. if (value < segments[len-1].x)
  1217. return segments[len-1].y;
  1218. for (i = 1; i < len - 1; i++) {
  1219. /* If value is identical, no need to interpolate */
  1220. if (value == segments[i].x)
  1221. return segments[i].y;
  1222. if (value > segments[i].x)
  1223. break;
  1224. }
  1225. /* Linear interpolation between the two (x,y) points */
  1226. dy = segments[i].y - segments[i - 1].y;
  1227. dx = segments[i - 1].x - segments[i].x;
  1228. tmp64 = value - segments[i].x;
  1229. tmp64 *= dy;
  1230. do_div(tmp64, dx);
  1231. ret = segments[i].y - tmp64;
  1232. return ret;
  1233. }
  1234. static int mb86a20s_get_main_CNR(struct dvb_frontend *fe)
  1235. {
  1236. struct mb86a20s_state *state = fe->demodulator_priv;
  1237. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  1238. u32 cnr_linear, cnr;
  1239. int rc, val;
  1240. /* Check if CNR is available */
  1241. rc = mb86a20s_readreg(state, 0x45);
  1242. if (rc < 0)
  1243. return rc;
  1244. if (!(rc & 0x40)) {
  1245. dev_dbg(&state->i2c->dev, "%s: CNR is not available yet.\n",
  1246. __func__);
  1247. return -EBUSY;
  1248. }
  1249. val = rc;
  1250. rc = mb86a20s_readreg(state, 0x46);
  1251. if (rc < 0)
  1252. return rc;
  1253. cnr_linear = rc << 8;
  1254. rc = mb86a20s_readreg(state, 0x46);
  1255. if (rc < 0)
  1256. return rc;
  1257. cnr_linear |= rc;
  1258. cnr = interpolate_value(cnr_linear,
  1259. cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table));
  1260. c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
  1261. c->cnr.stat[0].svalue = cnr;
  1262. dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n",
  1263. __func__, cnr / 1000, cnr % 1000, cnr_linear);
  1264. /* CNR counter reset */
  1265. rc = mb86a20s_writereg(state, 0x45, val | 0x10);
  1266. if (rc < 0)
  1267. return rc;
  1268. rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
  1269. return rc;
  1270. }
  1271. static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe)
  1272. {
  1273. struct mb86a20s_state *state = fe->demodulator_priv;
  1274. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  1275. u32 mer, cnr;
  1276. int rc, val, i;
  1277. struct linear_segments *segs;
  1278. unsigned segs_len;
  1279. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  1280. /* Check if the measures are already available */
  1281. rc = mb86a20s_writereg(state, 0x50, 0x5b);
  1282. if (rc < 0)
  1283. return rc;
  1284. rc = mb86a20s_readreg(state, 0x51);
  1285. if (rc < 0)
  1286. return rc;
  1287. /* Check if data is available */
  1288. if (!(rc & 0x01)) {
  1289. dev_dbg(&state->i2c->dev,
  1290. "%s: MER measures aren't available yet.\n", __func__);
  1291. return -EBUSY;
  1292. }
  1293. /* Read all layers */
  1294. for (i = 0; i < 3; i++) {
  1295. if (!(c->isdbt_layer_enabled & (1 << i))) {
  1296. c->cnr.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
  1297. continue;
  1298. }
  1299. rc = mb86a20s_writereg(state, 0x50, 0x52 + i * 3);
  1300. if (rc < 0)
  1301. return rc;
  1302. rc = mb86a20s_readreg(state, 0x51);
  1303. if (rc < 0)
  1304. return rc;
  1305. mer = rc << 16;
  1306. rc = mb86a20s_writereg(state, 0x50, 0x53 + i * 3);
  1307. if (rc < 0)
  1308. return rc;
  1309. rc = mb86a20s_readreg(state, 0x51);
  1310. if (rc < 0)
  1311. return rc;
  1312. mer |= rc << 8;
  1313. rc = mb86a20s_writereg(state, 0x50, 0x54 + i * 3);
  1314. if (rc < 0)
  1315. return rc;
  1316. rc = mb86a20s_readreg(state, 0x51);
  1317. if (rc < 0)
  1318. return rc;
  1319. mer |= rc;
  1320. switch (c->layer[i].modulation) {
  1321. case DQPSK:
  1322. case QPSK:
  1323. segs = cnr_qpsk_table;
  1324. segs_len = ARRAY_SIZE(cnr_qpsk_table);
  1325. break;
  1326. case QAM_16:
  1327. segs = cnr_16qam_table;
  1328. segs_len = ARRAY_SIZE(cnr_16qam_table);
  1329. break;
  1330. default:
  1331. case QAM_64:
  1332. segs = cnr_64qam_table;
  1333. segs_len = ARRAY_SIZE(cnr_64qam_table);
  1334. break;
  1335. }
  1336. cnr = interpolate_value(mer, segs, segs_len);
  1337. c->cnr.stat[1 + i].scale = FE_SCALE_DECIBEL;
  1338. c->cnr.stat[1 + i].svalue = cnr;
  1339. dev_dbg(&state->i2c->dev,
  1340. "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n",
  1341. __func__, 'A' + i, cnr / 1000, cnr % 1000, mer);
  1342. }
  1343. /* Start a new MER measurement */
  1344. /* MER counter reset */
  1345. rc = mb86a20s_writereg(state, 0x50, 0x50);
  1346. if (rc < 0)
  1347. return rc;
  1348. rc = mb86a20s_readreg(state, 0x51);
  1349. if (rc < 0)
  1350. return rc;
  1351. val = rc;
  1352. rc = mb86a20s_writereg(state, 0x51, val | 0x01);
  1353. if (rc < 0)
  1354. return rc;
  1355. rc = mb86a20s_writereg(state, 0x51, val & 0x06);
  1356. if (rc < 0)
  1357. return rc;
  1358. return 0;
  1359. }
  1360. static void mb86a20s_stats_not_ready(struct dvb_frontend *fe)
  1361. {
  1362. struct mb86a20s_state *state = fe->demodulator_priv;
  1363. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  1364. int i;
  1365. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  1366. /* Fill the length of each status counter */
  1367. /* Only global stats */
  1368. c->strength.len = 1;
  1369. /* Per-layer stats - 3 layers + global */
  1370. c->cnr.len = 4;
  1371. c->pre_bit_error.len = 4;
  1372. c->pre_bit_count.len = 4;
  1373. c->post_bit_error.len = 4;
  1374. c->post_bit_count.len = 4;
  1375. c->block_error.len = 4;
  1376. c->block_count.len = 4;
  1377. /* Signal is always available */
  1378. c->strength.stat[0].scale = FE_SCALE_RELATIVE;
  1379. c->strength.stat[0].uvalue = 0;
  1380. /* Put all of them at FE_SCALE_NOT_AVAILABLE */
  1381. for (i = 0; i < 4; i++) {
  1382. c->cnr.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
  1383. c->pre_bit_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
  1384. c->pre_bit_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
  1385. c->post_bit_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
  1386. c->post_bit_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
  1387. c->block_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
  1388. c->block_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
  1389. }
  1390. }
  1391. static int mb86a20s_get_stats(struct dvb_frontend *fe, int status_nr)
  1392. {
  1393. struct mb86a20s_state *state = fe->demodulator_priv;
  1394. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  1395. int rc = 0, i;
  1396. u32 bit_error = 0, bit_count = 0;
  1397. u32 t_pre_bit_error = 0, t_pre_bit_count = 0;
  1398. u32 t_post_bit_error = 0, t_post_bit_count = 0;
  1399. u32 block_error = 0, block_count = 0;
  1400. u32 t_block_error = 0, t_block_count = 0;
  1401. int active_layers = 0, pre_ber_layers = 0, post_ber_layers = 0;
  1402. int per_layers = 0;
  1403. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  1404. mb86a20s_get_main_CNR(fe);
  1405. /* Get per-layer stats */
  1406. mb86a20s_get_blk_error_layer_CNR(fe);
  1407. /*
  1408. * At state 7, only CNR is available
  1409. * For BER measures, state=9 is required
  1410. * FIXME: we may get MER measures with state=8
  1411. */
  1412. if (status_nr < 9)
  1413. return 0;
  1414. for (i = 0; i < 3; i++) {
  1415. if (c->isdbt_layer_enabled & (1 << i)) {
  1416. /* Layer is active and has rc segments */
  1417. active_layers++;
  1418. /* Handle BER before vterbi */
  1419. rc = mb86a20s_get_pre_ber(fe, i,
  1420. &bit_error, &bit_count);
  1421. if (rc >= 0) {
  1422. c->pre_bit_error.stat[1 + i].scale = FE_SCALE_COUNTER;
  1423. c->pre_bit_error.stat[1 + i].uvalue += bit_error;
  1424. c->pre_bit_count.stat[1 + i].scale = FE_SCALE_COUNTER;
  1425. c->pre_bit_count.stat[1 + i].uvalue += bit_count;
  1426. } else if (rc != -EBUSY) {
  1427. /*
  1428. * If an I/O error happened,
  1429. * measures are now unavailable
  1430. */
  1431. c->pre_bit_error.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
  1432. c->pre_bit_count.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
  1433. dev_err(&state->i2c->dev,
  1434. "%s: Can't get BER for layer %c (error %d).\n",
  1435. __func__, 'A' + i, rc);
  1436. }
  1437. if (c->block_error.stat[1 + i].scale != FE_SCALE_NOT_AVAILABLE)
  1438. pre_ber_layers++;
  1439. /* Handle BER post vterbi */
  1440. rc = mb86a20s_get_post_ber(fe, i,
  1441. &bit_error, &bit_count);
  1442. if (rc >= 0) {
  1443. c->post_bit_error.stat[1 + i].scale = FE_SCALE_COUNTER;
  1444. c->post_bit_error.stat[1 + i].uvalue += bit_error;
  1445. c->post_bit_count.stat[1 + i].scale = FE_SCALE_COUNTER;
  1446. c->post_bit_count.stat[1 + i].uvalue += bit_count;
  1447. } else if (rc != -EBUSY) {
  1448. /*
  1449. * If an I/O error happened,
  1450. * measures are now unavailable
  1451. */
  1452. c->post_bit_error.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
  1453. c->post_bit_count.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
  1454. dev_err(&state->i2c->dev,
  1455. "%s: Can't get BER for layer %c (error %d).\n",
  1456. __func__, 'A' + i, rc);
  1457. }
  1458. if (c->block_error.stat[1 + i].scale != FE_SCALE_NOT_AVAILABLE)
  1459. post_ber_layers++;
  1460. /* Handle Block errors for PER/UCB reports */
  1461. rc = mb86a20s_get_blk_error(fe, i,
  1462. &block_error,
  1463. &block_count);
  1464. if (rc >= 0) {
  1465. c->block_error.stat[1 + i].scale = FE_SCALE_COUNTER;
  1466. c->block_error.stat[1 + i].uvalue += block_error;
  1467. c->block_count.stat[1 + i].scale = FE_SCALE_COUNTER;
  1468. c->block_count.stat[1 + i].uvalue += block_count;
  1469. } else if (rc != -EBUSY) {
  1470. /*
  1471. * If an I/O error happened,
  1472. * measures are now unavailable
  1473. */
  1474. c->block_error.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
  1475. c->block_count.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
  1476. dev_err(&state->i2c->dev,
  1477. "%s: Can't get PER for layer %c (error %d).\n",
  1478. __func__, 'A' + i, rc);
  1479. }
  1480. if (c->block_error.stat[1 + i].scale != FE_SCALE_NOT_AVAILABLE)
  1481. per_layers++;
  1482. /* Update total preBER */
  1483. t_pre_bit_error += c->pre_bit_error.stat[1 + i].uvalue;
  1484. t_pre_bit_count += c->pre_bit_count.stat[1 + i].uvalue;
  1485. /* Update total postBER */
  1486. t_post_bit_error += c->post_bit_error.stat[1 + i].uvalue;
  1487. t_post_bit_count += c->post_bit_count.stat[1 + i].uvalue;
  1488. /* Update total PER */
  1489. t_block_error += c->block_error.stat[1 + i].uvalue;
  1490. t_block_count += c->block_count.stat[1 + i].uvalue;
  1491. }
  1492. }
  1493. /*
  1494. * Start showing global count if at least one error count is
  1495. * available.
  1496. */
  1497. if (pre_ber_layers) {
  1498. /*
  1499. * At least one per-layer BER measure was read. We can now
  1500. * calculate the total BER
  1501. *
  1502. * Total Bit Error/Count is calculated as the sum of the
  1503. * bit errors on all active layers.
  1504. */
  1505. c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
  1506. c->pre_bit_error.stat[0].uvalue = t_pre_bit_error;
  1507. c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
  1508. c->pre_bit_count.stat[0].uvalue = t_pre_bit_count;
  1509. } else {
  1510. c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
  1511. c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
  1512. }
  1513. /*
  1514. * Start showing global count if at least one error count is
  1515. * available.
  1516. */
  1517. if (post_ber_layers) {
  1518. /*
  1519. * At least one per-layer BER measure was read. We can now
  1520. * calculate the total BER
  1521. *
  1522. * Total Bit Error/Count is calculated as the sum of the
  1523. * bit errors on all active layers.
  1524. */
  1525. c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
  1526. c->post_bit_error.stat[0].uvalue = t_post_bit_error;
  1527. c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
  1528. c->post_bit_count.stat[0].uvalue = t_post_bit_count;
  1529. } else {
  1530. c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
  1531. c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
  1532. }
  1533. if (per_layers) {
  1534. /*
  1535. * At least one per-layer UCB measure was read. We can now
  1536. * calculate the total UCB
  1537. *
  1538. * Total block Error/Count is calculated as the sum of the
  1539. * block errors on all active layers.
  1540. */
  1541. c->block_error.stat[0].scale = FE_SCALE_COUNTER;
  1542. c->block_error.stat[0].uvalue = t_block_error;
  1543. c->block_count.stat[0].scale = FE_SCALE_COUNTER;
  1544. c->block_count.stat[0].uvalue = t_block_count;
  1545. } else {
  1546. c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
  1547. c->block_count.stat[0].scale = FE_SCALE_COUNTER;
  1548. }
  1549. return rc;
  1550. }
  1551. /*
  1552. * The functions below are called via DVB callbacks, so they need to
  1553. * properly use the I2C gate control
  1554. */
  1555. static int mb86a20s_initfe(struct dvb_frontend *fe)
  1556. {
  1557. struct mb86a20s_state *state = fe->demodulator_priv;
  1558. u64 pll;
  1559. u32 fclk;
  1560. int rc;
  1561. u8 regD5 = 1, reg71, reg09 = 0x3a;
  1562. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  1563. if (fe->ops.i2c_gate_ctrl)
  1564. fe->ops.i2c_gate_ctrl(fe, 0);
  1565. /* Initialize the frontend */
  1566. rc = mb86a20s_writeregdata(state, mb86a20s_init1);
  1567. if (rc < 0)
  1568. goto err;
  1569. if (!state->inversion)
  1570. reg09 |= 0x04;
  1571. rc = mb86a20s_writereg(state, 0x09, reg09);
  1572. if (rc < 0)
  1573. goto err;
  1574. if (!state->bw)
  1575. reg71 = 1;
  1576. else
  1577. reg71 = 0;
  1578. rc = mb86a20s_writereg(state, 0x39, reg71);
  1579. if (rc < 0)
  1580. goto err;
  1581. rc = mb86a20s_writereg(state, 0x71, state->bw);
  1582. if (rc < 0)
  1583. goto err;
  1584. if (state->subchannel) {
  1585. rc = mb86a20s_writereg(state, 0x44, state->subchannel);
  1586. if (rc < 0)
  1587. goto err;
  1588. }
  1589. fclk = state->config->fclk;
  1590. if (!fclk)
  1591. fclk = 32571428;
  1592. /* Adjust IF frequency to match tuner */
  1593. if (fe->ops.tuner_ops.get_if_frequency)
  1594. fe->ops.tuner_ops.get_if_frequency(fe, &state->if_freq);
  1595. if (!state->if_freq)
  1596. state->if_freq = 3300000;
  1597. pll = (((u64)1) << 34) * state->if_freq;
  1598. do_div(pll, 63 * fclk);
  1599. pll = (1 << 25) - pll;
  1600. rc = mb86a20s_writereg(state, 0x28, 0x2a);
  1601. if (rc < 0)
  1602. goto err;
  1603. rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
  1604. if (rc < 0)
  1605. goto err;
  1606. rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
  1607. if (rc < 0)
  1608. goto err;
  1609. rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
  1610. if (rc < 0)
  1611. goto err;
  1612. dev_dbg(&state->i2c->dev, "%s: fclk=%d, IF=%d, clock reg=0x%06llx\n",
  1613. __func__, fclk, state->if_freq, (long long)pll);
  1614. /* pll = freq[Hz] * 2^24/10^6 / 16.285714286 */
  1615. pll = state->if_freq * 1677721600L;
  1616. do_div(pll, 1628571429L);
  1617. rc = mb86a20s_writereg(state, 0x28, 0x20);
  1618. if (rc < 0)
  1619. goto err;
  1620. rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
  1621. if (rc < 0)
  1622. goto err;
  1623. rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
  1624. if (rc < 0)
  1625. goto err;
  1626. rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
  1627. if (rc < 0)
  1628. goto err;
  1629. dev_dbg(&state->i2c->dev, "%s: IF=%d, IF reg=0x%06llx\n",
  1630. __func__, state->if_freq, (long long)pll);
  1631. if (!state->config->is_serial) {
  1632. regD5 &= ~1;
  1633. rc = mb86a20s_writereg(state, 0x50, 0xd5);
  1634. if (rc < 0)
  1635. goto err;
  1636. rc = mb86a20s_writereg(state, 0x51, regD5);
  1637. if (rc < 0)
  1638. goto err;
  1639. }
  1640. rc = mb86a20s_writeregdata(state, mb86a20s_init2);
  1641. if (rc < 0)
  1642. goto err;
  1643. err:
  1644. if (fe->ops.i2c_gate_ctrl)
  1645. fe->ops.i2c_gate_ctrl(fe, 1);
  1646. if (rc < 0) {
  1647. state->need_init = true;
  1648. dev_info(&state->i2c->dev,
  1649. "mb86a20s: Init failed. Will try again later\n");
  1650. } else {
  1651. state->need_init = false;
  1652. dev_dbg(&state->i2c->dev, "Initialization succeeded.\n");
  1653. }
  1654. return rc;
  1655. }
  1656. static int mb86a20s_set_frontend(struct dvb_frontend *fe)
  1657. {
  1658. struct mb86a20s_state *state = fe->demodulator_priv;
  1659. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  1660. int rc, if_freq;
  1661. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  1662. if (!c->isdbt_layer_enabled)
  1663. c->isdbt_layer_enabled = 7;
  1664. if (c->isdbt_layer_enabled == 1)
  1665. state->bw = MB86A20S_1SEG;
  1666. else if (c->isdbt_partial_reception)
  1667. state->bw = MB86A20S_13SEG_PARTIAL;
  1668. else
  1669. state->bw = MB86A20S_13SEG;
  1670. if (c->inversion == INVERSION_ON)
  1671. state->inversion = true;
  1672. else
  1673. state->inversion = false;
  1674. if (!c->isdbt_sb_mode) {
  1675. state->subchannel = 0;
  1676. } else {
  1677. if (c->isdbt_sb_subchannel > ARRAY_SIZE(mb86a20s_subchannel))
  1678. c->isdbt_sb_subchannel = 0;
  1679. state->subchannel = mb86a20s_subchannel[c->isdbt_sb_subchannel];
  1680. }
  1681. /*
  1682. * Gate should already be opened, but it doesn't hurt to
  1683. * double-check
  1684. */
  1685. if (fe->ops.i2c_gate_ctrl)
  1686. fe->ops.i2c_gate_ctrl(fe, 1);
  1687. fe->ops.tuner_ops.set_params(fe);
  1688. if (fe->ops.tuner_ops.get_if_frequency)
  1689. fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
  1690. /*
  1691. * Make it more reliable: if, for some reason, the initial
  1692. * device initialization doesn't happen, initialize it when
  1693. * a SBTVD parameters are adjusted.
  1694. *
  1695. * Unfortunately, due to a hard to track bug at tda829x/tda18271,
  1696. * the agc callback logic is not called during DVB attach time,
  1697. * causing mb86a20s to not be initialized with Kworld SBTVD.
  1698. * So, this hack is needed, in order to make Kworld SBTVD to work.
  1699. *
  1700. * It is also needed to change the IF after the initial init.
  1701. *
  1702. * HACK: Always init the frontend when set_frontend is called:
  1703. * it was noticed that, on some devices, it fails to lock on a
  1704. * different channel. So, it is better to reset everything, even
  1705. * wasting some time, than to loose channel lock.
  1706. */
  1707. mb86a20s_initfe(fe);
  1708. if (fe->ops.i2c_gate_ctrl)
  1709. fe->ops.i2c_gate_ctrl(fe, 0);
  1710. rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception);
  1711. mb86a20s_reset_counters(fe);
  1712. mb86a20s_stats_not_ready(fe);
  1713. if (fe->ops.i2c_gate_ctrl)
  1714. fe->ops.i2c_gate_ctrl(fe, 1);
  1715. return rc;
  1716. }
  1717. static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe,
  1718. fe_status_t *status)
  1719. {
  1720. struct mb86a20s_state *state = fe->demodulator_priv;
  1721. int rc, status_nr;
  1722. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  1723. if (fe->ops.i2c_gate_ctrl)
  1724. fe->ops.i2c_gate_ctrl(fe, 0);
  1725. /* Get lock */
  1726. status_nr = mb86a20s_read_status(fe, status);
  1727. if (status_nr < 7) {
  1728. mb86a20s_stats_not_ready(fe);
  1729. mb86a20s_reset_frontend_cache(fe);
  1730. }
  1731. if (status_nr < 0) {
  1732. dev_err(&state->i2c->dev,
  1733. "%s: Can't read frontend lock status\n", __func__);
  1734. goto error;
  1735. }
  1736. /* Get signal strength */
  1737. rc = mb86a20s_read_signal_strength(fe);
  1738. if (rc < 0) {
  1739. dev_err(&state->i2c->dev,
  1740. "%s: Can't reset VBER registers.\n", __func__);
  1741. mb86a20s_stats_not_ready(fe);
  1742. mb86a20s_reset_frontend_cache(fe);
  1743. rc = 0; /* Status is OK */
  1744. goto error;
  1745. }
  1746. if (status_nr >= 7) {
  1747. /* Get TMCC info*/
  1748. rc = mb86a20s_get_frontend(fe);
  1749. if (rc < 0) {
  1750. dev_err(&state->i2c->dev,
  1751. "%s: Can't get FE TMCC data.\n", __func__);
  1752. rc = 0; /* Status is OK */
  1753. goto error;
  1754. }
  1755. /* Get statistics */
  1756. rc = mb86a20s_get_stats(fe, status_nr);
  1757. if (rc < 0 && rc != -EBUSY) {
  1758. dev_err(&state->i2c->dev,
  1759. "%s: Can't get FE statistics.\n", __func__);
  1760. rc = 0;
  1761. goto error;
  1762. }
  1763. rc = 0; /* Don't return EBUSY to userspace */
  1764. }
  1765. goto ok;
  1766. error:
  1767. mb86a20s_stats_not_ready(fe);
  1768. ok:
  1769. if (fe->ops.i2c_gate_ctrl)
  1770. fe->ops.i2c_gate_ctrl(fe, 1);
  1771. return rc;
  1772. }
  1773. static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe,
  1774. u16 *strength)
  1775. {
  1776. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  1777. *strength = c->strength.stat[0].uvalue;
  1778. return 0;
  1779. }
  1780. static int mb86a20s_get_frontend_dummy(struct dvb_frontend *fe)
  1781. {
  1782. /*
  1783. * get_frontend is now handled together with other stats
  1784. * retrival, when read_status() is called, as some statistics
  1785. * will depend on the layers detection.
  1786. */
  1787. return 0;
  1788. };
  1789. static int mb86a20s_tune(struct dvb_frontend *fe,
  1790. bool re_tune,
  1791. unsigned int mode_flags,
  1792. unsigned int *delay,
  1793. fe_status_t *status)
  1794. {
  1795. struct mb86a20s_state *state = fe->demodulator_priv;
  1796. int rc = 0;
  1797. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  1798. if (re_tune)
  1799. rc = mb86a20s_set_frontend(fe);
  1800. if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
  1801. mb86a20s_read_status_and_stats(fe, status);
  1802. return rc;
  1803. }
  1804. static void mb86a20s_release(struct dvb_frontend *fe)
  1805. {
  1806. struct mb86a20s_state *state = fe->demodulator_priv;
  1807. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  1808. kfree(state);
  1809. }
  1810. static struct dvb_frontend_ops mb86a20s_ops;
  1811. struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config,
  1812. struct i2c_adapter *i2c)
  1813. {
  1814. struct mb86a20s_state *state;
  1815. u8 rev;
  1816. dev_dbg(&i2c->dev, "%s called.\n", __func__);
  1817. /* allocate memory for the internal state */
  1818. state = kzalloc(sizeof(struct mb86a20s_state), GFP_KERNEL);
  1819. if (state == NULL) {
  1820. dev_err(&i2c->dev,
  1821. "%s: unable to allocate memory for state\n", __func__);
  1822. goto error;
  1823. }
  1824. /* setup the state */
  1825. state->config = config;
  1826. state->i2c = i2c;
  1827. /* create dvb_frontend */
  1828. memcpy(&state->frontend.ops, &mb86a20s_ops,
  1829. sizeof(struct dvb_frontend_ops));
  1830. state->frontend.demodulator_priv = state;
  1831. /* Check if it is a mb86a20s frontend */
  1832. rev = mb86a20s_readreg(state, 0);
  1833. if (rev == 0x13) {
  1834. dev_info(&i2c->dev,
  1835. "Detected a Fujitsu mb86a20s frontend\n");
  1836. } else {
  1837. dev_dbg(&i2c->dev,
  1838. "Frontend revision %d is unknown - aborting.\n",
  1839. rev);
  1840. goto error;
  1841. }
  1842. return &state->frontend;
  1843. error:
  1844. kfree(state);
  1845. return NULL;
  1846. }
  1847. EXPORT_SYMBOL(mb86a20s_attach);
  1848. static struct dvb_frontend_ops mb86a20s_ops = {
  1849. .delsys = { SYS_ISDBT },
  1850. /* Use dib8000 values per default */
  1851. .info = {
  1852. .name = "Fujitsu mb86A20s",
  1853. .caps = FE_CAN_RECOVER |
  1854. FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
  1855. FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
  1856. FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
  1857. FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO |
  1858. FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
  1859. /* Actually, those values depend on the used tuner */
  1860. .frequency_min = 45000000,
  1861. .frequency_max = 864000000,
  1862. .frequency_stepsize = 62500,
  1863. },
  1864. .release = mb86a20s_release,
  1865. .init = mb86a20s_initfe,
  1866. .set_frontend = mb86a20s_set_frontend,
  1867. .get_frontend = mb86a20s_get_frontend_dummy,
  1868. .read_status = mb86a20s_read_status_and_stats,
  1869. .read_signal_strength = mb86a20s_read_signal_strength_from_cache,
  1870. .tune = mb86a20s_tune,
  1871. };
  1872. MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware");
  1873. MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
  1874. MODULE_LICENSE("GPL");