i915_drv.c 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600
  1. /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
  2. */
  3. /*
  4. *
  5. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the
  10. * "Software"), to deal in the Software without restriction, including
  11. * without limitation the rights to use, copy, modify, merge, publish,
  12. * distribute, sub license, and/or sell copies of the Software, and to
  13. * permit persons to whom the Software is furnished to do so, subject to
  14. * the following conditions:
  15. *
  16. * The above copyright notice and this permission notice (including the
  17. * next paragraph) shall be included in all copies or substantial portions
  18. * of the Software.
  19. *
  20. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27. *
  28. */
  29. #include <linux/device.h>
  30. #include "drmP.h"
  31. #include "drm.h"
  32. #include "i915_drm.h"
  33. #include "i915_drv.h"
  34. #include <linux/console.h>
  35. #include "drm_crtc_helper.h"
  36. static int i915_modeset = -1;
  37. module_param_named(modeset, i915_modeset, int, 0400);
  38. unsigned int i915_fbpercrtc = 0;
  39. module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  40. unsigned int i915_powersave = 1;
  41. module_param_named(powersave, i915_powersave, int, 0400);
  42. unsigned int i915_lvds_downclock = 0;
  43. module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  44. static struct drm_driver driver;
  45. #define INTEL_VGA_DEVICE(id, info) { \
  46. .class = PCI_CLASS_DISPLAY_VGA << 8, \
  47. .class_mask = 0xffff00, \
  48. .vendor = 0x8086, \
  49. .device = id, \
  50. .subvendor = PCI_ANY_ID, \
  51. .subdevice = PCI_ANY_ID, \
  52. .driver_data = (unsigned long) info }
  53. const static struct intel_device_info intel_i830_info = {
  54. .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
  55. };
  56. const static struct intel_device_info intel_845g_info = {
  57. .is_i8xx = 1,
  58. };
  59. const static struct intel_device_info intel_i85x_info = {
  60. .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
  61. };
  62. const static struct intel_device_info intel_i865g_info = {
  63. .is_i8xx = 1,
  64. };
  65. const static struct intel_device_info intel_i915g_info = {
  66. .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1,
  67. };
  68. const static struct intel_device_info intel_i915gm_info = {
  69. .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1,
  70. .cursor_needs_physical = 1,
  71. };
  72. const static struct intel_device_info intel_i945g_info = {
  73. .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1,
  74. };
  75. const static struct intel_device_info intel_i945gm_info = {
  76. .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1,
  77. .has_hotplug = 1, .cursor_needs_physical = 1,
  78. };
  79. const static struct intel_device_info intel_i965g_info = {
  80. .is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1,
  81. };
  82. const static struct intel_device_info intel_i965gm_info = {
  83. .is_i965g = 1, .is_mobile = 1, .is_i965gm = 1, .is_i9xx = 1,
  84. .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1,
  85. .has_hotplug = 1,
  86. };
  87. const static struct intel_device_info intel_g33_info = {
  88. .is_g33 = 1, .is_i9xx = 1, .need_gfx_hws = 1,
  89. .has_hotplug = 1,
  90. };
  91. const static struct intel_device_info intel_g45_info = {
  92. .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1,
  93. .has_pipe_cxsr = 1,
  94. .has_hotplug = 1,
  95. };
  96. const static struct intel_device_info intel_gm45_info = {
  97. .is_i965g = 1, .is_mobile = 1, .is_g4x = 1, .is_i9xx = 1,
  98. .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
  99. .has_pipe_cxsr = 1,
  100. .has_hotplug = 1,
  101. };
  102. const static struct intel_device_info intel_pineview_info = {
  103. .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1,
  104. .need_gfx_hws = 1,
  105. .has_hotplug = 1,
  106. };
  107. const static struct intel_device_info intel_ironlake_d_info = {
  108. .is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,
  109. .has_pipe_cxsr = 1,
  110. .has_hotplug = 1,
  111. };
  112. const static struct intel_device_info intel_ironlake_m_info = {
  113. .is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1,
  114. .need_gfx_hws = 1, .has_rc6 = 1,
  115. .has_hotplug = 1,
  116. };
  117. const static struct pci_device_id pciidlist[] = {
  118. INTEL_VGA_DEVICE(0x3577, &intel_i830_info),
  119. INTEL_VGA_DEVICE(0x2562, &intel_845g_info),
  120. INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),
  121. INTEL_VGA_DEVICE(0x35e8, &intel_i85x_info),
  122. INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),
  123. INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),
  124. INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),
  125. INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),
  126. INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),
  127. INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),
  128. INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),
  129. INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),
  130. INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),
  131. INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),
  132. INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),
  133. INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),
  134. INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),
  135. INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),
  136. INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),
  137. INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),
  138. INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),
  139. INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),
  140. INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),
  141. INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),
  142. INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),
  143. INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),
  144. INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
  145. INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
  146. INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
  147. INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
  148. {0, 0, 0}
  149. };
  150. #if defined(CONFIG_DRM_I915_KMS)
  151. MODULE_DEVICE_TABLE(pci, pciidlist);
  152. #endif
  153. static int i915_drm_freeze(struct drm_device *dev)
  154. {
  155. pci_save_state(dev->pdev);
  156. /* If KMS is active, we do the leavevt stuff here */
  157. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  158. int error = i915_gem_idle(dev);
  159. if (error) {
  160. dev_err(&dev->pdev->dev,
  161. "GEM idle failed, resume might fail\n");
  162. return error;
  163. }
  164. drm_irq_uninstall(dev);
  165. }
  166. i915_save_state(dev);
  167. return 0;
  168. }
  169. static void i915_drm_suspend(struct drm_device *dev)
  170. {
  171. struct drm_i915_private *dev_priv = dev->dev_private;
  172. intel_opregion_free(dev, 1);
  173. /* Modeset on resume, not lid events */
  174. dev_priv->modeset_on_lid = 0;
  175. }
  176. static int i915_suspend(struct drm_device *dev, pm_message_t state)
  177. {
  178. int error;
  179. if (!dev || !dev->dev_private) {
  180. DRM_ERROR("dev: %p\n", dev);
  181. DRM_ERROR("DRM not initialized, aborting suspend.\n");
  182. return -ENODEV;
  183. }
  184. if (state.event == PM_EVENT_PRETHAW)
  185. return 0;
  186. error = i915_drm_freeze(dev);
  187. if (error)
  188. return error;
  189. i915_drm_suspend(dev);
  190. if (state.event == PM_EVENT_SUSPEND) {
  191. /* Shut down the device */
  192. pci_disable_device(dev->pdev);
  193. pci_set_power_state(dev->pdev, PCI_D3hot);
  194. }
  195. return 0;
  196. }
  197. static int i915_drm_thaw(struct drm_device *dev)
  198. {
  199. struct drm_i915_private *dev_priv = dev->dev_private;
  200. int error = 0;
  201. /* KMS EnterVT equivalent */
  202. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  203. mutex_lock(&dev->struct_mutex);
  204. dev_priv->mm.suspended = 0;
  205. error = i915_gem_init_ringbuffer(dev);
  206. mutex_unlock(&dev->struct_mutex);
  207. drm_irq_install(dev);
  208. /* Resume the modeset for every activated CRTC */
  209. drm_helper_resume_force_mode(dev);
  210. }
  211. dev_priv->modeset_on_lid = 0;
  212. return error;
  213. }
  214. static int i915_resume(struct drm_device *dev)
  215. {
  216. if (pci_enable_device(dev->pdev))
  217. return -EIO;
  218. pci_set_master(dev->pdev);
  219. i915_restore_state(dev);
  220. intel_opregion_init(dev, 1);
  221. return i915_drm_thaw(dev);
  222. }
  223. /**
  224. * i965_reset - reset chip after a hang
  225. * @dev: drm device to reset
  226. * @flags: reset domains
  227. *
  228. * Reset the chip. Useful if a hang is detected. Returns zero on successful
  229. * reset or otherwise an error code.
  230. *
  231. * Procedure is fairly simple:
  232. * - reset the chip using the reset reg
  233. * - re-init context state
  234. * - re-init hardware status page
  235. * - re-init ring buffer
  236. * - re-init interrupt state
  237. * - re-init display
  238. */
  239. int i965_reset(struct drm_device *dev, u8 flags)
  240. {
  241. drm_i915_private_t *dev_priv = dev->dev_private;
  242. unsigned long timeout;
  243. u8 gdrst;
  244. /*
  245. * We really should only reset the display subsystem if we actually
  246. * need to
  247. */
  248. bool need_display = true;
  249. mutex_lock(&dev->struct_mutex);
  250. /*
  251. * Clear request list
  252. */
  253. i915_gem_retire_requests(dev);
  254. if (need_display)
  255. i915_save_display(dev);
  256. if (IS_I965G(dev) || IS_G4X(dev)) {
  257. /*
  258. * Set the domains we want to reset, then the reset bit (bit 0).
  259. * Clear the reset bit after a while and wait for hardware status
  260. * bit (bit 1) to be set
  261. */
  262. pci_read_config_byte(dev->pdev, GDRST, &gdrst);
  263. pci_write_config_byte(dev->pdev, GDRST, gdrst | flags | ((flags == GDRST_FULL) ? 0x1 : 0x0));
  264. udelay(50);
  265. pci_write_config_byte(dev->pdev, GDRST, gdrst & 0xfe);
  266. /* ...we don't want to loop forever though, 500ms should be plenty */
  267. timeout = jiffies + msecs_to_jiffies(500);
  268. do {
  269. udelay(100);
  270. pci_read_config_byte(dev->pdev, GDRST, &gdrst);
  271. } while ((gdrst & 0x1) && time_after(timeout, jiffies));
  272. if (gdrst & 0x1) {
  273. WARN(true, "i915: Failed to reset chip\n");
  274. mutex_unlock(&dev->struct_mutex);
  275. return -EIO;
  276. }
  277. } else {
  278. DRM_ERROR("Error occurred. Don't know how to reset this chip.\n");
  279. return -ENODEV;
  280. }
  281. /* Ok, now get things going again... */
  282. /*
  283. * Everything depends on having the GTT running, so we need to start
  284. * there. Fortunately we don't need to do this unless we reset the
  285. * chip at a PCI level.
  286. *
  287. * Next we need to restore the context, but we don't use those
  288. * yet either...
  289. *
  290. * Ring buffer needs to be re-initialized in the KMS case, or if X
  291. * was running at the time of the reset (i.e. we weren't VT
  292. * switched away).
  293. */
  294. if (drm_core_check_feature(dev, DRIVER_MODESET) ||
  295. !dev_priv->mm.suspended) {
  296. drm_i915_ring_buffer_t *ring = &dev_priv->ring;
  297. struct drm_gem_object *obj = ring->ring_obj;
  298. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  299. dev_priv->mm.suspended = 0;
  300. /* Stop the ring if it's running. */
  301. I915_WRITE(PRB0_CTL, 0);
  302. I915_WRITE(PRB0_TAIL, 0);
  303. I915_WRITE(PRB0_HEAD, 0);
  304. /* Initialize the ring. */
  305. I915_WRITE(PRB0_START, obj_priv->gtt_offset);
  306. I915_WRITE(PRB0_CTL,
  307. ((obj->size - 4096) & RING_NR_PAGES) |
  308. RING_NO_REPORT |
  309. RING_VALID);
  310. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  311. i915_kernel_lost_context(dev);
  312. else {
  313. ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  314. ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
  315. ring->space = ring->head - (ring->tail + 8);
  316. if (ring->space < 0)
  317. ring->space += ring->Size;
  318. }
  319. mutex_unlock(&dev->struct_mutex);
  320. drm_irq_uninstall(dev);
  321. drm_irq_install(dev);
  322. mutex_lock(&dev->struct_mutex);
  323. }
  324. /*
  325. * Display needs restore too...
  326. */
  327. if (need_display)
  328. i915_restore_display(dev);
  329. mutex_unlock(&dev->struct_mutex);
  330. return 0;
  331. }
  332. static int __devinit
  333. i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  334. {
  335. return drm_get_dev(pdev, ent, &driver);
  336. }
  337. static void
  338. i915_pci_remove(struct pci_dev *pdev)
  339. {
  340. struct drm_device *dev = pci_get_drvdata(pdev);
  341. drm_put_dev(dev);
  342. }
  343. static int i915_pm_suspend(struct device *dev)
  344. {
  345. struct pci_dev *pdev = to_pci_dev(dev);
  346. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  347. int error;
  348. if (!drm_dev || !drm_dev->dev_private) {
  349. dev_err(dev, "DRM not initialized, aborting suspend.\n");
  350. return -ENODEV;
  351. }
  352. error = i915_drm_freeze(drm_dev);
  353. if (error)
  354. return error;
  355. i915_drm_suspend(drm_dev);
  356. pci_disable_device(pdev);
  357. pci_set_power_state(pdev, PCI_D3hot);
  358. return 0;
  359. }
  360. static int i915_pm_resume(struct device *dev)
  361. {
  362. struct pci_dev *pdev = to_pci_dev(dev);
  363. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  364. return i915_resume(drm_dev);
  365. }
  366. static int i915_pm_freeze(struct device *dev)
  367. {
  368. struct pci_dev *pdev = to_pci_dev(dev);
  369. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  370. if (!drm_dev || !drm_dev->dev_private) {
  371. dev_err(dev, "DRM not initialized, aborting suspend.\n");
  372. return -ENODEV;
  373. }
  374. return i915_drm_freeze(drm_dev);
  375. }
  376. static int i915_pm_thaw(struct device *dev)
  377. {
  378. struct pci_dev *pdev = to_pci_dev(dev);
  379. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  380. return i915_drm_thaw(drm_dev);
  381. }
  382. static int i915_pm_poweroff(struct device *dev)
  383. {
  384. struct pci_dev *pdev = to_pci_dev(dev);
  385. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  386. int error;
  387. error = i915_drm_freeze(drm_dev);
  388. if (!error)
  389. i915_drm_suspend(drm_dev);
  390. return error;
  391. }
  392. const struct dev_pm_ops i915_pm_ops = {
  393. .suspend = i915_pm_suspend,
  394. .resume = i915_pm_resume,
  395. .freeze = i915_pm_freeze,
  396. .thaw = i915_pm_thaw,
  397. .poweroff = i915_pm_poweroff,
  398. .restore = i915_pm_resume,
  399. };
  400. static struct vm_operations_struct i915_gem_vm_ops = {
  401. .fault = i915_gem_fault,
  402. .open = drm_gem_vm_open,
  403. .close = drm_gem_vm_close,
  404. };
  405. static struct drm_driver driver = {
  406. /* don't use mtrr's here, the Xserver or user space app should
  407. * deal with them for intel hardware.
  408. */
  409. .driver_features =
  410. DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
  411. DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
  412. .load = i915_driver_load,
  413. .unload = i915_driver_unload,
  414. .open = i915_driver_open,
  415. .lastclose = i915_driver_lastclose,
  416. .preclose = i915_driver_preclose,
  417. .postclose = i915_driver_postclose,
  418. /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
  419. .suspend = i915_suspend,
  420. .resume = i915_resume,
  421. .device_is_agp = i915_driver_device_is_agp,
  422. .enable_vblank = i915_enable_vblank,
  423. .disable_vblank = i915_disable_vblank,
  424. .irq_preinstall = i915_driver_irq_preinstall,
  425. .irq_postinstall = i915_driver_irq_postinstall,
  426. .irq_uninstall = i915_driver_irq_uninstall,
  427. .irq_handler = i915_driver_irq_handler,
  428. .reclaim_buffers = drm_core_reclaim_buffers,
  429. .get_map_ofs = drm_core_get_map_ofs,
  430. .get_reg_ofs = drm_core_get_reg_ofs,
  431. .master_create = i915_master_create,
  432. .master_destroy = i915_master_destroy,
  433. #if defined(CONFIG_DEBUG_FS)
  434. .debugfs_init = i915_debugfs_init,
  435. .debugfs_cleanup = i915_debugfs_cleanup,
  436. #endif
  437. .gem_init_object = i915_gem_init_object,
  438. .gem_free_object = i915_gem_free_object,
  439. .gem_vm_ops = &i915_gem_vm_ops,
  440. .ioctls = i915_ioctls,
  441. .fops = {
  442. .owner = THIS_MODULE,
  443. .open = drm_open,
  444. .release = drm_release,
  445. .unlocked_ioctl = drm_ioctl,
  446. .mmap = drm_gem_mmap,
  447. .poll = drm_poll,
  448. .fasync = drm_fasync,
  449. .read = drm_read,
  450. #ifdef CONFIG_COMPAT
  451. .compat_ioctl = i915_compat_ioctl,
  452. #endif
  453. },
  454. .pci_driver = {
  455. .name = DRIVER_NAME,
  456. .id_table = pciidlist,
  457. .probe = i915_pci_probe,
  458. .remove = i915_pci_remove,
  459. .driver.pm = &i915_pm_ops,
  460. },
  461. .name = DRIVER_NAME,
  462. .desc = DRIVER_DESC,
  463. .date = DRIVER_DATE,
  464. .major = DRIVER_MAJOR,
  465. .minor = DRIVER_MINOR,
  466. .patchlevel = DRIVER_PATCHLEVEL,
  467. };
  468. static int __init i915_init(void)
  469. {
  470. driver.num_ioctls = i915_max_ioctl;
  471. i915_gem_shrinker_init();
  472. /*
  473. * If CONFIG_DRM_I915_KMS is set, default to KMS unless
  474. * explicitly disabled with the module pararmeter.
  475. *
  476. * Otherwise, just follow the parameter (defaulting to off).
  477. *
  478. * Allow optional vga_text_mode_force boot option to override
  479. * the default behavior.
  480. */
  481. #if defined(CONFIG_DRM_I915_KMS)
  482. if (i915_modeset != 0)
  483. driver.driver_features |= DRIVER_MODESET;
  484. #endif
  485. if (i915_modeset == 1)
  486. driver.driver_features |= DRIVER_MODESET;
  487. #ifdef CONFIG_VGA_CONSOLE
  488. if (vgacon_text_force() && i915_modeset == -1)
  489. driver.driver_features &= ~DRIVER_MODESET;
  490. #endif
  491. return drm_init(&driver);
  492. }
  493. static void __exit i915_exit(void)
  494. {
  495. i915_gem_shrinker_exit();
  496. drm_exit(&driver);
  497. }
  498. module_init(i915_init);
  499. module_exit(i915_exit);
  500. MODULE_AUTHOR(DRIVER_AUTHOR);
  501. MODULE_DESCRIPTION(DRIVER_DESC);
  502. MODULE_LICENSE("GPL and additional rights");