prcm.c 19 KB

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  1. /*
  2. * linux/arch/arm/mach-omap2/prcm.c
  3. *
  4. * OMAP 24xx Power Reset and Clock Management (PRCM) functions
  5. *
  6. * Copyright (C) 2005 Nokia Corporation
  7. *
  8. * Written by Tony Lindgren <tony.lindgren@nokia.com>
  9. *
  10. * Copyright (C) 2007 Texas Instruments, Inc.
  11. * Rajendra Nayak <rnayak@ti.com>
  12. *
  13. * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
  14. * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com>
  15. *
  16. * This program is free software; you can redistribute it and/or modify
  17. * it under the terms of the GNU General Public License version 2 as
  18. * published by the Free Software Foundation.
  19. */
  20. #include <linux/module.h>
  21. #include <linux/init.h>
  22. #include <linux/clk.h>
  23. #include <linux/io.h>
  24. #include <linux/delay.h>
  25. #include <plat/common.h>
  26. #include <plat/prcm.h>
  27. #include <plat/irqs.h>
  28. #include <plat/control.h>
  29. #include "clock.h"
  30. #include "clock2xxx.h"
  31. #include "cm.h"
  32. #include "prm.h"
  33. #include "prm-regbits-24xx.h"
  34. static void __iomem *prm_base;
  35. static void __iomem *cm_base;
  36. static void __iomem *cm2_base;
  37. #define MAX_MODULE_ENABLE_WAIT 100000
  38. struct omap3_prcm_regs {
  39. u32 control_padconf_sys_nirq;
  40. u32 iva2_cm_clksel1;
  41. u32 iva2_cm_clksel2;
  42. u32 cm_sysconfig;
  43. u32 sgx_cm_clksel;
  44. u32 dss_cm_clksel;
  45. u32 cam_cm_clksel;
  46. u32 per_cm_clksel;
  47. u32 emu_cm_clksel;
  48. u32 emu_cm_clkstctrl;
  49. u32 pll_cm_autoidle2;
  50. u32 pll_cm_clksel4;
  51. u32 pll_cm_clksel5;
  52. u32 pll_cm_clken2;
  53. u32 cm_polctrl;
  54. u32 iva2_cm_fclken;
  55. u32 iva2_cm_clken_pll;
  56. u32 core_cm_fclken1;
  57. u32 core_cm_fclken3;
  58. u32 sgx_cm_fclken;
  59. u32 wkup_cm_fclken;
  60. u32 dss_cm_fclken;
  61. u32 cam_cm_fclken;
  62. u32 per_cm_fclken;
  63. u32 usbhost_cm_fclken;
  64. u32 core_cm_iclken1;
  65. u32 core_cm_iclken2;
  66. u32 core_cm_iclken3;
  67. u32 sgx_cm_iclken;
  68. u32 wkup_cm_iclken;
  69. u32 dss_cm_iclken;
  70. u32 cam_cm_iclken;
  71. u32 per_cm_iclken;
  72. u32 usbhost_cm_iclken;
  73. u32 iva2_cm_autiidle2;
  74. u32 mpu_cm_autoidle2;
  75. u32 iva2_cm_clkstctrl;
  76. u32 mpu_cm_clkstctrl;
  77. u32 core_cm_clkstctrl;
  78. u32 sgx_cm_clkstctrl;
  79. u32 dss_cm_clkstctrl;
  80. u32 cam_cm_clkstctrl;
  81. u32 per_cm_clkstctrl;
  82. u32 neon_cm_clkstctrl;
  83. u32 usbhost_cm_clkstctrl;
  84. u32 core_cm_autoidle1;
  85. u32 core_cm_autoidle2;
  86. u32 core_cm_autoidle3;
  87. u32 wkup_cm_autoidle;
  88. u32 dss_cm_autoidle;
  89. u32 cam_cm_autoidle;
  90. u32 per_cm_autoidle;
  91. u32 usbhost_cm_autoidle;
  92. u32 sgx_cm_sleepdep;
  93. u32 dss_cm_sleepdep;
  94. u32 cam_cm_sleepdep;
  95. u32 per_cm_sleepdep;
  96. u32 usbhost_cm_sleepdep;
  97. u32 cm_clkout_ctrl;
  98. u32 prm_clkout_ctrl;
  99. u32 sgx_pm_wkdep;
  100. u32 dss_pm_wkdep;
  101. u32 cam_pm_wkdep;
  102. u32 per_pm_wkdep;
  103. u32 neon_pm_wkdep;
  104. u32 usbhost_pm_wkdep;
  105. u32 core_pm_mpugrpsel1;
  106. u32 iva2_pm_ivagrpsel1;
  107. u32 core_pm_mpugrpsel3;
  108. u32 core_pm_ivagrpsel3;
  109. u32 wkup_pm_mpugrpsel;
  110. u32 wkup_pm_ivagrpsel;
  111. u32 per_pm_mpugrpsel;
  112. u32 per_pm_ivagrpsel;
  113. u32 wkup_pm_wken;
  114. };
  115. struct omap3_prcm_regs prcm_context;
  116. u32 omap_prcm_get_reset_sources(void)
  117. {
  118. /* XXX This presumably needs modification for 34XX */
  119. if (cpu_is_omap24xx() | cpu_is_omap34xx())
  120. return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
  121. if (cpu_is_omap44xx())
  122. return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
  123. }
  124. EXPORT_SYMBOL(omap_prcm_get_reset_sources);
  125. /* Resets clock rates and reboots the system. Only called from system.h */
  126. void omap_prcm_arch_reset(char mode)
  127. {
  128. s16 prcm_offs;
  129. if (cpu_is_omap24xx()) {
  130. omap2xxx_clk_prepare_for_reboot();
  131. prcm_offs = WKUP_MOD;
  132. } else if (cpu_is_omap34xx()) {
  133. u32 l;
  134. prcm_offs = OMAP3430_GR_MOD;
  135. l = ('B' << 24) | ('M' << 16) | mode;
  136. /* Reserve the first word in scratchpad for communicating
  137. * with the boot ROM. A pointer to a data structure
  138. * describing the boot process can be stored there,
  139. * cf. OMAP34xx TRM, Initialization / Software Booting
  140. * Configuration. */
  141. omap_writel(l, OMAP343X_SCRATCHPAD + 4);
  142. } else if (cpu_is_omap44xx())
  143. prcm_offs = OMAP4430_PRM_DEVICE_MOD;
  144. else
  145. WARN_ON(1);
  146. if (cpu_is_omap24xx() | cpu_is_omap34xx())
  147. prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs,
  148. OMAP2_RM_RSTCTRL);
  149. if (cpu_is_omap44xx())
  150. prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs,
  151. OMAP4_RM_RSTCTRL);
  152. }
  153. static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
  154. {
  155. BUG_ON(!base);
  156. return __raw_readl(base + module + reg);
  157. }
  158. static inline void __omap_prcm_write(u32 value, void __iomem *base,
  159. s16 module, u16 reg)
  160. {
  161. BUG_ON(!base);
  162. __raw_writel(value, base + module + reg);
  163. }
  164. /* Read a register in a PRM module */
  165. u32 prm_read_mod_reg(s16 module, u16 idx)
  166. {
  167. return __omap_prcm_read(prm_base, module, idx);
  168. }
  169. /* Write into a register in a PRM module */
  170. void prm_write_mod_reg(u32 val, s16 module, u16 idx)
  171. {
  172. __omap_prcm_write(val, prm_base, module, idx);
  173. }
  174. /* Read-modify-write a register in a PRM module. Caller must lock */
  175. u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
  176. {
  177. u32 v;
  178. v = prm_read_mod_reg(module, idx);
  179. v &= ~mask;
  180. v |= bits;
  181. prm_write_mod_reg(v, module, idx);
  182. return v;
  183. }
  184. /* Read a PRM register, AND it, and shift the result down to bit 0 */
  185. u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
  186. {
  187. u32 v;
  188. v = prm_read_mod_reg(domain, idx);
  189. v &= mask;
  190. v >>= __ffs(mask);
  191. return v;
  192. }
  193. /* Read a register in a CM module */
  194. u32 cm_read_mod_reg(s16 module, u16 idx)
  195. {
  196. return __omap_prcm_read(cm_base, module, idx);
  197. }
  198. /* Write into a register in a CM module */
  199. void cm_write_mod_reg(u32 val, s16 module, u16 idx)
  200. {
  201. __omap_prcm_write(val, cm_base, module, idx);
  202. }
  203. /* Read-modify-write a register in a CM module. Caller must lock */
  204. u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
  205. {
  206. u32 v;
  207. v = cm_read_mod_reg(module, idx);
  208. v &= ~mask;
  209. v |= bits;
  210. cm_write_mod_reg(v, module, idx);
  211. return v;
  212. }
  213. /**
  214. * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
  215. * @reg: physical address of module IDLEST register
  216. * @mask: value to mask against to determine if the module is active
  217. * @name: name of the clock (for printk)
  218. *
  219. * Returns 1 if the module indicated readiness in time, or 0 if it
  220. * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
  221. */
  222. int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name)
  223. {
  224. int i = 0;
  225. int ena = 0;
  226. /*
  227. * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
  228. * 34xx reverses this, just to keep us on our toes
  229. */
  230. if (cpu_is_omap24xx())
  231. ena = mask;
  232. else if (cpu_is_omap34xx())
  233. ena = 0;
  234. else
  235. BUG();
  236. /* Wait for lock */
  237. omap_test_timeout(((__raw_readl(reg) & mask) == ena),
  238. MAX_MODULE_ENABLE_WAIT, i);
  239. if (i < MAX_MODULE_ENABLE_WAIT)
  240. pr_debug("cm: Module associated with clock %s ready after %d "
  241. "loops\n", name, i);
  242. else
  243. pr_err("cm: Module associated with clock %s didn't enable in "
  244. "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
  245. return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
  246. };
  247. void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
  248. {
  249. prm_base = omap2_globals->prm;
  250. cm_base = omap2_globals->cm;
  251. cm2_base = omap2_globals->cm2;
  252. }
  253. #ifdef CONFIG_ARCH_OMAP3
  254. void omap3_prcm_save_context(void)
  255. {
  256. prcm_context.control_padconf_sys_nirq =
  257. omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
  258. prcm_context.iva2_cm_clksel1 =
  259. cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
  260. prcm_context.iva2_cm_clksel2 =
  261. cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
  262. prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
  263. prcm_context.sgx_cm_clksel =
  264. cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
  265. prcm_context.dss_cm_clksel =
  266. cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
  267. prcm_context.cam_cm_clksel =
  268. cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
  269. prcm_context.per_cm_clksel =
  270. cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
  271. prcm_context.emu_cm_clksel =
  272. cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
  273. prcm_context.emu_cm_clkstctrl =
  274. cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
  275. prcm_context.pll_cm_autoidle2 =
  276. cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
  277. prcm_context.pll_cm_clksel4 =
  278. cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
  279. prcm_context.pll_cm_clksel5 =
  280. cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
  281. prcm_context.pll_cm_clken2 =
  282. cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
  283. prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
  284. prcm_context.iva2_cm_fclken =
  285. cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
  286. prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD,
  287. OMAP3430_CM_CLKEN_PLL);
  288. prcm_context.core_cm_fclken1 =
  289. cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  290. prcm_context.core_cm_fclken3 =
  291. cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
  292. prcm_context.sgx_cm_fclken =
  293. cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
  294. prcm_context.wkup_cm_fclken =
  295. cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
  296. prcm_context.dss_cm_fclken =
  297. cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
  298. prcm_context.cam_cm_fclken =
  299. cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
  300. prcm_context.per_cm_fclken =
  301. cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
  302. prcm_context.usbhost_cm_fclken =
  303. cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
  304. prcm_context.core_cm_iclken1 =
  305. cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
  306. prcm_context.core_cm_iclken2 =
  307. cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
  308. prcm_context.core_cm_iclken3 =
  309. cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
  310. prcm_context.sgx_cm_iclken =
  311. cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
  312. prcm_context.wkup_cm_iclken =
  313. cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
  314. prcm_context.dss_cm_iclken =
  315. cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
  316. prcm_context.cam_cm_iclken =
  317. cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
  318. prcm_context.per_cm_iclken =
  319. cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
  320. prcm_context.usbhost_cm_iclken =
  321. cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
  322. prcm_context.iva2_cm_autiidle2 =
  323. cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
  324. prcm_context.mpu_cm_autoidle2 =
  325. cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
  326. prcm_context.iva2_cm_clkstctrl =
  327. cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
  328. prcm_context.mpu_cm_clkstctrl =
  329. cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
  330. prcm_context.core_cm_clkstctrl =
  331. cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
  332. prcm_context.sgx_cm_clkstctrl =
  333. cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
  334. OMAP2_CM_CLKSTCTRL);
  335. prcm_context.dss_cm_clkstctrl =
  336. cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
  337. prcm_context.cam_cm_clkstctrl =
  338. cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
  339. prcm_context.per_cm_clkstctrl =
  340. cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
  341. prcm_context.neon_cm_clkstctrl =
  342. cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
  343. prcm_context.usbhost_cm_clkstctrl =
  344. cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
  345. OMAP2_CM_CLKSTCTRL);
  346. prcm_context.core_cm_autoidle1 =
  347. cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
  348. prcm_context.core_cm_autoidle2 =
  349. cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
  350. prcm_context.core_cm_autoidle3 =
  351. cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
  352. prcm_context.wkup_cm_autoidle =
  353. cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
  354. prcm_context.dss_cm_autoidle =
  355. cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
  356. prcm_context.cam_cm_autoidle =
  357. cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
  358. prcm_context.per_cm_autoidle =
  359. cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
  360. prcm_context.usbhost_cm_autoidle =
  361. cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
  362. prcm_context.sgx_cm_sleepdep =
  363. cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP);
  364. prcm_context.dss_cm_sleepdep =
  365. cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
  366. prcm_context.cam_cm_sleepdep =
  367. cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
  368. prcm_context.per_cm_sleepdep =
  369. cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
  370. prcm_context.usbhost_cm_sleepdep =
  371. cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
  372. prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD,
  373. OMAP3_CM_CLKOUT_CTRL_OFFSET);
  374. prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD,
  375. OMAP3_PRM_CLKOUT_CTRL_OFFSET);
  376. prcm_context.sgx_pm_wkdep =
  377. prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP);
  378. prcm_context.dss_pm_wkdep =
  379. prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP);
  380. prcm_context.cam_pm_wkdep =
  381. prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP);
  382. prcm_context.per_pm_wkdep =
  383. prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP);
  384. prcm_context.neon_pm_wkdep =
  385. prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP);
  386. prcm_context.usbhost_pm_wkdep =
  387. prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
  388. prcm_context.core_pm_mpugrpsel1 =
  389. prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1);
  390. prcm_context.iva2_pm_ivagrpsel1 =
  391. prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1);
  392. prcm_context.core_pm_mpugrpsel3 =
  393. prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3);
  394. prcm_context.core_pm_ivagrpsel3 =
  395. prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
  396. prcm_context.wkup_pm_mpugrpsel =
  397. prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
  398. prcm_context.wkup_pm_ivagrpsel =
  399. prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
  400. prcm_context.per_pm_mpugrpsel =
  401. prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
  402. prcm_context.per_pm_ivagrpsel =
  403. prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
  404. prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
  405. return;
  406. }
  407. void omap3_prcm_restore_context(void)
  408. {
  409. omap_ctrl_writel(prcm_context.control_padconf_sys_nirq,
  410. OMAP343X_CONTROL_PADCONF_SYSNIRQ);
  411. cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
  412. CM_CLKSEL1);
  413. cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
  414. CM_CLKSEL2);
  415. __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
  416. cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
  417. CM_CLKSEL);
  418. cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
  419. CM_CLKSEL);
  420. cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
  421. CM_CLKSEL);
  422. cm_write_mod_reg(prcm_context.per_cm_clksel, OMAP3430_PER_MOD,
  423. CM_CLKSEL);
  424. cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
  425. CM_CLKSEL1);
  426. cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
  427. OMAP2_CM_CLKSTCTRL);
  428. cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD,
  429. CM_AUTOIDLE2);
  430. cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD,
  431. OMAP3430ES2_CM_CLKSEL4);
  432. cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
  433. OMAP3430ES2_CM_CLKSEL5);
  434. cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
  435. OMAP3430ES2_CM_CLKEN2);
  436. __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
  437. cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
  438. CM_FCLKEN);
  439. cm_write_mod_reg(prcm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
  440. OMAP3430_CM_CLKEN_PLL);
  441. cm_write_mod_reg(prcm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1);
  442. cm_write_mod_reg(prcm_context.core_cm_fclken3, CORE_MOD,
  443. OMAP3430ES2_CM_FCLKEN3);
  444. cm_write_mod_reg(prcm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
  445. CM_FCLKEN);
  446. cm_write_mod_reg(prcm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
  447. cm_write_mod_reg(prcm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
  448. CM_FCLKEN);
  449. cm_write_mod_reg(prcm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
  450. CM_FCLKEN);
  451. cm_write_mod_reg(prcm_context.per_cm_fclken, OMAP3430_PER_MOD,
  452. CM_FCLKEN);
  453. cm_write_mod_reg(prcm_context.usbhost_cm_fclken,
  454. OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
  455. cm_write_mod_reg(prcm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1);
  456. cm_write_mod_reg(prcm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2);
  457. cm_write_mod_reg(prcm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3);
  458. cm_write_mod_reg(prcm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
  459. CM_ICLKEN);
  460. cm_write_mod_reg(prcm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
  461. cm_write_mod_reg(prcm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
  462. CM_ICLKEN);
  463. cm_write_mod_reg(prcm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
  464. CM_ICLKEN);
  465. cm_write_mod_reg(prcm_context.per_cm_iclken, OMAP3430_PER_MOD,
  466. CM_ICLKEN);
  467. cm_write_mod_reg(prcm_context.usbhost_cm_iclken,
  468. OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
  469. cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD,
  470. CM_AUTOIDLE2);
  471. cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
  472. cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
  473. OMAP2_CM_CLKSTCTRL);
  474. cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD,
  475. OMAP2_CM_CLKSTCTRL);
  476. cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD,
  477. OMAP2_CM_CLKSTCTRL);
  478. cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
  479. OMAP2_CM_CLKSTCTRL);
  480. cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
  481. OMAP2_CM_CLKSTCTRL);
  482. cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
  483. OMAP2_CM_CLKSTCTRL);
  484. cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
  485. OMAP2_CM_CLKSTCTRL);
  486. cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
  487. OMAP2_CM_CLKSTCTRL);
  488. cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl,
  489. OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
  490. cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD,
  491. CM_AUTOIDLE1);
  492. cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD,
  493. CM_AUTOIDLE2);
  494. cm_write_mod_reg(prcm_context.core_cm_autoidle3, CORE_MOD,
  495. CM_AUTOIDLE3);
  496. cm_write_mod_reg(prcm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE);
  497. cm_write_mod_reg(prcm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
  498. CM_AUTOIDLE);
  499. cm_write_mod_reg(prcm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
  500. CM_AUTOIDLE);
  501. cm_write_mod_reg(prcm_context.per_cm_autoidle, OMAP3430_PER_MOD,
  502. CM_AUTOIDLE);
  503. cm_write_mod_reg(prcm_context.usbhost_cm_autoidle,
  504. OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
  505. cm_write_mod_reg(prcm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
  506. OMAP3430_CM_SLEEPDEP);
  507. cm_write_mod_reg(prcm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
  508. OMAP3430_CM_SLEEPDEP);
  509. cm_write_mod_reg(prcm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
  510. OMAP3430_CM_SLEEPDEP);
  511. cm_write_mod_reg(prcm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
  512. OMAP3430_CM_SLEEPDEP);
  513. cm_write_mod_reg(prcm_context.usbhost_cm_sleepdep,
  514. OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
  515. cm_write_mod_reg(prcm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
  516. OMAP3_CM_CLKOUT_CTRL_OFFSET);
  517. prm_write_mod_reg(prcm_context.prm_clkout_ctrl, OMAP3430_CCR_MOD,
  518. OMAP3_PRM_CLKOUT_CTRL_OFFSET);
  519. prm_write_mod_reg(prcm_context.sgx_pm_wkdep, OMAP3430ES2_SGX_MOD,
  520. PM_WKDEP);
  521. prm_write_mod_reg(prcm_context.dss_pm_wkdep, OMAP3430_DSS_MOD,
  522. PM_WKDEP);
  523. prm_write_mod_reg(prcm_context.cam_pm_wkdep, OMAP3430_CAM_MOD,
  524. PM_WKDEP);
  525. prm_write_mod_reg(prcm_context.per_pm_wkdep, OMAP3430_PER_MOD,
  526. PM_WKDEP);
  527. prm_write_mod_reg(prcm_context.neon_pm_wkdep, OMAP3430_NEON_MOD,
  528. PM_WKDEP);
  529. prm_write_mod_reg(prcm_context.usbhost_pm_wkdep,
  530. OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
  531. prm_write_mod_reg(prcm_context.core_pm_mpugrpsel1, CORE_MOD,
  532. OMAP3430_PM_MPUGRPSEL1);
  533. prm_write_mod_reg(prcm_context.iva2_pm_ivagrpsel1, OMAP3430_IVA2_MOD,
  534. OMAP3430_PM_IVAGRPSEL1);
  535. prm_write_mod_reg(prcm_context.core_pm_mpugrpsel3, CORE_MOD,
  536. OMAP3430ES2_PM_MPUGRPSEL3);
  537. prm_write_mod_reg(prcm_context.core_pm_ivagrpsel3, CORE_MOD,
  538. OMAP3430ES2_PM_IVAGRPSEL3);
  539. prm_write_mod_reg(prcm_context.wkup_pm_mpugrpsel, WKUP_MOD,
  540. OMAP3430_PM_MPUGRPSEL);
  541. prm_write_mod_reg(prcm_context.wkup_pm_ivagrpsel, WKUP_MOD,
  542. OMAP3430_PM_IVAGRPSEL);
  543. prm_write_mod_reg(prcm_context.per_pm_mpugrpsel, OMAP3430_PER_MOD,
  544. OMAP3430_PM_MPUGRPSEL);
  545. prm_write_mod_reg(prcm_context.per_pm_ivagrpsel, OMAP3430_PER_MOD,
  546. OMAP3430_PM_IVAGRPSEL);
  547. prm_write_mod_reg(prcm_context.wkup_pm_wken, WKUP_MOD, PM_WKEN);
  548. return;
  549. }
  550. #endif