powerdomains34xx.h 6.2 KB

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  1. /*
  2. * OMAP3 powerdomain definitions
  3. *
  4. * Copyright (C) 2007-2008 Texas Instruments, Inc.
  5. * Copyright (C) 2007-2010 Nokia Corporation
  6. *
  7. * Written by Paul Walmsley
  8. * Debugging and integration fixes by Jouni Högander
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
  15. #define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
  16. /*
  17. * N.B. If powerdomains are added or removed from this file, update
  18. * the array in mach-omap2/powerdomains.h.
  19. */
  20. #include <plat/powerdomain.h>
  21. #include "prcm-common.h"
  22. #include "prm.h"
  23. #include "prm-regbits-34xx.h"
  24. #include "cm.h"
  25. #include "cm-regbits-34xx.h"
  26. /*
  27. * 34XX-specific powerdomains, dependencies
  28. */
  29. #ifdef CONFIG_ARCH_OMAP3
  30. /*
  31. * Powerdomains
  32. */
  33. static struct powerdomain iva2_pwrdm = {
  34. .name = "iva2_pwrdm",
  35. .prcm_offs = OMAP3430_IVA2_MOD,
  36. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  37. .pwrsts = PWRSTS_OFF_RET_ON,
  38. .pwrsts_logic_ret = PWRSTS_OFF_RET,
  39. .banks = 4,
  40. .pwrsts_mem_ret = {
  41. [0] = PWRSTS_OFF_RET,
  42. [1] = PWRSTS_OFF_RET,
  43. [2] = PWRSTS_OFF_RET,
  44. [3] = PWRSTS_OFF_RET,
  45. },
  46. .pwrsts_mem_on = {
  47. [0] = PWRDM_POWER_ON,
  48. [1] = PWRDM_POWER_ON,
  49. [2] = PWRSTS_OFF_ON,
  50. [3] = PWRDM_POWER_ON,
  51. },
  52. };
  53. static struct powerdomain mpu_3xxx_pwrdm = {
  54. .name = "mpu_pwrdm",
  55. .prcm_offs = MPU_MOD,
  56. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  57. .pwrsts = PWRSTS_OFF_RET_ON,
  58. .pwrsts_logic_ret = PWRSTS_OFF_RET,
  59. .flags = PWRDM_HAS_MPU_QUIRK,
  60. .banks = 1,
  61. .pwrsts_mem_ret = {
  62. [0] = PWRSTS_OFF_RET,
  63. },
  64. .pwrsts_mem_on = {
  65. [0] = PWRSTS_OFF_ON,
  66. },
  67. };
  68. static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
  69. .name = "core_pwrdm",
  70. .prcm_offs = CORE_MOD,
  71. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
  72. CHIP_IS_OMAP3430ES2 |
  73. CHIP_IS_OMAP3430ES3_0),
  74. .pwrsts = PWRSTS_OFF_RET_ON,
  75. .banks = 2,
  76. .pwrsts_mem_ret = {
  77. [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
  78. [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
  79. },
  80. .pwrsts_mem_on = {
  81. [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
  82. [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
  83. },
  84. };
  85. static struct powerdomain core_3xxx_es3_1_pwrdm = {
  86. .name = "core_pwrdm",
  87. .prcm_offs = CORE_MOD,
  88. .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1),
  89. .pwrsts = PWRSTS_OFF_RET_ON,
  90. .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
  91. .banks = 2,
  92. .pwrsts_mem_ret = {
  93. [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
  94. [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
  95. },
  96. .pwrsts_mem_on = {
  97. [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
  98. [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
  99. },
  100. };
  101. static struct powerdomain dss_pwrdm = {
  102. .name = "dss_pwrdm",
  103. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  104. .prcm_offs = OMAP3430_DSS_MOD,
  105. .pwrsts = PWRSTS_OFF_RET_ON,
  106. .pwrsts_logic_ret = PWRDM_POWER_RET,
  107. .banks = 1,
  108. .pwrsts_mem_ret = {
  109. [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
  110. },
  111. .pwrsts_mem_on = {
  112. [0] = PWRDM_POWER_ON, /* MEMONSTATE */
  113. },
  114. };
  115. /*
  116. * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
  117. * possible SGX powerstate, the SGX device itself does not support
  118. * retention.
  119. */
  120. static struct powerdomain sgx_pwrdm = {
  121. .name = "sgx_pwrdm",
  122. .prcm_offs = OMAP3430ES2_SGX_MOD,
  123. .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
  124. /* XXX This is accurate for 3430 SGX, but what about GFX? */
  125. .pwrsts = PWRSTS_OFF_ON,
  126. .pwrsts_logic_ret = PWRDM_POWER_RET,
  127. .banks = 1,
  128. .pwrsts_mem_ret = {
  129. [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
  130. },
  131. .pwrsts_mem_on = {
  132. [0] = PWRDM_POWER_ON, /* MEMONSTATE */
  133. },
  134. };
  135. static struct powerdomain cam_pwrdm = {
  136. .name = "cam_pwrdm",
  137. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  138. .prcm_offs = OMAP3430_CAM_MOD,
  139. .pwrsts = PWRSTS_OFF_RET_ON,
  140. .pwrsts_logic_ret = PWRDM_POWER_RET,
  141. .banks = 1,
  142. .pwrsts_mem_ret = {
  143. [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
  144. },
  145. .pwrsts_mem_on = {
  146. [0] = PWRDM_POWER_ON, /* MEMONSTATE */
  147. },
  148. };
  149. static struct powerdomain per_pwrdm = {
  150. .name = "per_pwrdm",
  151. .prcm_offs = OMAP3430_PER_MOD,
  152. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  153. .pwrsts = PWRSTS_OFF_RET_ON,
  154. .pwrsts_logic_ret = PWRSTS_OFF_RET,
  155. .banks = 1,
  156. .pwrsts_mem_ret = {
  157. [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
  158. },
  159. .pwrsts_mem_on = {
  160. [0] = PWRDM_POWER_ON, /* MEMONSTATE */
  161. },
  162. };
  163. static struct powerdomain emu_pwrdm = {
  164. .name = "emu_pwrdm",
  165. .prcm_offs = OMAP3430_EMU_MOD,
  166. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  167. };
  168. static struct powerdomain neon_pwrdm = {
  169. .name = "neon_pwrdm",
  170. .prcm_offs = OMAP3430_NEON_MOD,
  171. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  172. .pwrsts = PWRSTS_OFF_RET_ON,
  173. .pwrsts_logic_ret = PWRDM_POWER_RET,
  174. };
  175. static struct powerdomain usbhost_pwrdm = {
  176. .name = "usbhost_pwrdm",
  177. .prcm_offs = OMAP3430ES2_USBHOST_MOD,
  178. .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
  179. .pwrsts = PWRSTS_OFF_RET_ON,
  180. .pwrsts_logic_ret = PWRDM_POWER_RET,
  181. /*
  182. * REVISIT: Enabling usb host save and restore mechanism seems to
  183. * leave the usb host domain permanently in ACTIVE mode after
  184. * changing the usb host power domain state from OFF to active once.
  185. * Disabling for now.
  186. */
  187. /*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
  188. .banks = 1,
  189. .pwrsts_mem_ret = {
  190. [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
  191. },
  192. .pwrsts_mem_on = {
  193. [0] = PWRDM_POWER_ON, /* MEMONSTATE */
  194. },
  195. };
  196. static struct powerdomain dpll1_pwrdm = {
  197. .name = "dpll1_pwrdm",
  198. .prcm_offs = MPU_MOD,
  199. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  200. };
  201. static struct powerdomain dpll2_pwrdm = {
  202. .name = "dpll2_pwrdm",
  203. .prcm_offs = OMAP3430_IVA2_MOD,
  204. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  205. };
  206. static struct powerdomain dpll3_pwrdm = {
  207. .name = "dpll3_pwrdm",
  208. .prcm_offs = PLL_MOD,
  209. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  210. };
  211. static struct powerdomain dpll4_pwrdm = {
  212. .name = "dpll4_pwrdm",
  213. .prcm_offs = PLL_MOD,
  214. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  215. };
  216. static struct powerdomain dpll5_pwrdm = {
  217. .name = "dpll5_pwrdm",
  218. .prcm_offs = PLL_MOD,
  219. .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
  220. };
  221. #endif /* CONFIG_ARCH_OMAP3 */
  222. #endif