sdhci-esdhc-imx.c 10 KB

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  1. /*
  2. * Freescale eSDHC i.MX controller driver for the platform bus.
  3. *
  4. * derived from the OF-version.
  5. *
  6. * Copyright (c) 2010 Pengutronix e.K.
  7. * Author: Wolfram Sang <w.sang@pengutronix.de>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License.
  12. */
  13. #include <linux/io.h>
  14. #include <linux/delay.h>
  15. #include <linux/err.h>
  16. #include <linux/clk.h>
  17. #include <linux/gpio.h>
  18. #include <linux/slab.h>
  19. #include <linux/mmc/host.h>
  20. #include <linux/mmc/mmc.h>
  21. #include <linux/mmc/sdio.h>
  22. #include <mach/hardware.h>
  23. #include <mach/esdhc.h>
  24. #include "sdhci-pltfm.h"
  25. #include "sdhci-esdhc.h"
  26. /* VENDOR SPEC register */
  27. #define SDHCI_VENDOR_SPEC 0xC0
  28. #define SDHCI_VENDOR_SPEC_SDIO_QUIRK 0x00000002
  29. #define ESDHC_FLAG_GPIO_FOR_CD_WP (1 << 0)
  30. /*
  31. * The CMDTYPE of the CMD register (offset 0xE) should be set to
  32. * "11" when the STOP CMD12 is issued on imx53 to abort one
  33. * open ended multi-blk IO. Otherwise the TC INT wouldn't
  34. * be generated.
  35. * In exact block transfer, the controller doesn't complete the
  36. * operations automatically as required at the end of the
  37. * transfer and remains on hold if the abort command is not sent.
  38. * As a result, the TC flag is not asserted and SW received timeout
  39. * exeception. Bit1 of Vendor Spec registor is used to fix it.
  40. */
  41. #define ESDHC_FLAG_MULTIBLK_NO_INT (1 << 1)
  42. struct pltfm_imx_data {
  43. int flags;
  44. u32 scratchpad;
  45. };
  46. static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
  47. {
  48. void __iomem *base = host->ioaddr + (reg & ~0x3);
  49. u32 shift = (reg & 0x3) * 8;
  50. writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
  51. }
  52. static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
  53. {
  54. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  55. struct pltfm_imx_data *imx_data = pltfm_host->priv;
  56. /* fake CARD_PRESENT flag on mx25/35 */
  57. u32 val = readl(host->ioaddr + reg);
  58. if (unlikely((reg == SDHCI_PRESENT_STATE)
  59. && (imx_data->flags & ESDHC_FLAG_GPIO_FOR_CD_WP))) {
  60. struct esdhc_platform_data *boarddata =
  61. host->mmc->parent->platform_data;
  62. if (boarddata && gpio_is_valid(boarddata->cd_gpio)
  63. && gpio_get_value(boarddata->cd_gpio))
  64. /* no card, if a valid gpio says so... */
  65. val &= ~SDHCI_CARD_PRESENT;
  66. else
  67. /* ... in all other cases assume card is present */
  68. val |= SDHCI_CARD_PRESENT;
  69. }
  70. return val;
  71. }
  72. static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
  73. {
  74. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  75. struct pltfm_imx_data *imx_data = pltfm_host->priv;
  76. if (unlikely((reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)
  77. && (imx_data->flags & ESDHC_FLAG_GPIO_FOR_CD_WP)))
  78. /*
  79. * these interrupts won't work with a custom card_detect gpio
  80. * (only applied to mx25/35)
  81. */
  82. val &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
  83. if (unlikely((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
  84. && (reg == SDHCI_INT_STATUS)
  85. && (val & SDHCI_INT_DATA_END))) {
  86. u32 v;
  87. v = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
  88. v &= ~SDHCI_VENDOR_SPEC_SDIO_QUIRK;
  89. writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
  90. }
  91. writel(val, host->ioaddr + reg);
  92. }
  93. static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
  94. {
  95. if (unlikely(reg == SDHCI_HOST_VERSION))
  96. reg ^= 2;
  97. return readw(host->ioaddr + reg);
  98. }
  99. static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
  100. {
  101. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  102. struct pltfm_imx_data *imx_data = pltfm_host->priv;
  103. switch (reg) {
  104. case SDHCI_TRANSFER_MODE:
  105. /*
  106. * Postpone this write, we must do it together with a
  107. * command write that is down below.
  108. */
  109. if ((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
  110. && (host->cmd->opcode == SD_IO_RW_EXTENDED)
  111. && (host->cmd->data->blocks > 1)
  112. && (host->cmd->data->flags & MMC_DATA_READ)) {
  113. u32 v;
  114. v = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
  115. v |= SDHCI_VENDOR_SPEC_SDIO_QUIRK;
  116. writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
  117. }
  118. imx_data->scratchpad = val;
  119. return;
  120. case SDHCI_COMMAND:
  121. if ((host->cmd->opcode == MMC_STOP_TRANSMISSION)
  122. && (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
  123. val |= SDHCI_CMD_ABORTCMD;
  124. writel(val << 16 | imx_data->scratchpad,
  125. host->ioaddr + SDHCI_TRANSFER_MODE);
  126. return;
  127. case SDHCI_BLOCK_SIZE:
  128. val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
  129. break;
  130. }
  131. esdhc_clrset_le(host, 0xffff, val, reg);
  132. }
  133. static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
  134. {
  135. u32 new_val;
  136. switch (reg) {
  137. case SDHCI_POWER_CONTROL:
  138. /*
  139. * FSL put some DMA bits here
  140. * If your board has a regulator, code should be here
  141. */
  142. return;
  143. case SDHCI_HOST_CONTROL:
  144. /* FSL messed up here, so we can just keep those two */
  145. new_val = val & (SDHCI_CTRL_LED | SDHCI_CTRL_4BITBUS);
  146. /* ensure the endianess */
  147. new_val |= ESDHC_HOST_CONTROL_LE;
  148. /* DMA mode bits are shifted */
  149. new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
  150. esdhc_clrset_le(host, 0xffff, new_val, reg);
  151. return;
  152. }
  153. esdhc_clrset_le(host, 0xff, val, reg);
  154. }
  155. static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
  156. {
  157. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  158. return clk_get_rate(pltfm_host->clk);
  159. }
  160. static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
  161. {
  162. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  163. return clk_get_rate(pltfm_host->clk) / 256 / 16;
  164. }
  165. static struct sdhci_ops sdhci_esdhc_ops = {
  166. .read_l = esdhc_readl_le,
  167. .read_w = esdhc_readw_le,
  168. .write_l = esdhc_writel_le,
  169. .write_w = esdhc_writew_le,
  170. .write_b = esdhc_writeb_le,
  171. .set_clock = esdhc_set_clock,
  172. .get_max_clock = esdhc_pltfm_get_max_clock,
  173. .get_min_clock = esdhc_pltfm_get_min_clock,
  174. };
  175. static struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
  176. .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_ADMA
  177. | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
  178. /* ADMA has issues. Might be fixable */
  179. .ops = &sdhci_esdhc_ops,
  180. };
  181. static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
  182. {
  183. struct esdhc_platform_data *boarddata =
  184. host->mmc->parent->platform_data;
  185. if (boarddata && gpio_is_valid(boarddata->wp_gpio))
  186. return gpio_get_value(boarddata->wp_gpio);
  187. else
  188. return -ENOSYS;
  189. }
  190. static irqreturn_t cd_irq(int irq, void *data)
  191. {
  192. struct sdhci_host *sdhost = (struct sdhci_host *)data;
  193. tasklet_schedule(&sdhost->card_tasklet);
  194. return IRQ_HANDLED;
  195. };
  196. static int __devinit sdhci_esdhc_imx_probe(struct platform_device *pdev)
  197. {
  198. struct sdhci_pltfm_host *pltfm_host;
  199. struct sdhci_host *host;
  200. struct esdhc_platform_data *boarddata;
  201. struct clk *clk;
  202. int err;
  203. struct pltfm_imx_data *imx_data;
  204. host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata);
  205. if (IS_ERR(host))
  206. return PTR_ERR(host);
  207. pltfm_host = sdhci_priv(host);
  208. imx_data = kzalloc(sizeof(struct pltfm_imx_data), GFP_KERNEL);
  209. if (!imx_data)
  210. return -ENOMEM;
  211. pltfm_host->priv = imx_data;
  212. clk = clk_get(mmc_dev(host->mmc), NULL);
  213. if (IS_ERR(clk)) {
  214. dev_err(mmc_dev(host->mmc), "clk err\n");
  215. err = PTR_ERR(clk);
  216. goto err_clk_get;
  217. }
  218. clk_enable(clk);
  219. pltfm_host->clk = clk;
  220. if (!cpu_is_mx25())
  221. host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
  222. if (cpu_is_mx25() || cpu_is_mx35()) {
  223. /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
  224. host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK;
  225. /* write_protect can't be routed to controller, use gpio */
  226. sdhci_esdhc_ops.get_ro = esdhc_pltfm_get_ro;
  227. }
  228. if (!(cpu_is_mx25() || cpu_is_mx35() || cpu_is_mx51()))
  229. imx_data->flags |= ESDHC_FLAG_MULTIBLK_NO_INT;
  230. boarddata = host->mmc->parent->platform_data;
  231. if (boarddata) {
  232. err = gpio_request_one(boarddata->wp_gpio, GPIOF_IN, "ESDHC_WP");
  233. if (err) {
  234. dev_warn(mmc_dev(host->mmc),
  235. "no write-protect pin available!\n");
  236. boarddata->wp_gpio = err;
  237. }
  238. err = gpio_request_one(boarddata->cd_gpio, GPIOF_IN, "ESDHC_CD");
  239. if (err) {
  240. dev_warn(mmc_dev(host->mmc),
  241. "no card-detect pin available!\n");
  242. goto no_card_detect_pin;
  243. }
  244. /* i.MX5x has issues to be researched */
  245. if (!cpu_is_mx25() && !cpu_is_mx35())
  246. goto not_supported;
  247. err = request_irq(gpio_to_irq(boarddata->cd_gpio), cd_irq,
  248. IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
  249. mmc_hostname(host->mmc), host);
  250. if (err) {
  251. dev_warn(mmc_dev(host->mmc), "request irq error\n");
  252. goto no_card_detect_irq;
  253. }
  254. imx_data->flags |= ESDHC_FLAG_GPIO_FOR_CD_WP;
  255. /* Now we have a working card_detect again */
  256. host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
  257. }
  258. err = sdhci_add_host(host);
  259. if (err)
  260. goto err_add_host;
  261. return 0;
  262. no_card_detect_irq:
  263. gpio_free(boarddata->cd_gpio);
  264. no_card_detect_pin:
  265. boarddata->cd_gpio = err;
  266. not_supported:
  267. kfree(imx_data);
  268. err_add_host:
  269. clk_disable(pltfm_host->clk);
  270. clk_put(pltfm_host->clk);
  271. err_clk_get:
  272. sdhci_pltfm_free(pdev);
  273. return err;
  274. }
  275. static int __devexit sdhci_esdhc_imx_remove(struct platform_device *pdev)
  276. {
  277. struct sdhci_host *host = platform_get_drvdata(pdev);
  278. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  279. struct esdhc_platform_data *boarddata = host->mmc->parent->platform_data;
  280. struct pltfm_imx_data *imx_data = pltfm_host->priv;
  281. int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
  282. sdhci_remove_host(host, dead);
  283. if (boarddata && gpio_is_valid(boarddata->wp_gpio))
  284. gpio_free(boarddata->wp_gpio);
  285. if (boarddata && gpio_is_valid(boarddata->cd_gpio)) {
  286. gpio_free(boarddata->cd_gpio);
  287. if (!(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION))
  288. free_irq(gpio_to_irq(boarddata->cd_gpio), host);
  289. }
  290. clk_disable(pltfm_host->clk);
  291. clk_put(pltfm_host->clk);
  292. kfree(imx_data);
  293. sdhci_pltfm_free(pdev);
  294. return 0;
  295. }
  296. static struct platform_driver sdhci_esdhc_imx_driver = {
  297. .driver = {
  298. .name = "sdhci-esdhc-imx",
  299. .owner = THIS_MODULE,
  300. },
  301. .probe = sdhci_esdhc_imx_probe,
  302. .remove = __devexit_p(sdhci_esdhc_imx_remove),
  303. #ifdef CONFIG_PM
  304. .suspend = sdhci_pltfm_suspend,
  305. .resume = sdhci_pltfm_resume,
  306. #endif
  307. };
  308. static int __init sdhci_esdhc_imx_init(void)
  309. {
  310. return platform_driver_register(&sdhci_esdhc_imx_driver);
  311. }
  312. module_init(sdhci_esdhc_imx_init);
  313. static void __exit sdhci_esdhc_imx_exit(void)
  314. {
  315. platform_driver_unregister(&sdhci_esdhc_imx_driver);
  316. }
  317. module_exit(sdhci_esdhc_imx_exit);
  318. MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
  319. MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
  320. MODULE_LICENSE("GPL v2");