tegra-seaboard.dts 9.3 KB

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  1. /dts-v1/;
  2. /include/ "tegra20.dtsi"
  3. / {
  4. model = "NVIDIA Seaboard";
  5. compatible = "nvidia,seaboard", "nvidia,tegra20";
  6. memory {
  7. device_type = "memory";
  8. reg = < 0x00000000 0x40000000 >;
  9. };
  10. pinmux@70000000 {
  11. pinctrl-names = "default";
  12. pinctrl-0 = <&state_default>;
  13. state_default: pinmux {
  14. ata {
  15. nvidia,pins = "ata";
  16. nvidia,function = "ide";
  17. };
  18. atb {
  19. nvidia,pins = "atb", "gma", "gme";
  20. nvidia,function = "sdio4";
  21. };
  22. atc {
  23. nvidia,pins = "atc";
  24. nvidia,function = "nand";
  25. };
  26. atd {
  27. nvidia,pins = "atd", "ate", "gmb", "spia",
  28. "spib", "spic";
  29. nvidia,function = "gmi";
  30. };
  31. cdev1 {
  32. nvidia,pins = "cdev1";
  33. nvidia,function = "plla_out";
  34. };
  35. cdev2 {
  36. nvidia,pins = "cdev2";
  37. nvidia,function = "pllp_out4";
  38. };
  39. crtp {
  40. nvidia,pins = "crtp", "lm1";
  41. nvidia,function = "crt";
  42. };
  43. csus {
  44. nvidia,pins = "csus";
  45. nvidia,function = "vi_sensor_clk";
  46. };
  47. dap1 {
  48. nvidia,pins = "dap1";
  49. nvidia,function = "dap1";
  50. };
  51. dap2 {
  52. nvidia,pins = "dap2";
  53. nvidia,function = "dap2";
  54. };
  55. dap3 {
  56. nvidia,pins = "dap3";
  57. nvidia,function = "dap3";
  58. };
  59. dap4 {
  60. nvidia,pins = "dap4";
  61. nvidia,function = "dap4";
  62. };
  63. ddc {
  64. nvidia,pins = "ddc", "owc", "spdi", "spdo",
  65. "uac";
  66. nvidia,function = "rsvd2";
  67. };
  68. dta {
  69. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  70. nvidia,function = "vi";
  71. };
  72. dtf {
  73. nvidia,pins = "dtf";
  74. nvidia,function = "i2c3";
  75. };
  76. gmc {
  77. nvidia,pins = "gmc";
  78. nvidia,function = "uartd";
  79. };
  80. gmd {
  81. nvidia,pins = "gmd";
  82. nvidia,function = "sflash";
  83. };
  84. gpu {
  85. nvidia,pins = "gpu";
  86. nvidia,function = "pwm";
  87. };
  88. gpu7 {
  89. nvidia,pins = "gpu7";
  90. nvidia,function = "rtck";
  91. };
  92. gpv {
  93. nvidia,pins = "gpv", "slxa", "slxk";
  94. nvidia,function = "pcie";
  95. };
  96. hdint {
  97. nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
  98. "lsck", "lsda";
  99. nvidia,function = "hdmi";
  100. };
  101. i2cp {
  102. nvidia,pins = "i2cp";
  103. nvidia,function = "i2cp";
  104. };
  105. irrx {
  106. nvidia,pins = "irrx", "irtx";
  107. nvidia,function = "uartb";
  108. };
  109. kbca {
  110. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  111. "kbce", "kbcf";
  112. nvidia,function = "kbc";
  113. };
  114. lcsn {
  115. nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
  116. "lsdi", "lvp0";
  117. nvidia,function = "rsvd4";
  118. };
  119. ld0 {
  120. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  121. "ld5", "ld6", "ld7", "ld8", "ld9",
  122. "ld10", "ld11", "ld12", "ld13", "ld14",
  123. "ld15", "ld16", "ld17", "ldi", "lhp0",
  124. "lhp1", "lhp2", "lhs", "lpp", "lsc0",
  125. "lspi", "lvp1", "lvs";
  126. nvidia,function = "displaya";
  127. };
  128. pmc {
  129. nvidia,pins = "pmc";
  130. nvidia,function = "pwr_on";
  131. };
  132. pta {
  133. nvidia,pins = "pta";
  134. nvidia,function = "i2c2";
  135. };
  136. rm {
  137. nvidia,pins = "rm";
  138. nvidia,function = "i2c1";
  139. };
  140. sdb {
  141. nvidia,pins = "sdb", "sdc", "sdd";
  142. nvidia,function = "sdio3";
  143. };
  144. sdio1 {
  145. nvidia,pins = "sdio1";
  146. nvidia,function = "sdio1";
  147. };
  148. slxc {
  149. nvidia,pins = "slxc", "slxd";
  150. nvidia,function = "spdif";
  151. };
  152. spid {
  153. nvidia,pins = "spid", "spie", "spif";
  154. nvidia,function = "spi1";
  155. };
  156. spig {
  157. nvidia,pins = "spig", "spih";
  158. nvidia,function = "spi2_alt";
  159. };
  160. uaa {
  161. nvidia,pins = "uaa", "uab", "uda";
  162. nvidia,function = "ulpi";
  163. };
  164. uad {
  165. nvidia,pins = "uad";
  166. nvidia,function = "irda";
  167. };
  168. uca {
  169. nvidia,pins = "uca", "ucb";
  170. nvidia,function = "uartc";
  171. };
  172. conf_ata {
  173. nvidia,pins = "ata", "atb", "atc", "atd",
  174. "cdev1", "cdev2", "dap1", "dap2",
  175. "dap4", "dtf", "gma", "gmc", "gmd",
  176. "gme", "gpu", "gpu7", "i2cp", "irrx",
  177. "irtx", "pta", "rm", "sdc", "sdd",
  178. "slxd", "slxk", "spdi", "spdo", "uac",
  179. "uad", "uca", "ucb", "uda";
  180. nvidia,pull = <0>;
  181. nvidia,tristate = <0>;
  182. };
  183. conf_ate {
  184. nvidia,pins = "ate", "csus", "dap3", "ddc",
  185. "gpv", "owc", "slxc", "spib", "spid",
  186. "spie";
  187. nvidia,pull = <0>;
  188. nvidia,tristate = <1>;
  189. };
  190. conf_ck32 {
  191. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  192. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  193. nvidia,pull = <0>;
  194. };
  195. conf_crtp {
  196. nvidia,pins = "crtp", "gmb", "slxa", "spia",
  197. "spig", "spih";
  198. nvidia,pull = <2>;
  199. nvidia,tristate = <1>;
  200. };
  201. conf_dta {
  202. nvidia,pins = "dta", "dtb", "dtc", "dtd";
  203. nvidia,pull = <1>;
  204. nvidia,tristate = <0>;
  205. };
  206. conf_dte {
  207. nvidia,pins = "dte", "spif";
  208. nvidia,pull = <1>;
  209. nvidia,tristate = <1>;
  210. };
  211. conf_hdint {
  212. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  213. "lpw1", "lsc1", "lsck", "lsda", "lsdi",
  214. "lvp0";
  215. nvidia,tristate = <1>;
  216. };
  217. conf_kbca {
  218. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  219. "kbce", "kbcf", "sdio1", "spic", "uaa",
  220. "uab";
  221. nvidia,pull = <2>;
  222. nvidia,tristate = <0>;
  223. };
  224. conf_lc {
  225. nvidia,pins = "lc", "ls";
  226. nvidia,pull = <2>;
  227. };
  228. conf_ld0 {
  229. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  230. "ld5", "ld6", "ld7", "ld8", "ld9",
  231. "ld10", "ld11", "ld12", "ld13", "ld14",
  232. "ld15", "ld16", "ld17", "ldi", "lhp0",
  233. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  234. "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
  235. "lvs", "pmc", "sdb";
  236. nvidia,tristate = <0>;
  237. };
  238. conf_ld17_0 {
  239. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  240. "ld23_22";
  241. nvidia,pull = <1>;
  242. };
  243. drive_sdio1 {
  244. nvidia,pins = "drive_sdio1";
  245. nvidia,high-speed-mode = <0>;
  246. nvidia,schmitt = <0>;
  247. nvidia,low-power-mode = <3>;
  248. nvidia,pull-down-strength = <31>;
  249. nvidia,pull-up-strength = <31>;
  250. nvidia,slew-rate-rising = <3>;
  251. nvidia,slew-rate-falling = <3>;
  252. };
  253. };
  254. };
  255. i2c@7000c000 {
  256. clock-frequency = <400000>;
  257. wm8903: wm8903@1a {
  258. compatible = "wlf,wm8903";
  259. reg = <0x1a>;
  260. interrupt-parent = <&gpio>;
  261. interrupts = < 187 0x04 >;
  262. gpio-controller;
  263. #gpio-cells = <2>;
  264. micdet-cfg = <0>;
  265. micdet-delay = <100>;
  266. gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >;
  267. };
  268. /* ALS and proximity sensor */
  269. isl29018@44 {
  270. compatible = "isil,isl29018";
  271. reg = <0x44>;
  272. interrupt-parent = <&gpio>;
  273. interrupts = < 202 0x04 >; /* GPIO PZ2 */
  274. };
  275. };
  276. i2c@7000c400 {
  277. clock-frequency = <100000>;
  278. };
  279. i2c@7000c500 {
  280. clock-frequency = <400000>;
  281. };
  282. i2c@7000d000 {
  283. clock-frequency = <400000>;
  284. adt7461@4c {
  285. compatible = "adt7461";
  286. reg = <0x4c>;
  287. };
  288. };
  289. i2s@70002a00 {
  290. status = "disable";
  291. };
  292. sound {
  293. compatible = "nvidia,tegra-audio-wm8903-seaboard",
  294. "nvidia,tegra-audio-wm8903";
  295. nvidia,model = "NVIDIA Tegra Seaboard";
  296. nvidia,audio-routing =
  297. "Headphone Jack", "HPOUTR",
  298. "Headphone Jack", "HPOUTL",
  299. "Int Spk", "ROP",
  300. "Int Spk", "RON",
  301. "Int Spk", "LOP",
  302. "Int Spk", "LON",
  303. "Mic Jack", "MICBIAS",
  304. "IN1R", "Mic Jack";
  305. nvidia,i2s-controller = <&tegra_i2s1>;
  306. nvidia,audio-codec = <&wm8903>;
  307. nvidia,spkr-en-gpios = <&wm8903 2 0>;
  308. nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
  309. };
  310. serial@70006000 {
  311. status = "disable";
  312. };
  313. serial@70006040 {
  314. status = "disable";
  315. };
  316. serial@70006200 {
  317. status = "disable";
  318. };
  319. serial@70006300 {
  320. clock-frequency = < 216000000 >;
  321. };
  322. serial@70006400 {
  323. status = "disable";
  324. };
  325. sdhci@c8000000 {
  326. status = "disable";
  327. };
  328. sdhci@c8000200 {
  329. status = "disable";
  330. };
  331. sdhci@c8000400 {
  332. cd-gpios = <&gpio 69 0>; /* gpio PI5 */
  333. wp-gpios = <&gpio 57 0>; /* gpio PH1 */
  334. power-gpios = <&gpio 70 0>; /* gpio PI6 */
  335. };
  336. sdhci@c8000600 {
  337. support-8bit;
  338. };
  339. usb@c5000000 {
  340. nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
  341. dr_mode = "otg";
  342. };
  343. gpio-keys {
  344. compatible = "gpio-keys";
  345. power {
  346. label = "Power";
  347. gpios = <&gpio 170 1>; /* gpio PV2, active low */
  348. linux,code = <116>; /* KEY_POWER */
  349. gpio-key,wakeup;
  350. };
  351. lid {
  352. label = "Lid";
  353. gpios = <&gpio 23 0>; /* gpio PC7 */
  354. linux,input-type = <5>; /* EV_SW */
  355. linux,code = <0>; /* SW_LID */
  356. debounce-interval = <1>;
  357. gpio-key,wakeup;
  358. };
  359. };
  360. emc@7000f400 {
  361. emc-table@190000 {
  362. reg = < 190000 >;
  363. compatible = "nvidia,tegra20-emc-table";
  364. clock-frequency = < 190000 >;
  365. nvidia,emc-registers = < 0x0000000c 0x00000026
  366. 0x00000009 0x00000003 0x00000004 0x00000004
  367. 0x00000002 0x0000000c 0x00000003 0x00000003
  368. 0x00000002 0x00000001 0x00000004 0x00000005
  369. 0x00000004 0x00000009 0x0000000d 0x0000059f
  370. 0x00000000 0x00000003 0x00000003 0x00000003
  371. 0x00000003 0x00000001 0x0000000b 0x000000c8
  372. 0x00000003 0x00000007 0x00000004 0x0000000f
  373. 0x00000002 0x00000000 0x00000000 0x00000002
  374. 0x00000000 0x00000000 0x00000083 0xa06204ae
  375. 0x007dc010 0x00000000 0x00000000 0x00000000
  376. 0x00000000 0x00000000 0x00000000 0x00000000 >;
  377. };
  378. emc-table@380000 {
  379. reg = < 380000 >;
  380. compatible = "nvidia,tegra20-emc-table";
  381. clock-frequency = < 380000 >;
  382. nvidia,emc-registers = < 0x00000017 0x0000004b
  383. 0x00000012 0x00000006 0x00000004 0x00000005
  384. 0x00000003 0x0000000c 0x00000006 0x00000006
  385. 0x00000003 0x00000001 0x00000004 0x00000005
  386. 0x00000004 0x00000009 0x0000000d 0x00000b5f
  387. 0x00000000 0x00000003 0x00000003 0x00000006
  388. 0x00000006 0x00000001 0x00000011 0x000000c8
  389. 0x00000003 0x0000000e 0x00000007 0x0000000f
  390. 0x00000002 0x00000000 0x00000000 0x00000002
  391. 0x00000000 0x00000000 0x00000083 0xe044048b
  392. 0x007d8010 0x00000000 0x00000000 0x00000000
  393. 0x00000000 0x00000000 0x00000000 0x00000000 >;
  394. };
  395. };
  396. };