pt1.c 25 KB

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  1. /*
  2. * driver for Earthsoft PT1/PT2
  3. *
  4. * Copyright (C) 2009 HIRANO Takahito <hiranotaka@zng.info>
  5. *
  6. * based on pt1dvr - http://pt1dvr.sourceforge.jp/
  7. * by Tomoaki Ishikawa <tomy@users.sourceforge.jp>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22. */
  23. #include <linux/kernel.h>
  24. #include <linux/module.h>
  25. #include <linux/slab.h>
  26. #include <linux/vmalloc.h>
  27. #include <linux/pci.h>
  28. #include <linux/kthread.h>
  29. #include <linux/freezer.h>
  30. #include <linux/ratelimit.h>
  31. #include "dvbdev.h"
  32. #include "dvb_demux.h"
  33. #include "dmxdev.h"
  34. #include "dvb_net.h"
  35. #include "dvb_frontend.h"
  36. #include "va1j5jf8007t.h"
  37. #include "va1j5jf8007s.h"
  38. #define DRIVER_NAME "earth-pt1"
  39. #define PT1_PAGE_SHIFT 12
  40. #define PT1_PAGE_SIZE (1 << PT1_PAGE_SHIFT)
  41. #define PT1_NR_UPACKETS 1024
  42. #define PT1_NR_BUFS 511
  43. struct pt1_buffer_page {
  44. __le32 upackets[PT1_NR_UPACKETS];
  45. };
  46. struct pt1_table_page {
  47. __le32 next_pfn;
  48. __le32 buf_pfns[PT1_NR_BUFS];
  49. };
  50. struct pt1_buffer {
  51. struct pt1_buffer_page *page;
  52. dma_addr_t addr;
  53. };
  54. struct pt1_table {
  55. struct pt1_table_page *page;
  56. dma_addr_t addr;
  57. struct pt1_buffer bufs[PT1_NR_BUFS];
  58. };
  59. #define PT1_NR_ADAPS 4
  60. struct pt1_adapter;
  61. struct pt1 {
  62. struct pci_dev *pdev;
  63. void __iomem *regs;
  64. struct i2c_adapter i2c_adap;
  65. int i2c_running;
  66. struct pt1_adapter *adaps[PT1_NR_ADAPS];
  67. struct pt1_table *tables;
  68. struct task_struct *kthread;
  69. int table_index;
  70. int buf_index;
  71. struct mutex lock;
  72. int power;
  73. int reset;
  74. };
  75. struct pt1_adapter {
  76. struct pt1 *pt1;
  77. int index;
  78. u8 *buf;
  79. int upacket_count;
  80. int packet_count;
  81. int st_count;
  82. struct dvb_adapter adap;
  83. struct dvb_demux demux;
  84. int users;
  85. struct dmxdev dmxdev;
  86. struct dvb_net net;
  87. struct dvb_frontend *fe;
  88. int (*orig_set_voltage)(struct dvb_frontend *fe,
  89. fe_sec_voltage_t voltage);
  90. int (*orig_sleep)(struct dvb_frontend *fe);
  91. int (*orig_init)(struct dvb_frontend *fe);
  92. fe_sec_voltage_t voltage;
  93. int sleep;
  94. };
  95. #define pt1_printk(level, pt1, format, arg...) \
  96. dev_printk(level, &(pt1)->pdev->dev, format, ##arg)
  97. static void pt1_write_reg(struct pt1 *pt1, int reg, u32 data)
  98. {
  99. writel(data, pt1->regs + reg * 4);
  100. }
  101. static u32 pt1_read_reg(struct pt1 *pt1, int reg)
  102. {
  103. return readl(pt1->regs + reg * 4);
  104. }
  105. static int pt1_nr_tables = 8;
  106. module_param_named(nr_tables, pt1_nr_tables, int, 0);
  107. static void pt1_increment_table_count(struct pt1 *pt1)
  108. {
  109. pt1_write_reg(pt1, 0, 0x00000020);
  110. }
  111. static void pt1_init_table_count(struct pt1 *pt1)
  112. {
  113. pt1_write_reg(pt1, 0, 0x00000010);
  114. }
  115. static void pt1_register_tables(struct pt1 *pt1, u32 first_pfn)
  116. {
  117. pt1_write_reg(pt1, 5, first_pfn);
  118. pt1_write_reg(pt1, 0, 0x0c000040);
  119. }
  120. static void pt1_unregister_tables(struct pt1 *pt1)
  121. {
  122. pt1_write_reg(pt1, 0, 0x08080000);
  123. }
  124. static int pt1_sync(struct pt1 *pt1)
  125. {
  126. int i;
  127. for (i = 0; i < 57; i++) {
  128. if (pt1_read_reg(pt1, 0) & 0x20000000)
  129. return 0;
  130. pt1_write_reg(pt1, 0, 0x00000008);
  131. }
  132. pt1_printk(KERN_ERR, pt1, "could not sync\n");
  133. return -EIO;
  134. }
  135. static u64 pt1_identify(struct pt1 *pt1)
  136. {
  137. int i;
  138. u64 id;
  139. id = 0;
  140. for (i = 0; i < 57; i++) {
  141. id |= (u64)(pt1_read_reg(pt1, 0) >> 30 & 1) << i;
  142. pt1_write_reg(pt1, 0, 0x00000008);
  143. }
  144. return id;
  145. }
  146. static int pt1_unlock(struct pt1 *pt1)
  147. {
  148. int i;
  149. pt1_write_reg(pt1, 0, 0x00000008);
  150. for (i = 0; i < 3; i++) {
  151. if (pt1_read_reg(pt1, 0) & 0x80000000)
  152. return 0;
  153. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  154. }
  155. pt1_printk(KERN_ERR, pt1, "could not unlock\n");
  156. return -EIO;
  157. }
  158. static int pt1_reset_pci(struct pt1 *pt1)
  159. {
  160. int i;
  161. pt1_write_reg(pt1, 0, 0x01010000);
  162. pt1_write_reg(pt1, 0, 0x01000000);
  163. for (i = 0; i < 10; i++) {
  164. if (pt1_read_reg(pt1, 0) & 0x00000001)
  165. return 0;
  166. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  167. }
  168. pt1_printk(KERN_ERR, pt1, "could not reset PCI\n");
  169. return -EIO;
  170. }
  171. static int pt1_reset_ram(struct pt1 *pt1)
  172. {
  173. int i;
  174. pt1_write_reg(pt1, 0, 0x02020000);
  175. pt1_write_reg(pt1, 0, 0x02000000);
  176. for (i = 0; i < 10; i++) {
  177. if (pt1_read_reg(pt1, 0) & 0x00000002)
  178. return 0;
  179. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  180. }
  181. pt1_printk(KERN_ERR, pt1, "could not reset RAM\n");
  182. return -EIO;
  183. }
  184. static int pt1_do_enable_ram(struct pt1 *pt1)
  185. {
  186. int i, j;
  187. u32 status;
  188. status = pt1_read_reg(pt1, 0) & 0x00000004;
  189. pt1_write_reg(pt1, 0, 0x00000002);
  190. for (i = 0; i < 10; i++) {
  191. for (j = 0; j < 1024; j++) {
  192. if ((pt1_read_reg(pt1, 0) & 0x00000004) != status)
  193. return 0;
  194. }
  195. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  196. }
  197. pt1_printk(KERN_ERR, pt1, "could not enable RAM\n");
  198. return -EIO;
  199. }
  200. static int pt1_enable_ram(struct pt1 *pt1)
  201. {
  202. int i, ret;
  203. int phase;
  204. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  205. phase = pt1->pdev->device == 0x211a ? 128 : 166;
  206. for (i = 0; i < phase; i++) {
  207. ret = pt1_do_enable_ram(pt1);
  208. if (ret < 0)
  209. return ret;
  210. }
  211. return 0;
  212. }
  213. static void pt1_disable_ram(struct pt1 *pt1)
  214. {
  215. pt1_write_reg(pt1, 0, 0x0b0b0000);
  216. }
  217. static void pt1_set_stream(struct pt1 *pt1, int index, int enabled)
  218. {
  219. pt1_write_reg(pt1, 2, 1 << (index + 8) | enabled << index);
  220. }
  221. static void pt1_init_streams(struct pt1 *pt1)
  222. {
  223. int i;
  224. for (i = 0; i < PT1_NR_ADAPS; i++)
  225. pt1_set_stream(pt1, i, 0);
  226. }
  227. static int pt1_filter(struct pt1 *pt1, struct pt1_buffer_page *page)
  228. {
  229. u32 upacket;
  230. int i;
  231. int index;
  232. struct pt1_adapter *adap;
  233. int offset;
  234. u8 *buf;
  235. int sc;
  236. if (!page->upackets[PT1_NR_UPACKETS - 1])
  237. return 0;
  238. for (i = 0; i < PT1_NR_UPACKETS; i++) {
  239. upacket = le32_to_cpu(page->upackets[i]);
  240. index = (upacket >> 29) - 1;
  241. if (index < 0 || index >= PT1_NR_ADAPS)
  242. continue;
  243. adap = pt1->adaps[index];
  244. if (upacket >> 25 & 1)
  245. adap->upacket_count = 0;
  246. else if (!adap->upacket_count)
  247. continue;
  248. if (upacket >> 24 & 1)
  249. printk_ratelimited(KERN_INFO "earth-pt1: device "
  250. "buffer overflowing. table[%d] buf[%d]\n",
  251. pt1->table_index, pt1->buf_index);
  252. sc = upacket >> 26 & 0x7;
  253. if (adap->st_count != -1 && sc != ((adap->st_count + 1) & 0x7))
  254. printk_ratelimited(KERN_INFO "earth-pt1: data loss"
  255. " in streamID(adapter)[%d]\n", index);
  256. adap->st_count = sc;
  257. buf = adap->buf;
  258. offset = adap->packet_count * 188 + adap->upacket_count * 3;
  259. buf[offset] = upacket >> 16;
  260. buf[offset + 1] = upacket >> 8;
  261. if (adap->upacket_count != 62)
  262. buf[offset + 2] = upacket;
  263. if (++adap->upacket_count >= 63) {
  264. adap->upacket_count = 0;
  265. if (++adap->packet_count >= 21) {
  266. dvb_dmx_swfilter_packets(&adap->demux, buf, 21);
  267. adap->packet_count = 0;
  268. }
  269. }
  270. }
  271. page->upackets[PT1_NR_UPACKETS - 1] = 0;
  272. return 1;
  273. }
  274. static int pt1_thread(void *data)
  275. {
  276. struct pt1 *pt1;
  277. struct pt1_buffer_page *page;
  278. pt1 = data;
  279. set_freezable();
  280. while (!kthread_should_stop()) {
  281. try_to_freeze();
  282. page = pt1->tables[pt1->table_index].bufs[pt1->buf_index].page;
  283. if (!pt1_filter(pt1, page)) {
  284. schedule_timeout_interruptible((HZ + 999) / 1000);
  285. continue;
  286. }
  287. if (++pt1->buf_index >= PT1_NR_BUFS) {
  288. pt1_increment_table_count(pt1);
  289. pt1->buf_index = 0;
  290. if (++pt1->table_index >= pt1_nr_tables)
  291. pt1->table_index = 0;
  292. }
  293. }
  294. return 0;
  295. }
  296. static void pt1_free_page(struct pt1 *pt1, void *page, dma_addr_t addr)
  297. {
  298. dma_free_coherent(&pt1->pdev->dev, PT1_PAGE_SIZE, page, addr);
  299. }
  300. static void *pt1_alloc_page(struct pt1 *pt1, dma_addr_t *addrp, u32 *pfnp)
  301. {
  302. void *page;
  303. dma_addr_t addr;
  304. page = dma_alloc_coherent(&pt1->pdev->dev, PT1_PAGE_SIZE, &addr,
  305. GFP_KERNEL);
  306. if (page == NULL)
  307. return NULL;
  308. BUG_ON(addr & (PT1_PAGE_SIZE - 1));
  309. BUG_ON(addr >> PT1_PAGE_SHIFT >> 31 >> 1);
  310. *addrp = addr;
  311. *pfnp = addr >> PT1_PAGE_SHIFT;
  312. return page;
  313. }
  314. static void pt1_cleanup_buffer(struct pt1 *pt1, struct pt1_buffer *buf)
  315. {
  316. pt1_free_page(pt1, buf->page, buf->addr);
  317. }
  318. static int
  319. pt1_init_buffer(struct pt1 *pt1, struct pt1_buffer *buf, u32 *pfnp)
  320. {
  321. struct pt1_buffer_page *page;
  322. dma_addr_t addr;
  323. page = pt1_alloc_page(pt1, &addr, pfnp);
  324. if (page == NULL)
  325. return -ENOMEM;
  326. page->upackets[PT1_NR_UPACKETS - 1] = 0;
  327. buf->page = page;
  328. buf->addr = addr;
  329. return 0;
  330. }
  331. static void pt1_cleanup_table(struct pt1 *pt1, struct pt1_table *table)
  332. {
  333. int i;
  334. for (i = 0; i < PT1_NR_BUFS; i++)
  335. pt1_cleanup_buffer(pt1, &table->bufs[i]);
  336. pt1_free_page(pt1, table->page, table->addr);
  337. }
  338. static int
  339. pt1_init_table(struct pt1 *pt1, struct pt1_table *table, u32 *pfnp)
  340. {
  341. struct pt1_table_page *page;
  342. dma_addr_t addr;
  343. int i, ret;
  344. u32 buf_pfn;
  345. page = pt1_alloc_page(pt1, &addr, pfnp);
  346. if (page == NULL)
  347. return -ENOMEM;
  348. for (i = 0; i < PT1_NR_BUFS; i++) {
  349. ret = pt1_init_buffer(pt1, &table->bufs[i], &buf_pfn);
  350. if (ret < 0)
  351. goto err;
  352. page->buf_pfns[i] = cpu_to_le32(buf_pfn);
  353. }
  354. pt1_increment_table_count(pt1);
  355. table->page = page;
  356. table->addr = addr;
  357. return 0;
  358. err:
  359. while (i--)
  360. pt1_cleanup_buffer(pt1, &table->bufs[i]);
  361. pt1_free_page(pt1, page, addr);
  362. return ret;
  363. }
  364. static void pt1_cleanup_tables(struct pt1 *pt1)
  365. {
  366. struct pt1_table *tables;
  367. int i;
  368. tables = pt1->tables;
  369. pt1_unregister_tables(pt1);
  370. for (i = 0; i < pt1_nr_tables; i++)
  371. pt1_cleanup_table(pt1, &tables[i]);
  372. vfree(tables);
  373. }
  374. static int pt1_init_tables(struct pt1 *pt1)
  375. {
  376. struct pt1_table *tables;
  377. int i, ret;
  378. u32 first_pfn, pfn;
  379. tables = vmalloc(sizeof(struct pt1_table) * pt1_nr_tables);
  380. if (tables == NULL)
  381. return -ENOMEM;
  382. pt1_init_table_count(pt1);
  383. i = 0;
  384. if (pt1_nr_tables) {
  385. ret = pt1_init_table(pt1, &tables[0], &first_pfn);
  386. if (ret)
  387. goto err;
  388. i++;
  389. }
  390. while (i < pt1_nr_tables) {
  391. ret = pt1_init_table(pt1, &tables[i], &pfn);
  392. if (ret)
  393. goto err;
  394. tables[i - 1].page->next_pfn = cpu_to_le32(pfn);
  395. i++;
  396. }
  397. tables[pt1_nr_tables - 1].page->next_pfn = cpu_to_le32(first_pfn);
  398. pt1_register_tables(pt1, first_pfn);
  399. pt1->tables = tables;
  400. return 0;
  401. err:
  402. while (i--)
  403. pt1_cleanup_table(pt1, &tables[i]);
  404. vfree(tables);
  405. return ret;
  406. }
  407. static int pt1_start_polling(struct pt1 *pt1)
  408. {
  409. int ret = 0;
  410. mutex_lock(&pt1->lock);
  411. if (!pt1->kthread) {
  412. pt1->kthread = kthread_run(pt1_thread, pt1, "earth-pt1");
  413. if (IS_ERR(pt1->kthread)) {
  414. ret = PTR_ERR(pt1->kthread);
  415. pt1->kthread = NULL;
  416. }
  417. }
  418. mutex_unlock(&pt1->lock);
  419. return ret;
  420. }
  421. static int pt1_start_feed(struct dvb_demux_feed *feed)
  422. {
  423. struct pt1_adapter *adap;
  424. adap = container_of(feed->demux, struct pt1_adapter, demux);
  425. if (!adap->users++) {
  426. int ret;
  427. ret = pt1_start_polling(adap->pt1);
  428. if (ret)
  429. return ret;
  430. pt1_set_stream(adap->pt1, adap->index, 1);
  431. }
  432. return 0;
  433. }
  434. static void pt1_stop_polling(struct pt1 *pt1)
  435. {
  436. int i, count;
  437. mutex_lock(&pt1->lock);
  438. for (i = 0, count = 0; i < PT1_NR_ADAPS; i++)
  439. count += pt1->adaps[i]->users;
  440. if (count == 0 && pt1->kthread) {
  441. kthread_stop(pt1->kthread);
  442. pt1->kthread = NULL;
  443. }
  444. mutex_unlock(&pt1->lock);
  445. }
  446. static int pt1_stop_feed(struct dvb_demux_feed *feed)
  447. {
  448. struct pt1_adapter *adap;
  449. adap = container_of(feed->demux, struct pt1_adapter, demux);
  450. if (!--adap->users) {
  451. pt1_set_stream(adap->pt1, adap->index, 0);
  452. pt1_stop_polling(adap->pt1);
  453. }
  454. return 0;
  455. }
  456. static void
  457. pt1_update_power(struct pt1 *pt1)
  458. {
  459. int bits;
  460. int i;
  461. struct pt1_adapter *adap;
  462. static const int sleep_bits[] = {
  463. 1 << 4,
  464. 1 << 6 | 1 << 7,
  465. 1 << 5,
  466. 1 << 6 | 1 << 8,
  467. };
  468. bits = pt1->power | !pt1->reset << 3;
  469. mutex_lock(&pt1->lock);
  470. for (i = 0; i < PT1_NR_ADAPS; i++) {
  471. adap = pt1->adaps[i];
  472. switch (adap->voltage) {
  473. case SEC_VOLTAGE_13: /* actually 11V */
  474. bits |= 1 << 1;
  475. break;
  476. case SEC_VOLTAGE_18: /* actually 15V */
  477. bits |= 1 << 1 | 1 << 2;
  478. break;
  479. default:
  480. break;
  481. }
  482. /* XXX: The bits should be changed depending on adap->sleep. */
  483. bits |= sleep_bits[i];
  484. }
  485. pt1_write_reg(pt1, 1, bits);
  486. mutex_unlock(&pt1->lock);
  487. }
  488. static int pt1_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
  489. {
  490. struct pt1_adapter *adap;
  491. adap = container_of(fe->dvb, struct pt1_adapter, adap);
  492. adap->voltage = voltage;
  493. pt1_update_power(adap->pt1);
  494. if (adap->orig_set_voltage)
  495. return adap->orig_set_voltage(fe, voltage);
  496. else
  497. return 0;
  498. }
  499. static int pt1_sleep(struct dvb_frontend *fe)
  500. {
  501. struct pt1_adapter *adap;
  502. adap = container_of(fe->dvb, struct pt1_adapter, adap);
  503. adap->sleep = 1;
  504. pt1_update_power(adap->pt1);
  505. if (adap->orig_sleep)
  506. return adap->orig_sleep(fe);
  507. else
  508. return 0;
  509. }
  510. static int pt1_wakeup(struct dvb_frontend *fe)
  511. {
  512. struct pt1_adapter *adap;
  513. adap = container_of(fe->dvb, struct pt1_adapter, adap);
  514. adap->sleep = 0;
  515. pt1_update_power(adap->pt1);
  516. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  517. if (adap->orig_init)
  518. return adap->orig_init(fe);
  519. else
  520. return 0;
  521. }
  522. static void pt1_free_adapter(struct pt1_adapter *adap)
  523. {
  524. dvb_net_release(&adap->net);
  525. adap->demux.dmx.close(&adap->demux.dmx);
  526. dvb_dmxdev_release(&adap->dmxdev);
  527. dvb_dmx_release(&adap->demux);
  528. dvb_unregister_adapter(&adap->adap);
  529. free_page((unsigned long)adap->buf);
  530. kfree(adap);
  531. }
  532. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  533. static struct pt1_adapter *
  534. pt1_alloc_adapter(struct pt1 *pt1)
  535. {
  536. struct pt1_adapter *adap;
  537. void *buf;
  538. struct dvb_adapter *dvb_adap;
  539. struct dvb_demux *demux;
  540. struct dmxdev *dmxdev;
  541. int ret;
  542. adap = kzalloc(sizeof(struct pt1_adapter), GFP_KERNEL);
  543. if (!adap) {
  544. ret = -ENOMEM;
  545. goto err;
  546. }
  547. adap->pt1 = pt1;
  548. adap->voltage = SEC_VOLTAGE_OFF;
  549. adap->sleep = 1;
  550. buf = (u8 *)__get_free_page(GFP_KERNEL);
  551. if (!buf) {
  552. ret = -ENOMEM;
  553. goto err_kfree;
  554. }
  555. adap->buf = buf;
  556. adap->upacket_count = 0;
  557. adap->packet_count = 0;
  558. adap->st_count = -1;
  559. dvb_adap = &adap->adap;
  560. dvb_adap->priv = adap;
  561. ret = dvb_register_adapter(dvb_adap, DRIVER_NAME, THIS_MODULE,
  562. &pt1->pdev->dev, adapter_nr);
  563. if (ret < 0)
  564. goto err_free_page;
  565. demux = &adap->demux;
  566. demux->dmx.capabilities = DMX_TS_FILTERING | DMX_SECTION_FILTERING;
  567. demux->priv = adap;
  568. demux->feednum = 256;
  569. demux->filternum = 256;
  570. demux->start_feed = pt1_start_feed;
  571. demux->stop_feed = pt1_stop_feed;
  572. demux->write_to_decoder = NULL;
  573. ret = dvb_dmx_init(demux);
  574. if (ret < 0)
  575. goto err_unregister_adapter;
  576. dmxdev = &adap->dmxdev;
  577. dmxdev->filternum = 256;
  578. dmxdev->demux = &demux->dmx;
  579. dmxdev->capabilities = 0;
  580. ret = dvb_dmxdev_init(dmxdev, dvb_adap);
  581. if (ret < 0)
  582. goto err_dmx_release;
  583. dvb_net_init(dvb_adap, &adap->net, &demux->dmx);
  584. return adap;
  585. err_dmx_release:
  586. dvb_dmx_release(demux);
  587. err_unregister_adapter:
  588. dvb_unregister_adapter(dvb_adap);
  589. err_free_page:
  590. free_page((unsigned long)buf);
  591. err_kfree:
  592. kfree(adap);
  593. err:
  594. return ERR_PTR(ret);
  595. }
  596. static void pt1_cleanup_adapters(struct pt1 *pt1)
  597. {
  598. int i;
  599. for (i = 0; i < PT1_NR_ADAPS; i++)
  600. pt1_free_adapter(pt1->adaps[i]);
  601. }
  602. static int pt1_init_adapters(struct pt1 *pt1)
  603. {
  604. int i;
  605. struct pt1_adapter *adap;
  606. int ret;
  607. for (i = 0; i < PT1_NR_ADAPS; i++) {
  608. adap = pt1_alloc_adapter(pt1);
  609. if (IS_ERR(adap)) {
  610. ret = PTR_ERR(adap);
  611. goto err;
  612. }
  613. adap->index = i;
  614. pt1->adaps[i] = adap;
  615. }
  616. return 0;
  617. err:
  618. while (i--)
  619. pt1_free_adapter(pt1->adaps[i]);
  620. return ret;
  621. }
  622. static void pt1_cleanup_frontend(struct pt1_adapter *adap)
  623. {
  624. dvb_unregister_frontend(adap->fe);
  625. }
  626. static int pt1_init_frontend(struct pt1_adapter *adap, struct dvb_frontend *fe)
  627. {
  628. int ret;
  629. adap->orig_set_voltage = fe->ops.set_voltage;
  630. adap->orig_sleep = fe->ops.sleep;
  631. adap->orig_init = fe->ops.init;
  632. fe->ops.set_voltage = pt1_set_voltage;
  633. fe->ops.sleep = pt1_sleep;
  634. fe->ops.init = pt1_wakeup;
  635. ret = dvb_register_frontend(&adap->adap, fe);
  636. if (ret < 0)
  637. return ret;
  638. adap->fe = fe;
  639. return 0;
  640. }
  641. static void pt1_cleanup_frontends(struct pt1 *pt1)
  642. {
  643. int i;
  644. for (i = 0; i < PT1_NR_ADAPS; i++)
  645. pt1_cleanup_frontend(pt1->adaps[i]);
  646. }
  647. struct pt1_config {
  648. struct va1j5jf8007s_config va1j5jf8007s_config;
  649. struct va1j5jf8007t_config va1j5jf8007t_config;
  650. };
  651. static const struct pt1_config pt1_configs[2] = {
  652. {
  653. {
  654. .demod_address = 0x1b,
  655. .frequency = VA1J5JF8007S_20MHZ,
  656. },
  657. {
  658. .demod_address = 0x1a,
  659. .frequency = VA1J5JF8007T_20MHZ,
  660. },
  661. }, {
  662. {
  663. .demod_address = 0x19,
  664. .frequency = VA1J5JF8007S_20MHZ,
  665. },
  666. {
  667. .demod_address = 0x18,
  668. .frequency = VA1J5JF8007T_20MHZ,
  669. },
  670. },
  671. };
  672. static const struct pt1_config pt2_configs[2] = {
  673. {
  674. {
  675. .demod_address = 0x1b,
  676. .frequency = VA1J5JF8007S_25MHZ,
  677. },
  678. {
  679. .demod_address = 0x1a,
  680. .frequency = VA1J5JF8007T_25MHZ,
  681. },
  682. }, {
  683. {
  684. .demod_address = 0x19,
  685. .frequency = VA1J5JF8007S_25MHZ,
  686. },
  687. {
  688. .demod_address = 0x18,
  689. .frequency = VA1J5JF8007T_25MHZ,
  690. },
  691. },
  692. };
  693. static int pt1_init_frontends(struct pt1 *pt1)
  694. {
  695. int i, j;
  696. struct i2c_adapter *i2c_adap;
  697. const struct pt1_config *configs, *config;
  698. struct dvb_frontend *fe[4];
  699. int ret;
  700. i = 0;
  701. j = 0;
  702. i2c_adap = &pt1->i2c_adap;
  703. configs = pt1->pdev->device == 0x211a ? pt1_configs : pt2_configs;
  704. do {
  705. config = &configs[i / 2];
  706. fe[i] = va1j5jf8007s_attach(&config->va1j5jf8007s_config,
  707. i2c_adap);
  708. if (!fe[i]) {
  709. ret = -ENODEV; /* This does not sound nice... */
  710. goto err;
  711. }
  712. i++;
  713. fe[i] = va1j5jf8007t_attach(&config->va1j5jf8007t_config,
  714. i2c_adap);
  715. if (!fe[i]) {
  716. ret = -ENODEV;
  717. goto err;
  718. }
  719. i++;
  720. ret = va1j5jf8007s_prepare(fe[i - 2]);
  721. if (ret < 0)
  722. goto err;
  723. ret = va1j5jf8007t_prepare(fe[i - 1]);
  724. if (ret < 0)
  725. goto err;
  726. } while (i < 4);
  727. do {
  728. ret = pt1_init_frontend(pt1->adaps[j], fe[j]);
  729. if (ret < 0)
  730. goto err;
  731. } while (++j < 4);
  732. return 0;
  733. err:
  734. while (i-- > j)
  735. fe[i]->ops.release(fe[i]);
  736. while (j--)
  737. dvb_unregister_frontend(fe[j]);
  738. return ret;
  739. }
  740. static void pt1_i2c_emit(struct pt1 *pt1, int addr, int busy, int read_enable,
  741. int clock, int data, int next_addr)
  742. {
  743. pt1_write_reg(pt1, 4, addr << 18 | busy << 13 | read_enable << 12 |
  744. !clock << 11 | !data << 10 | next_addr);
  745. }
  746. static void pt1_i2c_write_bit(struct pt1 *pt1, int addr, int *addrp, int data)
  747. {
  748. pt1_i2c_emit(pt1, addr, 1, 0, 0, data, addr + 1);
  749. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, data, addr + 2);
  750. pt1_i2c_emit(pt1, addr + 2, 1, 0, 0, data, addr + 3);
  751. *addrp = addr + 3;
  752. }
  753. static void pt1_i2c_read_bit(struct pt1 *pt1, int addr, int *addrp)
  754. {
  755. pt1_i2c_emit(pt1, addr, 1, 0, 0, 1, addr + 1);
  756. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 1, addr + 2);
  757. pt1_i2c_emit(pt1, addr + 2, 1, 1, 1, 1, addr + 3);
  758. pt1_i2c_emit(pt1, addr + 3, 1, 0, 0, 1, addr + 4);
  759. *addrp = addr + 4;
  760. }
  761. static void pt1_i2c_write_byte(struct pt1 *pt1, int addr, int *addrp, int data)
  762. {
  763. int i;
  764. for (i = 0; i < 8; i++)
  765. pt1_i2c_write_bit(pt1, addr, &addr, data >> (7 - i) & 1);
  766. pt1_i2c_write_bit(pt1, addr, &addr, 1);
  767. *addrp = addr;
  768. }
  769. static void pt1_i2c_read_byte(struct pt1 *pt1, int addr, int *addrp, int last)
  770. {
  771. int i;
  772. for (i = 0; i < 8; i++)
  773. pt1_i2c_read_bit(pt1, addr, &addr);
  774. pt1_i2c_write_bit(pt1, addr, &addr, last);
  775. *addrp = addr;
  776. }
  777. static void pt1_i2c_prepare(struct pt1 *pt1, int addr, int *addrp)
  778. {
  779. pt1_i2c_emit(pt1, addr, 1, 0, 1, 1, addr + 1);
  780. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  781. pt1_i2c_emit(pt1, addr + 2, 1, 0, 0, 0, addr + 3);
  782. *addrp = addr + 3;
  783. }
  784. static void
  785. pt1_i2c_write_msg(struct pt1 *pt1, int addr, int *addrp, struct i2c_msg *msg)
  786. {
  787. int i;
  788. pt1_i2c_prepare(pt1, addr, &addr);
  789. pt1_i2c_write_byte(pt1, addr, &addr, msg->addr << 1);
  790. for (i = 0; i < msg->len; i++)
  791. pt1_i2c_write_byte(pt1, addr, &addr, msg->buf[i]);
  792. *addrp = addr;
  793. }
  794. static void
  795. pt1_i2c_read_msg(struct pt1 *pt1, int addr, int *addrp, struct i2c_msg *msg)
  796. {
  797. int i;
  798. pt1_i2c_prepare(pt1, addr, &addr);
  799. pt1_i2c_write_byte(pt1, addr, &addr, msg->addr << 1 | 1);
  800. for (i = 0; i < msg->len; i++)
  801. pt1_i2c_read_byte(pt1, addr, &addr, i == msg->len - 1);
  802. *addrp = addr;
  803. }
  804. static int pt1_i2c_end(struct pt1 *pt1, int addr)
  805. {
  806. pt1_i2c_emit(pt1, addr, 1, 0, 0, 0, addr + 1);
  807. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  808. pt1_i2c_emit(pt1, addr + 2, 1, 0, 1, 1, 0);
  809. pt1_write_reg(pt1, 0, 0x00000004);
  810. do {
  811. if (signal_pending(current))
  812. return -EINTR;
  813. schedule_timeout_interruptible((HZ + 999) / 1000);
  814. } while (pt1_read_reg(pt1, 0) & 0x00000080);
  815. return 0;
  816. }
  817. static void pt1_i2c_begin(struct pt1 *pt1, int *addrp)
  818. {
  819. int addr;
  820. addr = 0;
  821. pt1_i2c_emit(pt1, addr, 0, 0, 1, 1, addr /* itself */);
  822. addr = addr + 1;
  823. if (!pt1->i2c_running) {
  824. pt1_i2c_emit(pt1, addr, 1, 0, 1, 1, addr + 1);
  825. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  826. addr = addr + 2;
  827. pt1->i2c_running = 1;
  828. }
  829. *addrp = addr;
  830. }
  831. static int pt1_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
  832. {
  833. struct pt1 *pt1;
  834. int i;
  835. struct i2c_msg *msg, *next_msg;
  836. int addr, ret;
  837. u16 len;
  838. u32 word;
  839. pt1 = i2c_get_adapdata(adap);
  840. for (i = 0; i < num; i++) {
  841. msg = &msgs[i];
  842. if (msg->flags & I2C_M_RD)
  843. return -ENOTSUPP;
  844. if (i + 1 < num)
  845. next_msg = &msgs[i + 1];
  846. else
  847. next_msg = NULL;
  848. if (next_msg && next_msg->flags & I2C_M_RD) {
  849. i++;
  850. len = next_msg->len;
  851. if (len > 4)
  852. return -ENOTSUPP;
  853. pt1_i2c_begin(pt1, &addr);
  854. pt1_i2c_write_msg(pt1, addr, &addr, msg);
  855. pt1_i2c_read_msg(pt1, addr, &addr, next_msg);
  856. ret = pt1_i2c_end(pt1, addr);
  857. if (ret < 0)
  858. return ret;
  859. word = pt1_read_reg(pt1, 2);
  860. while (len--) {
  861. next_msg->buf[len] = word;
  862. word >>= 8;
  863. }
  864. } else {
  865. pt1_i2c_begin(pt1, &addr);
  866. pt1_i2c_write_msg(pt1, addr, &addr, msg);
  867. ret = pt1_i2c_end(pt1, addr);
  868. if (ret < 0)
  869. return ret;
  870. }
  871. }
  872. return num;
  873. }
  874. static u32 pt1_i2c_func(struct i2c_adapter *adap)
  875. {
  876. return I2C_FUNC_I2C;
  877. }
  878. static const struct i2c_algorithm pt1_i2c_algo = {
  879. .master_xfer = pt1_i2c_xfer,
  880. .functionality = pt1_i2c_func,
  881. };
  882. static void pt1_i2c_wait(struct pt1 *pt1)
  883. {
  884. int i;
  885. for (i = 0; i < 128; i++)
  886. pt1_i2c_emit(pt1, 0, 0, 0, 1, 1, 0);
  887. }
  888. static void pt1_i2c_init(struct pt1 *pt1)
  889. {
  890. int i;
  891. for (i = 0; i < 1024; i++)
  892. pt1_i2c_emit(pt1, i, 0, 0, 1, 1, 0);
  893. }
  894. static void __devexit pt1_remove(struct pci_dev *pdev)
  895. {
  896. struct pt1 *pt1;
  897. void __iomem *regs;
  898. pt1 = pci_get_drvdata(pdev);
  899. regs = pt1->regs;
  900. if (pt1->kthread)
  901. kthread_stop(pt1->kthread);
  902. pt1_cleanup_tables(pt1);
  903. pt1_cleanup_frontends(pt1);
  904. pt1_disable_ram(pt1);
  905. pt1->power = 0;
  906. pt1->reset = 1;
  907. pt1_update_power(pt1);
  908. pt1_cleanup_adapters(pt1);
  909. i2c_del_adapter(&pt1->i2c_adap);
  910. pci_set_drvdata(pdev, NULL);
  911. kfree(pt1);
  912. pci_iounmap(pdev, regs);
  913. pci_release_regions(pdev);
  914. pci_disable_device(pdev);
  915. }
  916. static int __devinit
  917. pt1_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  918. {
  919. int ret;
  920. void __iomem *regs;
  921. struct pt1 *pt1;
  922. struct i2c_adapter *i2c_adap;
  923. ret = pci_enable_device(pdev);
  924. if (ret < 0)
  925. goto err;
  926. ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  927. if (ret < 0)
  928. goto err_pci_disable_device;
  929. pci_set_master(pdev);
  930. ret = pci_request_regions(pdev, DRIVER_NAME);
  931. if (ret < 0)
  932. goto err_pci_disable_device;
  933. regs = pci_iomap(pdev, 0, 0);
  934. if (!regs) {
  935. ret = -EIO;
  936. goto err_pci_release_regions;
  937. }
  938. pt1 = kzalloc(sizeof(struct pt1), GFP_KERNEL);
  939. if (!pt1) {
  940. ret = -ENOMEM;
  941. goto err_pci_iounmap;
  942. }
  943. mutex_init(&pt1->lock);
  944. pt1->pdev = pdev;
  945. pt1->regs = regs;
  946. pci_set_drvdata(pdev, pt1);
  947. ret = pt1_init_adapters(pt1);
  948. if (ret < 0)
  949. goto err_kfree;
  950. mutex_init(&pt1->lock);
  951. pt1->power = 0;
  952. pt1->reset = 1;
  953. pt1_update_power(pt1);
  954. i2c_adap = &pt1->i2c_adap;
  955. i2c_adap->algo = &pt1_i2c_algo;
  956. i2c_adap->algo_data = NULL;
  957. i2c_adap->dev.parent = &pdev->dev;
  958. strcpy(i2c_adap->name, DRIVER_NAME);
  959. i2c_set_adapdata(i2c_adap, pt1);
  960. ret = i2c_add_adapter(i2c_adap);
  961. if (ret < 0)
  962. goto err_pt1_cleanup_adapters;
  963. pt1_i2c_init(pt1);
  964. pt1_i2c_wait(pt1);
  965. ret = pt1_sync(pt1);
  966. if (ret < 0)
  967. goto err_i2c_del_adapter;
  968. pt1_identify(pt1);
  969. ret = pt1_unlock(pt1);
  970. if (ret < 0)
  971. goto err_i2c_del_adapter;
  972. ret = pt1_reset_pci(pt1);
  973. if (ret < 0)
  974. goto err_i2c_del_adapter;
  975. ret = pt1_reset_ram(pt1);
  976. if (ret < 0)
  977. goto err_i2c_del_adapter;
  978. ret = pt1_enable_ram(pt1);
  979. if (ret < 0)
  980. goto err_i2c_del_adapter;
  981. pt1_init_streams(pt1);
  982. pt1->power = 1;
  983. pt1_update_power(pt1);
  984. schedule_timeout_uninterruptible((HZ + 49) / 50);
  985. pt1->reset = 0;
  986. pt1_update_power(pt1);
  987. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  988. ret = pt1_init_frontends(pt1);
  989. if (ret < 0)
  990. goto err_pt1_disable_ram;
  991. ret = pt1_init_tables(pt1);
  992. if (ret < 0)
  993. goto err_pt1_cleanup_frontends;
  994. return 0;
  995. err_pt1_cleanup_frontends:
  996. pt1_cleanup_frontends(pt1);
  997. err_pt1_disable_ram:
  998. pt1_disable_ram(pt1);
  999. pt1->power = 0;
  1000. pt1->reset = 1;
  1001. pt1_update_power(pt1);
  1002. err_i2c_del_adapter:
  1003. i2c_del_adapter(i2c_adap);
  1004. err_pt1_cleanup_adapters:
  1005. pt1_cleanup_adapters(pt1);
  1006. err_kfree:
  1007. pci_set_drvdata(pdev, NULL);
  1008. kfree(pt1);
  1009. err_pci_iounmap:
  1010. pci_iounmap(pdev, regs);
  1011. err_pci_release_regions:
  1012. pci_release_regions(pdev);
  1013. err_pci_disable_device:
  1014. pci_disable_device(pdev);
  1015. err:
  1016. return ret;
  1017. }
  1018. static struct pci_device_id pt1_id_table[] = {
  1019. { PCI_DEVICE(0x10ee, 0x211a) },
  1020. { PCI_DEVICE(0x10ee, 0x222a) },
  1021. { },
  1022. };
  1023. MODULE_DEVICE_TABLE(pci, pt1_id_table);
  1024. static struct pci_driver pt1_driver = {
  1025. .name = DRIVER_NAME,
  1026. .probe = pt1_probe,
  1027. .remove = __devexit_p(pt1_remove),
  1028. .id_table = pt1_id_table,
  1029. };
  1030. static int __init pt1_init(void)
  1031. {
  1032. return pci_register_driver(&pt1_driver);
  1033. }
  1034. static void __exit pt1_cleanup(void)
  1035. {
  1036. pci_unregister_driver(&pt1_driver);
  1037. }
  1038. module_init(pt1_init);
  1039. module_exit(pt1_cleanup);
  1040. MODULE_AUTHOR("Takahito HIRANO <hiranotaka@zng.info>");
  1041. MODULE_DESCRIPTION("Earthsoft PT1/PT2 Driver");
  1042. MODULE_LICENSE("GPL");