main.c 55 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. static void ath9k_set_assoc_state(struct ath_softc *sc,
  21. struct ieee80211_vif *vif);
  22. u8 ath9k_parse_mpdudensity(u8 mpdudensity)
  23. {
  24. /*
  25. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  26. * 0 for no restriction
  27. * 1 for 1/4 us
  28. * 2 for 1/2 us
  29. * 3 for 1 us
  30. * 4 for 2 us
  31. * 5 for 4 us
  32. * 6 for 8 us
  33. * 7 for 16 us
  34. */
  35. switch (mpdudensity) {
  36. case 0:
  37. return 0;
  38. case 1:
  39. case 2:
  40. case 3:
  41. /* Our lower layer calculations limit our precision to
  42. 1 microsecond */
  43. return 1;
  44. case 4:
  45. return 2;
  46. case 5:
  47. return 4;
  48. case 6:
  49. return 8;
  50. case 7:
  51. return 16;
  52. default:
  53. return 0;
  54. }
  55. }
  56. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
  57. {
  58. bool pending = false;
  59. spin_lock_bh(&txq->axq_lock);
  60. if (txq->axq_depth || !list_empty(&txq->axq_acq))
  61. pending = true;
  62. spin_unlock_bh(&txq->axq_lock);
  63. return pending;
  64. }
  65. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  66. {
  67. unsigned long flags;
  68. bool ret;
  69. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  70. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  71. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  72. return ret;
  73. }
  74. void ath9k_ps_wakeup(struct ath_softc *sc)
  75. {
  76. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  77. unsigned long flags;
  78. enum ath9k_power_mode power_mode;
  79. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  80. if (++sc->ps_usecount != 1)
  81. goto unlock;
  82. power_mode = sc->sc_ah->power_mode;
  83. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  84. /*
  85. * While the hardware is asleep, the cycle counters contain no
  86. * useful data. Better clear them now so that they don't mess up
  87. * survey data results.
  88. */
  89. if (power_mode != ATH9K_PM_AWAKE) {
  90. spin_lock(&common->cc_lock);
  91. ath_hw_cycle_counters_update(common);
  92. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  93. memset(&common->cc_ani, 0, sizeof(common->cc_ani));
  94. spin_unlock(&common->cc_lock);
  95. }
  96. unlock:
  97. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  98. }
  99. void ath9k_ps_restore(struct ath_softc *sc)
  100. {
  101. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  102. enum ath9k_power_mode mode;
  103. unsigned long flags;
  104. bool reset;
  105. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  106. if (--sc->ps_usecount != 0)
  107. goto unlock;
  108. if (sc->ps_idle) {
  109. ath9k_hw_setrxabort(sc->sc_ah, 1);
  110. ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  111. mode = ATH9K_PM_FULL_SLEEP;
  112. } else if (sc->ps_enabled &&
  113. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  114. PS_WAIT_FOR_CAB |
  115. PS_WAIT_FOR_PSPOLL_DATA |
  116. PS_WAIT_FOR_TX_ACK |
  117. PS_WAIT_FOR_ANI))) {
  118. mode = ATH9K_PM_NETWORK_SLEEP;
  119. if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
  120. ath9k_btcoex_stop_gen_timer(sc);
  121. } else {
  122. goto unlock;
  123. }
  124. spin_lock(&common->cc_lock);
  125. ath_hw_cycle_counters_update(common);
  126. spin_unlock(&common->cc_lock);
  127. ath9k_hw_setpower(sc->sc_ah, mode);
  128. unlock:
  129. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  130. }
  131. static void __ath_cancel_work(struct ath_softc *sc)
  132. {
  133. cancel_work_sync(&sc->paprd_work);
  134. cancel_work_sync(&sc->hw_check_work);
  135. cancel_delayed_work_sync(&sc->tx_complete_work);
  136. cancel_delayed_work_sync(&sc->hw_pll_work);
  137. #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
  138. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  139. cancel_work_sync(&sc->mci_work);
  140. #endif
  141. }
  142. static void ath_cancel_work(struct ath_softc *sc)
  143. {
  144. __ath_cancel_work(sc);
  145. cancel_work_sync(&sc->hw_reset_work);
  146. }
  147. static void ath_restart_work(struct ath_softc *sc)
  148. {
  149. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  150. if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
  151. AR_SREV_9550(sc->sc_ah))
  152. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
  153. msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
  154. ath_start_rx_poll(sc, 3);
  155. ath_start_ani(sc);
  156. }
  157. static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
  158. {
  159. struct ath_hw *ah = sc->sc_ah;
  160. bool ret = true;
  161. ieee80211_stop_queues(sc->hw);
  162. sc->hw_busy_count = 0;
  163. ath_stop_ani(sc);
  164. del_timer_sync(&sc->rx_poll_timer);
  165. ath9k_debug_samp_bb_mac(sc);
  166. ath9k_hw_disable_interrupts(ah);
  167. tasklet_disable(&sc->intr_tq);
  168. if (!ath_stoprecv(sc))
  169. ret = false;
  170. if (!ath_drain_all_txq(sc, retry_tx))
  171. ret = false;
  172. if (!flush) {
  173. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  174. ath_rx_tasklet(sc, 1, true);
  175. ath_rx_tasklet(sc, 1, false);
  176. } else {
  177. ath_flushrecv(sc);
  178. }
  179. tasklet_enable(&sc->intr_tq);
  180. return ret;
  181. }
  182. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  183. {
  184. struct ath_hw *ah = sc->sc_ah;
  185. struct ath_common *common = ath9k_hw_common(ah);
  186. unsigned long flags;
  187. if (ath_startrecv(sc) != 0) {
  188. ath_err(common, "Unable to restart recv logic\n");
  189. return false;
  190. }
  191. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  192. sc->config.txpowlimit, &sc->curtxpow);
  193. clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
  194. ath9k_hw_set_interrupts(ah);
  195. ath9k_hw_enable_interrupts(ah);
  196. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
  197. if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
  198. goto work;
  199. ath9k_set_beacon(sc);
  200. if (ah->opmode == NL80211_IFTYPE_STATION &&
  201. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  202. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  203. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  204. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  205. }
  206. work:
  207. ath_restart_work(sc);
  208. }
  209. if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
  210. ath_ant_comb_update(sc);
  211. ieee80211_wake_queues(sc->hw);
  212. return true;
  213. }
  214. static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
  215. bool retry_tx)
  216. {
  217. struct ath_hw *ah = sc->sc_ah;
  218. struct ath_common *common = ath9k_hw_common(ah);
  219. struct ath9k_hw_cal_data *caldata = NULL;
  220. bool fastcc = true;
  221. bool flush = false;
  222. int r;
  223. __ath_cancel_work(sc);
  224. spin_lock_bh(&sc->sc_pcu_lock);
  225. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
  226. fastcc = false;
  227. caldata = &sc->caldata;
  228. }
  229. if (!hchan) {
  230. fastcc = false;
  231. flush = true;
  232. hchan = ah->curchan;
  233. }
  234. if (!ath_prepare_reset(sc, retry_tx, flush))
  235. fastcc = false;
  236. ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
  237. hchan->channel, IS_CHAN_HT40(hchan), fastcc);
  238. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  239. if (r) {
  240. ath_err(common,
  241. "Unable to reset channel, reset status %d\n", r);
  242. goto out;
  243. }
  244. if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
  245. (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
  246. ath9k_mci_set_txpower(sc, true, false);
  247. if (!ath_complete_reset(sc, true))
  248. r = -EIO;
  249. out:
  250. spin_unlock_bh(&sc->sc_pcu_lock);
  251. return r;
  252. }
  253. /*
  254. * Set/change channels. If the channel is really being changed, it's done
  255. * by reseting the chip. To accomplish this we must first cleanup any pending
  256. * DMA, then restart stuff.
  257. */
  258. static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  259. struct ath9k_channel *hchan)
  260. {
  261. int r;
  262. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  263. return -EIO;
  264. r = ath_reset_internal(sc, hchan, false);
  265. return r;
  266. }
  267. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
  268. struct ieee80211_vif *vif)
  269. {
  270. struct ath_node *an;
  271. u8 density;
  272. an = (struct ath_node *)sta->drv_priv;
  273. an->sc = sc;
  274. an->sta = sta;
  275. an->vif = vif;
  276. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
  277. ath_tx_node_init(sc, an);
  278. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  279. sta->ht_cap.ampdu_factor);
  280. density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
  281. an->mpdudensity = density;
  282. }
  283. }
  284. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  285. {
  286. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  287. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  288. ath_tx_node_cleanup(sc, an);
  289. }
  290. void ath9k_tasklet(unsigned long data)
  291. {
  292. struct ath_softc *sc = (struct ath_softc *)data;
  293. struct ath_hw *ah = sc->sc_ah;
  294. struct ath_common *common = ath9k_hw_common(ah);
  295. enum ath_reset_type type;
  296. unsigned long flags;
  297. u32 status = sc->intrstatus;
  298. u32 rxmask;
  299. ath9k_ps_wakeup(sc);
  300. spin_lock(&sc->sc_pcu_lock);
  301. if ((status & ATH9K_INT_FATAL) ||
  302. (status & ATH9K_INT_BB_WATCHDOG)) {
  303. if (status & ATH9K_INT_FATAL)
  304. type = RESET_TYPE_FATAL_INT;
  305. else
  306. type = RESET_TYPE_BB_WATCHDOG;
  307. ath9k_queue_reset(sc, type);
  308. goto out;
  309. }
  310. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  311. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  312. /*
  313. * TSF sync does not look correct; remain awake to sync with
  314. * the next Beacon.
  315. */
  316. ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
  317. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  318. }
  319. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  320. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  321. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  322. ATH9K_INT_RXORN);
  323. else
  324. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  325. if (status & rxmask) {
  326. /* Check for high priority Rx first */
  327. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  328. (status & ATH9K_INT_RXHP))
  329. ath_rx_tasklet(sc, 0, true);
  330. ath_rx_tasklet(sc, 0, false);
  331. }
  332. if (status & ATH9K_INT_TX) {
  333. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  334. ath_tx_edma_tasklet(sc);
  335. else
  336. ath_tx_tasklet(sc);
  337. }
  338. ath9k_btcoex_handle_interrupt(sc, status);
  339. out:
  340. /* re-enable hardware interrupt */
  341. ath9k_hw_enable_interrupts(ah);
  342. spin_unlock(&sc->sc_pcu_lock);
  343. ath9k_ps_restore(sc);
  344. }
  345. irqreturn_t ath_isr(int irq, void *dev)
  346. {
  347. #define SCHED_INTR ( \
  348. ATH9K_INT_FATAL | \
  349. ATH9K_INT_BB_WATCHDOG | \
  350. ATH9K_INT_RXORN | \
  351. ATH9K_INT_RXEOL | \
  352. ATH9K_INT_RX | \
  353. ATH9K_INT_RXLP | \
  354. ATH9K_INT_RXHP | \
  355. ATH9K_INT_TX | \
  356. ATH9K_INT_BMISS | \
  357. ATH9K_INT_CST | \
  358. ATH9K_INT_TSFOOR | \
  359. ATH9K_INT_GENTIMER | \
  360. ATH9K_INT_MCI)
  361. struct ath_softc *sc = dev;
  362. struct ath_hw *ah = sc->sc_ah;
  363. struct ath_common *common = ath9k_hw_common(ah);
  364. enum ath9k_int status;
  365. bool sched = false;
  366. /*
  367. * The hardware is not ready/present, don't
  368. * touch anything. Note this can happen early
  369. * on if the IRQ is shared.
  370. */
  371. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  372. return IRQ_NONE;
  373. /* shared irq, not for us */
  374. if (!ath9k_hw_intrpend(ah))
  375. return IRQ_NONE;
  376. if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) {
  377. ath9k_hw_kill_interrupts(ah);
  378. return IRQ_HANDLED;
  379. }
  380. /*
  381. * Figure out the reason(s) for the interrupt. Note
  382. * that the hal returns a pseudo-ISR that may include
  383. * bits we haven't explicitly enabled so we mask the
  384. * value to insure we only process bits we requested.
  385. */
  386. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  387. status &= ah->imask; /* discard unasked-for bits */
  388. /*
  389. * If there are no status bits set, then this interrupt was not
  390. * for me (should have been caught above).
  391. */
  392. if (!status)
  393. return IRQ_NONE;
  394. /* Cache the status */
  395. sc->intrstatus = status;
  396. if (status & SCHED_INTR)
  397. sched = true;
  398. /*
  399. * If a FATAL or RXORN interrupt is received, we have to reset the
  400. * chip immediately.
  401. */
  402. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  403. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  404. goto chip_reset;
  405. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  406. (status & ATH9K_INT_BB_WATCHDOG)) {
  407. spin_lock(&common->cc_lock);
  408. ath_hw_cycle_counters_update(common);
  409. ar9003_hw_bb_watchdog_dbg_info(ah);
  410. spin_unlock(&common->cc_lock);
  411. goto chip_reset;
  412. }
  413. #ifdef CONFIG_PM_SLEEP
  414. if (status & ATH9K_INT_BMISS) {
  415. if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
  416. ath_dbg(common, ANY, "during WoW we got a BMISS\n");
  417. atomic_inc(&sc->wow_got_bmiss_intr);
  418. atomic_dec(&sc->wow_sleep_proc_intr);
  419. }
  420. }
  421. #endif
  422. if (status & ATH9K_INT_SWBA)
  423. tasklet_schedule(&sc->bcon_tasklet);
  424. if (status & ATH9K_INT_TXURN)
  425. ath9k_hw_updatetxtriglevel(ah, true);
  426. if (status & ATH9K_INT_RXEOL) {
  427. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  428. ath9k_hw_set_interrupts(ah);
  429. }
  430. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  431. if (status & ATH9K_INT_TIM_TIMER) {
  432. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  433. goto chip_reset;
  434. /* Clear RxAbort bit so that we can
  435. * receive frames */
  436. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  437. spin_lock(&sc->sc_pm_lock);
  438. ath9k_hw_setrxabort(sc->sc_ah, 0);
  439. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  440. spin_unlock(&sc->sc_pm_lock);
  441. }
  442. chip_reset:
  443. ath_debug_stat_interrupt(sc, status);
  444. if (sched) {
  445. /* turn off every interrupt */
  446. ath9k_hw_disable_interrupts(ah);
  447. tasklet_schedule(&sc->intr_tq);
  448. }
  449. return IRQ_HANDLED;
  450. #undef SCHED_INTR
  451. }
  452. static int ath_reset(struct ath_softc *sc, bool retry_tx)
  453. {
  454. int r;
  455. ath9k_ps_wakeup(sc);
  456. r = ath_reset_internal(sc, NULL, retry_tx);
  457. if (retry_tx) {
  458. int i;
  459. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  460. if (ATH_TXQ_SETUP(sc, i)) {
  461. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  462. ath_txq_schedule(sc, &sc->tx.txq[i]);
  463. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  464. }
  465. }
  466. }
  467. ath9k_ps_restore(sc);
  468. return r;
  469. }
  470. void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
  471. {
  472. #ifdef CONFIG_ATH9K_DEBUGFS
  473. RESET_STAT_INC(sc, type);
  474. #endif
  475. set_bit(SC_OP_HW_RESET, &sc->sc_flags);
  476. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  477. }
  478. void ath_reset_work(struct work_struct *work)
  479. {
  480. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  481. ath_reset(sc, true);
  482. }
  483. /**********************/
  484. /* mac80211 callbacks */
  485. /**********************/
  486. static int ath9k_start(struct ieee80211_hw *hw)
  487. {
  488. struct ath_softc *sc = hw->priv;
  489. struct ath_hw *ah = sc->sc_ah;
  490. struct ath_common *common = ath9k_hw_common(ah);
  491. struct ieee80211_channel *curchan = hw->conf.channel;
  492. struct ath9k_channel *init_channel;
  493. int r;
  494. ath_dbg(common, CONFIG,
  495. "Starting driver with initial channel: %d MHz\n",
  496. curchan->center_freq);
  497. ath9k_ps_wakeup(sc);
  498. mutex_lock(&sc->mutex);
  499. init_channel = ath9k_cmn_get_curchannel(hw, ah);
  500. /* Reset SERDES registers */
  501. ath9k_hw_configpcipowersave(ah, false);
  502. /*
  503. * The basic interface to setting the hardware in a good
  504. * state is ``reset''. On return the hardware is known to
  505. * be powered up and with interrupts disabled. This must
  506. * be followed by initialization of the appropriate bits
  507. * and then setup of the interrupt mask.
  508. */
  509. spin_lock_bh(&sc->sc_pcu_lock);
  510. atomic_set(&ah->intr_ref_cnt, -1);
  511. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  512. if (r) {
  513. ath_err(common,
  514. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  515. r, curchan->center_freq);
  516. ah->reset_power_on = false;
  517. }
  518. /* Setup our intr mask. */
  519. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  520. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  521. ATH9K_INT_GLOBAL;
  522. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  523. ah->imask |= ATH9K_INT_RXHP |
  524. ATH9K_INT_RXLP |
  525. ATH9K_INT_BB_WATCHDOG;
  526. else
  527. ah->imask |= ATH9K_INT_RX;
  528. ah->imask |= ATH9K_INT_GTT;
  529. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  530. ah->imask |= ATH9K_INT_CST;
  531. ath_mci_enable(sc);
  532. clear_bit(SC_OP_INVALID, &sc->sc_flags);
  533. sc->sc_ah->is_monitoring = false;
  534. if (!ath_complete_reset(sc, false))
  535. ah->reset_power_on = false;
  536. if (ah->led_pin >= 0) {
  537. ath9k_hw_cfg_output(ah, ah->led_pin,
  538. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  539. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  540. }
  541. /*
  542. * Reset key cache to sane defaults (all entries cleared) instead of
  543. * semi-random values after suspend/resume.
  544. */
  545. ath9k_cmn_init_crypto(sc->sc_ah);
  546. spin_unlock_bh(&sc->sc_pcu_lock);
  547. mutex_unlock(&sc->mutex);
  548. ath9k_ps_restore(sc);
  549. return 0;
  550. }
  551. static void ath9k_tx(struct ieee80211_hw *hw,
  552. struct ieee80211_tx_control *control,
  553. struct sk_buff *skb)
  554. {
  555. struct ath_softc *sc = hw->priv;
  556. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  557. struct ath_tx_control txctl;
  558. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  559. unsigned long flags;
  560. if (sc->ps_enabled) {
  561. /*
  562. * mac80211 does not set PM field for normal data frames, so we
  563. * need to update that based on the current PS mode.
  564. */
  565. if (ieee80211_is_data(hdr->frame_control) &&
  566. !ieee80211_is_nullfunc(hdr->frame_control) &&
  567. !ieee80211_has_pm(hdr->frame_control)) {
  568. ath_dbg(common, PS,
  569. "Add PM=1 for a TX frame while in PS mode\n");
  570. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  571. }
  572. }
  573. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
  574. /*
  575. * We are using PS-Poll and mac80211 can request TX while in
  576. * power save mode. Need to wake up hardware for the TX to be
  577. * completed and if needed, also for RX of buffered frames.
  578. */
  579. ath9k_ps_wakeup(sc);
  580. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  581. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  582. ath9k_hw_setrxabort(sc->sc_ah, 0);
  583. if (ieee80211_is_pspoll(hdr->frame_control)) {
  584. ath_dbg(common, PS,
  585. "Sending PS-Poll to pick a buffered frame\n");
  586. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  587. } else {
  588. ath_dbg(common, PS, "Wake up to complete TX\n");
  589. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  590. }
  591. /*
  592. * The actual restore operation will happen only after
  593. * the ps_flags bit is cleared. We are just dropping
  594. * the ps_usecount here.
  595. */
  596. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  597. ath9k_ps_restore(sc);
  598. }
  599. /*
  600. * Cannot tx while the hardware is in full sleep, it first needs a full
  601. * chip reset to recover from that
  602. */
  603. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
  604. ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
  605. goto exit;
  606. }
  607. memset(&txctl, 0, sizeof(struct ath_tx_control));
  608. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  609. txctl.sta = control->sta;
  610. ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
  611. if (ath_tx_start(hw, skb, &txctl) != 0) {
  612. ath_dbg(common, XMIT, "TX failed\n");
  613. TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
  614. goto exit;
  615. }
  616. return;
  617. exit:
  618. ieee80211_free_txskb(hw, skb);
  619. }
  620. static void ath9k_stop(struct ieee80211_hw *hw)
  621. {
  622. struct ath_softc *sc = hw->priv;
  623. struct ath_hw *ah = sc->sc_ah;
  624. struct ath_common *common = ath9k_hw_common(ah);
  625. bool prev_idle;
  626. mutex_lock(&sc->mutex);
  627. ath_cancel_work(sc);
  628. del_timer_sync(&sc->rx_poll_timer);
  629. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  630. ath_dbg(common, ANY, "Device not present\n");
  631. mutex_unlock(&sc->mutex);
  632. return;
  633. }
  634. /* Ensure HW is awake when we try to shut it down. */
  635. ath9k_ps_wakeup(sc);
  636. spin_lock_bh(&sc->sc_pcu_lock);
  637. /* prevent tasklets to enable interrupts once we disable them */
  638. ah->imask &= ~ATH9K_INT_GLOBAL;
  639. /* make sure h/w will not generate any interrupt
  640. * before setting the invalid flag. */
  641. ath9k_hw_disable_interrupts(ah);
  642. spin_unlock_bh(&sc->sc_pcu_lock);
  643. /* we can now sync irq and kill any running tasklets, since we already
  644. * disabled interrupts and not holding a spin lock */
  645. synchronize_irq(sc->irq);
  646. tasklet_kill(&sc->intr_tq);
  647. tasklet_kill(&sc->bcon_tasklet);
  648. prev_idle = sc->ps_idle;
  649. sc->ps_idle = true;
  650. spin_lock_bh(&sc->sc_pcu_lock);
  651. if (ah->led_pin >= 0) {
  652. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  653. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  654. }
  655. ath_prepare_reset(sc, false, true);
  656. if (sc->rx.frag) {
  657. dev_kfree_skb_any(sc->rx.frag);
  658. sc->rx.frag = NULL;
  659. }
  660. if (!ah->curchan)
  661. ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
  662. ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  663. ath9k_hw_phy_disable(ah);
  664. ath9k_hw_configpcipowersave(ah, true);
  665. spin_unlock_bh(&sc->sc_pcu_lock);
  666. ath9k_ps_restore(sc);
  667. set_bit(SC_OP_INVALID, &sc->sc_flags);
  668. sc->ps_idle = prev_idle;
  669. mutex_unlock(&sc->mutex);
  670. ath_dbg(common, CONFIG, "Driver halt\n");
  671. }
  672. bool ath9k_uses_beacons(int type)
  673. {
  674. switch (type) {
  675. case NL80211_IFTYPE_AP:
  676. case NL80211_IFTYPE_ADHOC:
  677. case NL80211_IFTYPE_MESH_POINT:
  678. return true;
  679. default:
  680. return false;
  681. }
  682. }
  683. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  684. {
  685. struct ath9k_vif_iter_data *iter_data = data;
  686. int i;
  687. if (iter_data->hw_macaddr)
  688. for (i = 0; i < ETH_ALEN; i++)
  689. iter_data->mask[i] &=
  690. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  691. switch (vif->type) {
  692. case NL80211_IFTYPE_AP:
  693. iter_data->naps++;
  694. break;
  695. case NL80211_IFTYPE_STATION:
  696. iter_data->nstations++;
  697. break;
  698. case NL80211_IFTYPE_ADHOC:
  699. iter_data->nadhocs++;
  700. break;
  701. case NL80211_IFTYPE_MESH_POINT:
  702. iter_data->nmeshes++;
  703. break;
  704. case NL80211_IFTYPE_WDS:
  705. iter_data->nwds++;
  706. break;
  707. default:
  708. break;
  709. }
  710. }
  711. static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  712. {
  713. struct ath_softc *sc = data;
  714. struct ath_vif *avp = (void *)vif->drv_priv;
  715. if (vif->type != NL80211_IFTYPE_STATION)
  716. return;
  717. if (avp->primary_sta_vif)
  718. ath9k_set_assoc_state(sc, vif);
  719. }
  720. /* Called with sc->mutex held. */
  721. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  722. struct ieee80211_vif *vif,
  723. struct ath9k_vif_iter_data *iter_data)
  724. {
  725. struct ath_softc *sc = hw->priv;
  726. struct ath_hw *ah = sc->sc_ah;
  727. struct ath_common *common = ath9k_hw_common(ah);
  728. /*
  729. * Use the hardware MAC address as reference, the hardware uses it
  730. * together with the BSSID mask when matching addresses.
  731. */
  732. memset(iter_data, 0, sizeof(*iter_data));
  733. iter_data->hw_macaddr = common->macaddr;
  734. memset(&iter_data->mask, 0xff, ETH_ALEN);
  735. if (vif)
  736. ath9k_vif_iter(iter_data, vif->addr, vif);
  737. /* Get list of all active MAC addresses */
  738. ieee80211_iterate_active_interfaces_atomic(
  739. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  740. ath9k_vif_iter, iter_data);
  741. }
  742. /* Called with sc->mutex held. */
  743. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  744. struct ieee80211_vif *vif)
  745. {
  746. struct ath_softc *sc = hw->priv;
  747. struct ath_hw *ah = sc->sc_ah;
  748. struct ath_common *common = ath9k_hw_common(ah);
  749. struct ath9k_vif_iter_data iter_data;
  750. enum nl80211_iftype old_opmode = ah->opmode;
  751. ath9k_calculate_iter_data(hw, vif, &iter_data);
  752. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  753. ath_hw_setbssidmask(common);
  754. if (iter_data.naps > 0) {
  755. ath9k_hw_set_tsfadjust(ah, true);
  756. ah->opmode = NL80211_IFTYPE_AP;
  757. } else {
  758. ath9k_hw_set_tsfadjust(ah, false);
  759. if (iter_data.nmeshes)
  760. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  761. else if (iter_data.nwds)
  762. ah->opmode = NL80211_IFTYPE_AP;
  763. else if (iter_data.nadhocs)
  764. ah->opmode = NL80211_IFTYPE_ADHOC;
  765. else
  766. ah->opmode = NL80211_IFTYPE_STATION;
  767. }
  768. ath9k_hw_setopmode(ah);
  769. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
  770. ah->imask |= ATH9K_INT_TSFOOR;
  771. else
  772. ah->imask &= ~ATH9K_INT_TSFOOR;
  773. ath9k_hw_set_interrupts(ah);
  774. /*
  775. * If we are changing the opmode to STATION,
  776. * a beacon sync needs to be done.
  777. */
  778. if (ah->opmode == NL80211_IFTYPE_STATION &&
  779. old_opmode == NL80211_IFTYPE_AP &&
  780. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  781. ieee80211_iterate_active_interfaces_atomic(
  782. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  783. ath9k_sta_vif_iter, sc);
  784. }
  785. }
  786. static int ath9k_add_interface(struct ieee80211_hw *hw,
  787. struct ieee80211_vif *vif)
  788. {
  789. struct ath_softc *sc = hw->priv;
  790. struct ath_hw *ah = sc->sc_ah;
  791. struct ath_common *common = ath9k_hw_common(ah);
  792. mutex_lock(&sc->mutex);
  793. ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  794. sc->nvifs++;
  795. ath9k_ps_wakeup(sc);
  796. ath9k_calculate_summary_state(hw, vif);
  797. ath9k_ps_restore(sc);
  798. if (ath9k_uses_beacons(vif->type))
  799. ath9k_beacon_assign_slot(sc, vif);
  800. mutex_unlock(&sc->mutex);
  801. return 0;
  802. }
  803. static int ath9k_change_interface(struct ieee80211_hw *hw,
  804. struct ieee80211_vif *vif,
  805. enum nl80211_iftype new_type,
  806. bool p2p)
  807. {
  808. struct ath_softc *sc = hw->priv;
  809. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  810. ath_dbg(common, CONFIG, "Change Interface\n");
  811. mutex_lock(&sc->mutex);
  812. if (ath9k_uses_beacons(vif->type))
  813. ath9k_beacon_remove_slot(sc, vif);
  814. vif->type = new_type;
  815. vif->p2p = p2p;
  816. ath9k_ps_wakeup(sc);
  817. ath9k_calculate_summary_state(hw, vif);
  818. ath9k_ps_restore(sc);
  819. if (ath9k_uses_beacons(vif->type))
  820. ath9k_beacon_assign_slot(sc, vif);
  821. mutex_unlock(&sc->mutex);
  822. return 0;
  823. }
  824. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  825. struct ieee80211_vif *vif)
  826. {
  827. struct ath_softc *sc = hw->priv;
  828. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  829. ath_dbg(common, CONFIG, "Detach Interface\n");
  830. mutex_lock(&sc->mutex);
  831. sc->nvifs--;
  832. if (ath9k_uses_beacons(vif->type))
  833. ath9k_beacon_remove_slot(sc, vif);
  834. ath9k_ps_wakeup(sc);
  835. ath9k_calculate_summary_state(hw, NULL);
  836. ath9k_ps_restore(sc);
  837. mutex_unlock(&sc->mutex);
  838. }
  839. static void ath9k_enable_ps(struct ath_softc *sc)
  840. {
  841. struct ath_hw *ah = sc->sc_ah;
  842. struct ath_common *common = ath9k_hw_common(ah);
  843. sc->ps_enabled = true;
  844. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  845. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  846. ah->imask |= ATH9K_INT_TIM_TIMER;
  847. ath9k_hw_set_interrupts(ah);
  848. }
  849. ath9k_hw_setrxabort(ah, 1);
  850. }
  851. ath_dbg(common, PS, "PowerSave enabled\n");
  852. }
  853. static void ath9k_disable_ps(struct ath_softc *sc)
  854. {
  855. struct ath_hw *ah = sc->sc_ah;
  856. struct ath_common *common = ath9k_hw_common(ah);
  857. sc->ps_enabled = false;
  858. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  859. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  860. ath9k_hw_setrxabort(ah, 0);
  861. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  862. PS_WAIT_FOR_CAB |
  863. PS_WAIT_FOR_PSPOLL_DATA |
  864. PS_WAIT_FOR_TX_ACK);
  865. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  866. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  867. ath9k_hw_set_interrupts(ah);
  868. }
  869. }
  870. ath_dbg(common, PS, "PowerSave disabled\n");
  871. }
  872. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  873. {
  874. struct ath_softc *sc = hw->priv;
  875. struct ath_hw *ah = sc->sc_ah;
  876. struct ath_common *common = ath9k_hw_common(ah);
  877. struct ieee80211_conf *conf = &hw->conf;
  878. bool reset_channel = false;
  879. ath9k_ps_wakeup(sc);
  880. mutex_lock(&sc->mutex);
  881. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  882. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  883. if (sc->ps_idle) {
  884. ath_cancel_work(sc);
  885. ath9k_stop_btcoex(sc);
  886. } else {
  887. ath9k_start_btcoex(sc);
  888. /*
  889. * The chip needs a reset to properly wake up from
  890. * full sleep
  891. */
  892. reset_channel = ah->chip_fullsleep;
  893. }
  894. }
  895. /*
  896. * We just prepare to enable PS. We have to wait until our AP has
  897. * ACK'd our null data frame to disable RX otherwise we'll ignore
  898. * those ACKs and end up retransmitting the same null data frames.
  899. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  900. */
  901. if (changed & IEEE80211_CONF_CHANGE_PS) {
  902. unsigned long flags;
  903. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  904. if (conf->flags & IEEE80211_CONF_PS)
  905. ath9k_enable_ps(sc);
  906. else
  907. ath9k_disable_ps(sc);
  908. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  909. }
  910. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  911. if (conf->flags & IEEE80211_CONF_MONITOR) {
  912. ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
  913. sc->sc_ah->is_monitoring = true;
  914. } else {
  915. ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
  916. sc->sc_ah->is_monitoring = false;
  917. }
  918. }
  919. if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
  920. struct ieee80211_channel *curchan = hw->conf.channel;
  921. int pos = curchan->hw_value;
  922. int old_pos = -1;
  923. unsigned long flags;
  924. if (ah->curchan)
  925. old_pos = ah->curchan - &ah->channels[0];
  926. ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
  927. curchan->center_freq, conf->channel_type);
  928. /* update survey stats for the old channel before switching */
  929. spin_lock_irqsave(&common->cc_lock, flags);
  930. ath_update_survey_stats(sc);
  931. spin_unlock_irqrestore(&common->cc_lock, flags);
  932. /*
  933. * Preserve the current channel values, before updating
  934. * the same channel
  935. */
  936. if (ah->curchan && (old_pos == pos))
  937. ath9k_hw_getnf(ah, ah->curchan);
  938. ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
  939. curchan, conf->channel_type);
  940. /*
  941. * If the operating channel changes, change the survey in-use flags
  942. * along with it.
  943. * Reset the survey data for the new channel, unless we're switching
  944. * back to the operating channel from an off-channel operation.
  945. */
  946. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  947. sc->cur_survey != &sc->survey[pos]) {
  948. if (sc->cur_survey)
  949. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  950. sc->cur_survey = &sc->survey[pos];
  951. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  952. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  953. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  954. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  955. }
  956. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  957. ath_err(common, "Unable to set channel\n");
  958. mutex_unlock(&sc->mutex);
  959. ath9k_ps_restore(sc);
  960. return -EINVAL;
  961. }
  962. /*
  963. * The most recent snapshot of channel->noisefloor for the old
  964. * channel is only available after the hardware reset. Copy it to
  965. * the survey stats now.
  966. */
  967. if (old_pos >= 0)
  968. ath_update_survey_nf(sc, old_pos);
  969. }
  970. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  971. ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
  972. sc->config.txpowlimit = 2 * conf->power_level;
  973. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  974. sc->config.txpowlimit, &sc->curtxpow);
  975. }
  976. mutex_unlock(&sc->mutex);
  977. ath9k_ps_restore(sc);
  978. return 0;
  979. }
  980. #define SUPPORTED_FILTERS \
  981. (FIF_PROMISC_IN_BSS | \
  982. FIF_ALLMULTI | \
  983. FIF_CONTROL | \
  984. FIF_PSPOLL | \
  985. FIF_OTHER_BSS | \
  986. FIF_BCN_PRBRESP_PROMISC | \
  987. FIF_PROBE_REQ | \
  988. FIF_FCSFAIL)
  989. /* FIXME: sc->sc_full_reset ? */
  990. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  991. unsigned int changed_flags,
  992. unsigned int *total_flags,
  993. u64 multicast)
  994. {
  995. struct ath_softc *sc = hw->priv;
  996. u32 rfilt;
  997. changed_flags &= SUPPORTED_FILTERS;
  998. *total_flags &= SUPPORTED_FILTERS;
  999. sc->rx.rxfilter = *total_flags;
  1000. ath9k_ps_wakeup(sc);
  1001. rfilt = ath_calcrxfilter(sc);
  1002. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1003. ath9k_ps_restore(sc);
  1004. ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
  1005. rfilt);
  1006. }
  1007. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1008. struct ieee80211_vif *vif,
  1009. struct ieee80211_sta *sta)
  1010. {
  1011. struct ath_softc *sc = hw->priv;
  1012. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1013. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1014. struct ieee80211_key_conf ps_key = { };
  1015. ath_node_attach(sc, sta, vif);
  1016. if (vif->type != NL80211_IFTYPE_AP &&
  1017. vif->type != NL80211_IFTYPE_AP_VLAN)
  1018. return 0;
  1019. an->ps_key = ath_key_config(common, vif, sta, &ps_key);
  1020. return 0;
  1021. }
  1022. static void ath9k_del_ps_key(struct ath_softc *sc,
  1023. struct ieee80211_vif *vif,
  1024. struct ieee80211_sta *sta)
  1025. {
  1026. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1027. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1028. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1029. if (!an->ps_key)
  1030. return;
  1031. ath_key_delete(common, &ps_key);
  1032. }
  1033. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1034. struct ieee80211_vif *vif,
  1035. struct ieee80211_sta *sta)
  1036. {
  1037. struct ath_softc *sc = hw->priv;
  1038. ath9k_del_ps_key(sc, vif, sta);
  1039. ath_node_detach(sc, sta);
  1040. return 0;
  1041. }
  1042. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1043. struct ieee80211_vif *vif,
  1044. enum sta_notify_cmd cmd,
  1045. struct ieee80211_sta *sta)
  1046. {
  1047. struct ath_softc *sc = hw->priv;
  1048. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1049. if (!sta->ht_cap.ht_supported)
  1050. return;
  1051. switch (cmd) {
  1052. case STA_NOTIFY_SLEEP:
  1053. an->sleeping = true;
  1054. ath_tx_aggr_sleep(sta, sc, an);
  1055. break;
  1056. case STA_NOTIFY_AWAKE:
  1057. an->sleeping = false;
  1058. ath_tx_aggr_wakeup(sc, an);
  1059. break;
  1060. }
  1061. }
  1062. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1063. struct ieee80211_vif *vif, u16 queue,
  1064. const struct ieee80211_tx_queue_params *params)
  1065. {
  1066. struct ath_softc *sc = hw->priv;
  1067. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1068. struct ath_txq *txq;
  1069. struct ath9k_tx_queue_info qi;
  1070. int ret = 0;
  1071. if (queue >= IEEE80211_NUM_ACS)
  1072. return 0;
  1073. txq = sc->tx.txq_map[queue];
  1074. ath9k_ps_wakeup(sc);
  1075. mutex_lock(&sc->mutex);
  1076. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1077. qi.tqi_aifs = params->aifs;
  1078. qi.tqi_cwmin = params->cw_min;
  1079. qi.tqi_cwmax = params->cw_max;
  1080. qi.tqi_burstTime = params->txop * 32;
  1081. ath_dbg(common, CONFIG,
  1082. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1083. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1084. params->cw_max, params->txop);
  1085. ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
  1086. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1087. if (ret)
  1088. ath_err(common, "TXQ Update failed\n");
  1089. mutex_unlock(&sc->mutex);
  1090. ath9k_ps_restore(sc);
  1091. return ret;
  1092. }
  1093. static int ath9k_set_key(struct ieee80211_hw *hw,
  1094. enum set_key_cmd cmd,
  1095. struct ieee80211_vif *vif,
  1096. struct ieee80211_sta *sta,
  1097. struct ieee80211_key_conf *key)
  1098. {
  1099. struct ath_softc *sc = hw->priv;
  1100. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1101. int ret = 0;
  1102. if (ath9k_modparam_nohwcrypt)
  1103. return -ENOSPC;
  1104. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  1105. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  1106. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1107. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1108. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1109. /*
  1110. * For now, disable hw crypto for the RSN IBSS group keys. This
  1111. * could be optimized in the future to use a modified key cache
  1112. * design to support per-STA RX GTK, but until that gets
  1113. * implemented, use of software crypto for group addressed
  1114. * frames is a acceptable to allow RSN IBSS to be used.
  1115. */
  1116. return -EOPNOTSUPP;
  1117. }
  1118. mutex_lock(&sc->mutex);
  1119. ath9k_ps_wakeup(sc);
  1120. ath_dbg(common, CONFIG, "Set HW Key\n");
  1121. switch (cmd) {
  1122. case SET_KEY:
  1123. if (sta)
  1124. ath9k_del_ps_key(sc, vif, sta);
  1125. ret = ath_key_config(common, vif, sta, key);
  1126. if (ret >= 0) {
  1127. key->hw_key_idx = ret;
  1128. /* push IV and Michael MIC generation to stack */
  1129. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1130. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1131. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1132. if (sc->sc_ah->sw_mgmt_crypto &&
  1133. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1134. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
  1135. ret = 0;
  1136. }
  1137. break;
  1138. case DISABLE_KEY:
  1139. ath_key_delete(common, key);
  1140. break;
  1141. default:
  1142. ret = -EINVAL;
  1143. }
  1144. ath9k_ps_restore(sc);
  1145. mutex_unlock(&sc->mutex);
  1146. return ret;
  1147. }
  1148. static void ath9k_set_assoc_state(struct ath_softc *sc,
  1149. struct ieee80211_vif *vif)
  1150. {
  1151. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1152. struct ath_vif *avp = (void *)vif->drv_priv;
  1153. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1154. unsigned long flags;
  1155. set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1156. avp->primary_sta_vif = true;
  1157. /*
  1158. * Set the AID, BSSID and do beacon-sync only when
  1159. * the HW opmode is STATION.
  1160. *
  1161. * But the primary bit is set above in any case.
  1162. */
  1163. if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
  1164. return;
  1165. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1166. common->curaid = bss_conf->aid;
  1167. ath9k_hw_write_associd(sc->sc_ah);
  1168. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  1169. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1170. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1171. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  1172. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1173. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  1174. ath9k_mci_update_wlan_channels(sc, false);
  1175. ath_dbg(common, CONFIG,
  1176. "Primary Station interface: %pM, BSSID: %pM\n",
  1177. vif->addr, common->curbssid);
  1178. }
  1179. static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1180. {
  1181. struct ath_softc *sc = data;
  1182. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1183. if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
  1184. return;
  1185. if (bss_conf->assoc)
  1186. ath9k_set_assoc_state(sc, vif);
  1187. }
  1188. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1189. struct ieee80211_vif *vif,
  1190. struct ieee80211_bss_conf *bss_conf,
  1191. u32 changed)
  1192. {
  1193. #define CHECK_ANI \
  1194. (BSS_CHANGED_ASSOC | \
  1195. BSS_CHANGED_IBSS | \
  1196. BSS_CHANGED_BEACON_ENABLED)
  1197. struct ath_softc *sc = hw->priv;
  1198. struct ath_hw *ah = sc->sc_ah;
  1199. struct ath_common *common = ath9k_hw_common(ah);
  1200. struct ath_vif *avp = (void *)vif->drv_priv;
  1201. int slottime;
  1202. ath9k_ps_wakeup(sc);
  1203. mutex_lock(&sc->mutex);
  1204. if (changed & BSS_CHANGED_ASSOC) {
  1205. ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
  1206. bss_conf->bssid, bss_conf->assoc);
  1207. if (avp->primary_sta_vif && !bss_conf->assoc) {
  1208. clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1209. avp->primary_sta_vif = false;
  1210. if (ah->opmode == NL80211_IFTYPE_STATION)
  1211. clear_bit(SC_OP_BEACONS, &sc->sc_flags);
  1212. }
  1213. ieee80211_iterate_active_interfaces_atomic(
  1214. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  1215. ath9k_bss_assoc_iter, sc);
  1216. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) &&
  1217. ah->opmode == NL80211_IFTYPE_STATION) {
  1218. memset(common->curbssid, 0, ETH_ALEN);
  1219. common->curaid = 0;
  1220. ath9k_hw_write_associd(sc->sc_ah);
  1221. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  1222. ath9k_mci_update_wlan_channels(sc, true);
  1223. }
  1224. }
  1225. if (changed & BSS_CHANGED_IBSS) {
  1226. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1227. common->curaid = bss_conf->aid;
  1228. ath9k_hw_write_associd(sc->sc_ah);
  1229. }
  1230. if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
  1231. (changed & BSS_CHANGED_BEACON_INT)) {
  1232. if (ah->opmode == NL80211_IFTYPE_AP &&
  1233. bss_conf->enable_beacon)
  1234. ath9k_set_tsfadjust(sc, vif);
  1235. if (ath9k_allow_beacon_config(sc, vif))
  1236. ath9k_beacon_config(sc, vif, changed);
  1237. }
  1238. if (changed & BSS_CHANGED_ERP_SLOT) {
  1239. if (bss_conf->use_short_slot)
  1240. slottime = 9;
  1241. else
  1242. slottime = 20;
  1243. if (vif->type == NL80211_IFTYPE_AP) {
  1244. /*
  1245. * Defer update, so that connected stations can adjust
  1246. * their settings at the same time.
  1247. * See beacon.c for more details
  1248. */
  1249. sc->beacon.slottime = slottime;
  1250. sc->beacon.updateslot = UPDATE;
  1251. } else {
  1252. ah->slottime = slottime;
  1253. ath9k_hw_init_global_settings(ah);
  1254. }
  1255. }
  1256. if (changed & CHECK_ANI)
  1257. ath_check_ani(sc);
  1258. mutex_unlock(&sc->mutex);
  1259. ath9k_ps_restore(sc);
  1260. #undef CHECK_ANI
  1261. }
  1262. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1263. {
  1264. struct ath_softc *sc = hw->priv;
  1265. u64 tsf;
  1266. mutex_lock(&sc->mutex);
  1267. ath9k_ps_wakeup(sc);
  1268. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1269. ath9k_ps_restore(sc);
  1270. mutex_unlock(&sc->mutex);
  1271. return tsf;
  1272. }
  1273. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1274. struct ieee80211_vif *vif,
  1275. u64 tsf)
  1276. {
  1277. struct ath_softc *sc = hw->priv;
  1278. mutex_lock(&sc->mutex);
  1279. ath9k_ps_wakeup(sc);
  1280. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1281. ath9k_ps_restore(sc);
  1282. mutex_unlock(&sc->mutex);
  1283. }
  1284. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1285. {
  1286. struct ath_softc *sc = hw->priv;
  1287. mutex_lock(&sc->mutex);
  1288. ath9k_ps_wakeup(sc);
  1289. ath9k_hw_reset_tsf(sc->sc_ah);
  1290. ath9k_ps_restore(sc);
  1291. mutex_unlock(&sc->mutex);
  1292. }
  1293. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1294. struct ieee80211_vif *vif,
  1295. enum ieee80211_ampdu_mlme_action action,
  1296. struct ieee80211_sta *sta,
  1297. u16 tid, u16 *ssn, u8 buf_size)
  1298. {
  1299. struct ath_softc *sc = hw->priv;
  1300. int ret = 0;
  1301. local_bh_disable();
  1302. switch (action) {
  1303. case IEEE80211_AMPDU_RX_START:
  1304. break;
  1305. case IEEE80211_AMPDU_RX_STOP:
  1306. break;
  1307. case IEEE80211_AMPDU_TX_START:
  1308. ath9k_ps_wakeup(sc);
  1309. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1310. if (!ret)
  1311. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1312. ath9k_ps_restore(sc);
  1313. break;
  1314. case IEEE80211_AMPDU_TX_STOP:
  1315. ath9k_ps_wakeup(sc);
  1316. ath_tx_aggr_stop(sc, sta, tid);
  1317. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1318. ath9k_ps_restore(sc);
  1319. break;
  1320. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1321. ath9k_ps_wakeup(sc);
  1322. ath_tx_aggr_resume(sc, sta, tid);
  1323. ath9k_ps_restore(sc);
  1324. break;
  1325. default:
  1326. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1327. }
  1328. local_bh_enable();
  1329. return ret;
  1330. }
  1331. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1332. struct survey_info *survey)
  1333. {
  1334. struct ath_softc *sc = hw->priv;
  1335. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1336. struct ieee80211_supported_band *sband;
  1337. struct ieee80211_channel *chan;
  1338. unsigned long flags;
  1339. int pos;
  1340. spin_lock_irqsave(&common->cc_lock, flags);
  1341. if (idx == 0)
  1342. ath_update_survey_stats(sc);
  1343. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1344. if (sband && idx >= sband->n_channels) {
  1345. idx -= sband->n_channels;
  1346. sband = NULL;
  1347. }
  1348. if (!sband)
  1349. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1350. if (!sband || idx >= sband->n_channels) {
  1351. spin_unlock_irqrestore(&common->cc_lock, flags);
  1352. return -ENOENT;
  1353. }
  1354. chan = &sband->channels[idx];
  1355. pos = chan->hw_value;
  1356. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1357. survey->channel = chan;
  1358. spin_unlock_irqrestore(&common->cc_lock, flags);
  1359. return 0;
  1360. }
  1361. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1362. {
  1363. struct ath_softc *sc = hw->priv;
  1364. struct ath_hw *ah = sc->sc_ah;
  1365. mutex_lock(&sc->mutex);
  1366. ah->coverage_class = coverage_class;
  1367. ath9k_ps_wakeup(sc);
  1368. ath9k_hw_init_global_settings(ah);
  1369. ath9k_ps_restore(sc);
  1370. mutex_unlock(&sc->mutex);
  1371. }
  1372. static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
  1373. {
  1374. struct ath_softc *sc = hw->priv;
  1375. struct ath_hw *ah = sc->sc_ah;
  1376. struct ath_common *common = ath9k_hw_common(ah);
  1377. int timeout = 200; /* ms */
  1378. int i, j;
  1379. bool drain_txq;
  1380. mutex_lock(&sc->mutex);
  1381. cancel_delayed_work_sync(&sc->tx_complete_work);
  1382. if (ah->ah_flags & AH_UNPLUGGED) {
  1383. ath_dbg(common, ANY, "Device has been unplugged!\n");
  1384. mutex_unlock(&sc->mutex);
  1385. return;
  1386. }
  1387. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1388. ath_dbg(common, ANY, "Device not present\n");
  1389. mutex_unlock(&sc->mutex);
  1390. return;
  1391. }
  1392. for (j = 0; j < timeout; j++) {
  1393. bool npend = false;
  1394. if (j)
  1395. usleep_range(1000, 2000);
  1396. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1397. if (!ATH_TXQ_SETUP(sc, i))
  1398. continue;
  1399. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1400. if (npend)
  1401. break;
  1402. }
  1403. if (!npend)
  1404. break;
  1405. }
  1406. if (drop) {
  1407. ath9k_ps_wakeup(sc);
  1408. spin_lock_bh(&sc->sc_pcu_lock);
  1409. drain_txq = ath_drain_all_txq(sc, false);
  1410. spin_unlock_bh(&sc->sc_pcu_lock);
  1411. if (!drain_txq)
  1412. ath_reset(sc, false);
  1413. ath9k_ps_restore(sc);
  1414. ieee80211_wake_queues(hw);
  1415. }
  1416. ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
  1417. mutex_unlock(&sc->mutex);
  1418. }
  1419. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1420. {
  1421. struct ath_softc *sc = hw->priv;
  1422. int i;
  1423. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1424. if (!ATH_TXQ_SETUP(sc, i))
  1425. continue;
  1426. if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
  1427. return true;
  1428. }
  1429. return false;
  1430. }
  1431. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1432. {
  1433. struct ath_softc *sc = hw->priv;
  1434. struct ath_hw *ah = sc->sc_ah;
  1435. struct ieee80211_vif *vif;
  1436. struct ath_vif *avp;
  1437. struct ath_buf *bf;
  1438. struct ath_tx_status ts;
  1439. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1440. int status;
  1441. vif = sc->beacon.bslot[0];
  1442. if (!vif)
  1443. return 0;
  1444. if (!vif->bss_conf.enable_beacon)
  1445. return 0;
  1446. avp = (void *)vif->drv_priv;
  1447. if (!sc->beacon.tx_processed && !edma) {
  1448. tasklet_disable(&sc->bcon_tasklet);
  1449. bf = avp->av_bcbuf;
  1450. if (!bf || !bf->bf_mpdu)
  1451. goto skip;
  1452. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1453. if (status == -EINPROGRESS)
  1454. goto skip;
  1455. sc->beacon.tx_processed = true;
  1456. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1457. skip:
  1458. tasklet_enable(&sc->bcon_tasklet);
  1459. }
  1460. return sc->beacon.tx_last;
  1461. }
  1462. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1463. struct ieee80211_low_level_stats *stats)
  1464. {
  1465. struct ath_softc *sc = hw->priv;
  1466. struct ath_hw *ah = sc->sc_ah;
  1467. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1468. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1469. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1470. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1471. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1472. return 0;
  1473. }
  1474. static u32 fill_chainmask(u32 cap, u32 new)
  1475. {
  1476. u32 filled = 0;
  1477. int i;
  1478. for (i = 0; cap && new; i++, cap >>= 1) {
  1479. if (!(cap & BIT(0)))
  1480. continue;
  1481. if (new & BIT(0))
  1482. filled |= BIT(i);
  1483. new >>= 1;
  1484. }
  1485. return filled;
  1486. }
  1487. static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
  1488. {
  1489. switch (val & 0x7) {
  1490. case 0x1:
  1491. case 0x3:
  1492. case 0x7:
  1493. return true;
  1494. case 0x2:
  1495. return (ah->caps.rx_chainmask == 1);
  1496. default:
  1497. return false;
  1498. }
  1499. }
  1500. static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
  1501. {
  1502. struct ath_softc *sc = hw->priv;
  1503. struct ath_hw *ah = sc->sc_ah;
  1504. if (ah->caps.rx_chainmask != 1)
  1505. rx_ant |= tx_ant;
  1506. if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
  1507. return -EINVAL;
  1508. sc->ant_rx = rx_ant;
  1509. sc->ant_tx = tx_ant;
  1510. if (ah->caps.rx_chainmask == 1)
  1511. return 0;
  1512. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  1513. if (AR_SREV_9100(ah))
  1514. ah->rxchainmask = 0x7;
  1515. else
  1516. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  1517. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  1518. ath9k_reload_chainmask_settings(sc);
  1519. return 0;
  1520. }
  1521. static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
  1522. {
  1523. struct ath_softc *sc = hw->priv;
  1524. *tx_ant = sc->ant_tx;
  1525. *rx_ant = sc->ant_rx;
  1526. return 0;
  1527. }
  1528. #ifdef CONFIG_PM_SLEEP
  1529. static void ath9k_wow_map_triggers(struct ath_softc *sc,
  1530. struct cfg80211_wowlan *wowlan,
  1531. u32 *wow_triggers)
  1532. {
  1533. if (wowlan->disconnect)
  1534. *wow_triggers |= AH_WOW_LINK_CHANGE |
  1535. AH_WOW_BEACON_MISS;
  1536. if (wowlan->magic_pkt)
  1537. *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
  1538. if (wowlan->n_patterns)
  1539. *wow_triggers |= AH_WOW_USER_PATTERN_EN;
  1540. sc->wow_enabled = *wow_triggers;
  1541. }
  1542. static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
  1543. {
  1544. struct ath_hw *ah = sc->sc_ah;
  1545. struct ath_common *common = ath9k_hw_common(ah);
  1546. struct ath9k_hw_capabilities *pcaps = &ah->caps;
  1547. int pattern_count = 0;
  1548. int i, byte_cnt;
  1549. u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
  1550. u8 dis_deauth_mask[MAX_PATTERN_SIZE];
  1551. memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
  1552. memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
  1553. /*
  1554. * Create Dissassociate / Deauthenticate packet filter
  1555. *
  1556. * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
  1557. * +--------------+----------+---------+--------+--------+----
  1558. * + Frame Control+ Duration + DA + SA + BSSID +
  1559. * +--------------+----------+---------+--------+--------+----
  1560. *
  1561. * The above is the management frame format for disassociate/
  1562. * deauthenticate pattern, from this we need to match the first byte
  1563. * of 'Frame Control' and DA, SA, and BSSID fields
  1564. * (skipping 2nd byte of FC and Duration feild.
  1565. *
  1566. * Disassociate pattern
  1567. * --------------------
  1568. * Frame control = 00 00 1010
  1569. * DA, SA, BSSID = x:x:x:x:x:x
  1570. * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1571. * | x:x:x:x:x:x -- 22 bytes
  1572. *
  1573. * Deauthenticate pattern
  1574. * ----------------------
  1575. * Frame control = 00 00 1100
  1576. * DA, SA, BSSID = x:x:x:x:x:x
  1577. * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1578. * | x:x:x:x:x:x -- 22 bytes
  1579. */
  1580. /* Create Disassociate Pattern first */
  1581. byte_cnt = 0;
  1582. /* Fill out the mask with all FF's */
  1583. for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
  1584. dis_deauth_mask[i] = 0xff;
  1585. /* copy the first byte of frame control field */
  1586. dis_deauth_pattern[byte_cnt] = 0xa0;
  1587. byte_cnt++;
  1588. /* skip 2nd byte of frame control and Duration field */
  1589. byte_cnt += 3;
  1590. /*
  1591. * need not match the destination mac address, it can be a broadcast
  1592. * mac address or an unicast to this station
  1593. */
  1594. byte_cnt += 6;
  1595. /* copy the source mac address */
  1596. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1597. byte_cnt += 6;
  1598. /* copy the bssid, its same as the source mac address */
  1599. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1600. /* Create Disassociate pattern mask */
  1601. if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) {
  1602. if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) {
  1603. /*
  1604. * for AR9280, because of hardware limitation, the
  1605. * first 4 bytes have to be matched for all patterns.
  1606. * the mask for disassociation and de-auth pattern
  1607. * matching need to enable the first 4 bytes.
  1608. * also the duration field needs to be filled.
  1609. */
  1610. dis_deauth_mask[0] = 0xf0;
  1611. /*
  1612. * fill in duration field
  1613. FIXME: what is the exact value ?
  1614. */
  1615. dis_deauth_pattern[2] = 0xff;
  1616. dis_deauth_pattern[3] = 0xff;
  1617. } else {
  1618. dis_deauth_mask[0] = 0xfe;
  1619. }
  1620. dis_deauth_mask[1] = 0x03;
  1621. dis_deauth_mask[2] = 0xc0;
  1622. } else {
  1623. dis_deauth_mask[0] = 0xef;
  1624. dis_deauth_mask[1] = 0x3f;
  1625. dis_deauth_mask[2] = 0x00;
  1626. dis_deauth_mask[3] = 0xfc;
  1627. }
  1628. ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
  1629. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1630. pattern_count, byte_cnt);
  1631. pattern_count++;
  1632. /*
  1633. * for de-authenticate pattern, only the first byte of the frame
  1634. * control field gets changed from 0xA0 to 0xC0
  1635. */
  1636. dis_deauth_pattern[0] = 0xC0;
  1637. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1638. pattern_count, byte_cnt);
  1639. }
  1640. static void ath9k_wow_add_pattern(struct ath_softc *sc,
  1641. struct cfg80211_wowlan *wowlan)
  1642. {
  1643. struct ath_hw *ah = sc->sc_ah;
  1644. struct ath9k_wow_pattern *wow_pattern = NULL;
  1645. struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns;
  1646. int mask_len;
  1647. s8 i = 0;
  1648. if (!wowlan->n_patterns)
  1649. return;
  1650. /*
  1651. * Add the new user configured patterns
  1652. */
  1653. for (i = 0; i < wowlan->n_patterns; i++) {
  1654. wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
  1655. if (!wow_pattern)
  1656. return;
  1657. /*
  1658. * TODO: convert the generic user space pattern to
  1659. * appropriate chip specific/802.11 pattern.
  1660. */
  1661. mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
  1662. memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
  1663. memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
  1664. memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
  1665. patterns[i].pattern_len);
  1666. memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
  1667. wow_pattern->pattern_len = patterns[i].pattern_len;
  1668. /*
  1669. * just need to take care of deauth and disssoc pattern,
  1670. * make sure we don't overwrite them.
  1671. */
  1672. ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
  1673. wow_pattern->mask_bytes,
  1674. i + 2,
  1675. wow_pattern->pattern_len);
  1676. kfree(wow_pattern);
  1677. }
  1678. }
  1679. static int ath9k_suspend(struct ieee80211_hw *hw,
  1680. struct cfg80211_wowlan *wowlan)
  1681. {
  1682. struct ath_softc *sc = hw->priv;
  1683. struct ath_hw *ah = sc->sc_ah;
  1684. struct ath_common *common = ath9k_hw_common(ah);
  1685. u32 wow_triggers_enabled = 0;
  1686. int ret = 0;
  1687. mutex_lock(&sc->mutex);
  1688. ath_cancel_work(sc);
  1689. ath_stop_ani(sc);
  1690. del_timer_sync(&sc->rx_poll_timer);
  1691. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1692. ath_dbg(common, ANY, "Device not present\n");
  1693. ret = -EINVAL;
  1694. goto fail_wow;
  1695. }
  1696. if (WARN_ON(!wowlan)) {
  1697. ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
  1698. ret = -EINVAL;
  1699. goto fail_wow;
  1700. }
  1701. if (!device_can_wakeup(sc->dev)) {
  1702. ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
  1703. ret = 1;
  1704. goto fail_wow;
  1705. }
  1706. /*
  1707. * none of the sta vifs are associated
  1708. * and we are not currently handling multivif
  1709. * cases, for instance we have to seperately
  1710. * configure 'keep alive frame' for each
  1711. * STA.
  1712. */
  1713. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  1714. ath_dbg(common, WOW, "None of the STA vifs are associated\n");
  1715. ret = 1;
  1716. goto fail_wow;
  1717. }
  1718. if (sc->nvifs > 1) {
  1719. ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
  1720. ret = 1;
  1721. goto fail_wow;
  1722. }
  1723. ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
  1724. ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
  1725. wow_triggers_enabled);
  1726. ath9k_ps_wakeup(sc);
  1727. ath9k_stop_btcoex(sc);
  1728. /*
  1729. * Enable wake up on recieving disassoc/deauth
  1730. * frame by default.
  1731. */
  1732. ath9k_wow_add_disassoc_deauth_pattern(sc);
  1733. if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
  1734. ath9k_wow_add_pattern(sc, wowlan);
  1735. spin_lock_bh(&sc->sc_pcu_lock);
  1736. /*
  1737. * To avoid false wake, we enable beacon miss interrupt only
  1738. * when we go to sleep. We save the current interrupt mask
  1739. * so we can restore it after the system wakes up
  1740. */
  1741. sc->wow_intr_before_sleep = ah->imask;
  1742. ah->imask &= ~ATH9K_INT_GLOBAL;
  1743. ath9k_hw_disable_interrupts(ah);
  1744. ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
  1745. ath9k_hw_set_interrupts(ah);
  1746. ath9k_hw_enable_interrupts(ah);
  1747. spin_unlock_bh(&sc->sc_pcu_lock);
  1748. /*
  1749. * we can now sync irq and kill any running tasklets, since we already
  1750. * disabled interrupts and not holding a spin lock
  1751. */
  1752. synchronize_irq(sc->irq);
  1753. tasklet_kill(&sc->intr_tq);
  1754. ath9k_hw_wow_enable(ah, wow_triggers_enabled);
  1755. ath9k_ps_restore(sc);
  1756. ath_dbg(common, ANY, "WoW enabled in ath9k\n");
  1757. atomic_inc(&sc->wow_sleep_proc_intr);
  1758. fail_wow:
  1759. mutex_unlock(&sc->mutex);
  1760. return ret;
  1761. }
  1762. static int ath9k_resume(struct ieee80211_hw *hw)
  1763. {
  1764. struct ath_softc *sc = hw->priv;
  1765. struct ath_hw *ah = sc->sc_ah;
  1766. struct ath_common *common = ath9k_hw_common(ah);
  1767. u32 wow_status;
  1768. mutex_lock(&sc->mutex);
  1769. ath9k_ps_wakeup(sc);
  1770. spin_lock_bh(&sc->sc_pcu_lock);
  1771. ath9k_hw_disable_interrupts(ah);
  1772. ah->imask = sc->wow_intr_before_sleep;
  1773. ath9k_hw_set_interrupts(ah);
  1774. ath9k_hw_enable_interrupts(ah);
  1775. spin_unlock_bh(&sc->sc_pcu_lock);
  1776. wow_status = ath9k_hw_wow_wakeup(ah);
  1777. if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
  1778. /*
  1779. * some devices may not pick beacon miss
  1780. * as the reason they woke up so we add
  1781. * that here for that shortcoming.
  1782. */
  1783. wow_status |= AH_WOW_BEACON_MISS;
  1784. atomic_dec(&sc->wow_got_bmiss_intr);
  1785. ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
  1786. }
  1787. atomic_dec(&sc->wow_sleep_proc_intr);
  1788. if (wow_status) {
  1789. ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
  1790. ath9k_hw_wow_event_to_string(wow_status), wow_status);
  1791. }
  1792. ath_restart_work(sc);
  1793. ath9k_start_btcoex(sc);
  1794. ath9k_ps_restore(sc);
  1795. mutex_unlock(&sc->mutex);
  1796. return 0;
  1797. }
  1798. static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
  1799. {
  1800. struct ath_softc *sc = hw->priv;
  1801. mutex_lock(&sc->mutex);
  1802. device_init_wakeup(sc->dev, 1);
  1803. device_set_wakeup_enable(sc->dev, enabled);
  1804. mutex_unlock(&sc->mutex);
  1805. }
  1806. #endif
  1807. struct ieee80211_ops ath9k_ops = {
  1808. .tx = ath9k_tx,
  1809. .start = ath9k_start,
  1810. .stop = ath9k_stop,
  1811. .add_interface = ath9k_add_interface,
  1812. .change_interface = ath9k_change_interface,
  1813. .remove_interface = ath9k_remove_interface,
  1814. .config = ath9k_config,
  1815. .configure_filter = ath9k_configure_filter,
  1816. .sta_add = ath9k_sta_add,
  1817. .sta_remove = ath9k_sta_remove,
  1818. .sta_notify = ath9k_sta_notify,
  1819. .conf_tx = ath9k_conf_tx,
  1820. .bss_info_changed = ath9k_bss_info_changed,
  1821. .set_key = ath9k_set_key,
  1822. .get_tsf = ath9k_get_tsf,
  1823. .set_tsf = ath9k_set_tsf,
  1824. .reset_tsf = ath9k_reset_tsf,
  1825. .ampdu_action = ath9k_ampdu_action,
  1826. .get_survey = ath9k_get_survey,
  1827. .rfkill_poll = ath9k_rfkill_poll_state,
  1828. .set_coverage_class = ath9k_set_coverage_class,
  1829. .flush = ath9k_flush,
  1830. .tx_frames_pending = ath9k_tx_frames_pending,
  1831. .tx_last_beacon = ath9k_tx_last_beacon,
  1832. .get_stats = ath9k_get_stats,
  1833. .set_antenna = ath9k_set_antenna,
  1834. .get_antenna = ath9k_get_antenna,
  1835. #ifdef CONFIG_PM_SLEEP
  1836. .suspend = ath9k_suspend,
  1837. .resume = ath9k_resume,
  1838. .set_wakeup = ath9k_set_wakeup,
  1839. #endif
  1840. #ifdef CONFIG_ATH9K_DEBUGFS
  1841. .get_et_sset_count = ath9k_get_et_sset_count,
  1842. .get_et_stats = ath9k_get_et_stats,
  1843. .get_et_strings = ath9k_get_et_strings,
  1844. #endif
  1845. #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_DEBUGFS)
  1846. .sta_add_debugfs = ath9k_sta_add_debugfs,
  1847. .sta_remove_debugfs = ath9k_sta_remove_debugfs,
  1848. #endif
  1849. };