resource_tracker.c 79 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
  4. * All rights reserved.
  5. * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
  6. *
  7. * This software is available to you under a choice of one of two
  8. * licenses. You may choose to be licensed under the terms of the GNU
  9. * General Public License (GPL) Version 2, available from the file
  10. * COPYING in the main directory of this source tree, or the
  11. * OpenIB.org BSD license below:
  12. *
  13. * Redistribution and use in source and binary forms, with or
  14. * without modification, are permitted provided that the following
  15. * conditions are met:
  16. *
  17. * - Redistributions of source code must retain the above
  18. * copyright notice, this list of conditions and the following
  19. * disclaimer.
  20. *
  21. * - Redistributions in binary form must reproduce the above
  22. * copyright notice, this list of conditions and the following
  23. * disclaimer in the documentation and/or other materials
  24. * provided with the distribution.
  25. *
  26. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33. * SOFTWARE.
  34. */
  35. #include <linux/sched.h>
  36. #include <linux/pci.h>
  37. #include <linux/errno.h>
  38. #include <linux/kernel.h>
  39. #include <linux/io.h>
  40. #include <linux/slab.h>
  41. #include <linux/mlx4/cmd.h>
  42. #include <linux/mlx4/qp.h>
  43. #include <linux/if_ether.h>
  44. #include <linux/etherdevice.h>
  45. #include "mlx4.h"
  46. #include "fw.h"
  47. #define MLX4_MAC_VALID (1ull << 63)
  48. struct mac_res {
  49. struct list_head list;
  50. u64 mac;
  51. u8 port;
  52. };
  53. struct res_common {
  54. struct list_head list;
  55. struct rb_node node;
  56. u64 res_id;
  57. int owner;
  58. int state;
  59. int from_state;
  60. int to_state;
  61. int removing;
  62. };
  63. enum {
  64. RES_ANY_BUSY = 1
  65. };
  66. struct res_gid {
  67. struct list_head list;
  68. u8 gid[16];
  69. enum mlx4_protocol prot;
  70. enum mlx4_steer_type steer;
  71. };
  72. enum res_qp_states {
  73. RES_QP_BUSY = RES_ANY_BUSY,
  74. /* QP number was allocated */
  75. RES_QP_RESERVED,
  76. /* ICM memory for QP context was mapped */
  77. RES_QP_MAPPED,
  78. /* QP is in hw ownership */
  79. RES_QP_HW
  80. };
  81. struct res_qp {
  82. struct res_common com;
  83. struct res_mtt *mtt;
  84. struct res_cq *rcq;
  85. struct res_cq *scq;
  86. struct res_srq *srq;
  87. struct list_head mcg_list;
  88. spinlock_t mcg_spl;
  89. int local_qpn;
  90. };
  91. enum res_mtt_states {
  92. RES_MTT_BUSY = RES_ANY_BUSY,
  93. RES_MTT_ALLOCATED,
  94. };
  95. static inline const char *mtt_states_str(enum res_mtt_states state)
  96. {
  97. switch (state) {
  98. case RES_MTT_BUSY: return "RES_MTT_BUSY";
  99. case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
  100. default: return "Unknown";
  101. }
  102. }
  103. struct res_mtt {
  104. struct res_common com;
  105. int order;
  106. atomic_t ref_count;
  107. };
  108. enum res_mpt_states {
  109. RES_MPT_BUSY = RES_ANY_BUSY,
  110. RES_MPT_RESERVED,
  111. RES_MPT_MAPPED,
  112. RES_MPT_HW,
  113. };
  114. struct res_mpt {
  115. struct res_common com;
  116. struct res_mtt *mtt;
  117. int key;
  118. };
  119. enum res_eq_states {
  120. RES_EQ_BUSY = RES_ANY_BUSY,
  121. RES_EQ_RESERVED,
  122. RES_EQ_HW,
  123. };
  124. struct res_eq {
  125. struct res_common com;
  126. struct res_mtt *mtt;
  127. };
  128. enum res_cq_states {
  129. RES_CQ_BUSY = RES_ANY_BUSY,
  130. RES_CQ_ALLOCATED,
  131. RES_CQ_HW,
  132. };
  133. struct res_cq {
  134. struct res_common com;
  135. struct res_mtt *mtt;
  136. atomic_t ref_count;
  137. };
  138. enum res_srq_states {
  139. RES_SRQ_BUSY = RES_ANY_BUSY,
  140. RES_SRQ_ALLOCATED,
  141. RES_SRQ_HW,
  142. };
  143. struct res_srq {
  144. struct res_common com;
  145. struct res_mtt *mtt;
  146. struct res_cq *cq;
  147. atomic_t ref_count;
  148. };
  149. enum res_counter_states {
  150. RES_COUNTER_BUSY = RES_ANY_BUSY,
  151. RES_COUNTER_ALLOCATED,
  152. };
  153. struct res_counter {
  154. struct res_common com;
  155. int port;
  156. };
  157. enum res_xrcdn_states {
  158. RES_XRCD_BUSY = RES_ANY_BUSY,
  159. RES_XRCD_ALLOCATED,
  160. };
  161. struct res_xrcdn {
  162. struct res_common com;
  163. int port;
  164. };
  165. enum res_fs_rule_states {
  166. RES_FS_RULE_BUSY = RES_ANY_BUSY,
  167. RES_FS_RULE_ALLOCATED,
  168. };
  169. struct res_fs_rule {
  170. struct res_common com;
  171. };
  172. static void *res_tracker_lookup(struct rb_root *root, u64 res_id)
  173. {
  174. struct rb_node *node = root->rb_node;
  175. while (node) {
  176. struct res_common *res = container_of(node, struct res_common,
  177. node);
  178. if (res_id < res->res_id)
  179. node = node->rb_left;
  180. else if (res_id > res->res_id)
  181. node = node->rb_right;
  182. else
  183. return res;
  184. }
  185. return NULL;
  186. }
  187. static int res_tracker_insert(struct rb_root *root, struct res_common *res)
  188. {
  189. struct rb_node **new = &(root->rb_node), *parent = NULL;
  190. /* Figure out where to put new node */
  191. while (*new) {
  192. struct res_common *this = container_of(*new, struct res_common,
  193. node);
  194. parent = *new;
  195. if (res->res_id < this->res_id)
  196. new = &((*new)->rb_left);
  197. else if (res->res_id > this->res_id)
  198. new = &((*new)->rb_right);
  199. else
  200. return -EEXIST;
  201. }
  202. /* Add new node and rebalance tree. */
  203. rb_link_node(&res->node, parent, new);
  204. rb_insert_color(&res->node, root);
  205. return 0;
  206. }
  207. /* For Debug uses */
  208. static const char *ResourceType(enum mlx4_resource rt)
  209. {
  210. switch (rt) {
  211. case RES_QP: return "RES_QP";
  212. case RES_CQ: return "RES_CQ";
  213. case RES_SRQ: return "RES_SRQ";
  214. case RES_MPT: return "RES_MPT";
  215. case RES_MTT: return "RES_MTT";
  216. case RES_MAC: return "RES_MAC";
  217. case RES_EQ: return "RES_EQ";
  218. case RES_COUNTER: return "RES_COUNTER";
  219. case RES_FS_RULE: return "RES_FS_RULE";
  220. case RES_XRCD: return "RES_XRCD";
  221. default: return "Unknown resource type !!!";
  222. };
  223. }
  224. int mlx4_init_resource_tracker(struct mlx4_dev *dev)
  225. {
  226. struct mlx4_priv *priv = mlx4_priv(dev);
  227. int i;
  228. int t;
  229. priv->mfunc.master.res_tracker.slave_list =
  230. kzalloc(dev->num_slaves * sizeof(struct slave_list),
  231. GFP_KERNEL);
  232. if (!priv->mfunc.master.res_tracker.slave_list)
  233. return -ENOMEM;
  234. for (i = 0 ; i < dev->num_slaves; i++) {
  235. for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
  236. INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
  237. slave_list[i].res_list[t]);
  238. mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
  239. }
  240. mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
  241. dev->num_slaves);
  242. for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
  243. priv->mfunc.master.res_tracker.res_tree[i] = RB_ROOT;
  244. spin_lock_init(&priv->mfunc.master.res_tracker.lock);
  245. return 0 ;
  246. }
  247. void mlx4_free_resource_tracker(struct mlx4_dev *dev,
  248. enum mlx4_res_tracker_free_type type)
  249. {
  250. struct mlx4_priv *priv = mlx4_priv(dev);
  251. int i;
  252. if (priv->mfunc.master.res_tracker.slave_list) {
  253. if (type != RES_TR_FREE_STRUCTS_ONLY)
  254. for (i = 0 ; i < dev->num_slaves; i++)
  255. if (type == RES_TR_FREE_ALL ||
  256. dev->caps.function != i)
  257. mlx4_delete_all_resources_for_slave(dev, i);
  258. if (type != RES_TR_FREE_SLAVES_ONLY) {
  259. kfree(priv->mfunc.master.res_tracker.slave_list);
  260. priv->mfunc.master.res_tracker.slave_list = NULL;
  261. }
  262. }
  263. }
  264. static void update_ud_gid(struct mlx4_dev *dev,
  265. struct mlx4_qp_context *qp_ctx, u8 slave)
  266. {
  267. u32 ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
  268. if (MLX4_QP_ST_UD == ts)
  269. qp_ctx->pri_path.mgid_index = 0x80 | slave;
  270. mlx4_dbg(dev, "slave %d, new gid index: 0x%x ",
  271. slave, qp_ctx->pri_path.mgid_index);
  272. }
  273. static int mpt_mask(struct mlx4_dev *dev)
  274. {
  275. return dev->caps.num_mpts - 1;
  276. }
  277. static void *find_res(struct mlx4_dev *dev, int res_id,
  278. enum mlx4_resource type)
  279. {
  280. struct mlx4_priv *priv = mlx4_priv(dev);
  281. return res_tracker_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
  282. res_id);
  283. }
  284. static int get_res(struct mlx4_dev *dev, int slave, u64 res_id,
  285. enum mlx4_resource type,
  286. void *res)
  287. {
  288. struct res_common *r;
  289. int err = 0;
  290. spin_lock_irq(mlx4_tlock(dev));
  291. r = find_res(dev, res_id, type);
  292. if (!r) {
  293. err = -ENONET;
  294. goto exit;
  295. }
  296. if (r->state == RES_ANY_BUSY) {
  297. err = -EBUSY;
  298. goto exit;
  299. }
  300. if (r->owner != slave) {
  301. err = -EPERM;
  302. goto exit;
  303. }
  304. r->from_state = r->state;
  305. r->state = RES_ANY_BUSY;
  306. mlx4_dbg(dev, "res %s id 0x%llx to busy\n",
  307. ResourceType(type), r->res_id);
  308. if (res)
  309. *((struct res_common **)res) = r;
  310. exit:
  311. spin_unlock_irq(mlx4_tlock(dev));
  312. return err;
  313. }
  314. int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
  315. enum mlx4_resource type,
  316. u64 res_id, int *slave)
  317. {
  318. struct res_common *r;
  319. int err = -ENOENT;
  320. int id = res_id;
  321. if (type == RES_QP)
  322. id &= 0x7fffff;
  323. spin_lock(mlx4_tlock(dev));
  324. r = find_res(dev, id, type);
  325. if (r) {
  326. *slave = r->owner;
  327. err = 0;
  328. }
  329. spin_unlock(mlx4_tlock(dev));
  330. return err;
  331. }
  332. static void put_res(struct mlx4_dev *dev, int slave, u64 res_id,
  333. enum mlx4_resource type)
  334. {
  335. struct res_common *r;
  336. spin_lock_irq(mlx4_tlock(dev));
  337. r = find_res(dev, res_id, type);
  338. if (r)
  339. r->state = r->from_state;
  340. spin_unlock_irq(mlx4_tlock(dev));
  341. }
  342. static struct res_common *alloc_qp_tr(int id)
  343. {
  344. struct res_qp *ret;
  345. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  346. if (!ret)
  347. return NULL;
  348. ret->com.res_id = id;
  349. ret->com.state = RES_QP_RESERVED;
  350. ret->local_qpn = id;
  351. INIT_LIST_HEAD(&ret->mcg_list);
  352. spin_lock_init(&ret->mcg_spl);
  353. return &ret->com;
  354. }
  355. static struct res_common *alloc_mtt_tr(int id, int order)
  356. {
  357. struct res_mtt *ret;
  358. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  359. if (!ret)
  360. return NULL;
  361. ret->com.res_id = id;
  362. ret->order = order;
  363. ret->com.state = RES_MTT_ALLOCATED;
  364. atomic_set(&ret->ref_count, 0);
  365. return &ret->com;
  366. }
  367. static struct res_common *alloc_mpt_tr(int id, int key)
  368. {
  369. struct res_mpt *ret;
  370. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  371. if (!ret)
  372. return NULL;
  373. ret->com.res_id = id;
  374. ret->com.state = RES_MPT_RESERVED;
  375. ret->key = key;
  376. return &ret->com;
  377. }
  378. static struct res_common *alloc_eq_tr(int id)
  379. {
  380. struct res_eq *ret;
  381. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  382. if (!ret)
  383. return NULL;
  384. ret->com.res_id = id;
  385. ret->com.state = RES_EQ_RESERVED;
  386. return &ret->com;
  387. }
  388. static struct res_common *alloc_cq_tr(int id)
  389. {
  390. struct res_cq *ret;
  391. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  392. if (!ret)
  393. return NULL;
  394. ret->com.res_id = id;
  395. ret->com.state = RES_CQ_ALLOCATED;
  396. atomic_set(&ret->ref_count, 0);
  397. return &ret->com;
  398. }
  399. static struct res_common *alloc_srq_tr(int id)
  400. {
  401. struct res_srq *ret;
  402. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  403. if (!ret)
  404. return NULL;
  405. ret->com.res_id = id;
  406. ret->com.state = RES_SRQ_ALLOCATED;
  407. atomic_set(&ret->ref_count, 0);
  408. return &ret->com;
  409. }
  410. static struct res_common *alloc_counter_tr(int id)
  411. {
  412. struct res_counter *ret;
  413. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  414. if (!ret)
  415. return NULL;
  416. ret->com.res_id = id;
  417. ret->com.state = RES_COUNTER_ALLOCATED;
  418. return &ret->com;
  419. }
  420. static struct res_common *alloc_xrcdn_tr(int id)
  421. {
  422. struct res_xrcdn *ret;
  423. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  424. if (!ret)
  425. return NULL;
  426. ret->com.res_id = id;
  427. ret->com.state = RES_XRCD_ALLOCATED;
  428. return &ret->com;
  429. }
  430. static struct res_common *alloc_fs_rule_tr(u64 id)
  431. {
  432. struct res_fs_rule *ret;
  433. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  434. if (!ret)
  435. return NULL;
  436. ret->com.res_id = id;
  437. ret->com.state = RES_FS_RULE_ALLOCATED;
  438. return &ret->com;
  439. }
  440. static struct res_common *alloc_tr(u64 id, enum mlx4_resource type, int slave,
  441. int extra)
  442. {
  443. struct res_common *ret;
  444. switch (type) {
  445. case RES_QP:
  446. ret = alloc_qp_tr(id);
  447. break;
  448. case RES_MPT:
  449. ret = alloc_mpt_tr(id, extra);
  450. break;
  451. case RES_MTT:
  452. ret = alloc_mtt_tr(id, extra);
  453. break;
  454. case RES_EQ:
  455. ret = alloc_eq_tr(id);
  456. break;
  457. case RES_CQ:
  458. ret = alloc_cq_tr(id);
  459. break;
  460. case RES_SRQ:
  461. ret = alloc_srq_tr(id);
  462. break;
  463. case RES_MAC:
  464. printk(KERN_ERR "implementation missing\n");
  465. return NULL;
  466. case RES_COUNTER:
  467. ret = alloc_counter_tr(id);
  468. break;
  469. case RES_XRCD:
  470. ret = alloc_xrcdn_tr(id);
  471. break;
  472. case RES_FS_RULE:
  473. ret = alloc_fs_rule_tr(id);
  474. break;
  475. default:
  476. return NULL;
  477. }
  478. if (ret)
  479. ret->owner = slave;
  480. return ret;
  481. }
  482. static int add_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
  483. enum mlx4_resource type, int extra)
  484. {
  485. int i;
  486. int err;
  487. struct mlx4_priv *priv = mlx4_priv(dev);
  488. struct res_common **res_arr;
  489. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  490. struct rb_root *root = &tracker->res_tree[type];
  491. res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL);
  492. if (!res_arr)
  493. return -ENOMEM;
  494. for (i = 0; i < count; ++i) {
  495. res_arr[i] = alloc_tr(base + i, type, slave, extra);
  496. if (!res_arr[i]) {
  497. for (--i; i >= 0; --i)
  498. kfree(res_arr[i]);
  499. kfree(res_arr);
  500. return -ENOMEM;
  501. }
  502. }
  503. spin_lock_irq(mlx4_tlock(dev));
  504. for (i = 0; i < count; ++i) {
  505. if (find_res(dev, base + i, type)) {
  506. err = -EEXIST;
  507. goto undo;
  508. }
  509. err = res_tracker_insert(root, res_arr[i]);
  510. if (err)
  511. goto undo;
  512. list_add_tail(&res_arr[i]->list,
  513. &tracker->slave_list[slave].res_list[type]);
  514. }
  515. spin_unlock_irq(mlx4_tlock(dev));
  516. kfree(res_arr);
  517. return 0;
  518. undo:
  519. for (--i; i >= base; --i)
  520. rb_erase(&res_arr[i]->node, root);
  521. spin_unlock_irq(mlx4_tlock(dev));
  522. for (i = 0; i < count; ++i)
  523. kfree(res_arr[i]);
  524. kfree(res_arr);
  525. return err;
  526. }
  527. static int remove_qp_ok(struct res_qp *res)
  528. {
  529. if (res->com.state == RES_QP_BUSY)
  530. return -EBUSY;
  531. else if (res->com.state != RES_QP_RESERVED)
  532. return -EPERM;
  533. return 0;
  534. }
  535. static int remove_mtt_ok(struct res_mtt *res, int order)
  536. {
  537. if (res->com.state == RES_MTT_BUSY ||
  538. atomic_read(&res->ref_count)) {
  539. printk(KERN_DEBUG "%s-%d: state %s, ref_count %d\n",
  540. __func__, __LINE__,
  541. mtt_states_str(res->com.state),
  542. atomic_read(&res->ref_count));
  543. return -EBUSY;
  544. } else if (res->com.state != RES_MTT_ALLOCATED)
  545. return -EPERM;
  546. else if (res->order != order)
  547. return -EINVAL;
  548. return 0;
  549. }
  550. static int remove_mpt_ok(struct res_mpt *res)
  551. {
  552. if (res->com.state == RES_MPT_BUSY)
  553. return -EBUSY;
  554. else if (res->com.state != RES_MPT_RESERVED)
  555. return -EPERM;
  556. return 0;
  557. }
  558. static int remove_eq_ok(struct res_eq *res)
  559. {
  560. if (res->com.state == RES_MPT_BUSY)
  561. return -EBUSY;
  562. else if (res->com.state != RES_MPT_RESERVED)
  563. return -EPERM;
  564. return 0;
  565. }
  566. static int remove_counter_ok(struct res_counter *res)
  567. {
  568. if (res->com.state == RES_COUNTER_BUSY)
  569. return -EBUSY;
  570. else if (res->com.state != RES_COUNTER_ALLOCATED)
  571. return -EPERM;
  572. return 0;
  573. }
  574. static int remove_xrcdn_ok(struct res_xrcdn *res)
  575. {
  576. if (res->com.state == RES_XRCD_BUSY)
  577. return -EBUSY;
  578. else if (res->com.state != RES_XRCD_ALLOCATED)
  579. return -EPERM;
  580. return 0;
  581. }
  582. static int remove_fs_rule_ok(struct res_fs_rule *res)
  583. {
  584. if (res->com.state == RES_FS_RULE_BUSY)
  585. return -EBUSY;
  586. else if (res->com.state != RES_FS_RULE_ALLOCATED)
  587. return -EPERM;
  588. return 0;
  589. }
  590. static int remove_cq_ok(struct res_cq *res)
  591. {
  592. if (res->com.state == RES_CQ_BUSY)
  593. return -EBUSY;
  594. else if (res->com.state != RES_CQ_ALLOCATED)
  595. return -EPERM;
  596. return 0;
  597. }
  598. static int remove_srq_ok(struct res_srq *res)
  599. {
  600. if (res->com.state == RES_SRQ_BUSY)
  601. return -EBUSY;
  602. else if (res->com.state != RES_SRQ_ALLOCATED)
  603. return -EPERM;
  604. return 0;
  605. }
  606. static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
  607. {
  608. switch (type) {
  609. case RES_QP:
  610. return remove_qp_ok((struct res_qp *)res);
  611. case RES_CQ:
  612. return remove_cq_ok((struct res_cq *)res);
  613. case RES_SRQ:
  614. return remove_srq_ok((struct res_srq *)res);
  615. case RES_MPT:
  616. return remove_mpt_ok((struct res_mpt *)res);
  617. case RES_MTT:
  618. return remove_mtt_ok((struct res_mtt *)res, extra);
  619. case RES_MAC:
  620. return -ENOSYS;
  621. case RES_EQ:
  622. return remove_eq_ok((struct res_eq *)res);
  623. case RES_COUNTER:
  624. return remove_counter_ok((struct res_counter *)res);
  625. case RES_XRCD:
  626. return remove_xrcdn_ok((struct res_xrcdn *)res);
  627. case RES_FS_RULE:
  628. return remove_fs_rule_ok((struct res_fs_rule *)res);
  629. default:
  630. return -EINVAL;
  631. }
  632. }
  633. static int rem_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
  634. enum mlx4_resource type, int extra)
  635. {
  636. u64 i;
  637. int err;
  638. struct mlx4_priv *priv = mlx4_priv(dev);
  639. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  640. struct res_common *r;
  641. spin_lock_irq(mlx4_tlock(dev));
  642. for (i = base; i < base + count; ++i) {
  643. r = res_tracker_lookup(&tracker->res_tree[type], i);
  644. if (!r) {
  645. err = -ENOENT;
  646. goto out;
  647. }
  648. if (r->owner != slave) {
  649. err = -EPERM;
  650. goto out;
  651. }
  652. err = remove_ok(r, type, extra);
  653. if (err)
  654. goto out;
  655. }
  656. for (i = base; i < base + count; ++i) {
  657. r = res_tracker_lookup(&tracker->res_tree[type], i);
  658. rb_erase(&r->node, &tracker->res_tree[type]);
  659. list_del(&r->list);
  660. kfree(r);
  661. }
  662. err = 0;
  663. out:
  664. spin_unlock_irq(mlx4_tlock(dev));
  665. return err;
  666. }
  667. static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
  668. enum res_qp_states state, struct res_qp **qp,
  669. int alloc)
  670. {
  671. struct mlx4_priv *priv = mlx4_priv(dev);
  672. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  673. struct res_qp *r;
  674. int err = 0;
  675. spin_lock_irq(mlx4_tlock(dev));
  676. r = res_tracker_lookup(&tracker->res_tree[RES_QP], qpn);
  677. if (!r)
  678. err = -ENOENT;
  679. else if (r->com.owner != slave)
  680. err = -EPERM;
  681. else {
  682. switch (state) {
  683. case RES_QP_BUSY:
  684. mlx4_dbg(dev, "%s: failed RES_QP, 0x%llx\n",
  685. __func__, r->com.res_id);
  686. err = -EBUSY;
  687. break;
  688. case RES_QP_RESERVED:
  689. if (r->com.state == RES_QP_MAPPED && !alloc)
  690. break;
  691. mlx4_dbg(dev, "failed RES_QP, 0x%llx\n", r->com.res_id);
  692. err = -EINVAL;
  693. break;
  694. case RES_QP_MAPPED:
  695. if ((r->com.state == RES_QP_RESERVED && alloc) ||
  696. r->com.state == RES_QP_HW)
  697. break;
  698. else {
  699. mlx4_dbg(dev, "failed RES_QP, 0x%llx\n",
  700. r->com.res_id);
  701. err = -EINVAL;
  702. }
  703. break;
  704. case RES_QP_HW:
  705. if (r->com.state != RES_QP_MAPPED)
  706. err = -EINVAL;
  707. break;
  708. default:
  709. err = -EINVAL;
  710. }
  711. if (!err) {
  712. r->com.from_state = r->com.state;
  713. r->com.to_state = state;
  714. r->com.state = RES_QP_BUSY;
  715. if (qp)
  716. *qp = r;
  717. }
  718. }
  719. spin_unlock_irq(mlx4_tlock(dev));
  720. return err;
  721. }
  722. static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  723. enum res_mpt_states state, struct res_mpt **mpt)
  724. {
  725. struct mlx4_priv *priv = mlx4_priv(dev);
  726. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  727. struct res_mpt *r;
  728. int err = 0;
  729. spin_lock_irq(mlx4_tlock(dev));
  730. r = res_tracker_lookup(&tracker->res_tree[RES_MPT], index);
  731. if (!r)
  732. err = -ENOENT;
  733. else if (r->com.owner != slave)
  734. err = -EPERM;
  735. else {
  736. switch (state) {
  737. case RES_MPT_BUSY:
  738. err = -EINVAL;
  739. break;
  740. case RES_MPT_RESERVED:
  741. if (r->com.state != RES_MPT_MAPPED)
  742. err = -EINVAL;
  743. break;
  744. case RES_MPT_MAPPED:
  745. if (r->com.state != RES_MPT_RESERVED &&
  746. r->com.state != RES_MPT_HW)
  747. err = -EINVAL;
  748. break;
  749. case RES_MPT_HW:
  750. if (r->com.state != RES_MPT_MAPPED)
  751. err = -EINVAL;
  752. break;
  753. default:
  754. err = -EINVAL;
  755. }
  756. if (!err) {
  757. r->com.from_state = r->com.state;
  758. r->com.to_state = state;
  759. r->com.state = RES_MPT_BUSY;
  760. if (mpt)
  761. *mpt = r;
  762. }
  763. }
  764. spin_unlock_irq(mlx4_tlock(dev));
  765. return err;
  766. }
  767. static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  768. enum res_eq_states state, struct res_eq **eq)
  769. {
  770. struct mlx4_priv *priv = mlx4_priv(dev);
  771. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  772. struct res_eq *r;
  773. int err = 0;
  774. spin_lock_irq(mlx4_tlock(dev));
  775. r = res_tracker_lookup(&tracker->res_tree[RES_EQ], index);
  776. if (!r)
  777. err = -ENOENT;
  778. else if (r->com.owner != slave)
  779. err = -EPERM;
  780. else {
  781. switch (state) {
  782. case RES_EQ_BUSY:
  783. err = -EINVAL;
  784. break;
  785. case RES_EQ_RESERVED:
  786. if (r->com.state != RES_EQ_HW)
  787. err = -EINVAL;
  788. break;
  789. case RES_EQ_HW:
  790. if (r->com.state != RES_EQ_RESERVED)
  791. err = -EINVAL;
  792. break;
  793. default:
  794. err = -EINVAL;
  795. }
  796. if (!err) {
  797. r->com.from_state = r->com.state;
  798. r->com.to_state = state;
  799. r->com.state = RES_EQ_BUSY;
  800. if (eq)
  801. *eq = r;
  802. }
  803. }
  804. spin_unlock_irq(mlx4_tlock(dev));
  805. return err;
  806. }
  807. static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
  808. enum res_cq_states state, struct res_cq **cq)
  809. {
  810. struct mlx4_priv *priv = mlx4_priv(dev);
  811. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  812. struct res_cq *r;
  813. int err;
  814. spin_lock_irq(mlx4_tlock(dev));
  815. r = res_tracker_lookup(&tracker->res_tree[RES_CQ], cqn);
  816. if (!r)
  817. err = -ENOENT;
  818. else if (r->com.owner != slave)
  819. err = -EPERM;
  820. else {
  821. switch (state) {
  822. case RES_CQ_BUSY:
  823. err = -EBUSY;
  824. break;
  825. case RES_CQ_ALLOCATED:
  826. if (r->com.state != RES_CQ_HW)
  827. err = -EINVAL;
  828. else if (atomic_read(&r->ref_count))
  829. err = -EBUSY;
  830. else
  831. err = 0;
  832. break;
  833. case RES_CQ_HW:
  834. if (r->com.state != RES_CQ_ALLOCATED)
  835. err = -EINVAL;
  836. else
  837. err = 0;
  838. break;
  839. default:
  840. err = -EINVAL;
  841. }
  842. if (!err) {
  843. r->com.from_state = r->com.state;
  844. r->com.to_state = state;
  845. r->com.state = RES_CQ_BUSY;
  846. if (cq)
  847. *cq = r;
  848. }
  849. }
  850. spin_unlock_irq(mlx4_tlock(dev));
  851. return err;
  852. }
  853. static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  854. enum res_cq_states state, struct res_srq **srq)
  855. {
  856. struct mlx4_priv *priv = mlx4_priv(dev);
  857. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  858. struct res_srq *r;
  859. int err = 0;
  860. spin_lock_irq(mlx4_tlock(dev));
  861. r = res_tracker_lookup(&tracker->res_tree[RES_SRQ], index);
  862. if (!r)
  863. err = -ENOENT;
  864. else if (r->com.owner != slave)
  865. err = -EPERM;
  866. else {
  867. switch (state) {
  868. case RES_SRQ_BUSY:
  869. err = -EINVAL;
  870. break;
  871. case RES_SRQ_ALLOCATED:
  872. if (r->com.state != RES_SRQ_HW)
  873. err = -EINVAL;
  874. else if (atomic_read(&r->ref_count))
  875. err = -EBUSY;
  876. break;
  877. case RES_SRQ_HW:
  878. if (r->com.state != RES_SRQ_ALLOCATED)
  879. err = -EINVAL;
  880. break;
  881. default:
  882. err = -EINVAL;
  883. }
  884. if (!err) {
  885. r->com.from_state = r->com.state;
  886. r->com.to_state = state;
  887. r->com.state = RES_SRQ_BUSY;
  888. if (srq)
  889. *srq = r;
  890. }
  891. }
  892. spin_unlock_irq(mlx4_tlock(dev));
  893. return err;
  894. }
  895. static void res_abort_move(struct mlx4_dev *dev, int slave,
  896. enum mlx4_resource type, int id)
  897. {
  898. struct mlx4_priv *priv = mlx4_priv(dev);
  899. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  900. struct res_common *r;
  901. spin_lock_irq(mlx4_tlock(dev));
  902. r = res_tracker_lookup(&tracker->res_tree[type], id);
  903. if (r && (r->owner == slave))
  904. r->state = r->from_state;
  905. spin_unlock_irq(mlx4_tlock(dev));
  906. }
  907. static void res_end_move(struct mlx4_dev *dev, int slave,
  908. enum mlx4_resource type, int id)
  909. {
  910. struct mlx4_priv *priv = mlx4_priv(dev);
  911. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  912. struct res_common *r;
  913. spin_lock_irq(mlx4_tlock(dev));
  914. r = res_tracker_lookup(&tracker->res_tree[type], id);
  915. if (r && (r->owner == slave))
  916. r->state = r->to_state;
  917. spin_unlock_irq(mlx4_tlock(dev));
  918. }
  919. static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
  920. {
  921. return mlx4_is_qp_reserved(dev, qpn);
  922. }
  923. static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  924. u64 in_param, u64 *out_param)
  925. {
  926. int err;
  927. int count;
  928. int align;
  929. int base;
  930. int qpn;
  931. switch (op) {
  932. case RES_OP_RESERVE:
  933. count = get_param_l(&in_param);
  934. align = get_param_h(&in_param);
  935. err = __mlx4_qp_reserve_range(dev, count, align, &base);
  936. if (err)
  937. return err;
  938. err = add_res_range(dev, slave, base, count, RES_QP, 0);
  939. if (err) {
  940. __mlx4_qp_release_range(dev, base, count);
  941. return err;
  942. }
  943. set_param_l(out_param, base);
  944. break;
  945. case RES_OP_MAP_ICM:
  946. qpn = get_param_l(&in_param) & 0x7fffff;
  947. if (valid_reserved(dev, slave, qpn)) {
  948. err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
  949. if (err)
  950. return err;
  951. }
  952. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
  953. NULL, 1);
  954. if (err)
  955. return err;
  956. if (!valid_reserved(dev, slave, qpn)) {
  957. err = __mlx4_qp_alloc_icm(dev, qpn);
  958. if (err) {
  959. res_abort_move(dev, slave, RES_QP, qpn);
  960. return err;
  961. }
  962. }
  963. res_end_move(dev, slave, RES_QP, qpn);
  964. break;
  965. default:
  966. err = -EINVAL;
  967. break;
  968. }
  969. return err;
  970. }
  971. static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  972. u64 in_param, u64 *out_param)
  973. {
  974. int err = -EINVAL;
  975. int base;
  976. int order;
  977. if (op != RES_OP_RESERVE_AND_MAP)
  978. return err;
  979. order = get_param_l(&in_param);
  980. base = __mlx4_alloc_mtt_range(dev, order);
  981. if (base == -1)
  982. return -ENOMEM;
  983. err = add_res_range(dev, slave, base, 1, RES_MTT, order);
  984. if (err)
  985. __mlx4_free_mtt_range(dev, base, order);
  986. else
  987. set_param_l(out_param, base);
  988. return err;
  989. }
  990. static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  991. u64 in_param, u64 *out_param)
  992. {
  993. int err = -EINVAL;
  994. int index;
  995. int id;
  996. struct res_mpt *mpt;
  997. switch (op) {
  998. case RES_OP_RESERVE:
  999. index = __mlx4_mr_reserve(dev);
  1000. if (index == -1)
  1001. break;
  1002. id = index & mpt_mask(dev);
  1003. err = add_res_range(dev, slave, id, 1, RES_MPT, index);
  1004. if (err) {
  1005. __mlx4_mr_release(dev, index);
  1006. break;
  1007. }
  1008. set_param_l(out_param, index);
  1009. break;
  1010. case RES_OP_MAP_ICM:
  1011. index = get_param_l(&in_param);
  1012. id = index & mpt_mask(dev);
  1013. err = mr_res_start_move_to(dev, slave, id,
  1014. RES_MPT_MAPPED, &mpt);
  1015. if (err)
  1016. return err;
  1017. err = __mlx4_mr_alloc_icm(dev, mpt->key);
  1018. if (err) {
  1019. res_abort_move(dev, slave, RES_MPT, id);
  1020. return err;
  1021. }
  1022. res_end_move(dev, slave, RES_MPT, id);
  1023. break;
  1024. }
  1025. return err;
  1026. }
  1027. static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1028. u64 in_param, u64 *out_param)
  1029. {
  1030. int cqn;
  1031. int err;
  1032. switch (op) {
  1033. case RES_OP_RESERVE_AND_MAP:
  1034. err = __mlx4_cq_alloc_icm(dev, &cqn);
  1035. if (err)
  1036. break;
  1037. err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1038. if (err) {
  1039. __mlx4_cq_free_icm(dev, cqn);
  1040. break;
  1041. }
  1042. set_param_l(out_param, cqn);
  1043. break;
  1044. default:
  1045. err = -EINVAL;
  1046. }
  1047. return err;
  1048. }
  1049. static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1050. u64 in_param, u64 *out_param)
  1051. {
  1052. int srqn;
  1053. int err;
  1054. switch (op) {
  1055. case RES_OP_RESERVE_AND_MAP:
  1056. err = __mlx4_srq_alloc_icm(dev, &srqn);
  1057. if (err)
  1058. break;
  1059. err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1060. if (err) {
  1061. __mlx4_srq_free_icm(dev, srqn);
  1062. break;
  1063. }
  1064. set_param_l(out_param, srqn);
  1065. break;
  1066. default:
  1067. err = -EINVAL;
  1068. }
  1069. return err;
  1070. }
  1071. static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port)
  1072. {
  1073. struct mlx4_priv *priv = mlx4_priv(dev);
  1074. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1075. struct mac_res *res;
  1076. res = kzalloc(sizeof *res, GFP_KERNEL);
  1077. if (!res)
  1078. return -ENOMEM;
  1079. res->mac = mac;
  1080. res->port = (u8) port;
  1081. list_add_tail(&res->list,
  1082. &tracker->slave_list[slave].res_list[RES_MAC]);
  1083. return 0;
  1084. }
  1085. static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
  1086. int port)
  1087. {
  1088. struct mlx4_priv *priv = mlx4_priv(dev);
  1089. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1090. struct list_head *mac_list =
  1091. &tracker->slave_list[slave].res_list[RES_MAC];
  1092. struct mac_res *res, *tmp;
  1093. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1094. if (res->mac == mac && res->port == (u8) port) {
  1095. list_del(&res->list);
  1096. kfree(res);
  1097. break;
  1098. }
  1099. }
  1100. }
  1101. static void rem_slave_macs(struct mlx4_dev *dev, int slave)
  1102. {
  1103. struct mlx4_priv *priv = mlx4_priv(dev);
  1104. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1105. struct list_head *mac_list =
  1106. &tracker->slave_list[slave].res_list[RES_MAC];
  1107. struct mac_res *res, *tmp;
  1108. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1109. list_del(&res->list);
  1110. __mlx4_unregister_mac(dev, res->port, res->mac);
  1111. kfree(res);
  1112. }
  1113. }
  1114. static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1115. u64 in_param, u64 *out_param)
  1116. {
  1117. int err = -EINVAL;
  1118. int port;
  1119. u64 mac;
  1120. if (op != RES_OP_RESERVE_AND_MAP)
  1121. return err;
  1122. port = get_param_l(out_param);
  1123. mac = in_param;
  1124. err = __mlx4_register_mac(dev, port, mac);
  1125. if (err >= 0) {
  1126. set_param_l(out_param, err);
  1127. err = 0;
  1128. }
  1129. if (!err) {
  1130. err = mac_add_to_slave(dev, slave, mac, port);
  1131. if (err)
  1132. __mlx4_unregister_mac(dev, port, mac);
  1133. }
  1134. return err;
  1135. }
  1136. static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1137. u64 in_param, u64 *out_param)
  1138. {
  1139. return 0;
  1140. }
  1141. static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1142. u64 in_param, u64 *out_param)
  1143. {
  1144. u32 index;
  1145. int err;
  1146. if (op != RES_OP_RESERVE)
  1147. return -EINVAL;
  1148. err = __mlx4_counter_alloc(dev, &index);
  1149. if (err)
  1150. return err;
  1151. err = add_res_range(dev, slave, index, 1, RES_COUNTER, 0);
  1152. if (err)
  1153. __mlx4_counter_free(dev, index);
  1154. else
  1155. set_param_l(out_param, index);
  1156. return err;
  1157. }
  1158. static int xrcdn_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1159. u64 in_param, u64 *out_param)
  1160. {
  1161. u32 xrcdn;
  1162. int err;
  1163. if (op != RES_OP_RESERVE)
  1164. return -EINVAL;
  1165. err = __mlx4_xrcd_alloc(dev, &xrcdn);
  1166. if (err)
  1167. return err;
  1168. err = add_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
  1169. if (err)
  1170. __mlx4_xrcd_free(dev, xrcdn);
  1171. else
  1172. set_param_l(out_param, xrcdn);
  1173. return err;
  1174. }
  1175. int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
  1176. struct mlx4_vhcr *vhcr,
  1177. struct mlx4_cmd_mailbox *inbox,
  1178. struct mlx4_cmd_mailbox *outbox,
  1179. struct mlx4_cmd_info *cmd)
  1180. {
  1181. int err;
  1182. int alop = vhcr->op_modifier;
  1183. switch (vhcr->in_modifier) {
  1184. case RES_QP:
  1185. err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1186. vhcr->in_param, &vhcr->out_param);
  1187. break;
  1188. case RES_MTT:
  1189. err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1190. vhcr->in_param, &vhcr->out_param);
  1191. break;
  1192. case RES_MPT:
  1193. err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1194. vhcr->in_param, &vhcr->out_param);
  1195. break;
  1196. case RES_CQ:
  1197. err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1198. vhcr->in_param, &vhcr->out_param);
  1199. break;
  1200. case RES_SRQ:
  1201. err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1202. vhcr->in_param, &vhcr->out_param);
  1203. break;
  1204. case RES_MAC:
  1205. err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1206. vhcr->in_param, &vhcr->out_param);
  1207. break;
  1208. case RES_VLAN:
  1209. err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1210. vhcr->in_param, &vhcr->out_param);
  1211. break;
  1212. case RES_COUNTER:
  1213. err = counter_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1214. vhcr->in_param, &vhcr->out_param);
  1215. break;
  1216. case RES_XRCD:
  1217. err = xrcdn_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1218. vhcr->in_param, &vhcr->out_param);
  1219. break;
  1220. default:
  1221. err = -EINVAL;
  1222. break;
  1223. }
  1224. return err;
  1225. }
  1226. static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1227. u64 in_param)
  1228. {
  1229. int err;
  1230. int count;
  1231. int base;
  1232. int qpn;
  1233. switch (op) {
  1234. case RES_OP_RESERVE:
  1235. base = get_param_l(&in_param) & 0x7fffff;
  1236. count = get_param_h(&in_param);
  1237. err = rem_res_range(dev, slave, base, count, RES_QP, 0);
  1238. if (err)
  1239. break;
  1240. __mlx4_qp_release_range(dev, base, count);
  1241. break;
  1242. case RES_OP_MAP_ICM:
  1243. qpn = get_param_l(&in_param) & 0x7fffff;
  1244. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
  1245. NULL, 0);
  1246. if (err)
  1247. return err;
  1248. if (!valid_reserved(dev, slave, qpn))
  1249. __mlx4_qp_free_icm(dev, qpn);
  1250. res_end_move(dev, slave, RES_QP, qpn);
  1251. if (valid_reserved(dev, slave, qpn))
  1252. err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
  1253. break;
  1254. default:
  1255. err = -EINVAL;
  1256. break;
  1257. }
  1258. return err;
  1259. }
  1260. static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1261. u64 in_param, u64 *out_param)
  1262. {
  1263. int err = -EINVAL;
  1264. int base;
  1265. int order;
  1266. if (op != RES_OP_RESERVE_AND_MAP)
  1267. return err;
  1268. base = get_param_l(&in_param);
  1269. order = get_param_h(&in_param);
  1270. err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
  1271. if (!err)
  1272. __mlx4_free_mtt_range(dev, base, order);
  1273. return err;
  1274. }
  1275. static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1276. u64 in_param)
  1277. {
  1278. int err = -EINVAL;
  1279. int index;
  1280. int id;
  1281. struct res_mpt *mpt;
  1282. switch (op) {
  1283. case RES_OP_RESERVE:
  1284. index = get_param_l(&in_param);
  1285. id = index & mpt_mask(dev);
  1286. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1287. if (err)
  1288. break;
  1289. index = mpt->key;
  1290. put_res(dev, slave, id, RES_MPT);
  1291. err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
  1292. if (err)
  1293. break;
  1294. __mlx4_mr_release(dev, index);
  1295. break;
  1296. case RES_OP_MAP_ICM:
  1297. index = get_param_l(&in_param);
  1298. id = index & mpt_mask(dev);
  1299. err = mr_res_start_move_to(dev, slave, id,
  1300. RES_MPT_RESERVED, &mpt);
  1301. if (err)
  1302. return err;
  1303. __mlx4_mr_free_icm(dev, mpt->key);
  1304. res_end_move(dev, slave, RES_MPT, id);
  1305. return err;
  1306. break;
  1307. default:
  1308. err = -EINVAL;
  1309. break;
  1310. }
  1311. return err;
  1312. }
  1313. static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1314. u64 in_param, u64 *out_param)
  1315. {
  1316. int cqn;
  1317. int err;
  1318. switch (op) {
  1319. case RES_OP_RESERVE_AND_MAP:
  1320. cqn = get_param_l(&in_param);
  1321. err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1322. if (err)
  1323. break;
  1324. __mlx4_cq_free_icm(dev, cqn);
  1325. break;
  1326. default:
  1327. err = -EINVAL;
  1328. break;
  1329. }
  1330. return err;
  1331. }
  1332. static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1333. u64 in_param, u64 *out_param)
  1334. {
  1335. int srqn;
  1336. int err;
  1337. switch (op) {
  1338. case RES_OP_RESERVE_AND_MAP:
  1339. srqn = get_param_l(&in_param);
  1340. err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1341. if (err)
  1342. break;
  1343. __mlx4_srq_free_icm(dev, srqn);
  1344. break;
  1345. default:
  1346. err = -EINVAL;
  1347. break;
  1348. }
  1349. return err;
  1350. }
  1351. static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1352. u64 in_param, u64 *out_param)
  1353. {
  1354. int port;
  1355. int err = 0;
  1356. switch (op) {
  1357. case RES_OP_RESERVE_AND_MAP:
  1358. port = get_param_l(out_param);
  1359. mac_del_from_slave(dev, slave, in_param, port);
  1360. __mlx4_unregister_mac(dev, port, in_param);
  1361. break;
  1362. default:
  1363. err = -EINVAL;
  1364. break;
  1365. }
  1366. return err;
  1367. }
  1368. static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1369. u64 in_param, u64 *out_param)
  1370. {
  1371. return 0;
  1372. }
  1373. static int counter_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1374. u64 in_param, u64 *out_param)
  1375. {
  1376. int index;
  1377. int err;
  1378. if (op != RES_OP_RESERVE)
  1379. return -EINVAL;
  1380. index = get_param_l(&in_param);
  1381. err = rem_res_range(dev, slave, index, 1, RES_COUNTER, 0);
  1382. if (err)
  1383. return err;
  1384. __mlx4_counter_free(dev, index);
  1385. return err;
  1386. }
  1387. static int xrcdn_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1388. u64 in_param, u64 *out_param)
  1389. {
  1390. int xrcdn;
  1391. int err;
  1392. if (op != RES_OP_RESERVE)
  1393. return -EINVAL;
  1394. xrcdn = get_param_l(&in_param);
  1395. err = rem_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
  1396. if (err)
  1397. return err;
  1398. __mlx4_xrcd_free(dev, xrcdn);
  1399. return err;
  1400. }
  1401. int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
  1402. struct mlx4_vhcr *vhcr,
  1403. struct mlx4_cmd_mailbox *inbox,
  1404. struct mlx4_cmd_mailbox *outbox,
  1405. struct mlx4_cmd_info *cmd)
  1406. {
  1407. int err = -EINVAL;
  1408. int alop = vhcr->op_modifier;
  1409. switch (vhcr->in_modifier) {
  1410. case RES_QP:
  1411. err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
  1412. vhcr->in_param);
  1413. break;
  1414. case RES_MTT:
  1415. err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
  1416. vhcr->in_param, &vhcr->out_param);
  1417. break;
  1418. case RES_MPT:
  1419. err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
  1420. vhcr->in_param);
  1421. break;
  1422. case RES_CQ:
  1423. err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
  1424. vhcr->in_param, &vhcr->out_param);
  1425. break;
  1426. case RES_SRQ:
  1427. err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
  1428. vhcr->in_param, &vhcr->out_param);
  1429. break;
  1430. case RES_MAC:
  1431. err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
  1432. vhcr->in_param, &vhcr->out_param);
  1433. break;
  1434. case RES_VLAN:
  1435. err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
  1436. vhcr->in_param, &vhcr->out_param);
  1437. break;
  1438. case RES_COUNTER:
  1439. err = counter_free_res(dev, slave, vhcr->op_modifier, alop,
  1440. vhcr->in_param, &vhcr->out_param);
  1441. break;
  1442. case RES_XRCD:
  1443. err = xrcdn_free_res(dev, slave, vhcr->op_modifier, alop,
  1444. vhcr->in_param, &vhcr->out_param);
  1445. default:
  1446. break;
  1447. }
  1448. return err;
  1449. }
  1450. /* ugly but other choices are uglier */
  1451. static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
  1452. {
  1453. return (be32_to_cpu(mpt->flags) >> 9) & 1;
  1454. }
  1455. static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
  1456. {
  1457. return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
  1458. }
  1459. static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
  1460. {
  1461. return be32_to_cpu(mpt->mtt_sz);
  1462. }
  1463. static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
  1464. {
  1465. return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
  1466. }
  1467. static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
  1468. {
  1469. return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
  1470. }
  1471. static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
  1472. {
  1473. int page_shift = (qpc->log_page_size & 0x3f) + 12;
  1474. int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
  1475. int log_sq_sride = qpc->sq_size_stride & 7;
  1476. int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
  1477. int log_rq_stride = qpc->rq_size_stride & 7;
  1478. int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
  1479. int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
  1480. int xrc = (be32_to_cpu(qpc->local_qpn) >> 23) & 1;
  1481. int sq_size;
  1482. int rq_size;
  1483. int total_pages;
  1484. int total_mem;
  1485. int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
  1486. sq_size = 1 << (log_sq_size + log_sq_sride + 4);
  1487. rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
  1488. total_mem = sq_size + rq_size;
  1489. total_pages =
  1490. roundup_pow_of_two((total_mem + (page_offset << 6)) >>
  1491. page_shift);
  1492. return total_pages;
  1493. }
  1494. static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
  1495. int size, struct res_mtt *mtt)
  1496. {
  1497. int res_start = mtt->com.res_id;
  1498. int res_size = (1 << mtt->order);
  1499. if (start < res_start || start + size > res_start + res_size)
  1500. return -EPERM;
  1501. return 0;
  1502. }
  1503. int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1504. struct mlx4_vhcr *vhcr,
  1505. struct mlx4_cmd_mailbox *inbox,
  1506. struct mlx4_cmd_mailbox *outbox,
  1507. struct mlx4_cmd_info *cmd)
  1508. {
  1509. int err;
  1510. int index = vhcr->in_modifier;
  1511. struct res_mtt *mtt;
  1512. struct res_mpt *mpt;
  1513. int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
  1514. int phys;
  1515. int id;
  1516. id = index & mpt_mask(dev);
  1517. err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
  1518. if (err)
  1519. return err;
  1520. phys = mr_phys_mpt(inbox->buf);
  1521. if (!phys) {
  1522. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1523. if (err)
  1524. goto ex_abort;
  1525. err = check_mtt_range(dev, slave, mtt_base,
  1526. mr_get_mtt_size(inbox->buf), mtt);
  1527. if (err)
  1528. goto ex_put;
  1529. mpt->mtt = mtt;
  1530. }
  1531. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1532. if (err)
  1533. goto ex_put;
  1534. if (!phys) {
  1535. atomic_inc(&mtt->ref_count);
  1536. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1537. }
  1538. res_end_move(dev, slave, RES_MPT, id);
  1539. return 0;
  1540. ex_put:
  1541. if (!phys)
  1542. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1543. ex_abort:
  1544. res_abort_move(dev, slave, RES_MPT, id);
  1545. return err;
  1546. }
  1547. int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1548. struct mlx4_vhcr *vhcr,
  1549. struct mlx4_cmd_mailbox *inbox,
  1550. struct mlx4_cmd_mailbox *outbox,
  1551. struct mlx4_cmd_info *cmd)
  1552. {
  1553. int err;
  1554. int index = vhcr->in_modifier;
  1555. struct res_mpt *mpt;
  1556. int id;
  1557. id = index & mpt_mask(dev);
  1558. err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
  1559. if (err)
  1560. return err;
  1561. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1562. if (err)
  1563. goto ex_abort;
  1564. if (mpt->mtt)
  1565. atomic_dec(&mpt->mtt->ref_count);
  1566. res_end_move(dev, slave, RES_MPT, id);
  1567. return 0;
  1568. ex_abort:
  1569. res_abort_move(dev, slave, RES_MPT, id);
  1570. return err;
  1571. }
  1572. int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1573. struct mlx4_vhcr *vhcr,
  1574. struct mlx4_cmd_mailbox *inbox,
  1575. struct mlx4_cmd_mailbox *outbox,
  1576. struct mlx4_cmd_info *cmd)
  1577. {
  1578. int err;
  1579. int index = vhcr->in_modifier;
  1580. struct res_mpt *mpt;
  1581. int id;
  1582. id = index & mpt_mask(dev);
  1583. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1584. if (err)
  1585. return err;
  1586. if (mpt->com.from_state != RES_MPT_HW) {
  1587. err = -EBUSY;
  1588. goto out;
  1589. }
  1590. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1591. out:
  1592. put_res(dev, slave, id, RES_MPT);
  1593. return err;
  1594. }
  1595. static int qp_get_rcqn(struct mlx4_qp_context *qpc)
  1596. {
  1597. return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
  1598. }
  1599. static int qp_get_scqn(struct mlx4_qp_context *qpc)
  1600. {
  1601. return be32_to_cpu(qpc->cqn_send) & 0xffffff;
  1602. }
  1603. static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
  1604. {
  1605. return be32_to_cpu(qpc->srqn) & 0x1ffffff;
  1606. }
  1607. int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
  1608. struct mlx4_vhcr *vhcr,
  1609. struct mlx4_cmd_mailbox *inbox,
  1610. struct mlx4_cmd_mailbox *outbox,
  1611. struct mlx4_cmd_info *cmd)
  1612. {
  1613. int err;
  1614. int qpn = vhcr->in_modifier & 0x7fffff;
  1615. struct res_mtt *mtt;
  1616. struct res_qp *qp;
  1617. struct mlx4_qp_context *qpc = inbox->buf + 8;
  1618. int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
  1619. int mtt_size = qp_get_mtt_size(qpc);
  1620. struct res_cq *rcq;
  1621. struct res_cq *scq;
  1622. int rcqn = qp_get_rcqn(qpc);
  1623. int scqn = qp_get_scqn(qpc);
  1624. u32 srqn = qp_get_srqn(qpc) & 0xffffff;
  1625. int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
  1626. struct res_srq *srq;
  1627. int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff;
  1628. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
  1629. if (err)
  1630. return err;
  1631. qp->local_qpn = local_qpn;
  1632. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1633. if (err)
  1634. goto ex_abort;
  1635. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  1636. if (err)
  1637. goto ex_put_mtt;
  1638. err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
  1639. if (err)
  1640. goto ex_put_mtt;
  1641. if (scqn != rcqn) {
  1642. err = get_res(dev, slave, scqn, RES_CQ, &scq);
  1643. if (err)
  1644. goto ex_put_rcq;
  1645. } else
  1646. scq = rcq;
  1647. if (use_srq) {
  1648. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  1649. if (err)
  1650. goto ex_put_scq;
  1651. }
  1652. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1653. if (err)
  1654. goto ex_put_srq;
  1655. atomic_inc(&mtt->ref_count);
  1656. qp->mtt = mtt;
  1657. atomic_inc(&rcq->ref_count);
  1658. qp->rcq = rcq;
  1659. atomic_inc(&scq->ref_count);
  1660. qp->scq = scq;
  1661. if (scqn != rcqn)
  1662. put_res(dev, slave, scqn, RES_CQ);
  1663. if (use_srq) {
  1664. atomic_inc(&srq->ref_count);
  1665. put_res(dev, slave, srqn, RES_SRQ);
  1666. qp->srq = srq;
  1667. }
  1668. put_res(dev, slave, rcqn, RES_CQ);
  1669. put_res(dev, slave, mtt_base, RES_MTT);
  1670. res_end_move(dev, slave, RES_QP, qpn);
  1671. return 0;
  1672. ex_put_srq:
  1673. if (use_srq)
  1674. put_res(dev, slave, srqn, RES_SRQ);
  1675. ex_put_scq:
  1676. if (scqn != rcqn)
  1677. put_res(dev, slave, scqn, RES_CQ);
  1678. ex_put_rcq:
  1679. put_res(dev, slave, rcqn, RES_CQ);
  1680. ex_put_mtt:
  1681. put_res(dev, slave, mtt_base, RES_MTT);
  1682. ex_abort:
  1683. res_abort_move(dev, slave, RES_QP, qpn);
  1684. return err;
  1685. }
  1686. static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
  1687. {
  1688. return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
  1689. }
  1690. static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
  1691. {
  1692. int log_eq_size = eqc->log_eq_size & 0x1f;
  1693. int page_shift = (eqc->log_page_size & 0x3f) + 12;
  1694. if (log_eq_size + 5 < page_shift)
  1695. return 1;
  1696. return 1 << (log_eq_size + 5 - page_shift);
  1697. }
  1698. static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
  1699. {
  1700. return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
  1701. }
  1702. static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
  1703. {
  1704. int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
  1705. int page_shift = (cqc->log_page_size & 0x3f) + 12;
  1706. if (log_cq_size + 5 < page_shift)
  1707. return 1;
  1708. return 1 << (log_cq_size + 5 - page_shift);
  1709. }
  1710. int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1711. struct mlx4_vhcr *vhcr,
  1712. struct mlx4_cmd_mailbox *inbox,
  1713. struct mlx4_cmd_mailbox *outbox,
  1714. struct mlx4_cmd_info *cmd)
  1715. {
  1716. int err;
  1717. int eqn = vhcr->in_modifier;
  1718. int res_id = (slave << 8) | eqn;
  1719. struct mlx4_eq_context *eqc = inbox->buf;
  1720. int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
  1721. int mtt_size = eq_get_mtt_size(eqc);
  1722. struct res_eq *eq;
  1723. struct res_mtt *mtt;
  1724. err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1725. if (err)
  1726. return err;
  1727. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
  1728. if (err)
  1729. goto out_add;
  1730. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1731. if (err)
  1732. goto out_move;
  1733. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  1734. if (err)
  1735. goto out_put;
  1736. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1737. if (err)
  1738. goto out_put;
  1739. atomic_inc(&mtt->ref_count);
  1740. eq->mtt = mtt;
  1741. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1742. res_end_move(dev, slave, RES_EQ, res_id);
  1743. return 0;
  1744. out_put:
  1745. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1746. out_move:
  1747. res_abort_move(dev, slave, RES_EQ, res_id);
  1748. out_add:
  1749. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1750. return err;
  1751. }
  1752. static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
  1753. int len, struct res_mtt **res)
  1754. {
  1755. struct mlx4_priv *priv = mlx4_priv(dev);
  1756. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1757. struct res_mtt *mtt;
  1758. int err = -EINVAL;
  1759. spin_lock_irq(mlx4_tlock(dev));
  1760. list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
  1761. com.list) {
  1762. if (!check_mtt_range(dev, slave, start, len, mtt)) {
  1763. *res = mtt;
  1764. mtt->com.from_state = mtt->com.state;
  1765. mtt->com.state = RES_MTT_BUSY;
  1766. err = 0;
  1767. break;
  1768. }
  1769. }
  1770. spin_unlock_irq(mlx4_tlock(dev));
  1771. return err;
  1772. }
  1773. int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
  1774. struct mlx4_vhcr *vhcr,
  1775. struct mlx4_cmd_mailbox *inbox,
  1776. struct mlx4_cmd_mailbox *outbox,
  1777. struct mlx4_cmd_info *cmd)
  1778. {
  1779. struct mlx4_mtt mtt;
  1780. __be64 *page_list = inbox->buf;
  1781. u64 *pg_list = (u64 *)page_list;
  1782. int i;
  1783. struct res_mtt *rmtt = NULL;
  1784. int start = be64_to_cpu(page_list[0]);
  1785. int npages = vhcr->in_modifier;
  1786. int err;
  1787. err = get_containing_mtt(dev, slave, start, npages, &rmtt);
  1788. if (err)
  1789. return err;
  1790. /* Call the SW implementation of write_mtt:
  1791. * - Prepare a dummy mtt struct
  1792. * - Translate inbox contents to simple addresses in host endianess */
  1793. mtt.offset = 0; /* TBD this is broken but I don't handle it since
  1794. we don't really use it */
  1795. mtt.order = 0;
  1796. mtt.page_shift = 0;
  1797. for (i = 0; i < npages; ++i)
  1798. pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
  1799. err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
  1800. ((u64 *)page_list + 2));
  1801. if (rmtt)
  1802. put_res(dev, slave, rmtt->com.res_id, RES_MTT);
  1803. return err;
  1804. }
  1805. int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1806. struct mlx4_vhcr *vhcr,
  1807. struct mlx4_cmd_mailbox *inbox,
  1808. struct mlx4_cmd_mailbox *outbox,
  1809. struct mlx4_cmd_info *cmd)
  1810. {
  1811. int eqn = vhcr->in_modifier;
  1812. int res_id = eqn | (slave << 8);
  1813. struct res_eq *eq;
  1814. int err;
  1815. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
  1816. if (err)
  1817. return err;
  1818. err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
  1819. if (err)
  1820. goto ex_abort;
  1821. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1822. if (err)
  1823. goto ex_put;
  1824. atomic_dec(&eq->mtt->ref_count);
  1825. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  1826. res_end_move(dev, slave, RES_EQ, res_id);
  1827. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1828. return 0;
  1829. ex_put:
  1830. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  1831. ex_abort:
  1832. res_abort_move(dev, slave, RES_EQ, res_id);
  1833. return err;
  1834. }
  1835. int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
  1836. {
  1837. struct mlx4_priv *priv = mlx4_priv(dev);
  1838. struct mlx4_slave_event_eq_info *event_eq;
  1839. struct mlx4_cmd_mailbox *mailbox;
  1840. u32 in_modifier = 0;
  1841. int err;
  1842. int res_id;
  1843. struct res_eq *req;
  1844. if (!priv->mfunc.master.slave_state)
  1845. return -EINVAL;
  1846. event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type];
  1847. /* Create the event only if the slave is registered */
  1848. if (event_eq->eqn < 0)
  1849. return 0;
  1850. mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1851. res_id = (slave << 8) | event_eq->eqn;
  1852. err = get_res(dev, slave, res_id, RES_EQ, &req);
  1853. if (err)
  1854. goto unlock;
  1855. if (req->com.from_state != RES_EQ_HW) {
  1856. err = -EINVAL;
  1857. goto put;
  1858. }
  1859. mailbox = mlx4_alloc_cmd_mailbox(dev);
  1860. if (IS_ERR(mailbox)) {
  1861. err = PTR_ERR(mailbox);
  1862. goto put;
  1863. }
  1864. if (eqe->type == MLX4_EVENT_TYPE_CMD) {
  1865. ++event_eq->token;
  1866. eqe->event.cmd.token = cpu_to_be16(event_eq->token);
  1867. }
  1868. memcpy(mailbox->buf, (u8 *) eqe, 28);
  1869. in_modifier = (slave & 0xff) | ((event_eq->eqn & 0xff) << 16);
  1870. err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
  1871. MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
  1872. MLX4_CMD_NATIVE);
  1873. put_res(dev, slave, res_id, RES_EQ);
  1874. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1875. mlx4_free_cmd_mailbox(dev, mailbox);
  1876. return err;
  1877. put:
  1878. put_res(dev, slave, res_id, RES_EQ);
  1879. unlock:
  1880. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1881. return err;
  1882. }
  1883. int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1884. struct mlx4_vhcr *vhcr,
  1885. struct mlx4_cmd_mailbox *inbox,
  1886. struct mlx4_cmd_mailbox *outbox,
  1887. struct mlx4_cmd_info *cmd)
  1888. {
  1889. int eqn = vhcr->in_modifier;
  1890. int res_id = eqn | (slave << 8);
  1891. struct res_eq *eq;
  1892. int err;
  1893. err = get_res(dev, slave, res_id, RES_EQ, &eq);
  1894. if (err)
  1895. return err;
  1896. if (eq->com.from_state != RES_EQ_HW) {
  1897. err = -EINVAL;
  1898. goto ex_put;
  1899. }
  1900. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1901. ex_put:
  1902. put_res(dev, slave, res_id, RES_EQ);
  1903. return err;
  1904. }
  1905. int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1906. struct mlx4_vhcr *vhcr,
  1907. struct mlx4_cmd_mailbox *inbox,
  1908. struct mlx4_cmd_mailbox *outbox,
  1909. struct mlx4_cmd_info *cmd)
  1910. {
  1911. int err;
  1912. int cqn = vhcr->in_modifier;
  1913. struct mlx4_cq_context *cqc = inbox->buf;
  1914. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  1915. struct res_cq *cq;
  1916. struct res_mtt *mtt;
  1917. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
  1918. if (err)
  1919. return err;
  1920. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1921. if (err)
  1922. goto out_move;
  1923. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  1924. if (err)
  1925. goto out_put;
  1926. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1927. if (err)
  1928. goto out_put;
  1929. atomic_inc(&mtt->ref_count);
  1930. cq->mtt = mtt;
  1931. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1932. res_end_move(dev, slave, RES_CQ, cqn);
  1933. return 0;
  1934. out_put:
  1935. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1936. out_move:
  1937. res_abort_move(dev, slave, RES_CQ, cqn);
  1938. return err;
  1939. }
  1940. int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1941. struct mlx4_vhcr *vhcr,
  1942. struct mlx4_cmd_mailbox *inbox,
  1943. struct mlx4_cmd_mailbox *outbox,
  1944. struct mlx4_cmd_info *cmd)
  1945. {
  1946. int err;
  1947. int cqn = vhcr->in_modifier;
  1948. struct res_cq *cq;
  1949. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
  1950. if (err)
  1951. return err;
  1952. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1953. if (err)
  1954. goto out_move;
  1955. atomic_dec(&cq->mtt->ref_count);
  1956. res_end_move(dev, slave, RES_CQ, cqn);
  1957. return 0;
  1958. out_move:
  1959. res_abort_move(dev, slave, RES_CQ, cqn);
  1960. return err;
  1961. }
  1962. int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1963. struct mlx4_vhcr *vhcr,
  1964. struct mlx4_cmd_mailbox *inbox,
  1965. struct mlx4_cmd_mailbox *outbox,
  1966. struct mlx4_cmd_info *cmd)
  1967. {
  1968. int cqn = vhcr->in_modifier;
  1969. struct res_cq *cq;
  1970. int err;
  1971. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  1972. if (err)
  1973. return err;
  1974. if (cq->com.from_state != RES_CQ_HW)
  1975. goto ex_put;
  1976. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1977. ex_put:
  1978. put_res(dev, slave, cqn, RES_CQ);
  1979. return err;
  1980. }
  1981. static int handle_resize(struct mlx4_dev *dev, int slave,
  1982. struct mlx4_vhcr *vhcr,
  1983. struct mlx4_cmd_mailbox *inbox,
  1984. struct mlx4_cmd_mailbox *outbox,
  1985. struct mlx4_cmd_info *cmd,
  1986. struct res_cq *cq)
  1987. {
  1988. int err;
  1989. struct res_mtt *orig_mtt;
  1990. struct res_mtt *mtt;
  1991. struct mlx4_cq_context *cqc = inbox->buf;
  1992. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  1993. err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
  1994. if (err)
  1995. return err;
  1996. if (orig_mtt != cq->mtt) {
  1997. err = -EINVAL;
  1998. goto ex_put;
  1999. }
  2000. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2001. if (err)
  2002. goto ex_put;
  2003. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  2004. if (err)
  2005. goto ex_put1;
  2006. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2007. if (err)
  2008. goto ex_put1;
  2009. atomic_dec(&orig_mtt->ref_count);
  2010. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  2011. atomic_inc(&mtt->ref_count);
  2012. cq->mtt = mtt;
  2013. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2014. return 0;
  2015. ex_put1:
  2016. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2017. ex_put:
  2018. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  2019. return err;
  2020. }
  2021. int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2022. struct mlx4_vhcr *vhcr,
  2023. struct mlx4_cmd_mailbox *inbox,
  2024. struct mlx4_cmd_mailbox *outbox,
  2025. struct mlx4_cmd_info *cmd)
  2026. {
  2027. int cqn = vhcr->in_modifier;
  2028. struct res_cq *cq;
  2029. int err;
  2030. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  2031. if (err)
  2032. return err;
  2033. if (cq->com.from_state != RES_CQ_HW)
  2034. goto ex_put;
  2035. if (vhcr->op_modifier == 0) {
  2036. err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
  2037. goto ex_put;
  2038. }
  2039. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2040. ex_put:
  2041. put_res(dev, slave, cqn, RES_CQ);
  2042. return err;
  2043. }
  2044. static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
  2045. {
  2046. int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
  2047. int log_rq_stride = srqc->logstride & 7;
  2048. int page_shift = (srqc->log_page_size & 0x3f) + 12;
  2049. if (log_srq_size + log_rq_stride + 4 < page_shift)
  2050. return 1;
  2051. return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
  2052. }
  2053. int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2054. struct mlx4_vhcr *vhcr,
  2055. struct mlx4_cmd_mailbox *inbox,
  2056. struct mlx4_cmd_mailbox *outbox,
  2057. struct mlx4_cmd_info *cmd)
  2058. {
  2059. int err;
  2060. int srqn = vhcr->in_modifier;
  2061. struct res_mtt *mtt;
  2062. struct res_srq *srq;
  2063. struct mlx4_srq_context *srqc = inbox->buf;
  2064. int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
  2065. if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
  2066. return -EINVAL;
  2067. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
  2068. if (err)
  2069. return err;
  2070. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2071. if (err)
  2072. goto ex_abort;
  2073. err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
  2074. mtt);
  2075. if (err)
  2076. goto ex_put_mtt;
  2077. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2078. if (err)
  2079. goto ex_put_mtt;
  2080. atomic_inc(&mtt->ref_count);
  2081. srq->mtt = mtt;
  2082. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2083. res_end_move(dev, slave, RES_SRQ, srqn);
  2084. return 0;
  2085. ex_put_mtt:
  2086. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2087. ex_abort:
  2088. res_abort_move(dev, slave, RES_SRQ, srqn);
  2089. return err;
  2090. }
  2091. int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2092. struct mlx4_vhcr *vhcr,
  2093. struct mlx4_cmd_mailbox *inbox,
  2094. struct mlx4_cmd_mailbox *outbox,
  2095. struct mlx4_cmd_info *cmd)
  2096. {
  2097. int err;
  2098. int srqn = vhcr->in_modifier;
  2099. struct res_srq *srq;
  2100. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
  2101. if (err)
  2102. return err;
  2103. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2104. if (err)
  2105. goto ex_abort;
  2106. atomic_dec(&srq->mtt->ref_count);
  2107. if (srq->cq)
  2108. atomic_dec(&srq->cq->ref_count);
  2109. res_end_move(dev, slave, RES_SRQ, srqn);
  2110. return 0;
  2111. ex_abort:
  2112. res_abort_move(dev, slave, RES_SRQ, srqn);
  2113. return err;
  2114. }
  2115. int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2116. struct mlx4_vhcr *vhcr,
  2117. struct mlx4_cmd_mailbox *inbox,
  2118. struct mlx4_cmd_mailbox *outbox,
  2119. struct mlx4_cmd_info *cmd)
  2120. {
  2121. int err;
  2122. int srqn = vhcr->in_modifier;
  2123. struct res_srq *srq;
  2124. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2125. if (err)
  2126. return err;
  2127. if (srq->com.from_state != RES_SRQ_HW) {
  2128. err = -EBUSY;
  2129. goto out;
  2130. }
  2131. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2132. out:
  2133. put_res(dev, slave, srqn, RES_SRQ);
  2134. return err;
  2135. }
  2136. int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2137. struct mlx4_vhcr *vhcr,
  2138. struct mlx4_cmd_mailbox *inbox,
  2139. struct mlx4_cmd_mailbox *outbox,
  2140. struct mlx4_cmd_info *cmd)
  2141. {
  2142. int err;
  2143. int srqn = vhcr->in_modifier;
  2144. struct res_srq *srq;
  2145. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2146. if (err)
  2147. return err;
  2148. if (srq->com.from_state != RES_SRQ_HW) {
  2149. err = -EBUSY;
  2150. goto out;
  2151. }
  2152. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2153. out:
  2154. put_res(dev, slave, srqn, RES_SRQ);
  2155. return err;
  2156. }
  2157. int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
  2158. struct mlx4_vhcr *vhcr,
  2159. struct mlx4_cmd_mailbox *inbox,
  2160. struct mlx4_cmd_mailbox *outbox,
  2161. struct mlx4_cmd_info *cmd)
  2162. {
  2163. int err;
  2164. int qpn = vhcr->in_modifier & 0x7fffff;
  2165. struct res_qp *qp;
  2166. err = get_res(dev, slave, qpn, RES_QP, &qp);
  2167. if (err)
  2168. return err;
  2169. if (qp->com.from_state != RES_QP_HW) {
  2170. err = -EBUSY;
  2171. goto out;
  2172. }
  2173. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2174. out:
  2175. put_res(dev, slave, qpn, RES_QP);
  2176. return err;
  2177. }
  2178. int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
  2179. struct mlx4_vhcr *vhcr,
  2180. struct mlx4_cmd_mailbox *inbox,
  2181. struct mlx4_cmd_mailbox *outbox,
  2182. struct mlx4_cmd_info *cmd)
  2183. {
  2184. struct mlx4_qp_context *qpc = inbox->buf + 8;
  2185. update_ud_gid(dev, qpc, (u8)slave);
  2186. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2187. }
  2188. int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
  2189. struct mlx4_vhcr *vhcr,
  2190. struct mlx4_cmd_mailbox *inbox,
  2191. struct mlx4_cmd_mailbox *outbox,
  2192. struct mlx4_cmd_info *cmd)
  2193. {
  2194. int err;
  2195. int qpn = vhcr->in_modifier & 0x7fffff;
  2196. struct res_qp *qp;
  2197. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
  2198. if (err)
  2199. return err;
  2200. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2201. if (err)
  2202. goto ex_abort;
  2203. atomic_dec(&qp->mtt->ref_count);
  2204. atomic_dec(&qp->rcq->ref_count);
  2205. atomic_dec(&qp->scq->ref_count);
  2206. if (qp->srq)
  2207. atomic_dec(&qp->srq->ref_count);
  2208. res_end_move(dev, slave, RES_QP, qpn);
  2209. return 0;
  2210. ex_abort:
  2211. res_abort_move(dev, slave, RES_QP, qpn);
  2212. return err;
  2213. }
  2214. static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
  2215. struct res_qp *rqp, u8 *gid)
  2216. {
  2217. struct res_gid *res;
  2218. list_for_each_entry(res, &rqp->mcg_list, list) {
  2219. if (!memcmp(res->gid, gid, 16))
  2220. return res;
  2221. }
  2222. return NULL;
  2223. }
  2224. static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2225. u8 *gid, enum mlx4_protocol prot,
  2226. enum mlx4_steer_type steer)
  2227. {
  2228. struct res_gid *res;
  2229. int err;
  2230. res = kzalloc(sizeof *res, GFP_KERNEL);
  2231. if (!res)
  2232. return -ENOMEM;
  2233. spin_lock_irq(&rqp->mcg_spl);
  2234. if (find_gid(dev, slave, rqp, gid)) {
  2235. kfree(res);
  2236. err = -EEXIST;
  2237. } else {
  2238. memcpy(res->gid, gid, 16);
  2239. res->prot = prot;
  2240. res->steer = steer;
  2241. list_add_tail(&res->list, &rqp->mcg_list);
  2242. err = 0;
  2243. }
  2244. spin_unlock_irq(&rqp->mcg_spl);
  2245. return err;
  2246. }
  2247. static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2248. u8 *gid, enum mlx4_protocol prot,
  2249. enum mlx4_steer_type steer)
  2250. {
  2251. struct res_gid *res;
  2252. int err;
  2253. spin_lock_irq(&rqp->mcg_spl);
  2254. res = find_gid(dev, slave, rqp, gid);
  2255. if (!res || res->prot != prot || res->steer != steer)
  2256. err = -EINVAL;
  2257. else {
  2258. list_del(&res->list);
  2259. kfree(res);
  2260. err = 0;
  2261. }
  2262. spin_unlock_irq(&rqp->mcg_spl);
  2263. return err;
  2264. }
  2265. int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  2266. struct mlx4_vhcr *vhcr,
  2267. struct mlx4_cmd_mailbox *inbox,
  2268. struct mlx4_cmd_mailbox *outbox,
  2269. struct mlx4_cmd_info *cmd)
  2270. {
  2271. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2272. u8 *gid = inbox->buf;
  2273. enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
  2274. int err;
  2275. int qpn;
  2276. struct res_qp *rqp;
  2277. int attach = vhcr->op_modifier;
  2278. int block_loopback = vhcr->in_modifier >> 31;
  2279. u8 steer_type_mask = 2;
  2280. enum mlx4_steer_type type = (gid[7] & steer_type_mask) >> 1;
  2281. qpn = vhcr->in_modifier & 0xffffff;
  2282. err = get_res(dev, slave, qpn, RES_QP, &rqp);
  2283. if (err)
  2284. return err;
  2285. qp.qpn = qpn;
  2286. if (attach) {
  2287. err = add_mcg_res(dev, slave, rqp, gid, prot, type);
  2288. if (err)
  2289. goto ex_put;
  2290. err = mlx4_qp_attach_common(dev, &qp, gid,
  2291. block_loopback, prot, type);
  2292. if (err)
  2293. goto ex_rem;
  2294. } else {
  2295. err = rem_mcg_res(dev, slave, rqp, gid, prot, type);
  2296. if (err)
  2297. goto ex_put;
  2298. err = mlx4_qp_detach_common(dev, &qp, gid, prot, type);
  2299. }
  2300. put_res(dev, slave, qpn, RES_QP);
  2301. return 0;
  2302. ex_rem:
  2303. /* ignore error return below, already in error */
  2304. (void) rem_mcg_res(dev, slave, rqp, gid, prot, type);
  2305. ex_put:
  2306. put_res(dev, slave, qpn, RES_QP);
  2307. return err;
  2308. }
  2309. /*
  2310. * MAC validation for Flow Steering rules.
  2311. * VF can attach rules only with a mac address which is assigned to it.
  2312. */
  2313. static int validate_eth_header_mac(int slave, struct _rule_hw *eth_header,
  2314. struct list_head *rlist)
  2315. {
  2316. struct mac_res *res, *tmp;
  2317. __be64 be_mac;
  2318. /* make sure it isn't multicast or broadcast mac*/
  2319. if (!is_multicast_ether_addr(eth_header->eth.dst_mac) &&
  2320. !is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
  2321. list_for_each_entry_safe(res, tmp, rlist, list) {
  2322. be_mac = cpu_to_be64(res->mac << 16);
  2323. if (!memcmp(&be_mac, eth_header->eth.dst_mac, ETH_ALEN))
  2324. return 0;
  2325. }
  2326. pr_err("MAC %pM doesn't belong to VF %d, Steering rule rejected\n",
  2327. eth_header->eth.dst_mac, slave);
  2328. return -EINVAL;
  2329. }
  2330. return 0;
  2331. }
  2332. /*
  2333. * In case of missing eth header, append eth header with a MAC address
  2334. * assigned to the VF.
  2335. */
  2336. static int add_eth_header(struct mlx4_dev *dev, int slave,
  2337. struct mlx4_cmd_mailbox *inbox,
  2338. struct list_head *rlist, int header_id)
  2339. {
  2340. struct mac_res *res, *tmp;
  2341. u8 port;
  2342. struct mlx4_net_trans_rule_hw_ctrl *ctrl;
  2343. struct mlx4_net_trans_rule_hw_eth *eth_header;
  2344. struct mlx4_net_trans_rule_hw_ipv4 *ip_header;
  2345. struct mlx4_net_trans_rule_hw_tcp_udp *l4_header;
  2346. __be64 be_mac = 0;
  2347. __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
  2348. ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
  2349. port = be32_to_cpu(ctrl->vf_vep_port) & 0xff;
  2350. eth_header = (struct mlx4_net_trans_rule_hw_eth *)(ctrl + 1);
  2351. /* Clear a space in the inbox for eth header */
  2352. switch (header_id) {
  2353. case MLX4_NET_TRANS_RULE_ID_IPV4:
  2354. ip_header =
  2355. (struct mlx4_net_trans_rule_hw_ipv4 *)(eth_header + 1);
  2356. memmove(ip_header, eth_header,
  2357. sizeof(*ip_header) + sizeof(*l4_header));
  2358. break;
  2359. case MLX4_NET_TRANS_RULE_ID_TCP:
  2360. case MLX4_NET_TRANS_RULE_ID_UDP:
  2361. l4_header = (struct mlx4_net_trans_rule_hw_tcp_udp *)
  2362. (eth_header + 1);
  2363. memmove(l4_header, eth_header, sizeof(*l4_header));
  2364. break;
  2365. default:
  2366. return -EINVAL;
  2367. }
  2368. list_for_each_entry_safe(res, tmp, rlist, list) {
  2369. if (port == res->port) {
  2370. be_mac = cpu_to_be64(res->mac << 16);
  2371. break;
  2372. }
  2373. }
  2374. if (!be_mac) {
  2375. pr_err("Failed adding eth header to FS rule, Can't find matching MAC for port %d .\n",
  2376. port);
  2377. return -EINVAL;
  2378. }
  2379. memset(eth_header, 0, sizeof(*eth_header));
  2380. eth_header->size = sizeof(*eth_header) >> 2;
  2381. eth_header->id = cpu_to_be16(__sw_id_hw[MLX4_NET_TRANS_RULE_ID_ETH]);
  2382. memcpy(eth_header->dst_mac, &be_mac, ETH_ALEN);
  2383. memcpy(eth_header->dst_mac_msk, &mac_msk, ETH_ALEN);
  2384. return 0;
  2385. }
  2386. int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  2387. struct mlx4_vhcr *vhcr,
  2388. struct mlx4_cmd_mailbox *inbox,
  2389. struct mlx4_cmd_mailbox *outbox,
  2390. struct mlx4_cmd_info *cmd)
  2391. {
  2392. struct mlx4_priv *priv = mlx4_priv(dev);
  2393. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2394. struct list_head *rlist = &tracker->slave_list[slave].res_list[RES_MAC];
  2395. int err;
  2396. struct mlx4_net_trans_rule_hw_ctrl *ctrl;
  2397. struct _rule_hw *rule_header;
  2398. int header_id;
  2399. if (dev->caps.steering_mode !=
  2400. MLX4_STEERING_MODE_DEVICE_MANAGED)
  2401. return -EOPNOTSUPP;
  2402. ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
  2403. rule_header = (struct _rule_hw *)(ctrl + 1);
  2404. header_id = map_hw_to_sw_id(be16_to_cpu(rule_header->id));
  2405. switch (header_id) {
  2406. case MLX4_NET_TRANS_RULE_ID_ETH:
  2407. if (validate_eth_header_mac(slave, rule_header, rlist))
  2408. return -EINVAL;
  2409. break;
  2410. case MLX4_NET_TRANS_RULE_ID_IPV4:
  2411. case MLX4_NET_TRANS_RULE_ID_TCP:
  2412. case MLX4_NET_TRANS_RULE_ID_UDP:
  2413. pr_warn("Can't attach FS rule without L2 headers, adding L2 header.\n");
  2414. if (add_eth_header(dev, slave, inbox, rlist, header_id))
  2415. return -EINVAL;
  2416. vhcr->in_modifier +=
  2417. sizeof(struct mlx4_net_trans_rule_hw_eth) >> 2;
  2418. break;
  2419. default:
  2420. pr_err("Corrupted mailbox.\n");
  2421. return -EINVAL;
  2422. }
  2423. err = mlx4_cmd_imm(dev, inbox->dma, &vhcr->out_param,
  2424. vhcr->in_modifier, 0,
  2425. MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
  2426. MLX4_CMD_NATIVE);
  2427. if (err)
  2428. return err;
  2429. err = add_res_range(dev, slave, vhcr->out_param, 1, RES_FS_RULE, 0);
  2430. if (err) {
  2431. mlx4_err(dev, "Fail to add flow steering resources.\n ");
  2432. /* detach rule*/
  2433. mlx4_cmd(dev, vhcr->out_param, 0, 0,
  2434. MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
  2435. MLX4_CMD_NATIVE);
  2436. }
  2437. return err;
  2438. }
  2439. int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
  2440. struct mlx4_vhcr *vhcr,
  2441. struct mlx4_cmd_mailbox *inbox,
  2442. struct mlx4_cmd_mailbox *outbox,
  2443. struct mlx4_cmd_info *cmd)
  2444. {
  2445. int err;
  2446. if (dev->caps.steering_mode !=
  2447. MLX4_STEERING_MODE_DEVICE_MANAGED)
  2448. return -EOPNOTSUPP;
  2449. err = rem_res_range(dev, slave, vhcr->in_param, 1, RES_FS_RULE, 0);
  2450. if (err) {
  2451. mlx4_err(dev, "Fail to remove flow steering resources.\n ");
  2452. return err;
  2453. }
  2454. err = mlx4_cmd(dev, vhcr->in_param, 0, 0,
  2455. MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  2456. MLX4_CMD_NATIVE);
  2457. return err;
  2458. }
  2459. enum {
  2460. BUSY_MAX_RETRIES = 10
  2461. };
  2462. int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
  2463. struct mlx4_vhcr *vhcr,
  2464. struct mlx4_cmd_mailbox *inbox,
  2465. struct mlx4_cmd_mailbox *outbox,
  2466. struct mlx4_cmd_info *cmd)
  2467. {
  2468. int err;
  2469. int index = vhcr->in_modifier & 0xffff;
  2470. err = get_res(dev, slave, index, RES_COUNTER, NULL);
  2471. if (err)
  2472. return err;
  2473. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2474. put_res(dev, slave, index, RES_COUNTER);
  2475. return err;
  2476. }
  2477. static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
  2478. {
  2479. struct res_gid *rgid;
  2480. struct res_gid *tmp;
  2481. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2482. list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
  2483. qp.qpn = rqp->local_qpn;
  2484. (void) mlx4_qp_detach_common(dev, &qp, rgid->gid, rgid->prot,
  2485. rgid->steer);
  2486. list_del(&rgid->list);
  2487. kfree(rgid);
  2488. }
  2489. }
  2490. static int _move_all_busy(struct mlx4_dev *dev, int slave,
  2491. enum mlx4_resource type, int print)
  2492. {
  2493. struct mlx4_priv *priv = mlx4_priv(dev);
  2494. struct mlx4_resource_tracker *tracker =
  2495. &priv->mfunc.master.res_tracker;
  2496. struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
  2497. struct res_common *r;
  2498. struct res_common *tmp;
  2499. int busy;
  2500. busy = 0;
  2501. spin_lock_irq(mlx4_tlock(dev));
  2502. list_for_each_entry_safe(r, tmp, rlist, list) {
  2503. if (r->owner == slave) {
  2504. if (!r->removing) {
  2505. if (r->state == RES_ANY_BUSY) {
  2506. if (print)
  2507. mlx4_dbg(dev,
  2508. "%s id 0x%llx is busy\n",
  2509. ResourceType(type),
  2510. r->res_id);
  2511. ++busy;
  2512. } else {
  2513. r->from_state = r->state;
  2514. r->state = RES_ANY_BUSY;
  2515. r->removing = 1;
  2516. }
  2517. }
  2518. }
  2519. }
  2520. spin_unlock_irq(mlx4_tlock(dev));
  2521. return busy;
  2522. }
  2523. static int move_all_busy(struct mlx4_dev *dev, int slave,
  2524. enum mlx4_resource type)
  2525. {
  2526. unsigned long begin;
  2527. int busy;
  2528. begin = jiffies;
  2529. do {
  2530. busy = _move_all_busy(dev, slave, type, 0);
  2531. if (time_after(jiffies, begin + 5 * HZ))
  2532. break;
  2533. if (busy)
  2534. cond_resched();
  2535. } while (busy);
  2536. if (busy)
  2537. busy = _move_all_busy(dev, slave, type, 1);
  2538. return busy;
  2539. }
  2540. static void rem_slave_qps(struct mlx4_dev *dev, int slave)
  2541. {
  2542. struct mlx4_priv *priv = mlx4_priv(dev);
  2543. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2544. struct list_head *qp_list =
  2545. &tracker->slave_list[slave].res_list[RES_QP];
  2546. struct res_qp *qp;
  2547. struct res_qp *tmp;
  2548. int state;
  2549. u64 in_param;
  2550. int qpn;
  2551. int err;
  2552. err = move_all_busy(dev, slave, RES_QP);
  2553. if (err)
  2554. mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy"
  2555. "for slave %d\n", slave);
  2556. spin_lock_irq(mlx4_tlock(dev));
  2557. list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
  2558. spin_unlock_irq(mlx4_tlock(dev));
  2559. if (qp->com.owner == slave) {
  2560. qpn = qp->com.res_id;
  2561. detach_qp(dev, slave, qp);
  2562. state = qp->com.from_state;
  2563. while (state != 0) {
  2564. switch (state) {
  2565. case RES_QP_RESERVED:
  2566. spin_lock_irq(mlx4_tlock(dev));
  2567. rb_erase(&qp->com.node,
  2568. &tracker->res_tree[RES_QP]);
  2569. list_del(&qp->com.list);
  2570. spin_unlock_irq(mlx4_tlock(dev));
  2571. kfree(qp);
  2572. state = 0;
  2573. break;
  2574. case RES_QP_MAPPED:
  2575. if (!valid_reserved(dev, slave, qpn))
  2576. __mlx4_qp_free_icm(dev, qpn);
  2577. state = RES_QP_RESERVED;
  2578. break;
  2579. case RES_QP_HW:
  2580. in_param = slave;
  2581. err = mlx4_cmd(dev, in_param,
  2582. qp->local_qpn, 2,
  2583. MLX4_CMD_2RST_QP,
  2584. MLX4_CMD_TIME_CLASS_A,
  2585. MLX4_CMD_NATIVE);
  2586. if (err)
  2587. mlx4_dbg(dev, "rem_slave_qps: failed"
  2588. " to move slave %d qpn %d to"
  2589. " reset\n", slave,
  2590. qp->local_qpn);
  2591. atomic_dec(&qp->rcq->ref_count);
  2592. atomic_dec(&qp->scq->ref_count);
  2593. atomic_dec(&qp->mtt->ref_count);
  2594. if (qp->srq)
  2595. atomic_dec(&qp->srq->ref_count);
  2596. state = RES_QP_MAPPED;
  2597. break;
  2598. default:
  2599. state = 0;
  2600. }
  2601. }
  2602. }
  2603. spin_lock_irq(mlx4_tlock(dev));
  2604. }
  2605. spin_unlock_irq(mlx4_tlock(dev));
  2606. }
  2607. static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
  2608. {
  2609. struct mlx4_priv *priv = mlx4_priv(dev);
  2610. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2611. struct list_head *srq_list =
  2612. &tracker->slave_list[slave].res_list[RES_SRQ];
  2613. struct res_srq *srq;
  2614. struct res_srq *tmp;
  2615. int state;
  2616. u64 in_param;
  2617. LIST_HEAD(tlist);
  2618. int srqn;
  2619. int err;
  2620. err = move_all_busy(dev, slave, RES_SRQ);
  2621. if (err)
  2622. mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs to "
  2623. "busy for slave %d\n", slave);
  2624. spin_lock_irq(mlx4_tlock(dev));
  2625. list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
  2626. spin_unlock_irq(mlx4_tlock(dev));
  2627. if (srq->com.owner == slave) {
  2628. srqn = srq->com.res_id;
  2629. state = srq->com.from_state;
  2630. while (state != 0) {
  2631. switch (state) {
  2632. case RES_SRQ_ALLOCATED:
  2633. __mlx4_srq_free_icm(dev, srqn);
  2634. spin_lock_irq(mlx4_tlock(dev));
  2635. rb_erase(&srq->com.node,
  2636. &tracker->res_tree[RES_SRQ]);
  2637. list_del(&srq->com.list);
  2638. spin_unlock_irq(mlx4_tlock(dev));
  2639. kfree(srq);
  2640. state = 0;
  2641. break;
  2642. case RES_SRQ_HW:
  2643. in_param = slave;
  2644. err = mlx4_cmd(dev, in_param, srqn, 1,
  2645. MLX4_CMD_HW2SW_SRQ,
  2646. MLX4_CMD_TIME_CLASS_A,
  2647. MLX4_CMD_NATIVE);
  2648. if (err)
  2649. mlx4_dbg(dev, "rem_slave_srqs: failed"
  2650. " to move slave %d srq %d to"
  2651. " SW ownership\n",
  2652. slave, srqn);
  2653. atomic_dec(&srq->mtt->ref_count);
  2654. if (srq->cq)
  2655. atomic_dec(&srq->cq->ref_count);
  2656. state = RES_SRQ_ALLOCATED;
  2657. break;
  2658. default:
  2659. state = 0;
  2660. }
  2661. }
  2662. }
  2663. spin_lock_irq(mlx4_tlock(dev));
  2664. }
  2665. spin_unlock_irq(mlx4_tlock(dev));
  2666. }
  2667. static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
  2668. {
  2669. struct mlx4_priv *priv = mlx4_priv(dev);
  2670. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2671. struct list_head *cq_list =
  2672. &tracker->slave_list[slave].res_list[RES_CQ];
  2673. struct res_cq *cq;
  2674. struct res_cq *tmp;
  2675. int state;
  2676. u64 in_param;
  2677. LIST_HEAD(tlist);
  2678. int cqn;
  2679. int err;
  2680. err = move_all_busy(dev, slave, RES_CQ);
  2681. if (err)
  2682. mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs to "
  2683. "busy for slave %d\n", slave);
  2684. spin_lock_irq(mlx4_tlock(dev));
  2685. list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
  2686. spin_unlock_irq(mlx4_tlock(dev));
  2687. if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
  2688. cqn = cq->com.res_id;
  2689. state = cq->com.from_state;
  2690. while (state != 0) {
  2691. switch (state) {
  2692. case RES_CQ_ALLOCATED:
  2693. __mlx4_cq_free_icm(dev, cqn);
  2694. spin_lock_irq(mlx4_tlock(dev));
  2695. rb_erase(&cq->com.node,
  2696. &tracker->res_tree[RES_CQ]);
  2697. list_del(&cq->com.list);
  2698. spin_unlock_irq(mlx4_tlock(dev));
  2699. kfree(cq);
  2700. state = 0;
  2701. break;
  2702. case RES_CQ_HW:
  2703. in_param = slave;
  2704. err = mlx4_cmd(dev, in_param, cqn, 1,
  2705. MLX4_CMD_HW2SW_CQ,
  2706. MLX4_CMD_TIME_CLASS_A,
  2707. MLX4_CMD_NATIVE);
  2708. if (err)
  2709. mlx4_dbg(dev, "rem_slave_cqs: failed"
  2710. " to move slave %d cq %d to"
  2711. " SW ownership\n",
  2712. slave, cqn);
  2713. atomic_dec(&cq->mtt->ref_count);
  2714. state = RES_CQ_ALLOCATED;
  2715. break;
  2716. default:
  2717. state = 0;
  2718. }
  2719. }
  2720. }
  2721. spin_lock_irq(mlx4_tlock(dev));
  2722. }
  2723. spin_unlock_irq(mlx4_tlock(dev));
  2724. }
  2725. static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
  2726. {
  2727. struct mlx4_priv *priv = mlx4_priv(dev);
  2728. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2729. struct list_head *mpt_list =
  2730. &tracker->slave_list[slave].res_list[RES_MPT];
  2731. struct res_mpt *mpt;
  2732. struct res_mpt *tmp;
  2733. int state;
  2734. u64 in_param;
  2735. LIST_HEAD(tlist);
  2736. int mptn;
  2737. int err;
  2738. err = move_all_busy(dev, slave, RES_MPT);
  2739. if (err)
  2740. mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts to "
  2741. "busy for slave %d\n", slave);
  2742. spin_lock_irq(mlx4_tlock(dev));
  2743. list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
  2744. spin_unlock_irq(mlx4_tlock(dev));
  2745. if (mpt->com.owner == slave) {
  2746. mptn = mpt->com.res_id;
  2747. state = mpt->com.from_state;
  2748. while (state != 0) {
  2749. switch (state) {
  2750. case RES_MPT_RESERVED:
  2751. __mlx4_mr_release(dev, mpt->key);
  2752. spin_lock_irq(mlx4_tlock(dev));
  2753. rb_erase(&mpt->com.node,
  2754. &tracker->res_tree[RES_MPT]);
  2755. list_del(&mpt->com.list);
  2756. spin_unlock_irq(mlx4_tlock(dev));
  2757. kfree(mpt);
  2758. state = 0;
  2759. break;
  2760. case RES_MPT_MAPPED:
  2761. __mlx4_mr_free_icm(dev, mpt->key);
  2762. state = RES_MPT_RESERVED;
  2763. break;
  2764. case RES_MPT_HW:
  2765. in_param = slave;
  2766. err = mlx4_cmd(dev, in_param, mptn, 0,
  2767. MLX4_CMD_HW2SW_MPT,
  2768. MLX4_CMD_TIME_CLASS_A,
  2769. MLX4_CMD_NATIVE);
  2770. if (err)
  2771. mlx4_dbg(dev, "rem_slave_mrs: failed"
  2772. " to move slave %d mpt %d to"
  2773. " SW ownership\n",
  2774. slave, mptn);
  2775. if (mpt->mtt)
  2776. atomic_dec(&mpt->mtt->ref_count);
  2777. state = RES_MPT_MAPPED;
  2778. break;
  2779. default:
  2780. state = 0;
  2781. }
  2782. }
  2783. }
  2784. spin_lock_irq(mlx4_tlock(dev));
  2785. }
  2786. spin_unlock_irq(mlx4_tlock(dev));
  2787. }
  2788. static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
  2789. {
  2790. struct mlx4_priv *priv = mlx4_priv(dev);
  2791. struct mlx4_resource_tracker *tracker =
  2792. &priv->mfunc.master.res_tracker;
  2793. struct list_head *mtt_list =
  2794. &tracker->slave_list[slave].res_list[RES_MTT];
  2795. struct res_mtt *mtt;
  2796. struct res_mtt *tmp;
  2797. int state;
  2798. LIST_HEAD(tlist);
  2799. int base;
  2800. int err;
  2801. err = move_all_busy(dev, slave, RES_MTT);
  2802. if (err)
  2803. mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts to "
  2804. "busy for slave %d\n", slave);
  2805. spin_lock_irq(mlx4_tlock(dev));
  2806. list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
  2807. spin_unlock_irq(mlx4_tlock(dev));
  2808. if (mtt->com.owner == slave) {
  2809. base = mtt->com.res_id;
  2810. state = mtt->com.from_state;
  2811. while (state != 0) {
  2812. switch (state) {
  2813. case RES_MTT_ALLOCATED:
  2814. __mlx4_free_mtt_range(dev, base,
  2815. mtt->order);
  2816. spin_lock_irq(mlx4_tlock(dev));
  2817. rb_erase(&mtt->com.node,
  2818. &tracker->res_tree[RES_MTT]);
  2819. list_del(&mtt->com.list);
  2820. spin_unlock_irq(mlx4_tlock(dev));
  2821. kfree(mtt);
  2822. state = 0;
  2823. break;
  2824. default:
  2825. state = 0;
  2826. }
  2827. }
  2828. }
  2829. spin_lock_irq(mlx4_tlock(dev));
  2830. }
  2831. spin_unlock_irq(mlx4_tlock(dev));
  2832. }
  2833. static void rem_slave_fs_rule(struct mlx4_dev *dev, int slave)
  2834. {
  2835. struct mlx4_priv *priv = mlx4_priv(dev);
  2836. struct mlx4_resource_tracker *tracker =
  2837. &priv->mfunc.master.res_tracker;
  2838. struct list_head *fs_rule_list =
  2839. &tracker->slave_list[slave].res_list[RES_FS_RULE];
  2840. struct res_fs_rule *fs_rule;
  2841. struct res_fs_rule *tmp;
  2842. int state;
  2843. u64 base;
  2844. int err;
  2845. err = move_all_busy(dev, slave, RES_FS_RULE);
  2846. if (err)
  2847. mlx4_warn(dev, "rem_slave_fs_rule: Could not move all mtts to busy for slave %d\n",
  2848. slave);
  2849. spin_lock_irq(mlx4_tlock(dev));
  2850. list_for_each_entry_safe(fs_rule, tmp, fs_rule_list, com.list) {
  2851. spin_unlock_irq(mlx4_tlock(dev));
  2852. if (fs_rule->com.owner == slave) {
  2853. base = fs_rule->com.res_id;
  2854. state = fs_rule->com.from_state;
  2855. while (state != 0) {
  2856. switch (state) {
  2857. case RES_FS_RULE_ALLOCATED:
  2858. /* detach rule */
  2859. err = mlx4_cmd(dev, base, 0, 0,
  2860. MLX4_QP_FLOW_STEERING_DETACH,
  2861. MLX4_CMD_TIME_CLASS_A,
  2862. MLX4_CMD_NATIVE);
  2863. spin_lock_irq(mlx4_tlock(dev));
  2864. rb_erase(&fs_rule->com.node,
  2865. &tracker->res_tree[RES_FS_RULE]);
  2866. list_del(&fs_rule->com.list);
  2867. spin_unlock_irq(mlx4_tlock(dev));
  2868. kfree(fs_rule);
  2869. state = 0;
  2870. break;
  2871. default:
  2872. state = 0;
  2873. }
  2874. }
  2875. }
  2876. spin_lock_irq(mlx4_tlock(dev));
  2877. }
  2878. spin_unlock_irq(mlx4_tlock(dev));
  2879. }
  2880. static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
  2881. {
  2882. struct mlx4_priv *priv = mlx4_priv(dev);
  2883. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2884. struct list_head *eq_list =
  2885. &tracker->slave_list[slave].res_list[RES_EQ];
  2886. struct res_eq *eq;
  2887. struct res_eq *tmp;
  2888. int err;
  2889. int state;
  2890. LIST_HEAD(tlist);
  2891. int eqn;
  2892. struct mlx4_cmd_mailbox *mailbox;
  2893. err = move_all_busy(dev, slave, RES_EQ);
  2894. if (err)
  2895. mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs to "
  2896. "busy for slave %d\n", slave);
  2897. spin_lock_irq(mlx4_tlock(dev));
  2898. list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
  2899. spin_unlock_irq(mlx4_tlock(dev));
  2900. if (eq->com.owner == slave) {
  2901. eqn = eq->com.res_id;
  2902. state = eq->com.from_state;
  2903. while (state != 0) {
  2904. switch (state) {
  2905. case RES_EQ_RESERVED:
  2906. spin_lock_irq(mlx4_tlock(dev));
  2907. rb_erase(&eq->com.node,
  2908. &tracker->res_tree[RES_EQ]);
  2909. list_del(&eq->com.list);
  2910. spin_unlock_irq(mlx4_tlock(dev));
  2911. kfree(eq);
  2912. state = 0;
  2913. break;
  2914. case RES_EQ_HW:
  2915. mailbox = mlx4_alloc_cmd_mailbox(dev);
  2916. if (IS_ERR(mailbox)) {
  2917. cond_resched();
  2918. continue;
  2919. }
  2920. err = mlx4_cmd_box(dev, slave, 0,
  2921. eqn & 0xff, 0,
  2922. MLX4_CMD_HW2SW_EQ,
  2923. MLX4_CMD_TIME_CLASS_A,
  2924. MLX4_CMD_NATIVE);
  2925. if (err)
  2926. mlx4_dbg(dev, "rem_slave_eqs: failed"
  2927. " to move slave %d eqs %d to"
  2928. " SW ownership\n", slave, eqn);
  2929. mlx4_free_cmd_mailbox(dev, mailbox);
  2930. atomic_dec(&eq->mtt->ref_count);
  2931. state = RES_EQ_RESERVED;
  2932. break;
  2933. default:
  2934. state = 0;
  2935. }
  2936. }
  2937. }
  2938. spin_lock_irq(mlx4_tlock(dev));
  2939. }
  2940. spin_unlock_irq(mlx4_tlock(dev));
  2941. }
  2942. static void rem_slave_counters(struct mlx4_dev *dev, int slave)
  2943. {
  2944. struct mlx4_priv *priv = mlx4_priv(dev);
  2945. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2946. struct list_head *counter_list =
  2947. &tracker->slave_list[slave].res_list[RES_COUNTER];
  2948. struct res_counter *counter;
  2949. struct res_counter *tmp;
  2950. int err;
  2951. int index;
  2952. err = move_all_busy(dev, slave, RES_COUNTER);
  2953. if (err)
  2954. mlx4_warn(dev, "rem_slave_counters: Could not move all counters to "
  2955. "busy for slave %d\n", slave);
  2956. spin_lock_irq(mlx4_tlock(dev));
  2957. list_for_each_entry_safe(counter, tmp, counter_list, com.list) {
  2958. if (counter->com.owner == slave) {
  2959. index = counter->com.res_id;
  2960. rb_erase(&counter->com.node,
  2961. &tracker->res_tree[RES_COUNTER]);
  2962. list_del(&counter->com.list);
  2963. kfree(counter);
  2964. __mlx4_counter_free(dev, index);
  2965. }
  2966. }
  2967. spin_unlock_irq(mlx4_tlock(dev));
  2968. }
  2969. static void rem_slave_xrcdns(struct mlx4_dev *dev, int slave)
  2970. {
  2971. struct mlx4_priv *priv = mlx4_priv(dev);
  2972. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2973. struct list_head *xrcdn_list =
  2974. &tracker->slave_list[slave].res_list[RES_XRCD];
  2975. struct res_xrcdn *xrcd;
  2976. struct res_xrcdn *tmp;
  2977. int err;
  2978. int xrcdn;
  2979. err = move_all_busy(dev, slave, RES_XRCD);
  2980. if (err)
  2981. mlx4_warn(dev, "rem_slave_xrcdns: Could not move all xrcdns to "
  2982. "busy for slave %d\n", slave);
  2983. spin_lock_irq(mlx4_tlock(dev));
  2984. list_for_each_entry_safe(xrcd, tmp, xrcdn_list, com.list) {
  2985. if (xrcd->com.owner == slave) {
  2986. xrcdn = xrcd->com.res_id;
  2987. rb_erase(&xrcd->com.node, &tracker->res_tree[RES_XRCD]);
  2988. list_del(&xrcd->com.list);
  2989. kfree(xrcd);
  2990. __mlx4_xrcd_free(dev, xrcdn);
  2991. }
  2992. }
  2993. spin_unlock_irq(mlx4_tlock(dev));
  2994. }
  2995. void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
  2996. {
  2997. struct mlx4_priv *priv = mlx4_priv(dev);
  2998. mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  2999. /*VLAN*/
  3000. rem_slave_macs(dev, slave);
  3001. rem_slave_qps(dev, slave);
  3002. rem_slave_srqs(dev, slave);
  3003. rem_slave_cqs(dev, slave);
  3004. rem_slave_mrs(dev, slave);
  3005. rem_slave_eqs(dev, slave);
  3006. rem_slave_mtts(dev, slave);
  3007. rem_slave_counters(dev, slave);
  3008. rem_slave_xrcdns(dev, slave);
  3009. rem_slave_fs_rule(dev, slave);
  3010. mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  3011. }