xhci-hcd.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532
  1. /*
  2. * xHCI host controller driver
  3. *
  4. * Copyright (C) 2008 Intel Corp.
  5. *
  6. * Author: Sarah Sharp
  7. * Some code borrowed from the Linux EHCI driver.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16. * for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software Foundation,
  20. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <linux/irq.h>
  23. #include <linux/module.h>
  24. #include "xhci.h"
  25. #define DRIVER_AUTHOR "Sarah Sharp"
  26. #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
  27. /* TODO: copied from ehci-hcd.c - can this be refactored? */
  28. /*
  29. * handshake - spin reading hc until handshake completes or fails
  30. * @ptr: address of hc register to be read
  31. * @mask: bits to look at in result of read
  32. * @done: value of those bits when handshake succeeds
  33. * @usec: timeout in microseconds
  34. *
  35. * Returns negative errno, or zero on success
  36. *
  37. * Success happens when the "mask" bits have the specified value (hardware
  38. * handshake done). There are two failure modes: "usec" have passed (major
  39. * hardware flakeout), or the register reads as all-ones (hardware removed).
  40. */
  41. static int handshake(struct xhci_hcd *xhci, void __iomem *ptr,
  42. u32 mask, u32 done, int usec)
  43. {
  44. u32 result;
  45. do {
  46. result = xhci_readl(xhci, ptr);
  47. if (result == ~(u32)0) /* card removed */
  48. return -ENODEV;
  49. result &= mask;
  50. if (result == done)
  51. return 0;
  52. udelay(1);
  53. usec--;
  54. } while (usec > 0);
  55. return -ETIMEDOUT;
  56. }
  57. /*
  58. * Force HC into halt state.
  59. *
  60. * Disable any IRQs and clear the run/stop bit.
  61. * HC will complete any current and actively pipelined transactions, and
  62. * should halt within 16 microframes of the run/stop bit being cleared.
  63. * Read HC Halted bit in the status register to see when the HC is finished.
  64. * XXX: shouldn't we set HC_STATE_HALT here somewhere?
  65. */
  66. int xhci_halt(struct xhci_hcd *xhci)
  67. {
  68. u32 halted;
  69. u32 cmd;
  70. u32 mask;
  71. xhci_dbg(xhci, "// Halt the HC\n");
  72. /* Disable all interrupts from the host controller */
  73. mask = ~(XHCI_IRQS);
  74. halted = xhci_readl(xhci, &xhci->op_regs->status) & STS_HALT;
  75. if (!halted)
  76. mask &= ~CMD_RUN;
  77. cmd = xhci_readl(xhci, &xhci->op_regs->command);
  78. cmd &= mask;
  79. xhci_writel(xhci, cmd, &xhci->op_regs->command);
  80. return handshake(xhci, &xhci->op_regs->status,
  81. STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
  82. }
  83. /*
  84. * Reset a halted HC, and set the internal HC state to HC_STATE_HALT.
  85. *
  86. * This resets pipelines, timers, counters, state machines, etc.
  87. * Transactions will be terminated immediately, and operational registers
  88. * will be set to their defaults.
  89. */
  90. int xhci_reset(struct xhci_hcd *xhci)
  91. {
  92. u32 command;
  93. u32 state;
  94. state = xhci_readl(xhci, &xhci->op_regs->status);
  95. BUG_ON((state & STS_HALT) == 0);
  96. xhci_dbg(xhci, "// Reset the HC\n");
  97. command = xhci_readl(xhci, &xhci->op_regs->command);
  98. command |= CMD_RESET;
  99. xhci_writel(xhci, command, &xhci->op_regs->command);
  100. /* XXX: Why does EHCI set this here? Shouldn't other code do this? */
  101. xhci_to_hcd(xhci)->state = HC_STATE_HALT;
  102. return handshake(xhci, &xhci->op_regs->command, CMD_RESET, 0, 250 * 1000);
  103. }
  104. /*
  105. * Stop the HC from processing the endpoint queues.
  106. */
  107. static void xhci_quiesce(struct xhci_hcd *xhci)
  108. {
  109. /*
  110. * Queues are per endpoint, so we need to disable an endpoint or slot.
  111. *
  112. * To disable a slot, we need to insert a disable slot command on the
  113. * command ring and ring the doorbell. This will also free any internal
  114. * resources associated with the slot (which might not be what we want).
  115. *
  116. * A Release Endpoint command sounds better - doesn't free internal HC
  117. * memory, but removes the endpoints from the schedule and releases the
  118. * bandwidth, disables the doorbells, and clears the endpoint enable
  119. * flag. Usually used prior to a set interface command.
  120. *
  121. * TODO: Implement after command ring code is done.
  122. */
  123. BUG_ON(!HC_IS_RUNNING(xhci_to_hcd(xhci)->state));
  124. xhci_dbg(xhci, "Finished quiescing -- code not written yet\n");
  125. }
  126. #if 0
  127. /* Set up MSI-X table for entry 0 (may claim other entries later) */
  128. static int xhci_setup_msix(struct xhci_hcd *xhci)
  129. {
  130. int ret;
  131. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  132. xhci->msix_count = 0;
  133. /* XXX: did I do this right? ixgbe does kcalloc for more than one */
  134. xhci->msix_entries = kmalloc(sizeof(struct msix_entry), GFP_KERNEL);
  135. if (!xhci->msix_entries) {
  136. xhci_err(xhci, "Failed to allocate MSI-X entries\n");
  137. return -ENOMEM;
  138. }
  139. xhci->msix_entries[0].entry = 0;
  140. ret = pci_enable_msix(pdev, xhci->msix_entries, xhci->msix_count);
  141. if (ret) {
  142. xhci_err(xhci, "Failed to enable MSI-X\n");
  143. goto free_entries;
  144. }
  145. /*
  146. * Pass the xhci pointer value as the request_irq "cookie".
  147. * If more irqs are added, this will need to be unique for each one.
  148. */
  149. ret = request_irq(xhci->msix_entries[0].vector, &xhci_irq, 0,
  150. "xHCI", xhci_to_hcd(xhci));
  151. if (ret) {
  152. xhci_err(xhci, "Failed to allocate MSI-X interrupt\n");
  153. goto disable_msix;
  154. }
  155. xhci_dbg(xhci, "Finished setting up MSI-X\n");
  156. return 0;
  157. disable_msix:
  158. pci_disable_msix(pdev);
  159. free_entries:
  160. kfree(xhci->msix_entries);
  161. xhci->msix_entries = NULL;
  162. return ret;
  163. }
  164. /* XXX: code duplication; can xhci_setup_msix call this? */
  165. /* Free any IRQs and disable MSI-X */
  166. static void xhci_cleanup_msix(struct xhci_hcd *xhci)
  167. {
  168. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  169. if (!xhci->msix_entries)
  170. return;
  171. free_irq(xhci->msix_entries[0].vector, xhci);
  172. pci_disable_msix(pdev);
  173. kfree(xhci->msix_entries);
  174. xhci->msix_entries = NULL;
  175. xhci_dbg(xhci, "Finished cleaning up MSI-X\n");
  176. }
  177. #endif
  178. /*
  179. * Initialize memory for HCD and xHC (one-time init).
  180. *
  181. * Program the PAGESIZE register, initialize the device context array, create
  182. * device contexts (?), set up a command ring segment (or two?), create event
  183. * ring (one for now).
  184. */
  185. int xhci_init(struct usb_hcd *hcd)
  186. {
  187. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  188. int retval = 0;
  189. xhci_dbg(xhci, "xhci_init\n");
  190. spin_lock_init(&xhci->lock);
  191. retval = xhci_mem_init(xhci, GFP_KERNEL);
  192. xhci_dbg(xhci, "Finished xhci_init\n");
  193. return retval;
  194. }
  195. /*
  196. * Called in interrupt context when there might be work
  197. * queued on the event ring
  198. *
  199. * xhci->lock must be held by caller.
  200. */
  201. static void xhci_work(struct xhci_hcd *xhci)
  202. {
  203. u32 temp;
  204. /*
  205. * Clear the op reg interrupt status first,
  206. * so we can receive interrupts from other MSI-X interrupters.
  207. * Write 1 to clear the interrupt status.
  208. */
  209. temp = xhci_readl(xhci, &xhci->op_regs->status);
  210. temp |= STS_EINT;
  211. xhci_writel(xhci, temp, &xhci->op_regs->status);
  212. /* FIXME when MSI-X is supported and there are multiple vectors */
  213. /* Clear the MSI-X event interrupt status */
  214. /* Acknowledge the interrupt */
  215. temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  216. temp |= 0x3;
  217. xhci_writel(xhci, temp, &xhci->ir_set->irq_pending);
  218. /* Flush posted writes */
  219. xhci_readl(xhci, &xhci->ir_set->irq_pending);
  220. /* FIXME this should be a delayed service routine that clears the EHB */
  221. handle_event(xhci);
  222. /* Clear the event handler busy flag; the event ring should be empty. */
  223. temp = xhci_readl(xhci, &xhci->ir_set->erst_dequeue[0]);
  224. xhci_writel(xhci, temp & ~ERST_EHB, &xhci->ir_set->erst_dequeue[0]);
  225. /* Flush posted writes -- FIXME is this necessary? */
  226. xhci_readl(xhci, &xhci->ir_set->irq_pending);
  227. }
  228. /*-------------------------------------------------------------------------*/
  229. /*
  230. * xHCI spec says we can get an interrupt, and if the HC has an error condition,
  231. * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
  232. * indicators of an event TRB error, but we check the status *first* to be safe.
  233. */
  234. irqreturn_t xhci_irq(struct usb_hcd *hcd)
  235. {
  236. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  237. u32 temp, temp2;
  238. spin_lock(&xhci->lock);
  239. /* Check if the xHC generated the interrupt, or the irq is shared */
  240. temp = xhci_readl(xhci, &xhci->op_regs->status);
  241. temp2 = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  242. if (!(temp & STS_EINT) && !ER_IRQ_PENDING(temp2)) {
  243. spin_unlock(&xhci->lock);
  244. return IRQ_NONE;
  245. }
  246. temp = xhci_readl(xhci, &xhci->op_regs->status);
  247. if (temp & STS_FATAL) {
  248. xhci_warn(xhci, "WARNING: Host System Error\n");
  249. xhci_halt(xhci);
  250. xhci_to_hcd(xhci)->state = HC_STATE_HALT;
  251. return -ESHUTDOWN;
  252. }
  253. xhci_work(xhci);
  254. spin_unlock(&xhci->lock);
  255. return IRQ_HANDLED;
  256. }
  257. #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
  258. void event_ring_work(unsigned long arg)
  259. {
  260. unsigned long flags;
  261. int temp;
  262. struct xhci_hcd *xhci = (struct xhci_hcd *) arg;
  263. int i, j;
  264. xhci_dbg(xhci, "Poll event ring: %lu\n", jiffies);
  265. spin_lock_irqsave(&xhci->lock, flags);
  266. temp = xhci_readl(xhci, &xhci->op_regs->status);
  267. xhci_dbg(xhci, "op reg status = 0x%x\n", temp);
  268. temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  269. xhci_dbg(xhci, "ir_set 0 pending = 0x%x\n", temp);
  270. xhci_dbg(xhci, "No-op commands handled = %d\n", xhci->noops_handled);
  271. xhci_dbg(xhci, "HC error bitmask = 0x%x\n", xhci->error_bitmask);
  272. xhci->error_bitmask = 0;
  273. xhci_dbg(xhci, "Event ring:\n");
  274. xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
  275. xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
  276. temp = xhci_readl(xhci, &xhci->ir_set->erst_dequeue[0]);
  277. temp &= ERST_PTR_MASK;
  278. xhci_dbg(xhci, "ERST deq = 0x%x\n", temp);
  279. xhci_dbg(xhci, "Command ring:\n");
  280. xhci_debug_segment(xhci, xhci->cmd_ring->deq_seg);
  281. xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
  282. xhci_dbg_cmd_ptrs(xhci);
  283. if (xhci->noops_submitted != NUM_TEST_NOOPS)
  284. if (setup_one_noop(xhci))
  285. ring_cmd_db(xhci);
  286. spin_unlock_irqrestore(&xhci->lock, flags);
  287. if (!xhci->zombie)
  288. mod_timer(&xhci->event_ring_timer, jiffies + POLL_TIMEOUT * HZ);
  289. else
  290. xhci_dbg(xhci, "Quit polling the event ring.\n");
  291. }
  292. #endif
  293. /*
  294. * Start the HC after it was halted.
  295. *
  296. * This function is called by the USB core when the HC driver is added.
  297. * Its opposite is xhci_stop().
  298. *
  299. * xhci_init() must be called once before this function can be called.
  300. * Reset the HC, enable device slot contexts, program DCBAAP, and
  301. * set command ring pointer and event ring pointer.
  302. *
  303. * Setup MSI-X vectors and enable interrupts.
  304. */
  305. int xhci_run(struct usb_hcd *hcd)
  306. {
  307. u32 temp;
  308. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  309. void (*doorbell)(struct xhci_hcd *) = NULL;
  310. xhci_dbg(xhci, "xhci_run\n");
  311. #if 0 /* FIXME: MSI not setup yet */
  312. /* Do this at the very last minute */
  313. ret = xhci_setup_msix(xhci);
  314. if (!ret)
  315. return ret;
  316. return -ENOSYS;
  317. #endif
  318. #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
  319. init_timer(&xhci->event_ring_timer);
  320. xhci->event_ring_timer.data = (unsigned long) xhci;
  321. xhci->event_ring_timer.function = event_ring_work;
  322. /* Poll the event ring */
  323. xhci->event_ring_timer.expires = jiffies + POLL_TIMEOUT * HZ;
  324. xhci->zombie = 0;
  325. xhci_dbg(xhci, "Setting event ring polling timer\n");
  326. add_timer(&xhci->event_ring_timer);
  327. #endif
  328. xhci_dbg(xhci, "// Set the interrupt modulation register\n");
  329. temp = xhci_readl(xhci, &xhci->ir_set->irq_control);
  330. temp &= 0xffff;
  331. temp |= (u32) 160;
  332. xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
  333. /* Set the HCD state before we enable the irqs */
  334. hcd->state = HC_STATE_RUNNING;
  335. temp = xhci_readl(xhci, &xhci->op_regs->command);
  336. temp |= (CMD_EIE);
  337. xhci_dbg(xhci, "// Enable interrupts, cmd = 0x%x.\n",
  338. temp);
  339. xhci_writel(xhci, temp, &xhci->op_regs->command);
  340. temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  341. xhci_dbg(xhci, "// Enabling event ring interrupter 0x%x"
  342. " by writing 0x%x to irq_pending\n",
  343. (unsigned int) xhci->ir_set,
  344. (unsigned int) ER_IRQ_ENABLE(temp));
  345. xhci_writel(xhci, ER_IRQ_ENABLE(temp),
  346. &xhci->ir_set->irq_pending);
  347. xhci_print_ir_set(xhci, xhci->ir_set, 0);
  348. if (NUM_TEST_NOOPS > 0)
  349. doorbell = setup_one_noop(xhci);
  350. xhci_dbg(xhci, "Command ring memory map follows:\n");
  351. xhci_debug_ring(xhci, xhci->cmd_ring);
  352. xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
  353. xhci_dbg_cmd_ptrs(xhci);
  354. xhci_dbg(xhci, "ERST memory map follows:\n");
  355. xhci_dbg_erst(xhci, &xhci->erst);
  356. xhci_dbg(xhci, "Event ring:\n");
  357. xhci_debug_ring(xhci, xhci->event_ring);
  358. xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
  359. temp = xhci_readl(xhci, &xhci->ir_set->erst_dequeue[1]);
  360. xhci_dbg(xhci, "ERST deq upper = 0x%x\n", temp);
  361. temp = xhci_readl(xhci, &xhci->ir_set->erst_dequeue[0]);
  362. temp &= ERST_PTR_MASK;
  363. xhci_dbg(xhci, "ERST deq = 0x%x\n", temp);
  364. temp = xhci_readl(xhci, &xhci->op_regs->command);
  365. temp |= (CMD_RUN);
  366. xhci_dbg(xhci, "// Turn on HC, cmd = 0x%x.\n",
  367. temp);
  368. xhci_writel(xhci, temp, &xhci->op_regs->command);
  369. /* Flush PCI posted writes */
  370. temp = xhci_readl(xhci, &xhci->op_regs->command);
  371. xhci_dbg(xhci, "// @%x = 0x%x\n",
  372. (unsigned int) &xhci->op_regs->command, temp);
  373. if (doorbell)
  374. (*doorbell)(xhci);
  375. xhci_dbg(xhci, "Finished xhci_run\n");
  376. return 0;
  377. }
  378. /*
  379. * Stop xHCI driver.
  380. *
  381. * This function is called by the USB core when the HC driver is removed.
  382. * Its opposite is xhci_run().
  383. *
  384. * Disable device contexts, disable IRQs, and quiesce the HC.
  385. * Reset the HC, finish any completed transactions, and cleanup memory.
  386. */
  387. void xhci_stop(struct usb_hcd *hcd)
  388. {
  389. u32 temp;
  390. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  391. spin_lock_irq(&xhci->lock);
  392. if (HC_IS_RUNNING(hcd->state))
  393. xhci_quiesce(xhci);
  394. xhci_halt(xhci);
  395. xhci_reset(xhci);
  396. spin_unlock_irq(&xhci->lock);
  397. #if 0 /* No MSI yet */
  398. xhci_cleanup_msix(xhci);
  399. #endif
  400. #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
  401. /* Tell the event ring poll function not to reschedule */
  402. xhci->zombie = 1;
  403. del_timer_sync(&xhci->event_ring_timer);
  404. #endif
  405. xhci_dbg(xhci, "// Disabling event ring interrupts\n");
  406. temp = xhci_readl(xhci, &xhci->op_regs->status);
  407. xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
  408. temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  409. xhci_writel(xhci, ER_IRQ_DISABLE(temp),
  410. &xhci->ir_set->irq_pending);
  411. xhci_print_ir_set(xhci, xhci->ir_set, 0);
  412. xhci_dbg(xhci, "cleaning up memory\n");
  413. xhci_mem_cleanup(xhci);
  414. xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
  415. xhci_readl(xhci, &xhci->op_regs->status));
  416. }
  417. /*
  418. * Shutdown HC (not bus-specific)
  419. *
  420. * This is called when the machine is rebooting or halting. We assume that the
  421. * machine will be powered off, and the HC's internal state will be reset.
  422. * Don't bother to free memory.
  423. */
  424. void xhci_shutdown(struct usb_hcd *hcd)
  425. {
  426. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  427. spin_lock_irq(&xhci->lock);
  428. xhci_halt(xhci);
  429. spin_unlock_irq(&xhci->lock);
  430. #if 0
  431. xhci_cleanup_msix(xhci);
  432. #endif
  433. xhci_dbg(xhci, "xhci_shutdown completed - status = %x\n",
  434. xhci_readl(xhci, &xhci->op_regs->status));
  435. }
  436. /*-------------------------------------------------------------------------*/
  437. int xhci_get_frame(struct usb_hcd *hcd)
  438. {
  439. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  440. /* EHCI mods by the periodic size. Why? */
  441. return xhci_readl(xhci, &xhci->run_regs->microframe_index) >> 3;
  442. }
  443. MODULE_DESCRIPTION(DRIVER_DESC);
  444. MODULE_AUTHOR(DRIVER_AUTHOR);
  445. MODULE_LICENSE("GPL");
  446. static int __init xhci_hcd_init(void)
  447. {
  448. #ifdef CONFIG_PCI
  449. int retval = 0;
  450. retval = xhci_register_pci();
  451. if (retval < 0) {
  452. printk(KERN_DEBUG "Problem registering PCI driver.");
  453. return retval;
  454. }
  455. #endif
  456. return 0;
  457. }
  458. module_init(xhci_hcd_init);
  459. static void __exit xhci_hcd_cleanup(void)
  460. {
  461. #ifdef CONFIG_PCI
  462. xhci_unregister_pci();
  463. #endif
  464. }
  465. module_exit(xhci_hcd_cleanup);