mac-fec.c 13 KB

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  1. /*
  2. * Freescale Ethernet controllers
  3. *
  4. * Copyright (c) 2005 Intracom S.A.
  5. * by Pantelis Antoniou <panto@intracom.gr>
  6. *
  7. * 2005 (c) MontaVista Software, Inc.
  8. * Vitaly Bordug <vbordug@ru.mvista.com>
  9. *
  10. * This file is licensed under the terms of the GNU General Public License
  11. * version 2. This program is licensed "as is" without any warranty of any
  12. * kind, whether express or implied.
  13. */
  14. #include <linux/module.h>
  15. #include <linux/kernel.h>
  16. #include <linux/types.h>
  17. #include <linux/sched.h>
  18. #include <linux/string.h>
  19. #include <linux/ptrace.h>
  20. #include <linux/errno.h>
  21. #include <linux/ioport.h>
  22. #include <linux/slab.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/pci.h>
  25. #include <linux/init.h>
  26. #include <linux/delay.h>
  27. #include <linux/netdevice.h>
  28. #include <linux/etherdevice.h>
  29. #include <linux/skbuff.h>
  30. #include <linux/spinlock.h>
  31. #include <linux/mii.h>
  32. #include <linux/ethtool.h>
  33. #include <linux/bitops.h>
  34. #include <linux/fs.h>
  35. #include <linux/platform_device.h>
  36. #include <asm/irq.h>
  37. #include <asm/uaccess.h>
  38. #ifdef CONFIG_8xx
  39. #include <asm/8xx_immap.h>
  40. #include <asm/pgtable.h>
  41. #include <asm/mpc8xx.h>
  42. #include <asm/commproc.h>
  43. #endif
  44. #include "fs_enet.h"
  45. #include "fec.h"
  46. /*************************************************/
  47. #if defined(CONFIG_CPM1)
  48. /* for a CPM1 __raw_xxx's are sufficient */
  49. #define __fs_out32(addr, x) __raw_writel(x, addr)
  50. #define __fs_out16(addr, x) __raw_writew(x, addr)
  51. #define __fs_in32(addr) __raw_readl(addr)
  52. #define __fs_in16(addr) __raw_readw(addr)
  53. #else
  54. /* for others play it safe */
  55. #define __fs_out32(addr, x) out_be32(addr, x)
  56. #define __fs_out16(addr, x) out_be16(addr, x)
  57. #define __fs_in32(addr) in_be32(addr)
  58. #define __fs_in16(addr) in_be16(addr)
  59. #endif
  60. /* write */
  61. #define FW(_fecp, _reg, _v) __fs_out32(&(_fecp)->fec_ ## _reg, (_v))
  62. /* read */
  63. #define FR(_fecp, _reg) __fs_in32(&(_fecp)->fec_ ## _reg)
  64. /* set bits */
  65. #define FS(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) | (_v))
  66. /* clear bits */
  67. #define FC(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) & ~(_v))
  68. /*
  69. * Delay to wait for FEC reset command to complete (in us)
  70. */
  71. #define FEC_RESET_DELAY 50
  72. static int whack_reset(fec_t * fecp)
  73. {
  74. int i;
  75. FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
  76. for (i = 0; i < FEC_RESET_DELAY; i++) {
  77. if ((FR(fecp, ecntrl) & FEC_ECNTRL_RESET) == 0)
  78. return 0; /* OK */
  79. udelay(1);
  80. }
  81. return -1;
  82. }
  83. static int do_pd_setup(struct fs_enet_private *fep)
  84. {
  85. struct platform_device *pdev = to_platform_device(fep->dev);
  86. struct resource *r;
  87. /* Fill out IRQ field */
  88. fep->interrupt = platform_get_irq_byname(pdev,"interrupt");
  89. if (fep->interrupt < 0)
  90. return -EINVAL;
  91. r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
  92. fep->fec.fecp = ioremap(r->start, r->end - r->start + 1);
  93. if(fep->fec.fecp == NULL)
  94. return -EINVAL;
  95. return 0;
  96. }
  97. #define FEC_NAPI_RX_EVENT_MSK (FEC_ENET_RXF | FEC_ENET_RXB)
  98. #define FEC_RX_EVENT (FEC_ENET_RXF)
  99. #define FEC_TX_EVENT (FEC_ENET_TXF)
  100. #define FEC_ERR_EVENT_MSK (FEC_ENET_HBERR | FEC_ENET_BABR | \
  101. FEC_ENET_BABT | FEC_ENET_EBERR)
  102. static int setup_data(struct net_device *dev)
  103. {
  104. struct fs_enet_private *fep = netdev_priv(dev);
  105. if (do_pd_setup(fep) != 0)
  106. return -EINVAL;
  107. fep->fec.hthi = 0;
  108. fep->fec.htlo = 0;
  109. fep->ev_napi_rx = FEC_NAPI_RX_EVENT_MSK;
  110. fep->ev_rx = FEC_RX_EVENT;
  111. fep->ev_tx = FEC_TX_EVENT;
  112. fep->ev_err = FEC_ERR_EVENT_MSK;
  113. return 0;
  114. }
  115. static int allocate_bd(struct net_device *dev)
  116. {
  117. struct fs_enet_private *fep = netdev_priv(dev);
  118. const struct fs_platform_info *fpi = fep->fpi;
  119. fep->ring_base = dma_alloc_coherent(fep->dev,
  120. (fpi->tx_ring + fpi->rx_ring) *
  121. sizeof(cbd_t), &fep->ring_mem_addr,
  122. GFP_KERNEL);
  123. if (fep->ring_base == NULL)
  124. return -ENOMEM;
  125. return 0;
  126. }
  127. static void free_bd(struct net_device *dev)
  128. {
  129. struct fs_enet_private *fep = netdev_priv(dev);
  130. const struct fs_platform_info *fpi = fep->fpi;
  131. if(fep->ring_base)
  132. dma_free_coherent(fep->dev, (fpi->tx_ring + fpi->rx_ring)
  133. * sizeof(cbd_t),
  134. fep->ring_base,
  135. fep->ring_mem_addr);
  136. }
  137. static void cleanup_data(struct net_device *dev)
  138. {
  139. /* nothing */
  140. }
  141. static void set_promiscuous_mode(struct net_device *dev)
  142. {
  143. struct fs_enet_private *fep = netdev_priv(dev);
  144. fec_t *fecp = fep->fec.fecp;
  145. FS(fecp, r_cntrl, FEC_RCNTRL_PROM);
  146. }
  147. static void set_multicast_start(struct net_device *dev)
  148. {
  149. struct fs_enet_private *fep = netdev_priv(dev);
  150. fep->fec.hthi = 0;
  151. fep->fec.htlo = 0;
  152. }
  153. static void set_multicast_one(struct net_device *dev, const u8 *mac)
  154. {
  155. struct fs_enet_private *fep = netdev_priv(dev);
  156. int temp, hash_index, i, j;
  157. u32 crc, csrVal;
  158. u8 byte, msb;
  159. crc = 0xffffffff;
  160. for (i = 0; i < 6; i++) {
  161. byte = mac[i];
  162. for (j = 0; j < 8; j++) {
  163. msb = crc >> 31;
  164. crc <<= 1;
  165. if (msb ^ (byte & 0x1))
  166. crc ^= FEC_CRC_POLY;
  167. byte >>= 1;
  168. }
  169. }
  170. temp = (crc & 0x3f) >> 1;
  171. hash_index = ((temp & 0x01) << 4) |
  172. ((temp & 0x02) << 2) |
  173. ((temp & 0x04)) |
  174. ((temp & 0x08) >> 2) |
  175. ((temp & 0x10) >> 4);
  176. csrVal = 1 << hash_index;
  177. if (crc & 1)
  178. fep->fec.hthi |= csrVal;
  179. else
  180. fep->fec.htlo |= csrVal;
  181. }
  182. static void set_multicast_finish(struct net_device *dev)
  183. {
  184. struct fs_enet_private *fep = netdev_priv(dev);
  185. fec_t *fecp = fep->fec.fecp;
  186. /* if all multi or too many multicasts; just enable all */
  187. if ((dev->flags & IFF_ALLMULTI) != 0 ||
  188. dev->mc_count > FEC_MAX_MULTICAST_ADDRS) {
  189. fep->fec.hthi = 0xffffffffU;
  190. fep->fec.htlo = 0xffffffffU;
  191. }
  192. FC(fecp, r_cntrl, FEC_RCNTRL_PROM);
  193. FW(fecp, hash_table_high, fep->fec.hthi);
  194. FW(fecp, hash_table_low, fep->fec.htlo);
  195. }
  196. static void set_multicast_list(struct net_device *dev)
  197. {
  198. struct dev_mc_list *pmc;
  199. if ((dev->flags & IFF_PROMISC) == 0) {
  200. set_multicast_start(dev);
  201. for (pmc = dev->mc_list; pmc != NULL; pmc = pmc->next)
  202. set_multicast_one(dev, pmc->dmi_addr);
  203. set_multicast_finish(dev);
  204. } else
  205. set_promiscuous_mode(dev);
  206. }
  207. static void restart(struct net_device *dev)
  208. {
  209. #ifdef CONFIG_DUET
  210. immap_t *immap = fs_enet_immap;
  211. u32 cptr;
  212. #endif
  213. struct fs_enet_private *fep = netdev_priv(dev);
  214. fec_t *fecp = fep->fec.fecp;
  215. const struct fs_platform_info *fpi = fep->fpi;
  216. dma_addr_t rx_bd_base_phys, tx_bd_base_phys;
  217. int r;
  218. u32 addrhi, addrlo;
  219. struct mii_bus* mii = fep->phydev->bus;
  220. struct fec_info* fec_inf = mii->priv;
  221. r = whack_reset(fep->fec.fecp);
  222. if (r != 0)
  223. printk(KERN_ERR DRV_MODULE_NAME
  224. ": %s FEC Reset FAILED!\n", dev->name);
  225. /*
  226. * Set station address.
  227. */
  228. addrhi = ((u32) dev->dev_addr[0] << 24) |
  229. ((u32) dev->dev_addr[1] << 16) |
  230. ((u32) dev->dev_addr[2] << 8) |
  231. (u32) dev->dev_addr[3];
  232. addrlo = ((u32) dev->dev_addr[4] << 24) |
  233. ((u32) dev->dev_addr[5] << 16);
  234. FW(fecp, addr_low, addrhi);
  235. FW(fecp, addr_high, addrlo);
  236. /*
  237. * Reset all multicast.
  238. */
  239. FW(fecp, hash_table_high, fep->fec.hthi);
  240. FW(fecp, hash_table_low, fep->fec.htlo);
  241. /*
  242. * Set maximum receive buffer size.
  243. */
  244. FW(fecp, r_buff_size, PKT_MAXBLR_SIZE);
  245. FW(fecp, r_hash, PKT_MAXBUF_SIZE);
  246. /* get physical address */
  247. rx_bd_base_phys = fep->ring_mem_addr;
  248. tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring;
  249. /*
  250. * Set receive and transmit descriptor base.
  251. */
  252. FW(fecp, r_des_start, rx_bd_base_phys);
  253. FW(fecp, x_des_start, tx_bd_base_phys);
  254. fs_init_bds(dev);
  255. /*
  256. * Enable big endian and don't care about SDMA FC.
  257. */
  258. FW(fecp, fun_code, 0x78000000);
  259. /*
  260. * Set MII speed.
  261. */
  262. FW(fecp, mii_speed, fec_inf->mii_speed);
  263. /*
  264. * Clear any outstanding interrupt.
  265. */
  266. FW(fecp, ievent, 0xffc0);
  267. #ifndef CONFIG_PPC_MERGE
  268. FW(fecp, ivec, (fep->interrupt / 2) << 29);
  269. #else
  270. FW(fecp, ivec, (virq_to_hw(fep->interrupt) / 2) << 29);
  271. #endif
  272. /*
  273. * adjust to speed (only for DUET & RMII)
  274. */
  275. #ifdef CONFIG_DUET
  276. if (fpi->use_rmii) {
  277. cptr = in_be32(&immap->im_cpm.cp_cptr);
  278. switch (fs_get_fec_index(fpi->fs_no)) {
  279. case 0:
  280. cptr |= 0x100;
  281. if (fep->speed == 10)
  282. cptr |= 0x0000010;
  283. else if (fep->speed == 100)
  284. cptr &= ~0x0000010;
  285. break;
  286. case 1:
  287. cptr |= 0x80;
  288. if (fep->speed == 10)
  289. cptr |= 0x0000008;
  290. else if (fep->speed == 100)
  291. cptr &= ~0x0000008;
  292. break;
  293. default:
  294. BUG(); /* should never happen */
  295. break;
  296. }
  297. out_be32(&immap->im_cpm.cp_cptr, cptr);
  298. }
  299. #endif
  300. FW(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
  301. /*
  302. * adjust to duplex mode
  303. */
  304. if (fep->phydev->duplex) {
  305. FC(fecp, r_cntrl, FEC_RCNTRL_DRT);
  306. FS(fecp, x_cntrl, FEC_TCNTRL_FDEN); /* FD enable */
  307. } else {
  308. FS(fecp, r_cntrl, FEC_RCNTRL_DRT);
  309. FC(fecp, x_cntrl, FEC_TCNTRL_FDEN); /* FD disable */
  310. }
  311. /*
  312. * Enable interrupts we wish to service.
  313. */
  314. FW(fecp, imask, FEC_ENET_TXF | FEC_ENET_TXB |
  315. FEC_ENET_RXF | FEC_ENET_RXB);
  316. /*
  317. * And last, enable the transmit and receive processing.
  318. */
  319. FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
  320. FW(fecp, r_des_active, 0x01000000);
  321. }
  322. static void stop(struct net_device *dev)
  323. {
  324. struct fs_enet_private *fep = netdev_priv(dev);
  325. const struct fs_platform_info *fpi = fep->fpi;
  326. fec_t *fecp = fep->fec.fecp;
  327. struct fec_info* feci= fep->phydev->bus->priv;
  328. int i;
  329. if ((FR(fecp, ecntrl) & FEC_ECNTRL_ETHER_EN) == 0)
  330. return; /* already down */
  331. FW(fecp, x_cntrl, 0x01); /* Graceful transmit stop */
  332. for (i = 0; ((FR(fecp, ievent) & 0x10000000) == 0) &&
  333. i < FEC_RESET_DELAY; i++)
  334. udelay(1);
  335. if (i == FEC_RESET_DELAY)
  336. printk(KERN_WARNING DRV_MODULE_NAME
  337. ": %s FEC timeout on graceful transmit stop\n",
  338. dev->name);
  339. /*
  340. * Disable FEC. Let only MII interrupts.
  341. */
  342. FW(fecp, imask, 0);
  343. FC(fecp, ecntrl, FEC_ECNTRL_ETHER_EN);
  344. fs_cleanup_bds(dev);
  345. /* shut down FEC1? that's where the mii bus is */
  346. if (fpi->has_phy) {
  347. FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
  348. FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
  349. FW(fecp, ievent, FEC_ENET_MII);
  350. FW(fecp, mii_speed, feci->mii_speed);
  351. }
  352. }
  353. static void pre_request_irq(struct net_device *dev, int irq)
  354. {
  355. #ifndef CONFIG_PPC_MERGE
  356. immap_t *immap = fs_enet_immap;
  357. u32 siel;
  358. /* SIU interrupt */
  359. if (irq >= SIU_IRQ0 && irq < SIU_LEVEL7) {
  360. siel = in_be32(&immap->im_siu_conf.sc_siel);
  361. if ((irq & 1) == 0)
  362. siel |= (0x80000000 >> irq);
  363. else
  364. siel &= ~(0x80000000 >> (irq & ~1));
  365. out_be32(&immap->im_siu_conf.sc_siel, siel);
  366. }
  367. #endif
  368. }
  369. static void post_free_irq(struct net_device *dev, int irq)
  370. {
  371. /* nothing */
  372. }
  373. static void napi_clear_rx_event(struct net_device *dev)
  374. {
  375. struct fs_enet_private *fep = netdev_priv(dev);
  376. fec_t *fecp = fep->fec.fecp;
  377. FW(fecp, ievent, FEC_NAPI_RX_EVENT_MSK);
  378. }
  379. static void napi_enable_rx(struct net_device *dev)
  380. {
  381. struct fs_enet_private *fep = netdev_priv(dev);
  382. fec_t *fecp = fep->fec.fecp;
  383. FS(fecp, imask, FEC_NAPI_RX_EVENT_MSK);
  384. }
  385. static void napi_disable_rx(struct net_device *dev)
  386. {
  387. struct fs_enet_private *fep = netdev_priv(dev);
  388. fec_t *fecp = fep->fec.fecp;
  389. FC(fecp, imask, FEC_NAPI_RX_EVENT_MSK);
  390. }
  391. static void rx_bd_done(struct net_device *dev)
  392. {
  393. struct fs_enet_private *fep = netdev_priv(dev);
  394. fec_t *fecp = fep->fec.fecp;
  395. FW(fecp, r_des_active, 0x01000000);
  396. }
  397. static void tx_kickstart(struct net_device *dev)
  398. {
  399. struct fs_enet_private *fep = netdev_priv(dev);
  400. fec_t *fecp = fep->fec.fecp;
  401. FW(fecp, x_des_active, 0x01000000);
  402. }
  403. static u32 get_int_events(struct net_device *dev)
  404. {
  405. struct fs_enet_private *fep = netdev_priv(dev);
  406. fec_t *fecp = fep->fec.fecp;
  407. return FR(fecp, ievent) & FR(fecp, imask);
  408. }
  409. static void clear_int_events(struct net_device *dev, u32 int_events)
  410. {
  411. struct fs_enet_private *fep = netdev_priv(dev);
  412. fec_t *fecp = fep->fec.fecp;
  413. FW(fecp, ievent, int_events);
  414. }
  415. static void ev_error(struct net_device *dev, u32 int_events)
  416. {
  417. printk(KERN_WARNING DRV_MODULE_NAME
  418. ": %s FEC ERROR(s) 0x%x\n", dev->name, int_events);
  419. }
  420. int get_regs(struct net_device *dev, void *p, int *sizep)
  421. {
  422. struct fs_enet_private *fep = netdev_priv(dev);
  423. if (*sizep < sizeof(fec_t))
  424. return -EINVAL;
  425. memcpy_fromio(p, fep->fec.fecp, sizeof(fec_t));
  426. return 0;
  427. }
  428. int get_regs_len(struct net_device *dev)
  429. {
  430. return sizeof(fec_t);
  431. }
  432. void tx_restart(struct net_device *dev)
  433. {
  434. /* nothing */
  435. }
  436. /*************************************************************************/
  437. const struct fs_ops fs_fec_ops = {
  438. .setup_data = setup_data,
  439. .cleanup_data = cleanup_data,
  440. .set_multicast_list = set_multicast_list,
  441. .restart = restart,
  442. .stop = stop,
  443. .pre_request_irq = pre_request_irq,
  444. .post_free_irq = post_free_irq,
  445. .napi_clear_rx_event = napi_clear_rx_event,
  446. .napi_enable_rx = napi_enable_rx,
  447. .napi_disable_rx = napi_disable_rx,
  448. .rx_bd_done = rx_bd_done,
  449. .tx_kickstart = tx_kickstart,
  450. .get_int_events = get_int_events,
  451. .clear_int_events = clear_int_events,
  452. .ev_error = ev_error,
  453. .get_regs = get_regs,
  454. .get_regs_len = get_regs_len,
  455. .tx_restart = tx_restart,
  456. .allocate_bd = allocate_bd,
  457. .free_bd = free_bd,
  458. };