firmware_exports.h 5.0 KB

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  1. /*
  2. * ----------------------------------------------------------------------------
  3. * >>>>>>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<
  4. * ----------------------------------------------------------------------------
  5. * Copyright 2004 (C) Chelsio Communications, Inc. (Chelsio)
  6. *
  7. * Chelsio Communications, Inc. owns the sole copyright to this software.
  8. * You may not make a copy, you may not derive works herefrom, and you may
  9. * not distribute this work to others. Other restrictions of rights may apply
  10. * as well. This is unpublished, confidential information. All rights reserved.
  11. * This software contains confidential information and trade secrets of Chelsio
  12. * Communications, Inc. Use, disclosure, or reproduction is prohibited without
  13. * the prior express written permission of Chelsio Communications, Inc.
  14. * ----------------------------------------------------------------------------
  15. * >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> Warranty <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
  16. * ----------------------------------------------------------------------------
  17. * CHELSIO MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THE USE OF THIS
  18. * SOFTWARE, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO, THE
  19. * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
  20. * ----------------------------------------------------------------------------
  21. *
  22. * This is the firmware_exports.h header file, firmware interface defines.
  23. *
  24. * Written January 2005 by felix marti (felix@chelsio.com)
  25. */
  26. #ifndef _FIRMWARE_EXPORTS_H_
  27. #define _FIRMWARE_EXPORTS_H_
  28. /* WR OPCODES supported by the firmware.
  29. */
  30. #define FW_WROPCODE_FORWARD 0x01
  31. #define FW_WROPCODE_BYPASS 0x05
  32. #define FW_WROPCODE_TUNNEL_TX_PKT 0x03
  33. #define FW_WROPOCDE_ULPTX_DATA_SGL 0x00
  34. #define FW_WROPCODE_ULPTX_MEM_READ 0x02
  35. #define FW_WROPCODE_ULPTX_PKT 0x04
  36. #define FW_WROPCODE_ULPTX_INVALIDATE 0x06
  37. #define FW_WROPCODE_TUNNEL_RX_PKT 0x07
  38. #define FW_WROPCODE_OFLD_GETTCB_RPL 0x08
  39. #define FW_WROPCODE_OFLD_CLOSE_CON 0x09
  40. #define FW_WROPCODE_OFLD_TP_ABORT_CON_REQ 0x0A
  41. #define FW_WROPCODE_OFLD_HOST_ABORT_CON_RPL 0x0F
  42. #define FW_WROPCODE_OFLD_HOST_ABORT_CON_REQ 0x0B
  43. #define FW_WROPCODE_OFLD_TP_ABORT_CON_RPL 0x0C
  44. #define FW_WROPCODE_OFLD_TX_DATA 0x0D
  45. #define FW_WROPCODE_OFLD_TX_DATA_ACK 0x0E
  46. #define FW_WROPCODE_RI_RDMA_INIT 0x10
  47. #define FW_WROPCODE_RI_RDMA_WRITE 0x11
  48. #define FW_WROPCODE_RI_RDMA_READ_REQ 0x12
  49. #define FW_WROPCODE_RI_RDMA_READ_RESP 0x13
  50. #define FW_WROPCODE_RI_SEND 0x14
  51. #define FW_WROPCODE_RI_TERMINATE 0x15
  52. #define FW_WROPCODE_RI_RDMA_READ 0x16
  53. #define FW_WROPCODE_RI_RECEIVE 0x17
  54. #define FW_WROPCODE_RI_BIND_MW 0x18
  55. #define FW_WROPCODE_RI_FASTREGISTER_MR 0x19
  56. #define FW_WROPCODE_RI_LOCAL_INV 0x1A
  57. #define FW_WROPCODE_RI_MODIFY_QP 0x1B
  58. #define FW_WROPCODE_RI_BYPASS 0x1C
  59. #define FW_WROPOCDE_RSVD 0x1E
  60. #define FW_WROPCODE_SGE_EGRESSCONTEXT_RR 0x1F
  61. #define FW_WROPCODE_MNGT 0x1D
  62. #define FW_MNGTOPCODE_PKTSCHED_SET 0x00
  63. /* Maximum size of a WR sent from the host, limited by the SGE.
  64. *
  65. * Note: WR coming from ULP or TP are only limited by CIM.
  66. */
  67. #define FW_WR_SIZE 128
  68. /* Maximum number of outstanding WRs sent from the host. Value must be
  69. * programmed in the CTRL/TUNNEL/QP SGE Egress Context and used by
  70. * offload modules to limit the number of WRs per connection.
  71. */
  72. #define FW_T3_WR_NUM 16
  73. #define FW_N3_WR_NUM 7
  74. #ifndef N3
  75. # define FW_WR_NUM FW_T3_WR_NUM
  76. #else
  77. # define FW_WR_NUM FW_N3_WR_NUM
  78. #endif
  79. /* FW_TUNNEL_NUM corresponds to the number of supported TUNNEL Queues. These
  80. * queues must start at SGE Egress Context FW_TUNNEL_SGEEC_START and must
  81. * start at 'TID' (or 'uP Token') FW_TUNNEL_TID_START.
  82. *
  83. * Ingress Traffic (e.g. DMA completion credit) for TUNNEL Queue[i] is sent
  84. * to RESP Queue[i].
  85. */
  86. #define FW_TUNNEL_NUM 8
  87. #define FW_TUNNEL_SGEEC_START 8
  88. #define FW_TUNNEL_TID_START 65544
  89. /* FW_CTRL_NUM corresponds to the number of supported CTRL Queues. These queues
  90. * must start at SGE Egress Context FW_CTRL_SGEEC_START and must start at 'TID'
  91. * (or 'uP Token') FW_CTRL_TID_START.
  92. *
  93. * Ingress Traffic for CTRL Queue[i] is sent to RESP Queue[i].
  94. */
  95. #define FW_CTRL_NUM 8
  96. #define FW_CTRL_SGEEC_START 65528
  97. #define FW_CTRL_TID_START 65536
  98. /* FW_OFLD_NUM corresponds to the number of supported OFFLOAD Queues. These
  99. * queues must start at SGE Egress Context FW_OFLD_SGEEC_START.
  100. *
  101. * Note: the 'uP Token' in the SGE Egress Context fields is irrelevant for
  102. * OFFLOAD Queues, as the host is responsible for providing the correct TID in
  103. * every WR.
  104. *
  105. * Ingress Trafffic for OFFLOAD Queue[i] is sent to RESP Queue[i].
  106. */
  107. #define FW_OFLD_NUM 8
  108. #define FW_OFLD_SGEEC_START 0
  109. /*
  110. *
  111. */
  112. #define FW_RI_NUM 1
  113. #define FW_RI_SGEEC_START 65527
  114. #define FW_RI_TID_START 65552
  115. /*
  116. * The RX_PKT_TID
  117. */
  118. #define FW_RX_PKT_NUM 1
  119. #define FW_RX_PKT_TID_START 65553
  120. /* FW_WRC_NUM corresponds to the number of Work Request Context that supported
  121. * by the firmware.
  122. */
  123. #define FW_WRC_NUM \
  124. (65536 + FW_TUNNEL_NUM + FW_CTRL_NUM + FW_RI_NUM + FW_RX_PKT_NUM)
  125. #endif /* _FIRMWARE_EXPORTS_H_ */