common.h 22 KB

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  1. /*
  2. * This file is part of the Chelsio T3 Ethernet driver.
  3. *
  4. * Copyright (C) 2005-2006 Chelsio Communications. All rights reserved.
  5. *
  6. * This program is distributed in the hope that it will be useful, but WITHOUT
  7. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  8. * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this
  9. * release for licensing terms and conditions.
  10. */
  11. #ifndef __CHELSIO_COMMON_H
  12. #define __CHELSIO_COMMON_H
  13. #include <linux/kernel.h>
  14. #include <linux/types.h>
  15. #include <linux/ctype.h>
  16. #include <linux/delay.h>
  17. #include <linux/init.h>
  18. #include <linux/netdevice.h>
  19. #include <linux/ethtool.h>
  20. #include <linux/mii.h>
  21. #include "version.h"
  22. #define CH_ERR(adap, fmt, ...) dev_err(&adap->pdev->dev, fmt, ## __VA_ARGS__)
  23. #define CH_WARN(adap, fmt, ...) dev_warn(&adap->pdev->dev, fmt, ## __VA_ARGS__)
  24. #define CH_ALERT(adap, fmt, ...) \
  25. dev_printk(KERN_ALERT, &adap->pdev->dev, fmt, ## __VA_ARGS__)
  26. /*
  27. * More powerful macro that selectively prints messages based on msg_enable.
  28. * For info and debugging messages.
  29. */
  30. #define CH_MSG(adapter, level, category, fmt, ...) do { \
  31. if ((adapter)->msg_enable & NETIF_MSG_##category) \
  32. dev_printk(KERN_##level, &adapter->pdev->dev, fmt, \
  33. ## __VA_ARGS__); \
  34. } while (0)
  35. #ifdef DEBUG
  36. # define CH_DBG(adapter, category, fmt, ...) \
  37. CH_MSG(adapter, DEBUG, category, fmt, ## __VA_ARGS__)
  38. #else
  39. # define CH_DBG(adapter, category, fmt, ...)
  40. #endif
  41. /* Additional NETIF_MSG_* categories */
  42. #define NETIF_MSG_MMIO 0x8000000
  43. struct t3_rx_mode {
  44. struct net_device *dev;
  45. struct dev_mc_list *mclist;
  46. unsigned int idx;
  47. };
  48. static inline void init_rx_mode(struct t3_rx_mode *p, struct net_device *dev,
  49. struct dev_mc_list *mclist)
  50. {
  51. p->dev = dev;
  52. p->mclist = mclist;
  53. p->idx = 0;
  54. }
  55. static inline u8 *t3_get_next_mcaddr(struct t3_rx_mode *rm)
  56. {
  57. u8 *addr = NULL;
  58. if (rm->mclist && rm->idx < rm->dev->mc_count) {
  59. addr = rm->mclist->dmi_addr;
  60. rm->mclist = rm->mclist->next;
  61. rm->idx++;
  62. }
  63. return addr;
  64. }
  65. enum {
  66. MAX_NPORTS = 2, /* max # of ports */
  67. MAX_FRAME_SIZE = 10240, /* max MAC frame size, including header + FCS */
  68. EEPROMSIZE = 8192, /* Serial EEPROM size */
  69. RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */
  70. TCB_SIZE = 128, /* TCB size */
  71. NMTUS = 16, /* size of MTU table */
  72. NCCTRL_WIN = 32, /* # of congestion control windows */
  73. };
  74. #define MAX_RX_COALESCING_LEN 16224U
  75. enum {
  76. PAUSE_RX = 1 << 0,
  77. PAUSE_TX = 1 << 1,
  78. PAUSE_AUTONEG = 1 << 2
  79. };
  80. enum {
  81. SUPPORTED_OFFLOAD = 1 << 24,
  82. SUPPORTED_IRQ = 1 << 25
  83. };
  84. enum { /* adapter interrupt-maintained statistics */
  85. STAT_ULP_CH0_PBL_OOB,
  86. STAT_ULP_CH1_PBL_OOB,
  87. STAT_PCI_CORR_ECC,
  88. IRQ_NUM_STATS /* keep last */
  89. };
  90. enum {
  91. SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */
  92. SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */
  93. SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */
  94. };
  95. enum sge_context_type { /* SGE egress context types */
  96. SGE_CNTXT_RDMA = 0,
  97. SGE_CNTXT_ETH = 2,
  98. SGE_CNTXT_OFLD = 4,
  99. SGE_CNTXT_CTRL = 5
  100. };
  101. enum {
  102. AN_PKT_SIZE = 32, /* async notification packet size */
  103. IMMED_PKT_SIZE = 48 /* packet size for immediate data */
  104. };
  105. struct sg_ent { /* SGE scatter/gather entry */
  106. u32 len[2];
  107. u64 addr[2];
  108. };
  109. #ifndef SGE_NUM_GENBITS
  110. /* Must be 1 or 2 */
  111. # define SGE_NUM_GENBITS 2
  112. #endif
  113. #define TX_DESC_FLITS 16U
  114. #define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS)
  115. struct cphy;
  116. struct adapter;
  117. struct mdio_ops {
  118. int (*read)(struct adapter *adapter, int phy_addr, int mmd_addr,
  119. int reg_addr, unsigned int *val);
  120. int (*write)(struct adapter *adapter, int phy_addr, int mmd_addr,
  121. int reg_addr, unsigned int val);
  122. };
  123. struct adapter_info {
  124. unsigned char nports; /* # of ports */
  125. unsigned char phy_base_addr; /* MDIO PHY base address */
  126. unsigned char mdien;
  127. unsigned char mdiinv;
  128. unsigned int gpio_out; /* GPIO output settings */
  129. unsigned int gpio_intr; /* GPIO IRQ enable mask */
  130. unsigned long caps; /* adapter capabilities */
  131. const struct mdio_ops *mdio_ops; /* MDIO operations */
  132. const char *desc; /* product description */
  133. };
  134. struct port_type_info {
  135. void (*phy_prep)(struct cphy *phy, struct adapter *adapter,
  136. int phy_addr, const struct mdio_ops *ops);
  137. unsigned int caps;
  138. const char *desc;
  139. };
  140. struct mc5_stats {
  141. unsigned long parity_err;
  142. unsigned long active_rgn_full;
  143. unsigned long nfa_srch_err;
  144. unsigned long unknown_cmd;
  145. unsigned long reqq_parity_err;
  146. unsigned long dispq_parity_err;
  147. unsigned long del_act_empty;
  148. };
  149. struct mc7_stats {
  150. unsigned long corr_err;
  151. unsigned long uncorr_err;
  152. unsigned long parity_err;
  153. unsigned long addr_err;
  154. };
  155. struct mac_stats {
  156. u64 tx_octets; /* total # of octets in good frames */
  157. u64 tx_octets_bad; /* total # of octets in error frames */
  158. u64 tx_frames; /* all good frames */
  159. u64 tx_mcast_frames; /* good multicast frames */
  160. u64 tx_bcast_frames; /* good broadcast frames */
  161. u64 tx_pause; /* # of transmitted pause frames */
  162. u64 tx_deferred; /* frames with deferred transmissions */
  163. u64 tx_late_collisions; /* # of late collisions */
  164. u64 tx_total_collisions; /* # of total collisions */
  165. u64 tx_excess_collisions; /* frame errors from excessive collissions */
  166. u64 tx_underrun; /* # of Tx FIFO underruns */
  167. u64 tx_len_errs; /* # of Tx length errors */
  168. u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */
  169. u64 tx_excess_deferral; /* # of frames with excessive deferral */
  170. u64 tx_fcs_errs; /* # of frames with bad FCS */
  171. u64 tx_frames_64; /* # of Tx frames in a particular range */
  172. u64 tx_frames_65_127;
  173. u64 tx_frames_128_255;
  174. u64 tx_frames_256_511;
  175. u64 tx_frames_512_1023;
  176. u64 tx_frames_1024_1518;
  177. u64 tx_frames_1519_max;
  178. u64 rx_octets; /* total # of octets in good frames */
  179. u64 rx_octets_bad; /* total # of octets in error frames */
  180. u64 rx_frames; /* all good frames */
  181. u64 rx_mcast_frames; /* good multicast frames */
  182. u64 rx_bcast_frames; /* good broadcast frames */
  183. u64 rx_pause; /* # of received pause frames */
  184. u64 rx_fcs_errs; /* # of received frames with bad FCS */
  185. u64 rx_align_errs; /* alignment errors */
  186. u64 rx_symbol_errs; /* symbol errors */
  187. u64 rx_data_errs; /* data errors */
  188. u64 rx_sequence_errs; /* sequence errors */
  189. u64 rx_runt; /* # of runt frames */
  190. u64 rx_jabber; /* # of jabber frames */
  191. u64 rx_short; /* # of short frames */
  192. u64 rx_too_long; /* # of oversized frames */
  193. u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */
  194. u64 rx_frames_64; /* # of Rx frames in a particular range */
  195. u64 rx_frames_65_127;
  196. u64 rx_frames_128_255;
  197. u64 rx_frames_256_511;
  198. u64 rx_frames_512_1023;
  199. u64 rx_frames_1024_1518;
  200. u64 rx_frames_1519_max;
  201. u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */
  202. unsigned long tx_fifo_parity_err;
  203. unsigned long rx_fifo_parity_err;
  204. unsigned long tx_fifo_urun;
  205. unsigned long rx_fifo_ovfl;
  206. unsigned long serdes_signal_loss;
  207. unsigned long xaui_pcs_ctc_err;
  208. unsigned long xaui_pcs_align_change;
  209. };
  210. struct tp_mib_stats {
  211. u32 ipInReceive_hi;
  212. u32 ipInReceive_lo;
  213. u32 ipInHdrErrors_hi;
  214. u32 ipInHdrErrors_lo;
  215. u32 ipInAddrErrors_hi;
  216. u32 ipInAddrErrors_lo;
  217. u32 ipInUnknownProtos_hi;
  218. u32 ipInUnknownProtos_lo;
  219. u32 ipInDiscards_hi;
  220. u32 ipInDiscards_lo;
  221. u32 ipInDelivers_hi;
  222. u32 ipInDelivers_lo;
  223. u32 ipOutRequests_hi;
  224. u32 ipOutRequests_lo;
  225. u32 ipOutDiscards_hi;
  226. u32 ipOutDiscards_lo;
  227. u32 ipOutNoRoutes_hi;
  228. u32 ipOutNoRoutes_lo;
  229. u32 ipReasmTimeout;
  230. u32 ipReasmReqds;
  231. u32 ipReasmOKs;
  232. u32 ipReasmFails;
  233. u32 reserved[8];
  234. u32 tcpActiveOpens;
  235. u32 tcpPassiveOpens;
  236. u32 tcpAttemptFails;
  237. u32 tcpEstabResets;
  238. u32 tcpOutRsts;
  239. u32 tcpCurrEstab;
  240. u32 tcpInSegs_hi;
  241. u32 tcpInSegs_lo;
  242. u32 tcpOutSegs_hi;
  243. u32 tcpOutSegs_lo;
  244. u32 tcpRetransSeg_hi;
  245. u32 tcpRetransSeg_lo;
  246. u32 tcpInErrs_hi;
  247. u32 tcpInErrs_lo;
  248. u32 tcpRtoMin;
  249. u32 tcpRtoMax;
  250. };
  251. struct tp_params {
  252. unsigned int nchan; /* # of channels */
  253. unsigned int pmrx_size; /* total PMRX capacity */
  254. unsigned int pmtx_size; /* total PMTX capacity */
  255. unsigned int cm_size; /* total CM capacity */
  256. unsigned int chan_rx_size; /* per channel Rx size */
  257. unsigned int chan_tx_size; /* per channel Tx size */
  258. unsigned int rx_pg_size; /* Rx page size */
  259. unsigned int tx_pg_size; /* Tx page size */
  260. unsigned int rx_num_pgs; /* # of Rx pages */
  261. unsigned int tx_num_pgs; /* # of Tx pages */
  262. unsigned int ntimer_qs; /* # of timer queues */
  263. };
  264. struct qset_params { /* SGE queue set parameters */
  265. unsigned int polling; /* polling/interrupt service for rspq */
  266. unsigned int coalesce_usecs; /* irq coalescing timer */
  267. unsigned int rspq_size; /* # of entries in response queue */
  268. unsigned int fl_size; /* # of entries in regular free list */
  269. unsigned int jumbo_size; /* # of entries in jumbo free list */
  270. unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */
  271. unsigned int cong_thres; /* FL congestion threshold */
  272. };
  273. struct sge_params {
  274. unsigned int max_pkt_size; /* max offload pkt size */
  275. struct qset_params qset[SGE_QSETS];
  276. };
  277. struct mc5_params {
  278. unsigned int mode; /* selects MC5 width */
  279. unsigned int nservers; /* size of server region */
  280. unsigned int nfilters; /* size of filter region */
  281. unsigned int nroutes; /* size of routing region */
  282. };
  283. /* Default MC5 region sizes */
  284. enum {
  285. DEFAULT_NSERVERS = 512,
  286. DEFAULT_NFILTERS = 128
  287. };
  288. /* MC5 modes, these must be non-0 */
  289. enum {
  290. MC5_MODE_144_BIT = 1,
  291. MC5_MODE_72_BIT = 2
  292. };
  293. struct vpd_params {
  294. unsigned int cclk;
  295. unsigned int mclk;
  296. unsigned int uclk;
  297. unsigned int mdc;
  298. unsigned int mem_timing;
  299. u8 eth_base[6];
  300. u8 port_type[MAX_NPORTS];
  301. unsigned short xauicfg[2];
  302. };
  303. struct pci_params {
  304. unsigned int vpd_cap_addr;
  305. unsigned int pcie_cap_addr;
  306. unsigned short speed;
  307. unsigned char width;
  308. unsigned char variant;
  309. };
  310. enum {
  311. PCI_VARIANT_PCI,
  312. PCI_VARIANT_PCIX_MODE1_PARITY,
  313. PCI_VARIANT_PCIX_MODE1_ECC,
  314. PCI_VARIANT_PCIX_266_MODE2,
  315. PCI_VARIANT_PCIE
  316. };
  317. struct adapter_params {
  318. struct sge_params sge;
  319. struct mc5_params mc5;
  320. struct tp_params tp;
  321. struct vpd_params vpd;
  322. struct pci_params pci;
  323. const struct adapter_info *info;
  324. unsigned short mtus[NMTUS];
  325. unsigned short a_wnd[NCCTRL_WIN];
  326. unsigned short b_wnd[NCCTRL_WIN];
  327. unsigned int nports; /* # of ethernet ports */
  328. unsigned int stats_update_period; /* MAC stats accumulation period */
  329. unsigned int linkpoll_period; /* link poll period in 0.1s */
  330. unsigned int rev; /* chip revision */
  331. };
  332. struct trace_params {
  333. u32 sip;
  334. u32 sip_mask;
  335. u32 dip;
  336. u32 dip_mask;
  337. u16 sport;
  338. u16 sport_mask;
  339. u16 dport;
  340. u16 dport_mask;
  341. u32 vlan:12;
  342. u32 vlan_mask:12;
  343. u32 intf:4;
  344. u32 intf_mask:4;
  345. u8 proto;
  346. u8 proto_mask;
  347. };
  348. struct link_config {
  349. unsigned int supported; /* link capabilities */
  350. unsigned int advertising; /* advertised capabilities */
  351. unsigned short requested_speed; /* speed user has requested */
  352. unsigned short speed; /* actual link speed */
  353. unsigned char requested_duplex; /* duplex user has requested */
  354. unsigned char duplex; /* actual link duplex */
  355. unsigned char requested_fc; /* flow control user has requested */
  356. unsigned char fc; /* actual link flow control */
  357. unsigned char autoneg; /* autonegotiating? */
  358. unsigned int link_ok; /* link up? */
  359. };
  360. #define SPEED_INVALID 0xffff
  361. #define DUPLEX_INVALID 0xff
  362. struct mc5 {
  363. struct adapter *adapter;
  364. unsigned int tcam_size;
  365. unsigned char part_type;
  366. unsigned char parity_enabled;
  367. unsigned char mode;
  368. struct mc5_stats stats;
  369. };
  370. static inline unsigned int t3_mc5_size(const struct mc5 *p)
  371. {
  372. return p->tcam_size;
  373. }
  374. struct mc7 {
  375. struct adapter *adapter; /* backpointer to adapter */
  376. unsigned int size; /* memory size in bytes */
  377. unsigned int width; /* MC7 interface width */
  378. unsigned int offset; /* register address offset for MC7 instance */
  379. const char *name; /* name of MC7 instance */
  380. struct mc7_stats stats; /* MC7 statistics */
  381. };
  382. static inline unsigned int t3_mc7_size(const struct mc7 *p)
  383. {
  384. return p->size;
  385. }
  386. struct cmac {
  387. struct adapter *adapter;
  388. unsigned int offset;
  389. unsigned int nucast; /* # of address filters for unicast MACs */
  390. struct mac_stats stats;
  391. };
  392. enum {
  393. MAC_DIRECTION_RX = 1,
  394. MAC_DIRECTION_TX = 2,
  395. MAC_RXFIFO_SIZE = 32768
  396. };
  397. /* IEEE 802.3ae specified MDIO devices */
  398. enum {
  399. MDIO_DEV_PMA_PMD = 1,
  400. MDIO_DEV_WIS = 2,
  401. MDIO_DEV_PCS = 3,
  402. MDIO_DEV_XGXS = 4
  403. };
  404. /* PHY loopback direction */
  405. enum {
  406. PHY_LOOPBACK_TX = 1,
  407. PHY_LOOPBACK_RX = 2
  408. };
  409. /* PHY interrupt types */
  410. enum {
  411. cphy_cause_link_change = 1,
  412. cphy_cause_fifo_error = 2
  413. };
  414. /* PHY operations */
  415. struct cphy_ops {
  416. void (*destroy)(struct cphy *phy);
  417. int (*reset)(struct cphy *phy, int wait);
  418. int (*intr_enable)(struct cphy *phy);
  419. int (*intr_disable)(struct cphy *phy);
  420. int (*intr_clear)(struct cphy *phy);
  421. int (*intr_handler)(struct cphy *phy);
  422. int (*autoneg_enable)(struct cphy *phy);
  423. int (*autoneg_restart)(struct cphy *phy);
  424. int (*advertise)(struct cphy *phy, unsigned int advertise_map);
  425. int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable);
  426. int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex);
  427. int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed,
  428. int *duplex, int *fc);
  429. int (*power_down)(struct cphy *phy, int enable);
  430. };
  431. /* A PHY instance */
  432. struct cphy {
  433. int addr; /* PHY address */
  434. struct adapter *adapter; /* associated adapter */
  435. unsigned long fifo_errors; /* FIFO over/under-flows */
  436. const struct cphy_ops *ops; /* PHY operations */
  437. int (*mdio_read)(struct adapter *adapter, int phy_addr, int mmd_addr,
  438. int reg_addr, unsigned int *val);
  439. int (*mdio_write)(struct adapter *adapter, int phy_addr, int mmd_addr,
  440. int reg_addr, unsigned int val);
  441. };
  442. /* Convenience MDIO read/write wrappers */
  443. static inline int mdio_read(struct cphy *phy, int mmd, int reg,
  444. unsigned int *valp)
  445. {
  446. return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp);
  447. }
  448. static inline int mdio_write(struct cphy *phy, int mmd, int reg,
  449. unsigned int val)
  450. {
  451. return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val);
  452. }
  453. /* Convenience initializer */
  454. static inline void cphy_init(struct cphy *phy, struct adapter *adapter,
  455. int phy_addr, struct cphy_ops *phy_ops,
  456. const struct mdio_ops *mdio_ops)
  457. {
  458. phy->adapter = adapter;
  459. phy->addr = phy_addr;
  460. phy->ops = phy_ops;
  461. if (mdio_ops) {
  462. phy->mdio_read = mdio_ops->read;
  463. phy->mdio_write = mdio_ops->write;
  464. }
  465. }
  466. /* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */
  467. #define MAC_STATS_ACCUM_SECS 180
  468. #define XGM_REG(reg_addr, idx) \
  469. ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR))
  470. struct addr_val_pair {
  471. unsigned int reg_addr;
  472. unsigned int val;
  473. };
  474. #include "adapter.h"
  475. #ifndef PCI_VENDOR_ID_CHELSIO
  476. # define PCI_VENDOR_ID_CHELSIO 0x1425
  477. #endif
  478. #define for_each_port(adapter, iter) \
  479. for (iter = 0; iter < (adapter)->params.nports; ++iter)
  480. #define adapter_info(adap) ((adap)->params.info)
  481. static inline int uses_xaui(const struct adapter *adap)
  482. {
  483. return adapter_info(adap)->caps & SUPPORTED_AUI;
  484. }
  485. static inline int is_10G(const struct adapter *adap)
  486. {
  487. return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full;
  488. }
  489. static inline int is_offload(const struct adapter *adap)
  490. {
  491. return adapter_info(adap)->caps & SUPPORTED_OFFLOAD;
  492. }
  493. static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
  494. {
  495. return adap->params.vpd.cclk / 1000;
  496. }
  497. static inline unsigned int is_pcie(const struct adapter *adap)
  498. {
  499. return adap->params.pci.variant == PCI_VARIANT_PCIE;
  500. }
  501. void t3_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
  502. u32 val);
  503. void t3_write_regs(struct adapter *adapter, const struct addr_val_pair *p,
  504. int n, unsigned int offset);
  505. int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
  506. int polarity, int attempts, int delay, u32 *valp);
  507. static inline int t3_wait_op_done(struct adapter *adapter, int reg, u32 mask,
  508. int polarity, int attempts, int delay)
  509. {
  510. return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts,
  511. delay, NULL);
  512. }
  513. int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,
  514. unsigned int set);
  515. int t3_phy_reset(struct cphy *phy, int mmd, int wait);
  516. int t3_phy_advertise(struct cphy *phy, unsigned int advert);
  517. int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex);
  518. void t3_intr_enable(struct adapter *adapter);
  519. void t3_intr_disable(struct adapter *adapter);
  520. void t3_intr_clear(struct adapter *adapter);
  521. void t3_port_intr_enable(struct adapter *adapter, int idx);
  522. void t3_port_intr_disable(struct adapter *adapter, int idx);
  523. void t3_port_intr_clear(struct adapter *adapter, int idx);
  524. int t3_slow_intr_handler(struct adapter *adapter);
  525. int t3_phy_intr_handler(struct adapter *adapter);
  526. void t3_link_changed(struct adapter *adapter, int port_id);
  527. int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
  528. const struct adapter_info *t3_get_adapter_info(unsigned int board_id);
  529. int t3_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
  530. int t3_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
  531. int t3_seeprom_wp(struct adapter *adapter, int enable);
  532. int t3_read_flash(struct adapter *adapter, unsigned int addr,
  533. unsigned int nwords, u32 *data, int byte_oriented);
  534. int t3_load_fw(struct adapter *adapter, const u8 * fw_data, unsigned int size);
  535. int t3_get_fw_version(struct adapter *adapter, u32 *vers);
  536. int t3_check_fw_version(struct adapter *adapter);
  537. int t3_init_hw(struct adapter *adapter, u32 fw_params);
  538. void mac_prep(struct cmac *mac, struct adapter *adapter, int index);
  539. void early_hw_init(struct adapter *adapter, const struct adapter_info *ai);
  540. int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai,
  541. int reset);
  542. void t3_led_ready(struct adapter *adapter);
  543. void t3_fatal_err(struct adapter *adapter);
  544. void t3_set_vlan_accel(struct adapter *adapter, unsigned int ports, int on);
  545. void t3_config_rss(struct adapter *adapter, unsigned int rss_config,
  546. const u8 * cpus, const u16 *rspq);
  547. int t3_read_rss(struct adapter *adapter, u8 * lkup, u16 *map);
  548. int t3_mps_set_active_ports(struct adapter *adap, unsigned int port_mask);
  549. int t3_cim_ctl_blk_read(struct adapter *adap, unsigned int addr,
  550. unsigned int n, unsigned int *valp);
  551. int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
  552. u64 *buf);
  553. int t3_mac_reset(struct cmac *mac);
  554. void t3b_pcs_reset(struct cmac *mac);
  555. int t3_mac_enable(struct cmac *mac, int which);
  556. int t3_mac_disable(struct cmac *mac, int which);
  557. int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu);
  558. int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm);
  559. int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]);
  560. int t3_mac_set_num_ucast(struct cmac *mac, int n);
  561. const struct mac_stats *t3_mac_update_stats(struct cmac *mac);
  562. int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc);
  563. void t3_mc5_prep(struct adapter *adapter, struct mc5 *mc5, int mode);
  564. int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
  565. unsigned int nroutes);
  566. void t3_mc5_intr_handler(struct mc5 *mc5);
  567. int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n,
  568. u32 *buf);
  569. int t3_tp_set_coalescing_size(struct adapter *adap, unsigned int size, int psh);
  570. void t3_tp_set_max_rxsize(struct adapter *adap, unsigned int size);
  571. void t3_tp_set_offload_mode(struct adapter *adap, int enable);
  572. void t3_tp_get_mib_stats(struct adapter *adap, struct tp_mib_stats *tps);
  573. void t3_load_mtus(struct adapter *adap, unsigned short mtus[NMTUS],
  574. unsigned short alpha[NCCTRL_WIN],
  575. unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap);
  576. void t3_read_hw_mtus(struct adapter *adap, unsigned short mtus[NMTUS]);
  577. void t3_get_cong_cntl_tab(struct adapter *adap,
  578. unsigned short incr[NMTUS][NCCTRL_WIN]);
  579. void t3_config_trace_filter(struct adapter *adapter,
  580. const struct trace_params *tp, int filter_index,
  581. int invert, int enable);
  582. int t3_config_sched(struct adapter *adap, unsigned int kbps, int sched);
  583. void t3_sge_prep(struct adapter *adap, struct sge_params *p);
  584. void t3_sge_init(struct adapter *adap, struct sge_params *p);
  585. int t3_sge_init_ecntxt(struct adapter *adapter, unsigned int id, int gts_enable,
  586. enum sge_context_type type, int respq, u64 base_addr,
  587. unsigned int size, unsigned int token, int gen,
  588. unsigned int cidx);
  589. int t3_sge_init_flcntxt(struct adapter *adapter, unsigned int id,
  590. int gts_enable, u64 base_addr, unsigned int size,
  591. unsigned int esize, unsigned int cong_thres, int gen,
  592. unsigned int cidx);
  593. int t3_sge_init_rspcntxt(struct adapter *adapter, unsigned int id,
  594. int irq_vec_idx, u64 base_addr, unsigned int size,
  595. unsigned int fl_thres, int gen, unsigned int cidx);
  596. int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr,
  597. unsigned int size, int rspq, int ovfl_mode,
  598. unsigned int credits, unsigned int credit_thres);
  599. int t3_sge_enable_ecntxt(struct adapter *adapter, unsigned int id, int enable);
  600. int t3_sge_disable_fl(struct adapter *adapter, unsigned int id);
  601. int t3_sge_disable_rspcntxt(struct adapter *adapter, unsigned int id);
  602. int t3_sge_disable_cqcntxt(struct adapter *adapter, unsigned int id);
  603. int t3_sge_read_ecntxt(struct adapter *adapter, unsigned int id, u32 data[4]);
  604. int t3_sge_read_fl(struct adapter *adapter, unsigned int id, u32 data[4]);
  605. int t3_sge_read_cq(struct adapter *adapter, unsigned int id, u32 data[4]);
  606. int t3_sge_read_rspq(struct adapter *adapter, unsigned int id, u32 data[4]);
  607. int t3_sge_cqcntxt_op(struct adapter *adapter, unsigned int id, unsigned int op,
  608. unsigned int credits);
  609. void t3_vsc8211_phy_prep(struct cphy *phy, struct adapter *adapter,
  610. int phy_addr, const struct mdio_ops *mdio_ops);
  611. void t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter,
  612. int phy_addr, const struct mdio_ops *mdio_ops);
  613. void t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter,
  614. int phy_addr, const struct mdio_ops *mdio_ops);
  615. void t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter, int phy_addr,
  616. const struct mdio_ops *mdio_ops);
  617. void t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter,
  618. int phy_addr, const struct mdio_ops *mdio_ops);
  619. #endif /* __CHELSIO_COMMON_H */