mach-smdk6410.c 12 KB

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  1. /* linux/arch/arm/mach-s3c64xx/mach-smdk6410.c
  2. *
  3. * Copyright 2008 Openmoko, Inc.
  4. * Copyright 2008 Simtec Electronics
  5. * Ben Dooks <ben@simtec.co.uk>
  6. * http://armlinux.simtec.co.uk/
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/types.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/list.h>
  17. #include <linux/timer.h>
  18. #include <linux/init.h>
  19. #include <linux/serial_core.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/io.h>
  22. #include <linux/i2c.h>
  23. #include <linux/fb.h>
  24. #include <linux/gpio.h>
  25. #include <linux/delay.h>
  26. #include <linux/smsc911x.h>
  27. #include <linux/regulator/fixed.h>
  28. #ifdef CONFIG_SMDK6410_WM1190_EV1
  29. #include <linux/mfd/wm8350/core.h>
  30. #include <linux/mfd/wm8350/pmic.h>
  31. #endif
  32. #include <video/platform_lcd.h>
  33. #include <asm/mach/arch.h>
  34. #include <asm/mach/map.h>
  35. #include <asm/mach/irq.h>
  36. #include <mach/hardware.h>
  37. #include <mach/regs-fb.h>
  38. #include <mach/map.h>
  39. #include <asm/irq.h>
  40. #include <asm/mach-types.h>
  41. #include <plat/regs-serial.h>
  42. #include <mach/regs-modem.h>
  43. #include <mach/regs-gpio.h>
  44. #include <mach/regs-sys.h>
  45. #include <mach/regs-srom.h>
  46. #include <plat/iic.h>
  47. #include <plat/fb.h>
  48. #include <plat/gpio-cfg.h>
  49. #include <mach/s3c6410.h>
  50. #include <plat/clock.h>
  51. #include <plat/devs.h>
  52. #include <plat/cpu.h>
  53. #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
  54. #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  55. #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  56. static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
  57. [0] = {
  58. .hwport = 0,
  59. .flags = 0,
  60. .ucon = UCON,
  61. .ulcon = ULCON,
  62. .ufcon = UFCON,
  63. },
  64. [1] = {
  65. .hwport = 1,
  66. .flags = 0,
  67. .ucon = UCON,
  68. .ulcon = ULCON,
  69. .ufcon = UFCON,
  70. },
  71. [2] = {
  72. .hwport = 2,
  73. .flags = 0,
  74. .ucon = UCON,
  75. .ulcon = ULCON,
  76. .ufcon = UFCON,
  77. },
  78. [3] = {
  79. .hwport = 3,
  80. .flags = 0,
  81. .ucon = UCON,
  82. .ulcon = ULCON,
  83. .ufcon = UFCON,
  84. },
  85. };
  86. /* framebuffer and LCD setup. */
  87. /* GPF15 = LCD backlight control
  88. * GPF13 => Panel power
  89. * GPN5 = LCD nRESET signal
  90. * PWM_TOUT1 => backlight brightness
  91. */
  92. static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
  93. unsigned int power)
  94. {
  95. if (power) {
  96. gpio_direction_output(S3C64XX_GPF(13), 1);
  97. gpio_direction_output(S3C64XX_GPF(15), 1);
  98. /* fire nRESET on power up */
  99. gpio_direction_output(S3C64XX_GPN(5), 0);
  100. msleep(10);
  101. gpio_direction_output(S3C64XX_GPN(5), 1);
  102. msleep(1);
  103. } else {
  104. gpio_direction_output(S3C64XX_GPF(15), 0);
  105. gpio_direction_output(S3C64XX_GPF(13), 0);
  106. }
  107. }
  108. static struct plat_lcd_data smdk6410_lcd_power_data = {
  109. .set_power = smdk6410_lcd_power_set,
  110. };
  111. static struct platform_device smdk6410_lcd_powerdev = {
  112. .name = "platform-lcd",
  113. .dev.parent = &s3c_device_fb.dev,
  114. .dev.platform_data = &smdk6410_lcd_power_data,
  115. };
  116. static struct s3c_fb_pd_win smdk6410_fb_win0 = {
  117. /* this is to ensure we use win0 */
  118. .win_mode = {
  119. .pixclock = 41094,
  120. .left_margin = 8,
  121. .right_margin = 13,
  122. .upper_margin = 7,
  123. .lower_margin = 5,
  124. .hsync_len = 3,
  125. .vsync_len = 1,
  126. .xres = 800,
  127. .yres = 480,
  128. },
  129. .max_bpp = 32,
  130. .default_bpp = 16,
  131. };
  132. /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
  133. static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
  134. .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
  135. .win[0] = &smdk6410_fb_win0,
  136. .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
  137. .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
  138. };
  139. /*
  140. * Configuring Ethernet on SMDK6410
  141. *
  142. * Both CS8900A and LAN9115 chips share one chip select mediated by CFG6.
  143. * The constant address below corresponds to nCS1
  144. *
  145. * 1) Set CFGB2 p3 ON others off, no other CFGB selects "ethernet"
  146. * 2) CFG6 needs to be switched to "LAN9115" side
  147. */
  148. static struct resource smdk6410_smsc911x_resources[] = {
  149. [0] = {
  150. .start = S3C64XX_PA_XM0CSN1,
  151. .end = S3C64XX_PA_XM0CSN1 + SZ_64K - 1,
  152. .flags = IORESOURCE_MEM,
  153. },
  154. [1] = {
  155. .start = S3C_EINT(10),
  156. .end = S3C_EINT(10),
  157. .flags = IORESOURCE_IRQ | IRQ_TYPE_LEVEL_LOW,
  158. },
  159. };
  160. static struct smsc911x_platform_config smdk6410_smsc911x_pdata = {
  161. .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
  162. .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
  163. .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
  164. .phy_interface = PHY_INTERFACE_MODE_MII,
  165. };
  166. static struct platform_device smdk6410_smsc911x = {
  167. .name = "smsc911x",
  168. .id = -1,
  169. .num_resources = ARRAY_SIZE(smdk6410_smsc911x_resources),
  170. .resource = &smdk6410_smsc911x_resources[0],
  171. .dev = {
  172. .platform_data = &smdk6410_smsc911x_pdata,
  173. },
  174. };
  175. #ifdef CONFIG_REGULATOR
  176. static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = {
  177. {
  178. /* WM8580 */
  179. .supply = "PVDD",
  180. .dev_name = "0-001b",
  181. },
  182. {
  183. /* WM8580 */
  184. .supply = "AVDD",
  185. .dev_name = "0-001b",
  186. },
  187. };
  188. static struct regulator_init_data smdk6410_b_pwr_5v_data = {
  189. .constraints = {
  190. .always_on = 1,
  191. },
  192. .num_consumer_supplies = ARRAY_SIZE(smdk6410_b_pwr_5v_consumers),
  193. .consumer_supplies = smdk6410_b_pwr_5v_consumers,
  194. };
  195. static struct fixed_voltage_config smdk6410_b_pwr_5v_pdata = {
  196. .supply_name = "B_PWR_5V",
  197. .microvolts = 5000000,
  198. .init_data = &smdk6410_b_pwr_5v_data,
  199. .gpio = -EINVAL,
  200. };
  201. static struct platform_device smdk6410_b_pwr_5v = {
  202. .name = "reg-fixed-voltage",
  203. .id = -1,
  204. .dev = {
  205. .platform_data = &smdk6410_b_pwr_5v_pdata,
  206. },
  207. };
  208. #endif
  209. static struct map_desc smdk6410_iodesc[] = {};
  210. static struct platform_device *smdk6410_devices[] __initdata = {
  211. #ifdef CONFIG_SMDK6410_SD_CH0
  212. &s3c_device_hsmmc0,
  213. #endif
  214. #ifdef CONFIG_SMDK6410_SD_CH1
  215. &s3c_device_hsmmc1,
  216. #endif
  217. &s3c_device_i2c0,
  218. &s3c_device_i2c1,
  219. &s3c_device_fb,
  220. &s3c_device_ohci,
  221. &s3c_device_usb_hsotg,
  222. #ifdef CONFIG_REGULATOR
  223. &smdk6410_b_pwr_5v,
  224. #endif
  225. &smdk6410_lcd_powerdev,
  226. &smdk6410_smsc911x,
  227. };
  228. #ifdef CONFIG_SMDK6410_WM1190_EV1
  229. /* S3C64xx internal logic & PLL */
  230. static struct regulator_init_data wm8350_dcdc1_data = {
  231. .constraints = {
  232. .name = "PVDD_INT/PVDD_PLL",
  233. .min_uV = 1200000,
  234. .max_uV = 1200000,
  235. .always_on = 1,
  236. .apply_uV = 1,
  237. },
  238. };
  239. /* Memory */
  240. static struct regulator_init_data wm8350_dcdc3_data = {
  241. .constraints = {
  242. .name = "PVDD_MEM",
  243. .min_uV = 1800000,
  244. .max_uV = 1800000,
  245. .always_on = 1,
  246. .state_mem = {
  247. .uV = 1800000,
  248. .mode = REGULATOR_MODE_NORMAL,
  249. .enabled = 1,
  250. },
  251. .initial_state = PM_SUSPEND_MEM,
  252. },
  253. };
  254. /* USB, EXT, PCM, ADC/DAC, USB, MMC */
  255. static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
  256. {
  257. /* WM8580 */
  258. .supply = "DVDD",
  259. .dev_name = "0-001b",
  260. },
  261. };
  262. static struct regulator_init_data wm8350_dcdc4_data = {
  263. .constraints = {
  264. .name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
  265. .min_uV = 3000000,
  266. .max_uV = 3000000,
  267. .always_on = 1,
  268. },
  269. .num_consumer_supplies = ARRAY_SIZE(wm8350_dcdc4_consumers),
  270. .consumer_supplies = wm8350_dcdc4_consumers,
  271. };
  272. /* ARM core */
  273. static struct regulator_consumer_supply dcdc6_consumers[] = {
  274. {
  275. .supply = "vddarm",
  276. }
  277. };
  278. static struct regulator_init_data wm8350_dcdc6_data = {
  279. .constraints = {
  280. .name = "PVDD_ARM",
  281. .min_uV = 1000000,
  282. .max_uV = 1300000,
  283. .always_on = 1,
  284. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
  285. },
  286. .num_consumer_supplies = ARRAY_SIZE(dcdc6_consumers),
  287. .consumer_supplies = dcdc6_consumers,
  288. };
  289. /* Alive */
  290. static struct regulator_init_data wm8350_ldo1_data = {
  291. .constraints = {
  292. .name = "PVDD_ALIVE",
  293. .min_uV = 1200000,
  294. .max_uV = 1200000,
  295. .always_on = 1,
  296. .apply_uV = 1,
  297. },
  298. };
  299. /* OTG */
  300. static struct regulator_init_data wm8350_ldo2_data = {
  301. .constraints = {
  302. .name = "PVDD_OTG",
  303. .min_uV = 3300000,
  304. .max_uV = 3300000,
  305. .always_on = 1,
  306. },
  307. };
  308. /* LCD */
  309. static struct regulator_init_data wm8350_ldo3_data = {
  310. .constraints = {
  311. .name = "PVDD_LCD",
  312. .min_uV = 3000000,
  313. .max_uV = 3000000,
  314. .always_on = 1,
  315. },
  316. };
  317. /* OTGi/1190-EV1 HPVDD & AVDD */
  318. static struct regulator_init_data wm8350_ldo4_data = {
  319. .constraints = {
  320. .name = "PVDD_OTGI/HPVDD/AVDD",
  321. .min_uV = 1200000,
  322. .max_uV = 1200000,
  323. .apply_uV = 1,
  324. .always_on = 1,
  325. },
  326. };
  327. static struct {
  328. int regulator;
  329. struct regulator_init_data *initdata;
  330. } wm1190_regulators[] = {
  331. { WM8350_DCDC_1, &wm8350_dcdc1_data },
  332. { WM8350_DCDC_3, &wm8350_dcdc3_data },
  333. { WM8350_DCDC_4, &wm8350_dcdc4_data },
  334. { WM8350_DCDC_6, &wm8350_dcdc6_data },
  335. { WM8350_LDO_1, &wm8350_ldo1_data },
  336. { WM8350_LDO_2, &wm8350_ldo2_data },
  337. { WM8350_LDO_3, &wm8350_ldo3_data },
  338. { WM8350_LDO_4, &wm8350_ldo4_data },
  339. };
  340. static int __init smdk6410_wm8350_init(struct wm8350 *wm8350)
  341. {
  342. int i;
  343. /* Configure the IRQ line */
  344. s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP);
  345. /* Instantiate the regulators */
  346. for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++)
  347. wm8350_register_regulator(wm8350,
  348. wm1190_regulators[i].regulator,
  349. wm1190_regulators[i].initdata);
  350. return 0;
  351. }
  352. static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = {
  353. .init = smdk6410_wm8350_init,
  354. .irq_high = 1,
  355. .irq_base = IRQ_BOARD_START,
  356. };
  357. #endif
  358. static struct i2c_board_info i2c_devs0[] __initdata = {
  359. { I2C_BOARD_INFO("24c08", 0x50), },
  360. { I2C_BOARD_INFO("wm8580", 0x1b), },
  361. #ifdef CONFIG_SMDK6410_WM1190_EV1
  362. { I2C_BOARD_INFO("wm8350", 0x1a),
  363. .platform_data = &smdk6410_wm8350_pdata,
  364. .irq = S3C_EINT(12),
  365. },
  366. #endif
  367. };
  368. static struct i2c_board_info i2c_devs1[] __initdata = {
  369. { I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */
  370. };
  371. static void __init smdk6410_map_io(void)
  372. {
  373. u32 tmp;
  374. s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
  375. s3c24xx_init_clocks(12000000);
  376. s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
  377. /* set the LCD type */
  378. tmp = __raw_readl(S3C64XX_SPCON);
  379. tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
  380. tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
  381. __raw_writel(tmp, S3C64XX_SPCON);
  382. /* remove the lcd bypass */
  383. tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
  384. tmp &= ~MIFPCON_LCD_BYPASS;
  385. __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
  386. }
  387. static void __init smdk6410_machine_init(void)
  388. {
  389. u32 cs1;
  390. s3c_i2c0_set_platdata(NULL);
  391. s3c_i2c1_set_platdata(NULL);
  392. s3c_fb_set_platdata(&smdk6410_lcd_pdata);
  393. /* configure nCS1 width to 16 bits */
  394. cs1 = __raw_readl(S3C64XX_SROM_BW) &
  395. ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
  396. cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
  397. (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
  398. (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
  399. S3C64XX_SROM_BW__NCS1__SHIFT;
  400. __raw_writel(cs1, S3C64XX_SROM_BW);
  401. /* set timing for nCS1 suitable for ethernet chip */
  402. __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
  403. (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
  404. (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
  405. (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
  406. (0xe << S3C64XX_SROM_BCX__TACC__SHIFT) |
  407. (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
  408. (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
  409. gpio_request(S3C64XX_GPN(5), "LCD power");
  410. gpio_request(S3C64XX_GPF(13), "LCD power");
  411. gpio_request(S3C64XX_GPF(15), "LCD power");
  412. i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
  413. i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
  414. platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
  415. }
  416. MACHINE_START(SMDK6410, "SMDK6410")
  417. /* Maintainer: Ben Dooks <ben@fluff.org> */
  418. .phys_io = S3C_PA_UART & 0xfff00000,
  419. .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
  420. .boot_params = S3C64XX_PA_SDRAM + 0x100,
  421. .init_irq = s3c6410_init_irq,
  422. .map_io = smdk6410_map_io,
  423. .init_machine = smdk6410_machine_init,
  424. .timer = &s3c24xx_timer,
  425. MACHINE_END