oxygen_pcm.c 22 KB

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  1. /*
  2. * C-Media CMI8788 driver - PCM code
  3. *
  4. * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
  5. *
  6. *
  7. * This driver is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License, version 2.
  9. *
  10. * This driver is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this driver; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/pci.h>
  20. #include <sound/control.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include "oxygen.h"
  25. static struct snd_pcm_hardware oxygen_hardware[PCM_COUNT] = {
  26. [PCM_A] = {
  27. .info = SNDRV_PCM_INFO_MMAP |
  28. SNDRV_PCM_INFO_MMAP_VALID |
  29. SNDRV_PCM_INFO_INTERLEAVED |
  30. SNDRV_PCM_INFO_PAUSE |
  31. SNDRV_PCM_INFO_SYNC_START,
  32. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  33. SNDRV_PCM_FMTBIT_S32_LE,
  34. .rates = SNDRV_PCM_RATE_32000 |
  35. SNDRV_PCM_RATE_44100 |
  36. SNDRV_PCM_RATE_48000 |
  37. SNDRV_PCM_RATE_64000 |
  38. SNDRV_PCM_RATE_88200 |
  39. SNDRV_PCM_RATE_96000 |
  40. SNDRV_PCM_RATE_176400 |
  41. SNDRV_PCM_RATE_192000,
  42. .rate_min = 32000,
  43. .rate_max = 192000,
  44. .channels_min = 2,
  45. .channels_max = 2,
  46. .buffer_bytes_max = 256 * 1024,
  47. .period_bytes_min = 128,
  48. .period_bytes_max = 128 * 1024,
  49. .periods_min = 2,
  50. .periods_max = 2048,
  51. },
  52. [PCM_B] = {
  53. .info = SNDRV_PCM_INFO_MMAP |
  54. SNDRV_PCM_INFO_MMAP_VALID |
  55. SNDRV_PCM_INFO_INTERLEAVED |
  56. SNDRV_PCM_INFO_PAUSE |
  57. SNDRV_PCM_INFO_SYNC_START,
  58. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  59. SNDRV_PCM_FMTBIT_S32_LE,
  60. .rates = SNDRV_PCM_RATE_32000 |
  61. SNDRV_PCM_RATE_44100 |
  62. SNDRV_PCM_RATE_48000 |
  63. SNDRV_PCM_RATE_64000 |
  64. SNDRV_PCM_RATE_88200 |
  65. SNDRV_PCM_RATE_96000 |
  66. SNDRV_PCM_RATE_176400 |
  67. SNDRV_PCM_RATE_192000,
  68. .rate_min = 32000,
  69. .rate_max = 192000,
  70. .channels_min = 2,
  71. .channels_max = 2,
  72. .buffer_bytes_max = 256 * 1024,
  73. .period_bytes_min = 128,
  74. .period_bytes_max = 128 * 1024,
  75. .periods_min = 2,
  76. .periods_max = 2048,
  77. },
  78. [PCM_C] = {
  79. .info = SNDRV_PCM_INFO_MMAP |
  80. SNDRV_PCM_INFO_MMAP_VALID |
  81. SNDRV_PCM_INFO_INTERLEAVED |
  82. SNDRV_PCM_INFO_PAUSE |
  83. SNDRV_PCM_INFO_SYNC_START,
  84. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  85. SNDRV_PCM_FMTBIT_S32_LE,
  86. .rates = SNDRV_PCM_RATE_32000 |
  87. SNDRV_PCM_RATE_44100 |
  88. SNDRV_PCM_RATE_48000 |
  89. SNDRV_PCM_RATE_64000 |
  90. SNDRV_PCM_RATE_88200 |
  91. SNDRV_PCM_RATE_96000 |
  92. SNDRV_PCM_RATE_176400 |
  93. SNDRV_PCM_RATE_192000,
  94. .rate_min = 32000,
  95. .rate_max = 192000,
  96. .channels_min = 2,
  97. .channels_max = 2,
  98. .buffer_bytes_max = 256 * 1024,
  99. .period_bytes_min = 128,
  100. .period_bytes_max = 128 * 1024,
  101. .periods_min = 2,
  102. .periods_max = 2048,
  103. },
  104. [PCM_SPDIF] = {
  105. .info = SNDRV_PCM_INFO_MMAP |
  106. SNDRV_PCM_INFO_MMAP_VALID |
  107. SNDRV_PCM_INFO_INTERLEAVED |
  108. SNDRV_PCM_INFO_PAUSE |
  109. SNDRV_PCM_INFO_SYNC_START,
  110. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  111. SNDRV_PCM_FMTBIT_S32_LE,
  112. .rates = SNDRV_PCM_RATE_32000 |
  113. SNDRV_PCM_RATE_44100 |
  114. SNDRV_PCM_RATE_48000 |
  115. SNDRV_PCM_RATE_64000 |
  116. SNDRV_PCM_RATE_88200 |
  117. SNDRV_PCM_RATE_96000 |
  118. SNDRV_PCM_RATE_176400 |
  119. SNDRV_PCM_RATE_192000,
  120. .rate_min = 32000,
  121. .rate_max = 192000,
  122. .channels_min = 2,
  123. .channels_max = 2,
  124. .buffer_bytes_max = 256 * 1024,
  125. .period_bytes_min = 128,
  126. .period_bytes_max = 128 * 1024,
  127. .periods_min = 2,
  128. .periods_max = 2048,
  129. },
  130. [PCM_MULTICH] = {
  131. .info = SNDRV_PCM_INFO_MMAP |
  132. SNDRV_PCM_INFO_MMAP_VALID |
  133. SNDRV_PCM_INFO_INTERLEAVED |
  134. SNDRV_PCM_INFO_PAUSE |
  135. SNDRV_PCM_INFO_SYNC_START,
  136. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  137. SNDRV_PCM_FMTBIT_S32_LE,
  138. .rates = SNDRV_PCM_RATE_32000 |
  139. SNDRV_PCM_RATE_44100 |
  140. SNDRV_PCM_RATE_48000 |
  141. SNDRV_PCM_RATE_64000 |
  142. SNDRV_PCM_RATE_88200 |
  143. SNDRV_PCM_RATE_96000 |
  144. SNDRV_PCM_RATE_176400 |
  145. SNDRV_PCM_RATE_192000,
  146. .rate_min = 32000,
  147. .rate_max = 192000,
  148. .channels_min = 2,
  149. .channels_max = 8,
  150. .buffer_bytes_max = 2048 * 1024,
  151. .period_bytes_min = 128,
  152. .period_bytes_max = 256 * 1024,
  153. .periods_min = 2,
  154. .periods_max = 16384,
  155. },
  156. [PCM_AC97] = {
  157. .info = SNDRV_PCM_INFO_MMAP |
  158. SNDRV_PCM_INFO_MMAP_VALID |
  159. SNDRV_PCM_INFO_INTERLEAVED |
  160. SNDRV_PCM_INFO_PAUSE |
  161. SNDRV_PCM_INFO_SYNC_START,
  162. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  163. .rates = SNDRV_PCM_RATE_48000,
  164. .rate_min = 48000,
  165. .rate_max = 48000,
  166. .channels_min = 2,
  167. .channels_max = 2,
  168. .buffer_bytes_max = 256 * 1024,
  169. .period_bytes_min = 128,
  170. .period_bytes_max = 128 * 1024,
  171. .periods_min = 2,
  172. .periods_max = 2048,
  173. },
  174. };
  175. static inline unsigned int
  176. oxygen_substream_channel(struct snd_pcm_substream *substream)
  177. {
  178. return (unsigned int)(uintptr_t)substream->runtime->private_data;
  179. }
  180. static int oxygen_open(struct snd_pcm_substream *substream,
  181. unsigned int channel)
  182. {
  183. struct oxygen *chip = snd_pcm_substream_chip(substream);
  184. struct snd_pcm_runtime *runtime = substream->runtime;
  185. int err;
  186. runtime->private_data = (void *)(uintptr_t)channel;
  187. runtime->hw = oxygen_hardware[channel];
  188. if (chip->model->pcm_hardware_filter)
  189. chip->model->pcm_hardware_filter(channel, &runtime->hw);
  190. err = snd_pcm_hw_constraint_step(runtime, 0,
  191. SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
  192. if (err < 0)
  193. return err;
  194. err = snd_pcm_hw_constraint_step(runtime, 0,
  195. SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
  196. if (err < 0)
  197. return err;
  198. if (runtime->hw.formats & SNDRV_PCM_FMTBIT_S32_LE) {
  199. err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  200. if (err < 0)
  201. return err;
  202. }
  203. if (runtime->hw.channels_max > 2) {
  204. err = snd_pcm_hw_constraint_step(runtime, 0,
  205. SNDRV_PCM_HW_PARAM_CHANNELS,
  206. 2);
  207. if (err < 0)
  208. return err;
  209. }
  210. snd_pcm_set_sync(substream);
  211. chip->streams[channel] = substream;
  212. mutex_lock(&chip->mutex);
  213. chip->pcm_active |= 1 << channel;
  214. if (channel == PCM_SPDIF) {
  215. chip->spdif_pcm_bits = chip->spdif_bits;
  216. chip->controls[CONTROL_SPDIF_PCM]->vd[0].access &=
  217. ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  218. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  219. SNDRV_CTL_EVENT_MASK_INFO,
  220. &chip->controls[CONTROL_SPDIF_PCM]->id);
  221. }
  222. mutex_unlock(&chip->mutex);
  223. return 0;
  224. }
  225. static int oxygen_rec_a_open(struct snd_pcm_substream *substream)
  226. {
  227. return oxygen_open(substream, PCM_A);
  228. }
  229. static int oxygen_rec_b_open(struct snd_pcm_substream *substream)
  230. {
  231. return oxygen_open(substream, PCM_B);
  232. }
  233. static int oxygen_rec_c_open(struct snd_pcm_substream *substream)
  234. {
  235. return oxygen_open(substream, PCM_C);
  236. }
  237. static int oxygen_spdif_open(struct snd_pcm_substream *substream)
  238. {
  239. return oxygen_open(substream, PCM_SPDIF);
  240. }
  241. static int oxygen_multich_open(struct snd_pcm_substream *substream)
  242. {
  243. return oxygen_open(substream, PCM_MULTICH);
  244. }
  245. static int oxygen_ac97_open(struct snd_pcm_substream *substream)
  246. {
  247. return oxygen_open(substream, PCM_AC97);
  248. }
  249. static int oxygen_close(struct snd_pcm_substream *substream)
  250. {
  251. struct oxygen *chip = snd_pcm_substream_chip(substream);
  252. unsigned int channel = oxygen_substream_channel(substream);
  253. mutex_lock(&chip->mutex);
  254. chip->pcm_active &= ~(1 << channel);
  255. if (channel == PCM_SPDIF) {
  256. chip->controls[CONTROL_SPDIF_PCM]->vd[0].access |=
  257. SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  258. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  259. SNDRV_CTL_EVENT_MASK_INFO,
  260. &chip->controls[CONTROL_SPDIF_PCM]->id);
  261. }
  262. if (channel == PCM_SPDIF || channel == PCM_MULTICH)
  263. oxygen_update_spdif_source(chip);
  264. mutex_unlock(&chip->mutex);
  265. chip->streams[channel] = NULL;
  266. return 0;
  267. }
  268. static unsigned int oxygen_format(struct snd_pcm_hw_params *hw_params)
  269. {
  270. if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
  271. return OXYGEN_FORMAT_24;
  272. else
  273. return OXYGEN_FORMAT_16;
  274. }
  275. static unsigned int oxygen_rate(struct snd_pcm_hw_params *hw_params)
  276. {
  277. switch (params_rate(hw_params)) {
  278. case 32000:
  279. return OXYGEN_RATE_32000;
  280. case 44100:
  281. return OXYGEN_RATE_44100;
  282. default: /* 48000 */
  283. return OXYGEN_RATE_48000;
  284. case 64000:
  285. return OXYGEN_RATE_64000;
  286. case 88200:
  287. return OXYGEN_RATE_88200;
  288. case 96000:
  289. return OXYGEN_RATE_96000;
  290. case 176400:
  291. return OXYGEN_RATE_176400;
  292. case 192000:
  293. return OXYGEN_RATE_192000;
  294. }
  295. }
  296. static unsigned int oxygen_i2s_mclk(struct snd_pcm_hw_params *hw_params)
  297. {
  298. return params_rate(hw_params) <= 96000
  299. ? OXYGEN_I2S_MCLK_256 : OXYGEN_I2S_MCLK_128;
  300. }
  301. static unsigned int oxygen_i2s_bits(struct snd_pcm_hw_params *hw_params)
  302. {
  303. if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
  304. return OXYGEN_I2S_BITS_24;
  305. else
  306. return OXYGEN_I2S_BITS_16;
  307. }
  308. static unsigned int oxygen_play_channels(struct snd_pcm_hw_params *hw_params)
  309. {
  310. switch (params_channels(hw_params)) {
  311. default: /* 2 */
  312. return OXYGEN_PLAY_CHANNELS_2;
  313. case 4:
  314. return OXYGEN_PLAY_CHANNELS_4;
  315. case 6:
  316. return OXYGEN_PLAY_CHANNELS_6;
  317. case 8:
  318. return OXYGEN_PLAY_CHANNELS_8;
  319. }
  320. }
  321. static const unsigned int channel_base_registers[PCM_COUNT] = {
  322. [PCM_A] = OXYGEN_DMA_A_ADDRESS,
  323. [PCM_B] = OXYGEN_DMA_B_ADDRESS,
  324. [PCM_C] = OXYGEN_DMA_C_ADDRESS,
  325. [PCM_SPDIF] = OXYGEN_DMA_SPDIF_ADDRESS,
  326. [PCM_MULTICH] = OXYGEN_DMA_MULTICH_ADDRESS,
  327. [PCM_AC97] = OXYGEN_DMA_AC97_ADDRESS,
  328. };
  329. static int oxygen_hw_params(struct snd_pcm_substream *substream,
  330. struct snd_pcm_hw_params *hw_params)
  331. {
  332. struct oxygen *chip = snd_pcm_substream_chip(substream);
  333. unsigned int channel = oxygen_substream_channel(substream);
  334. int err;
  335. err = snd_pcm_lib_malloc_pages(substream,
  336. params_buffer_bytes(hw_params));
  337. if (err < 0)
  338. return err;
  339. oxygen_write32(chip, channel_base_registers[channel],
  340. (u32)substream->runtime->dma_addr);
  341. if (channel == PCM_MULTICH) {
  342. oxygen_write32(chip, OXYGEN_DMA_MULTICH_COUNT,
  343. params_buffer_bytes(hw_params) / 4 - 1);
  344. oxygen_write32(chip, OXYGEN_DMA_MULTICH_TCOUNT,
  345. params_period_bytes(hw_params) / 4 - 1);
  346. } else {
  347. oxygen_write16(chip, channel_base_registers[channel] + 4,
  348. params_buffer_bytes(hw_params) / 4 - 1);
  349. oxygen_write16(chip, channel_base_registers[channel] + 6,
  350. params_period_bytes(hw_params) / 4 - 1);
  351. }
  352. return 0;
  353. }
  354. static int oxygen_rec_a_hw_params(struct snd_pcm_substream *substream,
  355. struct snd_pcm_hw_params *hw_params)
  356. {
  357. struct oxygen *chip = snd_pcm_substream_chip(substream);
  358. int err;
  359. err = oxygen_hw_params(substream, hw_params);
  360. if (err < 0)
  361. return err;
  362. spin_lock_irq(&chip->reg_lock);
  363. oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
  364. oxygen_format(hw_params) << OXYGEN_REC_FORMAT_A_SHIFT,
  365. OXYGEN_REC_FORMAT_A_MASK);
  366. oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT,
  367. oxygen_rate(hw_params) |
  368. oxygen_i2s_mclk(hw_params) |
  369. chip->model->adc_i2s_format |
  370. oxygen_i2s_bits(hw_params),
  371. OXYGEN_I2S_RATE_MASK |
  372. OXYGEN_I2S_FORMAT_MASK |
  373. OXYGEN_I2S_MCLK_MASK |
  374. OXYGEN_I2S_BITS_MASK);
  375. oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
  376. OXYGEN_REC_A_ROUTE_I2S_ADC_1,
  377. OXYGEN_REC_A_ROUTE_MASK);
  378. spin_unlock_irq(&chip->reg_lock);
  379. mutex_lock(&chip->mutex);
  380. chip->model->set_adc_params(chip, hw_params);
  381. mutex_unlock(&chip->mutex);
  382. return 0;
  383. }
  384. static int oxygen_rec_b_hw_params(struct snd_pcm_substream *substream,
  385. struct snd_pcm_hw_params *hw_params)
  386. {
  387. struct oxygen *chip = snd_pcm_substream_chip(substream);
  388. int err;
  389. err = oxygen_hw_params(substream, hw_params);
  390. if (err < 0)
  391. return err;
  392. spin_lock_irq(&chip->reg_lock);
  393. oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
  394. oxygen_format(hw_params) << OXYGEN_REC_FORMAT_B_SHIFT,
  395. OXYGEN_REC_FORMAT_B_MASK);
  396. oxygen_write16_masked(chip, OXYGEN_I2S_B_FORMAT,
  397. oxygen_rate(hw_params) |
  398. oxygen_i2s_mclk(hw_params) |
  399. chip->model->adc_i2s_format |
  400. oxygen_i2s_bits(hw_params),
  401. OXYGEN_I2S_RATE_MASK |
  402. OXYGEN_I2S_FORMAT_MASK |
  403. OXYGEN_I2S_MCLK_MASK |
  404. OXYGEN_I2S_BITS_MASK);
  405. oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
  406. OXYGEN_REC_B_ROUTE_I2S_ADC_2,
  407. OXYGEN_REC_B_ROUTE_MASK);
  408. spin_unlock_irq(&chip->reg_lock);
  409. mutex_lock(&chip->mutex);
  410. chip->model->set_adc_params(chip, hw_params);
  411. mutex_unlock(&chip->mutex);
  412. return 0;
  413. }
  414. static int oxygen_rec_c_hw_params(struct snd_pcm_substream *substream,
  415. struct snd_pcm_hw_params *hw_params)
  416. {
  417. struct oxygen *chip = snd_pcm_substream_chip(substream);
  418. int err;
  419. err = oxygen_hw_params(substream, hw_params);
  420. if (err < 0)
  421. return err;
  422. spin_lock_irq(&chip->reg_lock);
  423. oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
  424. oxygen_format(hw_params) << OXYGEN_REC_FORMAT_C_SHIFT,
  425. OXYGEN_REC_FORMAT_C_MASK);
  426. oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
  427. OXYGEN_REC_C_ROUTE_SPDIF,
  428. OXYGEN_REC_C_ROUTE_MASK);
  429. spin_unlock_irq(&chip->reg_lock);
  430. return 0;
  431. }
  432. static int oxygen_spdif_hw_params(struct snd_pcm_substream *substream,
  433. struct snd_pcm_hw_params *hw_params)
  434. {
  435. struct oxygen *chip = snd_pcm_substream_chip(substream);
  436. int err;
  437. err = oxygen_hw_params(substream, hw_params);
  438. if (err < 0)
  439. return err;
  440. spin_lock_irq(&chip->reg_lock);
  441. oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
  442. OXYGEN_SPDIF_OUT_ENABLE);
  443. oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
  444. oxygen_format(hw_params) << OXYGEN_SPDIF_FORMAT_SHIFT,
  445. OXYGEN_SPDIF_FORMAT_MASK);
  446. oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
  447. oxygen_rate(hw_params) << OXYGEN_SPDIF_OUT_RATE_SHIFT,
  448. OXYGEN_SPDIF_OUT_RATE_MASK);
  449. oxygen_update_spdif_source(chip);
  450. spin_unlock_irq(&chip->reg_lock);
  451. return 0;
  452. }
  453. static int oxygen_multich_hw_params(struct snd_pcm_substream *substream,
  454. struct snd_pcm_hw_params *hw_params)
  455. {
  456. struct oxygen *chip = snd_pcm_substream_chip(substream);
  457. int err;
  458. err = oxygen_hw_params(substream, hw_params);
  459. if (err < 0)
  460. return err;
  461. spin_lock_irq(&chip->reg_lock);
  462. oxygen_write8_masked(chip, OXYGEN_PLAY_CHANNELS,
  463. oxygen_play_channels(hw_params),
  464. OXYGEN_PLAY_CHANNELS_MASK);
  465. oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
  466. oxygen_format(hw_params) << OXYGEN_MULTICH_FORMAT_SHIFT,
  467. OXYGEN_MULTICH_FORMAT_MASK);
  468. oxygen_write16_masked(chip, OXYGEN_I2S_MULTICH_FORMAT,
  469. oxygen_rate(hw_params) |
  470. chip->model->dac_i2s_format |
  471. oxygen_i2s_bits(hw_params),
  472. OXYGEN_I2S_RATE_MASK |
  473. OXYGEN_I2S_FORMAT_MASK |
  474. OXYGEN_I2S_BITS_MASK);
  475. oxygen_write16_masked(chip, OXYGEN_PLAY_ROUTING,
  476. OXYGEN_PLAY_MULTICH_I2S_DAC,
  477. OXYGEN_PLAY_MUTE01 | OXYGEN_PLAY_MUTE23 |
  478. OXYGEN_PLAY_MUTE45 | OXYGEN_PLAY_MUTE67 |
  479. OXYGEN_PLAY_MULTICH_MASK);
  480. oxygen_update_dac_routing(chip);
  481. oxygen_update_spdif_source(chip);
  482. spin_unlock_irq(&chip->reg_lock);
  483. mutex_lock(&chip->mutex);
  484. chip->model->set_dac_params(chip, hw_params);
  485. mutex_unlock(&chip->mutex);
  486. return 0;
  487. }
  488. static int oxygen_hw_free(struct snd_pcm_substream *substream)
  489. {
  490. struct oxygen *chip = snd_pcm_substream_chip(substream);
  491. unsigned int channel = oxygen_substream_channel(substream);
  492. spin_lock_irq(&chip->reg_lock);
  493. chip->interrupt_mask &= ~(1 << channel);
  494. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
  495. spin_unlock_irq(&chip->reg_lock);
  496. return snd_pcm_lib_free_pages(substream);
  497. }
  498. static int oxygen_spdif_hw_free(struct snd_pcm_substream *substream)
  499. {
  500. struct oxygen *chip = snd_pcm_substream_chip(substream);
  501. spin_lock_irq(&chip->reg_lock);
  502. oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
  503. OXYGEN_SPDIF_OUT_ENABLE);
  504. spin_unlock_irq(&chip->reg_lock);
  505. return oxygen_hw_free(substream);
  506. }
  507. static int oxygen_prepare(struct snd_pcm_substream *substream)
  508. {
  509. struct oxygen *chip = snd_pcm_substream_chip(substream);
  510. unsigned int channel = oxygen_substream_channel(substream);
  511. unsigned int channel_mask = 1 << channel;
  512. spin_lock_irq(&chip->reg_lock);
  513. oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
  514. oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
  515. chip->interrupt_mask |= channel_mask;
  516. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
  517. spin_unlock_irq(&chip->reg_lock);
  518. return 0;
  519. }
  520. static int oxygen_trigger(struct snd_pcm_substream *substream, int cmd)
  521. {
  522. struct oxygen *chip = snd_pcm_substream_chip(substream);
  523. struct snd_pcm_substream *s;
  524. unsigned int mask = 0;
  525. int pausing;
  526. switch (cmd) {
  527. case SNDRV_PCM_TRIGGER_STOP:
  528. case SNDRV_PCM_TRIGGER_START:
  529. pausing = 0;
  530. break;
  531. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  532. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  533. pausing = 1;
  534. break;
  535. default:
  536. return -EINVAL;
  537. }
  538. snd_pcm_group_for_each_entry(s, substream) {
  539. if (snd_pcm_substream_chip(s) == chip) {
  540. mask |= 1 << oxygen_substream_channel(s);
  541. snd_pcm_trigger_done(s, substream);
  542. }
  543. }
  544. spin_lock(&chip->reg_lock);
  545. if (!pausing) {
  546. if (cmd == SNDRV_PCM_TRIGGER_START)
  547. chip->pcm_running |= mask;
  548. else
  549. chip->pcm_running &= ~mask;
  550. oxygen_write8(chip, OXYGEN_DMA_STATUS, chip->pcm_running);
  551. } else {
  552. if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
  553. oxygen_set_bits8(chip, OXYGEN_DMA_PAUSE, mask);
  554. else
  555. oxygen_clear_bits8(chip, OXYGEN_DMA_PAUSE, mask);
  556. }
  557. spin_unlock(&chip->reg_lock);
  558. return 0;
  559. }
  560. static snd_pcm_uframes_t oxygen_pointer(struct snd_pcm_substream *substream)
  561. {
  562. struct oxygen *chip = snd_pcm_substream_chip(substream);
  563. struct snd_pcm_runtime *runtime = substream->runtime;
  564. unsigned int channel = oxygen_substream_channel(substream);
  565. u32 curr_addr;
  566. /* no spinlock, this read should be atomic */
  567. curr_addr = oxygen_read32(chip, channel_base_registers[channel]);
  568. return bytes_to_frames(runtime, curr_addr - (u32)runtime->dma_addr);
  569. }
  570. static struct snd_pcm_ops oxygen_rec_a_ops = {
  571. .open = oxygen_rec_a_open,
  572. .close = oxygen_close,
  573. .ioctl = snd_pcm_lib_ioctl,
  574. .hw_params = oxygen_rec_a_hw_params,
  575. .hw_free = oxygen_hw_free,
  576. .prepare = oxygen_prepare,
  577. .trigger = oxygen_trigger,
  578. .pointer = oxygen_pointer,
  579. };
  580. static struct snd_pcm_ops oxygen_rec_b_ops = {
  581. .open = oxygen_rec_b_open,
  582. .close = oxygen_close,
  583. .ioctl = snd_pcm_lib_ioctl,
  584. .hw_params = oxygen_rec_b_hw_params,
  585. .hw_free = oxygen_hw_free,
  586. .prepare = oxygen_prepare,
  587. .trigger = oxygen_trigger,
  588. .pointer = oxygen_pointer,
  589. };
  590. static struct snd_pcm_ops oxygen_rec_c_ops = {
  591. .open = oxygen_rec_c_open,
  592. .close = oxygen_close,
  593. .ioctl = snd_pcm_lib_ioctl,
  594. .hw_params = oxygen_rec_c_hw_params,
  595. .hw_free = oxygen_hw_free,
  596. .prepare = oxygen_prepare,
  597. .trigger = oxygen_trigger,
  598. .pointer = oxygen_pointer,
  599. };
  600. static struct snd_pcm_ops oxygen_spdif_ops = {
  601. .open = oxygen_spdif_open,
  602. .close = oxygen_close,
  603. .ioctl = snd_pcm_lib_ioctl,
  604. .hw_params = oxygen_spdif_hw_params,
  605. .hw_free = oxygen_spdif_hw_free,
  606. .prepare = oxygen_prepare,
  607. .trigger = oxygen_trigger,
  608. .pointer = oxygen_pointer,
  609. };
  610. static struct snd_pcm_ops oxygen_multich_ops = {
  611. .open = oxygen_multich_open,
  612. .close = oxygen_close,
  613. .ioctl = snd_pcm_lib_ioctl,
  614. .hw_params = oxygen_multich_hw_params,
  615. .hw_free = oxygen_hw_free,
  616. .prepare = oxygen_prepare,
  617. .trigger = oxygen_trigger,
  618. .pointer = oxygen_pointer,
  619. };
  620. static struct snd_pcm_ops oxygen_ac97_ops = {
  621. .open = oxygen_ac97_open,
  622. .close = oxygen_close,
  623. .ioctl = snd_pcm_lib_ioctl,
  624. .hw_params = oxygen_hw_params,
  625. .hw_free = oxygen_hw_free,
  626. .prepare = oxygen_prepare,
  627. .trigger = oxygen_trigger,
  628. .pointer = oxygen_pointer,
  629. };
  630. static void oxygen_pcm_free(struct snd_pcm *pcm)
  631. {
  632. snd_pcm_lib_preallocate_free_for_all(pcm);
  633. }
  634. int __devinit oxygen_pcm_init(struct oxygen *chip)
  635. {
  636. struct snd_pcm *pcm;
  637. int outs, ins;
  638. int err;
  639. outs = 1; /* OXYGEN_CHANNEL_MULTICH is always used */
  640. ins = !!(chip->model->used_channels & (OXYGEN_CHANNEL_A |
  641. OXYGEN_CHANNEL_B));
  642. err = snd_pcm_new(chip->card, "Analog", 0, outs, ins, &pcm);
  643. if (err < 0)
  644. return err;
  645. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &oxygen_multich_ops);
  646. if (chip->model->used_channels & OXYGEN_CHANNEL_A)
  647. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  648. &oxygen_rec_a_ops);
  649. else if (chip->model->used_channels & OXYGEN_CHANNEL_B)
  650. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  651. &oxygen_rec_b_ops);
  652. pcm->private_data = chip;
  653. pcm->private_free = oxygen_pcm_free;
  654. strcpy(pcm->name, "Analog");
  655. snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream,
  656. SNDRV_DMA_TYPE_DEV,
  657. snd_dma_pci_data(chip->pci),
  658. 512 * 1024, 2048 * 1024);
  659. if (ins)
  660. snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream,
  661. SNDRV_DMA_TYPE_DEV,
  662. snd_dma_pci_data(chip->pci),
  663. 128 * 1024, 256 * 1024);
  664. outs = !!(chip->model->used_channels & OXYGEN_CHANNEL_SPDIF);
  665. ins = !!(chip->model->used_channels & OXYGEN_CHANNEL_C);
  666. if (outs | ins) {
  667. err = snd_pcm_new(chip->card, "Digital", 1, outs, ins, &pcm);
  668. if (err < 0)
  669. return err;
  670. if (outs)
  671. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  672. &oxygen_spdif_ops);
  673. if (ins)
  674. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  675. &oxygen_rec_c_ops);
  676. pcm->private_data = chip;
  677. pcm->private_free = oxygen_pcm_free;
  678. strcpy(pcm->name, "Digital");
  679. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  680. snd_dma_pci_data(chip->pci),
  681. 128 * 1024, 256 * 1024);
  682. }
  683. outs = chip->has_ac97_1 &&
  684. (chip->model->used_channels & OXYGEN_CHANNEL_AC97);
  685. ins = (chip->model->used_channels & (OXYGEN_CHANNEL_A |
  686. OXYGEN_CHANNEL_B))
  687. == (OXYGEN_CHANNEL_A | OXYGEN_CHANNEL_B);
  688. if (outs | ins) {
  689. err = snd_pcm_new(chip->card, ins ? "Analog2" : "AC97",
  690. 2, outs, ins, &pcm);
  691. if (err < 0)
  692. return err;
  693. if (outs)
  694. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  695. &oxygen_ac97_ops);
  696. if (ins)
  697. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  698. &oxygen_rec_b_ops);
  699. pcm->private_data = chip;
  700. pcm->private_free = oxygen_pcm_free;
  701. strcpy(pcm->name, ins ? "Analog 2" : "Front Panel");
  702. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  703. snd_dma_pci_data(chip->pci),
  704. 128 * 1024, 256 * 1024);
  705. }
  706. return 0;
  707. }