ql4_mbx.c 35 KB

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  1. /*
  2. * QLogic iSCSI HBA Driver
  3. * Copyright (c) 2003-2010 QLogic Corporation
  4. *
  5. * See LICENSE.qla4xxx for copyright and licensing details.
  6. */
  7. #include "ql4_def.h"
  8. #include "ql4_glbl.h"
  9. #include "ql4_dbg.h"
  10. #include "ql4_inline.h"
  11. /**
  12. * qla4xxx_mailbox_command - issues mailbox commands
  13. * @ha: Pointer to host adapter structure.
  14. * @inCount: number of mailbox registers to load.
  15. * @outCount: number of mailbox registers to return.
  16. * @mbx_cmd: data pointer for mailbox in registers.
  17. * @mbx_sts: data pointer for mailbox out registers.
  18. *
  19. * This routine isssue mailbox commands and waits for completion.
  20. * If outCount is 0, this routine completes successfully WITHOUT waiting
  21. * for the mailbox command to complete.
  22. **/
  23. int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
  24. uint8_t outCount, uint32_t *mbx_cmd,
  25. uint32_t *mbx_sts)
  26. {
  27. int status = QLA_ERROR;
  28. uint8_t i;
  29. u_long wait_count;
  30. uint32_t intr_status;
  31. unsigned long flags = 0;
  32. uint32_t dev_state;
  33. /* Make sure that pointers are valid */
  34. if (!mbx_cmd || !mbx_sts) {
  35. DEBUG2(printk("scsi%ld: %s: Invalid mbx_cmd or mbx_sts "
  36. "pointer\n", ha->host_no, __func__));
  37. return status;
  38. }
  39. if (is_qla8022(ha)) {
  40. if (test_bit(AF_FW_RECOVERY, &ha->flags)) {
  41. DEBUG2(ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: "
  42. "prematurely completing mbx cmd as firmware "
  43. "recovery detected\n", ha->host_no, __func__));
  44. return status;
  45. }
  46. /* Do not send any mbx cmd if h/w is in failed state*/
  47. qla4_8xxx_idc_lock(ha);
  48. dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
  49. qla4_8xxx_idc_unlock(ha);
  50. if (dev_state == QLA82XX_DEV_FAILED) {
  51. ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: H/W is in "
  52. "failed state, do not send any mailbox commands\n",
  53. ha->host_no, __func__);
  54. return status;
  55. }
  56. }
  57. if ((is_aer_supported(ha)) &&
  58. (test_bit(AF_PCI_CHANNEL_IO_PERM_FAILURE, &ha->flags))) {
  59. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: Perm failure on EEH, "
  60. "timeout MBX Exiting.\n", ha->host_no, __func__));
  61. return status;
  62. }
  63. /* Mailbox code active */
  64. wait_count = MBOX_TOV * 100;
  65. while (wait_count--) {
  66. mutex_lock(&ha->mbox_sem);
  67. if (!test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  68. set_bit(AF_MBOX_COMMAND, &ha->flags);
  69. mutex_unlock(&ha->mbox_sem);
  70. break;
  71. }
  72. mutex_unlock(&ha->mbox_sem);
  73. if (!wait_count) {
  74. DEBUG2(printk("scsi%ld: %s: mbox_sem failed\n",
  75. ha->host_no, __func__));
  76. return status;
  77. }
  78. msleep(10);
  79. }
  80. /* To prevent overwriting mailbox registers for a command that has
  81. * not yet been serviced, check to see if an active command
  82. * (AEN, IOCB, etc.) is interrupting, then service it.
  83. * -----------------------------------------------------------------
  84. */
  85. spin_lock_irqsave(&ha->hardware_lock, flags);
  86. if (!is_qla8022(ha)) {
  87. intr_status = readl(&ha->reg->ctrl_status);
  88. if (intr_status & CSR_SCSI_PROCESSOR_INTR) {
  89. /* Service existing interrupt */
  90. ha->isp_ops->interrupt_service_routine(ha, intr_status);
  91. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  92. }
  93. }
  94. ha->mbox_status_count = outCount;
  95. for (i = 0; i < outCount; i++)
  96. ha->mbox_status[i] = 0;
  97. if (is_qla8022(ha)) {
  98. /* Load all mailbox registers, except mailbox 0. */
  99. DEBUG5(
  100. printk("scsi%ld: %s: Cmd ", ha->host_no, __func__);
  101. for (i = 0; i < inCount; i++)
  102. printk("mb%d=%04x ", i, mbx_cmd[i]);
  103. printk("\n"));
  104. for (i = 1; i < inCount; i++)
  105. writel(mbx_cmd[i], &ha->qla4_8xxx_reg->mailbox_in[i]);
  106. writel(mbx_cmd[0], &ha->qla4_8xxx_reg->mailbox_in[0]);
  107. readl(&ha->qla4_8xxx_reg->mailbox_in[0]);
  108. writel(HINT_MBX_INT_PENDING, &ha->qla4_8xxx_reg->hint);
  109. } else {
  110. /* Load all mailbox registers, except mailbox 0. */
  111. for (i = 1; i < inCount; i++)
  112. writel(mbx_cmd[i], &ha->reg->mailbox[i]);
  113. /* Wakeup firmware */
  114. writel(mbx_cmd[0], &ha->reg->mailbox[0]);
  115. readl(&ha->reg->mailbox[0]);
  116. writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
  117. readl(&ha->reg->ctrl_status);
  118. }
  119. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  120. /* Wait for completion */
  121. /*
  122. * If we don't want status, don't wait for the mailbox command to
  123. * complete. For example, MBOX_CMD_RESET_FW doesn't return status,
  124. * you must poll the inbound Interrupt Mask for completion.
  125. */
  126. if (outCount == 0) {
  127. status = QLA_SUCCESS;
  128. goto mbox_exit;
  129. }
  130. /*
  131. * Wait for completion: Poll or completion queue
  132. */
  133. if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
  134. test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
  135. test_bit(AF_ONLINE, &ha->flags) &&
  136. !test_bit(AF_HA_REMOVAL, &ha->flags)) {
  137. /* Do not poll for completion. Use completion queue */
  138. set_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  139. wait_for_completion_timeout(&ha->mbx_intr_comp, MBOX_TOV * HZ);
  140. clear_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  141. } else {
  142. /* Poll for command to complete */
  143. wait_count = jiffies + MBOX_TOV * HZ;
  144. while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) {
  145. if (time_after_eq(jiffies, wait_count))
  146. break;
  147. /*
  148. * Service the interrupt.
  149. * The ISR will save the mailbox status registers
  150. * to a temporary storage location in the adapter
  151. * structure.
  152. */
  153. spin_lock_irqsave(&ha->hardware_lock, flags);
  154. if (is_qla8022(ha)) {
  155. intr_status =
  156. readl(&ha->qla4_8xxx_reg->host_int);
  157. if (intr_status & ISRX_82XX_RISC_INT) {
  158. ha->mbox_status_count = outCount;
  159. intr_status =
  160. readl(&ha->qla4_8xxx_reg->host_status);
  161. ha->isp_ops->interrupt_service_routine(
  162. ha, intr_status);
  163. if (test_bit(AF_INTERRUPTS_ON,
  164. &ha->flags) &&
  165. test_bit(AF_INTx_ENABLED,
  166. &ha->flags))
  167. qla4_8xxx_wr_32(ha,
  168. ha->nx_legacy_intr.tgt_mask_reg,
  169. 0xfbff);
  170. }
  171. } else {
  172. intr_status = readl(&ha->reg->ctrl_status);
  173. if (intr_status & INTR_PENDING) {
  174. /*
  175. * Service the interrupt.
  176. * The ISR will save the mailbox status
  177. * registers to a temporary storage
  178. * location in the adapter structure.
  179. */
  180. ha->mbox_status_count = outCount;
  181. ha->isp_ops->interrupt_service_routine(
  182. ha, intr_status);
  183. }
  184. }
  185. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  186. msleep(10);
  187. }
  188. }
  189. /* Check for mailbox timeout. */
  190. if (!test_bit(AF_MBOX_COMMAND_DONE, &ha->flags)) {
  191. if (is_qla8022(ha) &&
  192. test_bit(AF_FW_RECOVERY, &ha->flags)) {
  193. DEBUG2(ql4_printk(KERN_INFO, ha,
  194. "scsi%ld: %s: prematurely completing mbx cmd as "
  195. "firmware recovery detected\n",
  196. ha->host_no, __func__));
  197. goto mbox_exit;
  198. }
  199. DEBUG2(printk("scsi%ld: Mailbox Cmd 0x%08X timed out ...,"
  200. " Scheduling Adapter Reset\n", ha->host_no,
  201. mbx_cmd[0]));
  202. ha->mailbox_timeout_count++;
  203. mbx_sts[0] = (-1);
  204. set_bit(DPC_RESET_HA, &ha->dpc_flags);
  205. goto mbox_exit;
  206. }
  207. /*
  208. * Copy the mailbox out registers to the caller's mailbox in/out
  209. * structure.
  210. */
  211. spin_lock_irqsave(&ha->hardware_lock, flags);
  212. for (i = 0; i < outCount; i++)
  213. mbx_sts[i] = ha->mbox_status[i];
  214. /* Set return status and error flags (if applicable). */
  215. switch (ha->mbox_status[0]) {
  216. case MBOX_STS_COMMAND_COMPLETE:
  217. status = QLA_SUCCESS;
  218. break;
  219. case MBOX_STS_INTERMEDIATE_COMPLETION:
  220. status = QLA_SUCCESS;
  221. break;
  222. case MBOX_STS_BUSY:
  223. DEBUG2( printk("scsi%ld: %s: Cmd = %08X, ISP BUSY\n",
  224. ha->host_no, __func__, mbx_cmd[0]));
  225. ha->mailbox_timeout_count++;
  226. break;
  227. default:
  228. DEBUG2(printk("scsi%ld: %s: **** FAILED, cmd = %08X, "
  229. "sts = %08X ****\n", ha->host_no, __func__,
  230. mbx_cmd[0], mbx_sts[0]));
  231. break;
  232. }
  233. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  234. mbox_exit:
  235. mutex_lock(&ha->mbox_sem);
  236. clear_bit(AF_MBOX_COMMAND, &ha->flags);
  237. mutex_unlock(&ha->mbox_sem);
  238. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  239. return status;
  240. }
  241. void qla4xxx_mailbox_premature_completion(struct scsi_qla_host *ha)
  242. {
  243. set_bit(AF_FW_RECOVERY, &ha->flags);
  244. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: set FW RECOVERY!\n",
  245. ha->host_no, __func__);
  246. if (test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  247. if (test_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags)) {
  248. complete(&ha->mbx_intr_comp);
  249. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  250. "recovery, doing premature completion of "
  251. "mbx cmd\n", ha->host_no, __func__);
  252. } else {
  253. set_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  254. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  255. "recovery, doing premature completion of "
  256. "polling mbx cmd\n", ha->host_no, __func__);
  257. }
  258. }
  259. }
  260. static uint8_t
  261. qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  262. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  263. {
  264. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  265. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  266. if (is_qla8022(ha))
  267. qla4_8xxx_wr_32(ha, ha->nx_db_wr_ptr, 0);
  268. mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
  269. mbox_cmd[1] = 0;
  270. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  271. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  272. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  273. mbox_cmd[5] = (IFCB_VER_MAX << 8) | IFCB_VER_MIN;
  274. if (qla4xxx_mailbox_command(ha, 6, 6, mbox_cmd, mbox_sts) !=
  275. QLA_SUCCESS) {
  276. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  277. "MBOX_CMD_INITIALIZE_FIRMWARE"
  278. " failed w/ status %04X\n",
  279. ha->host_no, __func__, mbox_sts[0]));
  280. return QLA_ERROR;
  281. }
  282. return QLA_SUCCESS;
  283. }
  284. static uint8_t
  285. qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  286. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  287. {
  288. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  289. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  290. mbox_cmd[0] = MBOX_CMD_GET_INIT_FW_CTRL_BLOCK;
  291. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  292. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  293. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  294. if (qla4xxx_mailbox_command(ha, 5, 5, mbox_cmd, mbox_sts) !=
  295. QLA_SUCCESS) {
  296. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  297. "MBOX_CMD_GET_INIT_FW_CTRL_BLOCK"
  298. " failed w/ status %04X\n",
  299. ha->host_no, __func__, mbox_sts[0]));
  300. return QLA_ERROR;
  301. }
  302. return QLA_SUCCESS;
  303. }
  304. static void
  305. qla4xxx_update_local_ip(struct scsi_qla_host *ha,
  306. struct addr_ctrl_blk *init_fw_cb)
  307. {
  308. /* Save IPv4 Address Info */
  309. memcpy(ha->ip_address, init_fw_cb->ipv4_addr,
  310. min(sizeof(ha->ip_address), sizeof(init_fw_cb->ipv4_addr)));
  311. memcpy(ha->subnet_mask, init_fw_cb->ipv4_subnet,
  312. min(sizeof(ha->subnet_mask), sizeof(init_fw_cb->ipv4_subnet)));
  313. memcpy(ha->gateway, init_fw_cb->ipv4_gw_addr,
  314. min(sizeof(ha->gateway), sizeof(init_fw_cb->ipv4_gw_addr)));
  315. if (is_ipv6_enabled(ha)) {
  316. /* Save IPv6 Address */
  317. ha->ipv6_link_local_state = init_fw_cb->ipv6_lnk_lcl_addr_state;
  318. ha->ipv6_addr0_state = init_fw_cb->ipv6_addr0_state;
  319. ha->ipv6_addr1_state = init_fw_cb->ipv6_addr1_state;
  320. ha->ipv6_default_router_state = init_fw_cb->ipv6_dflt_rtr_state;
  321. ha->ipv6_link_local_addr.in6_u.u6_addr8[0] = 0xFE;
  322. ha->ipv6_link_local_addr.in6_u.u6_addr8[1] = 0x80;
  323. memcpy(&ha->ipv6_link_local_addr.in6_u.u6_addr8[8],
  324. init_fw_cb->ipv6_if_id,
  325. min(sizeof(ha->ipv6_link_local_addr)/2,
  326. sizeof(init_fw_cb->ipv6_if_id)));
  327. memcpy(&ha->ipv6_addr0, init_fw_cb->ipv6_addr0,
  328. min(sizeof(ha->ipv6_addr0),
  329. sizeof(init_fw_cb->ipv6_addr0)));
  330. memcpy(&ha->ipv6_addr1, init_fw_cb->ipv6_addr1,
  331. min(sizeof(ha->ipv6_addr1),
  332. sizeof(init_fw_cb->ipv6_addr1)));
  333. memcpy(&ha->ipv6_default_router_addr,
  334. init_fw_cb->ipv6_dflt_rtr_addr,
  335. min(sizeof(ha->ipv6_default_router_addr),
  336. sizeof(init_fw_cb->ipv6_dflt_rtr_addr)));
  337. }
  338. }
  339. static uint8_t
  340. qla4xxx_update_local_ifcb(struct scsi_qla_host *ha,
  341. uint32_t *mbox_cmd,
  342. uint32_t *mbox_sts,
  343. struct addr_ctrl_blk *init_fw_cb,
  344. dma_addr_t init_fw_cb_dma)
  345. {
  346. if (qla4xxx_get_ifcb(ha, mbox_cmd, mbox_sts, init_fw_cb_dma)
  347. != QLA_SUCCESS) {
  348. DEBUG2(printk(KERN_WARNING
  349. "scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  350. ha->host_no, __func__));
  351. return QLA_ERROR;
  352. }
  353. DEBUG2(qla4xxx_dump_buffer(init_fw_cb, sizeof(struct addr_ctrl_blk)));
  354. /* Save some info in adapter structure. */
  355. ha->acb_version = init_fw_cb->acb_version;
  356. ha->firmware_options = le16_to_cpu(init_fw_cb->fw_options);
  357. ha->tcp_options = le16_to_cpu(init_fw_cb->ipv4_tcp_opts);
  358. ha->ipv4_options = le16_to_cpu(init_fw_cb->ipv4_ip_opts);
  359. ha->ipv4_addr_state = le16_to_cpu(init_fw_cb->ipv4_addr_state);
  360. ha->heartbeat_interval = init_fw_cb->hb_interval;
  361. memcpy(ha->name_string, init_fw_cb->iscsi_name,
  362. min(sizeof(ha->name_string),
  363. sizeof(init_fw_cb->iscsi_name)));
  364. /*memcpy(ha->alias, init_fw_cb->Alias,
  365. min(sizeof(ha->alias), sizeof(init_fw_cb->Alias)));*/
  366. if (ha->acb_version == ACB_SUPPORTED) {
  367. ha->ipv6_options = init_fw_cb->ipv6_opts;
  368. ha->ipv6_addl_options = init_fw_cb->ipv6_addtl_opts;
  369. }
  370. qla4xxx_update_local_ip(ha, init_fw_cb);
  371. return QLA_SUCCESS;
  372. }
  373. /**
  374. * qla4xxx_initialize_fw_cb - initializes firmware control block.
  375. * @ha: Pointer to host adapter structure.
  376. **/
  377. int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha)
  378. {
  379. struct addr_ctrl_blk *init_fw_cb;
  380. dma_addr_t init_fw_cb_dma;
  381. uint32_t mbox_cmd[MBOX_REG_COUNT];
  382. uint32_t mbox_sts[MBOX_REG_COUNT];
  383. int status = QLA_ERROR;
  384. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  385. sizeof(struct addr_ctrl_blk),
  386. &init_fw_cb_dma, GFP_KERNEL);
  387. if (init_fw_cb == NULL) {
  388. DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n",
  389. ha->host_no, __func__));
  390. goto exit_init_fw_cb_no_free;
  391. }
  392. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  393. /* Get Initialize Firmware Control Block. */
  394. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  395. memset(&mbox_sts, 0, sizeof(mbox_sts));
  396. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  397. QLA_SUCCESS) {
  398. dma_free_coherent(&ha->pdev->dev,
  399. sizeof(struct addr_ctrl_blk),
  400. init_fw_cb, init_fw_cb_dma);
  401. goto exit_init_fw_cb;
  402. }
  403. /* Initialize request and response queues. */
  404. qla4xxx_init_rings(ha);
  405. /* Fill in the request and response queue information. */
  406. init_fw_cb->rqq_consumer_idx = cpu_to_le16(ha->request_out);
  407. init_fw_cb->compq_producer_idx = cpu_to_le16(ha->response_in);
  408. init_fw_cb->rqq_len = __constant_cpu_to_le16(REQUEST_QUEUE_DEPTH);
  409. init_fw_cb->compq_len = __constant_cpu_to_le16(RESPONSE_QUEUE_DEPTH);
  410. init_fw_cb->rqq_addr_lo = cpu_to_le32(LSDW(ha->request_dma));
  411. init_fw_cb->rqq_addr_hi = cpu_to_le32(MSDW(ha->request_dma));
  412. init_fw_cb->compq_addr_lo = cpu_to_le32(LSDW(ha->response_dma));
  413. init_fw_cb->compq_addr_hi = cpu_to_le32(MSDW(ha->response_dma));
  414. init_fw_cb->shdwreg_addr_lo = cpu_to_le32(LSDW(ha->shadow_regs_dma));
  415. init_fw_cb->shdwreg_addr_hi = cpu_to_le32(MSDW(ha->shadow_regs_dma));
  416. /* Set up required options. */
  417. init_fw_cb->fw_options |=
  418. __constant_cpu_to_le16(FWOPT_SESSION_MODE |
  419. FWOPT_INITIATOR_MODE);
  420. if (is_qla8022(ha))
  421. init_fw_cb->fw_options |=
  422. __constant_cpu_to_le16(FWOPT_ENABLE_CRBDB);
  423. init_fw_cb->fw_options &= __constant_cpu_to_le16(~FWOPT_TARGET_MODE);
  424. if (qla4xxx_set_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma)
  425. != QLA_SUCCESS) {
  426. DEBUG2(printk(KERN_WARNING
  427. "scsi%ld: %s: Failed to set init_fw_ctrl_blk\n",
  428. ha->host_no, __func__));
  429. goto exit_init_fw_cb;
  430. }
  431. if (qla4xxx_update_local_ifcb(ha, &mbox_cmd[0], &mbox_sts[0],
  432. init_fw_cb, init_fw_cb_dma) != QLA_SUCCESS) {
  433. DEBUG2(printk("scsi%ld: %s: Failed to update local ifcb\n",
  434. ha->host_no, __func__));
  435. goto exit_init_fw_cb;
  436. }
  437. status = QLA_SUCCESS;
  438. exit_init_fw_cb:
  439. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  440. init_fw_cb, init_fw_cb_dma);
  441. exit_init_fw_cb_no_free:
  442. return status;
  443. }
  444. /**
  445. * qla4xxx_get_dhcp_ip_address - gets HBA ip address via DHCP
  446. * @ha: Pointer to host adapter structure.
  447. **/
  448. int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host * ha)
  449. {
  450. struct addr_ctrl_blk *init_fw_cb;
  451. dma_addr_t init_fw_cb_dma;
  452. uint32_t mbox_cmd[MBOX_REG_COUNT];
  453. uint32_t mbox_sts[MBOX_REG_COUNT];
  454. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  455. sizeof(struct addr_ctrl_blk),
  456. &init_fw_cb_dma, GFP_KERNEL);
  457. if (init_fw_cb == NULL) {
  458. printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no,
  459. __func__);
  460. return QLA_ERROR;
  461. }
  462. /* Get Initialize Firmware Control Block. */
  463. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  464. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  465. QLA_SUCCESS) {
  466. DEBUG2(printk("scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  467. ha->host_no, __func__));
  468. dma_free_coherent(&ha->pdev->dev,
  469. sizeof(struct addr_ctrl_blk),
  470. init_fw_cb, init_fw_cb_dma);
  471. return QLA_ERROR;
  472. }
  473. /* Save IP Address. */
  474. qla4xxx_update_local_ip(ha, init_fw_cb);
  475. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  476. init_fw_cb, init_fw_cb_dma);
  477. return QLA_SUCCESS;
  478. }
  479. /**
  480. * qla4xxx_get_firmware_state - gets firmware state of HBA
  481. * @ha: Pointer to host adapter structure.
  482. **/
  483. int qla4xxx_get_firmware_state(struct scsi_qla_host * ha)
  484. {
  485. uint32_t mbox_cmd[MBOX_REG_COUNT];
  486. uint32_t mbox_sts[MBOX_REG_COUNT];
  487. /* Get firmware version */
  488. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  489. memset(&mbox_sts, 0, sizeof(mbox_sts));
  490. mbox_cmd[0] = MBOX_CMD_GET_FW_STATE;
  491. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 4, &mbox_cmd[0], &mbox_sts[0]) !=
  492. QLA_SUCCESS) {
  493. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATE failed w/ "
  494. "status %04X\n", ha->host_no, __func__,
  495. mbox_sts[0]));
  496. return QLA_ERROR;
  497. }
  498. ha->firmware_state = mbox_sts[1];
  499. ha->board_id = mbox_sts[2];
  500. ha->addl_fw_state = mbox_sts[3];
  501. DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n",
  502. ha->host_no, __func__, ha->firmware_state);)
  503. return QLA_SUCCESS;
  504. }
  505. /**
  506. * qla4xxx_get_firmware_status - retrieves firmware status
  507. * @ha: Pointer to host adapter structure.
  508. **/
  509. int qla4xxx_get_firmware_status(struct scsi_qla_host * ha)
  510. {
  511. uint32_t mbox_cmd[MBOX_REG_COUNT];
  512. uint32_t mbox_sts[MBOX_REG_COUNT];
  513. /* Get firmware version */
  514. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  515. memset(&mbox_sts, 0, sizeof(mbox_sts));
  516. mbox_cmd[0] = MBOX_CMD_GET_FW_STATUS;
  517. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
  518. QLA_SUCCESS) {
  519. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATUS failed w/ "
  520. "status %04X\n", ha->host_no, __func__,
  521. mbox_sts[0]));
  522. return QLA_ERROR;
  523. }
  524. ql4_printk(KERN_INFO, ha, "%ld firmare IOCBs available (%d).\n",
  525. ha->host_no, mbox_sts[2]);
  526. return QLA_SUCCESS;
  527. }
  528. /**
  529. * qla4xxx_get_fwddb_entry - retrieves firmware ddb entry
  530. * @ha: Pointer to host adapter structure.
  531. * @fw_ddb_index: Firmware's device database index
  532. * @fw_ddb_entry: Pointer to firmware's device database entry structure
  533. * @num_valid_ddb_entries: Pointer to number of valid ddb entries
  534. * @next_ddb_index: Pointer to next valid device database index
  535. * @fw_ddb_device_state: Pointer to device state
  536. **/
  537. int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha,
  538. uint16_t fw_ddb_index,
  539. struct dev_db_entry *fw_ddb_entry,
  540. dma_addr_t fw_ddb_entry_dma,
  541. uint32_t *num_valid_ddb_entries,
  542. uint32_t *next_ddb_index,
  543. uint32_t *fw_ddb_device_state,
  544. uint32_t *conn_err_detail,
  545. uint16_t *tcp_source_port_num,
  546. uint16_t *connection_id)
  547. {
  548. int status = QLA_ERROR;
  549. uint16_t options;
  550. uint32_t mbox_cmd[MBOX_REG_COUNT];
  551. uint32_t mbox_sts[MBOX_REG_COUNT];
  552. /* Make sure the device index is valid */
  553. if (fw_ddb_index >= MAX_DDB_ENTRIES) {
  554. DEBUG2(printk("scsi%ld: %s: ddb [%d] out of range.\n",
  555. ha->host_no, __func__, fw_ddb_index));
  556. goto exit_get_fwddb;
  557. }
  558. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  559. memset(&mbox_sts, 0, sizeof(mbox_sts));
  560. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY;
  561. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  562. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  563. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  564. mbox_cmd[4] = sizeof(struct dev_db_entry);
  565. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 7, &mbox_cmd[0], &mbox_sts[0]) ==
  566. QLA_ERROR) {
  567. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_DATABASE_ENTRY failed"
  568. " with status 0x%04X\n", ha->host_no, __func__,
  569. mbox_sts[0]));
  570. goto exit_get_fwddb;
  571. }
  572. if (fw_ddb_index != mbox_sts[1]) {
  573. DEBUG2(printk("scsi%ld: %s: ddb mismatch [%d] != [%d].\n",
  574. ha->host_no, __func__, fw_ddb_index,
  575. mbox_sts[1]));
  576. goto exit_get_fwddb;
  577. }
  578. if (fw_ddb_entry) {
  579. options = le16_to_cpu(fw_ddb_entry->options);
  580. if (options & DDB_OPT_IPV6_DEVICE) {
  581. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  582. "Next %d State %04x ConnErr %08x %pI6 "
  583. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  584. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  585. mbox_sts[4], mbox_sts[5],
  586. fw_ddb_entry->ip_addr,
  587. le16_to_cpu(fw_ddb_entry->port),
  588. fw_ddb_entry->iscsi_name);
  589. } else {
  590. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  591. "Next %d State %04x ConnErr %08x %pI4 "
  592. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  593. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  594. mbox_sts[4], mbox_sts[5],
  595. fw_ddb_entry->ip_addr,
  596. le16_to_cpu(fw_ddb_entry->port),
  597. fw_ddb_entry->iscsi_name);
  598. }
  599. }
  600. if (num_valid_ddb_entries)
  601. *num_valid_ddb_entries = mbox_sts[2];
  602. if (next_ddb_index)
  603. *next_ddb_index = mbox_sts[3];
  604. if (fw_ddb_device_state)
  605. *fw_ddb_device_state = mbox_sts[4];
  606. /*
  607. * RA: This mailbox has been changed to pass connection error and
  608. * details. Its true for ISP4010 as per Version E - Not sure when it
  609. * was changed. Get the time2wait from the fw_dd_entry field :
  610. * default_time2wait which we call it as minTime2Wait DEV_DB_ENTRY
  611. * struct.
  612. */
  613. if (conn_err_detail)
  614. *conn_err_detail = mbox_sts[5];
  615. if (tcp_source_port_num)
  616. *tcp_source_port_num = (uint16_t) (mbox_sts[6] >> 16);
  617. if (connection_id)
  618. *connection_id = (uint16_t) mbox_sts[6] & 0x00FF;
  619. status = QLA_SUCCESS;
  620. exit_get_fwddb:
  621. return status;
  622. }
  623. /**
  624. * qla4xxx_set_fwddb_entry - sets a ddb entry.
  625. * @ha: Pointer to host adapter structure.
  626. * @fw_ddb_index: Firmware's device database index
  627. * @fw_ddb_entry: Pointer to firmware's ddb entry structure, or NULL.
  628. *
  629. * This routine initializes or updates the adapter's device database
  630. * entry for the specified device. It also triggers a login for the
  631. * specified device. Therefore, it may also be used as a secondary
  632. * login routine when a NULL pointer is specified for the fw_ddb_entry.
  633. **/
  634. int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index,
  635. dma_addr_t fw_ddb_entry_dma)
  636. {
  637. uint32_t mbox_cmd[MBOX_REG_COUNT];
  638. uint32_t mbox_sts[MBOX_REG_COUNT];
  639. int status;
  640. /* Do not wait for completion. The firmware will send us an
  641. * ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status.
  642. */
  643. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  644. memset(&mbox_sts, 0, sizeof(mbox_sts));
  645. mbox_cmd[0] = MBOX_CMD_SET_DATABASE_ENTRY;
  646. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  647. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  648. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  649. mbox_cmd[4] = sizeof(struct dev_db_entry);
  650. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  651. &mbox_sts[0]);
  652. DEBUG2(printk("scsi%ld: %s: status=%d mbx0=0x%x mbx4=0x%x\n",
  653. ha->host_no, __func__, status, mbox_sts[0], mbox_sts[4]);)
  654. return status;
  655. }
  656. /**
  657. * qla4xxx_get_crash_record - retrieves crash record.
  658. * @ha: Pointer to host adapter structure.
  659. *
  660. * This routine retrieves a crash record from the QLA4010 after an 8002h aen.
  661. **/
  662. void qla4xxx_get_crash_record(struct scsi_qla_host * ha)
  663. {
  664. uint32_t mbox_cmd[MBOX_REG_COUNT];
  665. uint32_t mbox_sts[MBOX_REG_COUNT];
  666. struct crash_record *crash_record = NULL;
  667. dma_addr_t crash_record_dma = 0;
  668. uint32_t crash_record_size = 0;
  669. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  670. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  671. /* Get size of crash record. */
  672. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  673. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  674. QLA_SUCCESS) {
  675. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve size!\n",
  676. ha->host_no, __func__));
  677. goto exit_get_crash_record;
  678. }
  679. crash_record_size = mbox_sts[4];
  680. if (crash_record_size == 0) {
  681. DEBUG2(printk("scsi%ld: %s: ERROR: Crash record size is 0!\n",
  682. ha->host_no, __func__));
  683. goto exit_get_crash_record;
  684. }
  685. /* Alloc Memory for Crash Record. */
  686. crash_record = dma_alloc_coherent(&ha->pdev->dev, crash_record_size,
  687. &crash_record_dma, GFP_KERNEL);
  688. if (crash_record == NULL)
  689. goto exit_get_crash_record;
  690. /* Get Crash Record. */
  691. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  692. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  693. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  694. mbox_cmd[2] = LSDW(crash_record_dma);
  695. mbox_cmd[3] = MSDW(crash_record_dma);
  696. mbox_cmd[4] = crash_record_size;
  697. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  698. QLA_SUCCESS)
  699. goto exit_get_crash_record;
  700. /* Dump Crash Record. */
  701. exit_get_crash_record:
  702. if (crash_record)
  703. dma_free_coherent(&ha->pdev->dev, crash_record_size,
  704. crash_record, crash_record_dma);
  705. }
  706. /**
  707. * qla4xxx_get_conn_event_log - retrieves connection event log
  708. * @ha: Pointer to host adapter structure.
  709. **/
  710. void qla4xxx_get_conn_event_log(struct scsi_qla_host * ha)
  711. {
  712. uint32_t mbox_cmd[MBOX_REG_COUNT];
  713. uint32_t mbox_sts[MBOX_REG_COUNT];
  714. struct conn_event_log_entry *event_log = NULL;
  715. dma_addr_t event_log_dma = 0;
  716. uint32_t event_log_size = 0;
  717. uint32_t num_valid_entries;
  718. uint32_t oldest_entry = 0;
  719. uint32_t max_event_log_entries;
  720. uint8_t i;
  721. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  722. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  723. /* Get size of crash record. */
  724. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  725. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  726. QLA_SUCCESS)
  727. goto exit_get_event_log;
  728. event_log_size = mbox_sts[4];
  729. if (event_log_size == 0)
  730. goto exit_get_event_log;
  731. /* Alloc Memory for Crash Record. */
  732. event_log = dma_alloc_coherent(&ha->pdev->dev, event_log_size,
  733. &event_log_dma, GFP_KERNEL);
  734. if (event_log == NULL)
  735. goto exit_get_event_log;
  736. /* Get Crash Record. */
  737. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  738. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  739. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  740. mbox_cmd[2] = LSDW(event_log_dma);
  741. mbox_cmd[3] = MSDW(event_log_dma);
  742. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  743. QLA_SUCCESS) {
  744. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve event "
  745. "log!\n", ha->host_no, __func__));
  746. goto exit_get_event_log;
  747. }
  748. /* Dump Event Log. */
  749. num_valid_entries = mbox_sts[1];
  750. max_event_log_entries = event_log_size /
  751. sizeof(struct conn_event_log_entry);
  752. if (num_valid_entries > max_event_log_entries)
  753. oldest_entry = num_valid_entries % max_event_log_entries;
  754. DEBUG3(printk("scsi%ld: Connection Event Log Dump (%d entries):\n",
  755. ha->host_no, num_valid_entries));
  756. if (ql4xextended_error_logging == 3) {
  757. if (oldest_entry == 0) {
  758. /* Circular Buffer has not wrapped around */
  759. for (i=0; i < num_valid_entries; i++) {
  760. qla4xxx_dump_buffer((uint8_t *)event_log+
  761. (i*sizeof(*event_log)),
  762. sizeof(*event_log));
  763. }
  764. }
  765. else {
  766. /* Circular Buffer has wrapped around -
  767. * display accordingly*/
  768. for (i=oldest_entry; i < max_event_log_entries; i++) {
  769. qla4xxx_dump_buffer((uint8_t *)event_log+
  770. (i*sizeof(*event_log)),
  771. sizeof(*event_log));
  772. }
  773. for (i=0; i < oldest_entry; i++) {
  774. qla4xxx_dump_buffer((uint8_t *)event_log+
  775. (i*sizeof(*event_log)),
  776. sizeof(*event_log));
  777. }
  778. }
  779. }
  780. exit_get_event_log:
  781. if (event_log)
  782. dma_free_coherent(&ha->pdev->dev, event_log_size, event_log,
  783. event_log_dma);
  784. }
  785. /**
  786. * qla4xxx_abort_task - issues Abort Task
  787. * @ha: Pointer to host adapter structure.
  788. * @srb: Pointer to srb entry
  789. *
  790. * This routine performs a LUN RESET on the specified target/lun.
  791. * The caller must ensure that the ddb_entry and lun_entry pointers
  792. * are valid before calling this routine.
  793. **/
  794. int qla4xxx_abort_task(struct scsi_qla_host *ha, struct srb *srb)
  795. {
  796. uint32_t mbox_cmd[MBOX_REG_COUNT];
  797. uint32_t mbox_sts[MBOX_REG_COUNT];
  798. struct scsi_cmnd *cmd = srb->cmd;
  799. int status = QLA_SUCCESS;
  800. unsigned long flags = 0;
  801. uint32_t index;
  802. /*
  803. * Send abort task command to ISP, so that the ISP will return
  804. * request with ABORT status
  805. */
  806. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  807. memset(&mbox_sts, 0, sizeof(mbox_sts));
  808. spin_lock_irqsave(&ha->hardware_lock, flags);
  809. index = (unsigned long)(unsigned char *)cmd->host_scribble;
  810. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  811. /* Firmware already posted completion on response queue */
  812. if (index == MAX_SRBS)
  813. return status;
  814. mbox_cmd[0] = MBOX_CMD_ABORT_TASK;
  815. mbox_cmd[1] = srb->ddb->fw_ddb_index;
  816. mbox_cmd[2] = index;
  817. /* Immediate Command Enable */
  818. mbox_cmd[5] = 0x01;
  819. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  820. &mbox_sts[0]);
  821. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE) {
  822. status = QLA_ERROR;
  823. DEBUG2(printk(KERN_WARNING "scsi%ld:%d:%d: abort task FAILED: "
  824. "mbx0=%04X, mb1=%04X, mb2=%04X, mb3=%04X, mb4=%04X\n",
  825. ha->host_no, cmd->device->id, cmd->device->lun, mbox_sts[0],
  826. mbox_sts[1], mbox_sts[2], mbox_sts[3], mbox_sts[4]));
  827. }
  828. return status;
  829. }
  830. /**
  831. * qla4xxx_reset_lun - issues LUN Reset
  832. * @ha: Pointer to host adapter structure.
  833. * @ddb_entry: Pointer to device database entry
  834. * @lun: lun number
  835. *
  836. * This routine performs a LUN RESET on the specified target/lun.
  837. * The caller must ensure that the ddb_entry and lun_entry pointers
  838. * are valid before calling this routine.
  839. **/
  840. int qla4xxx_reset_lun(struct scsi_qla_host * ha, struct ddb_entry * ddb_entry,
  841. int lun)
  842. {
  843. uint32_t mbox_cmd[MBOX_REG_COUNT];
  844. uint32_t mbox_sts[MBOX_REG_COUNT];
  845. int status = QLA_SUCCESS;
  846. DEBUG2(printk("scsi%ld:%d:%d: lun reset issued\n", ha->host_no,
  847. ddb_entry->fw_ddb_index, lun));
  848. /*
  849. * Send lun reset command to ISP, so that the ISP will return all
  850. * outstanding requests with RESET status
  851. */
  852. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  853. memset(&mbox_sts, 0, sizeof(mbox_sts));
  854. mbox_cmd[0] = MBOX_CMD_LUN_RESET;
  855. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  856. mbox_cmd[2] = lun << 8;
  857. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  858. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]);
  859. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  860. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  861. status = QLA_ERROR;
  862. return status;
  863. }
  864. /**
  865. * qla4xxx_reset_target - issues target Reset
  866. * @ha: Pointer to host adapter structure.
  867. * @db_entry: Pointer to device database entry
  868. * @un_entry: Pointer to lun entry structure
  869. *
  870. * This routine performs a TARGET RESET on the specified target.
  871. * The caller must ensure that the ddb_entry pointers
  872. * are valid before calling this routine.
  873. **/
  874. int qla4xxx_reset_target(struct scsi_qla_host *ha,
  875. struct ddb_entry *ddb_entry)
  876. {
  877. uint32_t mbox_cmd[MBOX_REG_COUNT];
  878. uint32_t mbox_sts[MBOX_REG_COUNT];
  879. int status = QLA_SUCCESS;
  880. DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no,
  881. ddb_entry->fw_ddb_index));
  882. /*
  883. * Send target reset command to ISP, so that the ISP will return all
  884. * outstanding requests with RESET status
  885. */
  886. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  887. memset(&mbox_sts, 0, sizeof(mbox_sts));
  888. mbox_cmd[0] = MBOX_CMD_TARGET_WARM_RESET;
  889. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  890. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  891. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  892. &mbox_sts[0]);
  893. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  894. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  895. status = QLA_ERROR;
  896. return status;
  897. }
  898. int qla4xxx_get_flash(struct scsi_qla_host * ha, dma_addr_t dma_addr,
  899. uint32_t offset, uint32_t len)
  900. {
  901. uint32_t mbox_cmd[MBOX_REG_COUNT];
  902. uint32_t mbox_sts[MBOX_REG_COUNT];
  903. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  904. memset(&mbox_sts, 0, sizeof(mbox_sts));
  905. mbox_cmd[0] = MBOX_CMD_READ_FLASH;
  906. mbox_cmd[1] = LSDW(dma_addr);
  907. mbox_cmd[2] = MSDW(dma_addr);
  908. mbox_cmd[3] = offset;
  909. mbox_cmd[4] = len;
  910. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], &mbox_sts[0]) !=
  911. QLA_SUCCESS) {
  912. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_READ_FLASH, failed w/ "
  913. "status %04X %04X, offset %08x, len %08x\n", ha->host_no,
  914. __func__, mbox_sts[0], mbox_sts[1], offset, len));
  915. return QLA_ERROR;
  916. }
  917. return QLA_SUCCESS;
  918. }
  919. /**
  920. * qla4xxx_get_fw_version - gets firmware version
  921. * @ha: Pointer to host adapter structure.
  922. *
  923. * Retrieves the firmware version on HBA. In QLA4010, mailboxes 2 & 3 may
  924. * hold an address for data. Make sure that we write 0 to those mailboxes,
  925. * if unused.
  926. **/
  927. int qla4xxx_get_fw_version(struct scsi_qla_host * ha)
  928. {
  929. uint32_t mbox_cmd[MBOX_REG_COUNT];
  930. uint32_t mbox_sts[MBOX_REG_COUNT];
  931. /* Get firmware version. */
  932. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  933. memset(&mbox_sts, 0, sizeof(mbox_sts));
  934. mbox_cmd[0] = MBOX_CMD_ABOUT_FW;
  935. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  936. QLA_SUCCESS) {
  937. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_ABOUT_FW failed w/ "
  938. "status %04X\n", ha->host_no, __func__, mbox_sts[0]));
  939. return QLA_ERROR;
  940. }
  941. /* Save firmware version information. */
  942. ha->firmware_version[0] = mbox_sts[1];
  943. ha->firmware_version[1] = mbox_sts[2];
  944. ha->patch_number = mbox_sts[3];
  945. ha->build_number = mbox_sts[4];
  946. return QLA_SUCCESS;
  947. }
  948. static int qla4xxx_get_default_ddb(struct scsi_qla_host *ha,
  949. dma_addr_t dma_addr)
  950. {
  951. uint32_t mbox_cmd[MBOX_REG_COUNT];
  952. uint32_t mbox_sts[MBOX_REG_COUNT];
  953. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  954. memset(&mbox_sts, 0, sizeof(mbox_sts));
  955. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS;
  956. mbox_cmd[2] = LSDW(dma_addr);
  957. mbox_cmd[3] = MSDW(dma_addr);
  958. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]) !=
  959. QLA_SUCCESS) {
  960. DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
  961. ha->host_no, __func__, mbox_sts[0]));
  962. return QLA_ERROR;
  963. }
  964. return QLA_SUCCESS;
  965. }
  966. static int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t *ddb_index)
  967. {
  968. uint32_t mbox_cmd[MBOX_REG_COUNT];
  969. uint32_t mbox_sts[MBOX_REG_COUNT];
  970. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  971. memset(&mbox_sts, 0, sizeof(mbox_sts));
  972. mbox_cmd[0] = MBOX_CMD_REQUEST_DATABASE_ENTRY;
  973. mbox_cmd[1] = MAX_PRST_DEV_DB_ENTRIES;
  974. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
  975. QLA_SUCCESS) {
  976. if (mbox_sts[0] == MBOX_STS_COMMAND_ERROR) {
  977. *ddb_index = mbox_sts[2];
  978. } else {
  979. DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
  980. ha->host_no, __func__, mbox_sts[0]));
  981. return QLA_ERROR;
  982. }
  983. } else {
  984. *ddb_index = MAX_PRST_DEV_DB_ENTRIES;
  985. }
  986. return QLA_SUCCESS;
  987. }
  988. int qla4xxx_send_tgts(struct scsi_qla_host *ha, char *ip, uint16_t port)
  989. {
  990. struct dev_db_entry *fw_ddb_entry;
  991. dma_addr_t fw_ddb_entry_dma;
  992. uint32_t ddb_index;
  993. int ret_val = QLA_SUCCESS;
  994. fw_ddb_entry = dma_alloc_coherent(&ha->pdev->dev,
  995. sizeof(*fw_ddb_entry),
  996. &fw_ddb_entry_dma, GFP_KERNEL);
  997. if (!fw_ddb_entry) {
  998. DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
  999. ha->host_no, __func__));
  1000. ret_val = QLA_ERROR;
  1001. goto exit_send_tgts_no_free;
  1002. }
  1003. ret_val = qla4xxx_get_default_ddb(ha, fw_ddb_entry_dma);
  1004. if (ret_val != QLA_SUCCESS)
  1005. goto exit_send_tgts;
  1006. ret_val = qla4xxx_req_ddb_entry(ha, &ddb_index);
  1007. if (ret_val != QLA_SUCCESS)
  1008. goto exit_send_tgts;
  1009. memset(fw_ddb_entry->iscsi_alias, 0,
  1010. sizeof(fw_ddb_entry->iscsi_alias));
  1011. memset(fw_ddb_entry->iscsi_name, 0,
  1012. sizeof(fw_ddb_entry->iscsi_name));
  1013. memset(fw_ddb_entry->ip_addr, 0, sizeof(fw_ddb_entry->ip_addr));
  1014. memset(fw_ddb_entry->tgt_addr, 0,
  1015. sizeof(fw_ddb_entry->tgt_addr));
  1016. fw_ddb_entry->options = (DDB_OPT_DISC_SESSION | DDB_OPT_TARGET);
  1017. fw_ddb_entry->port = cpu_to_le16(ntohs(port));
  1018. fw_ddb_entry->ip_addr[0] = *ip;
  1019. fw_ddb_entry->ip_addr[1] = *(ip + 1);
  1020. fw_ddb_entry->ip_addr[2] = *(ip + 2);
  1021. fw_ddb_entry->ip_addr[3] = *(ip + 3);
  1022. ret_val = qla4xxx_set_ddb_entry(ha, ddb_index, fw_ddb_entry_dma);
  1023. exit_send_tgts:
  1024. dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
  1025. fw_ddb_entry, fw_ddb_entry_dma);
  1026. exit_send_tgts_no_free:
  1027. return ret_val;
  1028. }