hw_host1x01_sync.h 4.0 KB

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  1. /*
  2. * Copyright (c) 2012-2013, NVIDIA Corporation.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms and conditions of the GNU General Public License,
  6. * version 2, as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope it will be useful, but WITHOUT
  9. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11. * more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  15. *
  16. */
  17. /*
  18. * Function naming determines intended use:
  19. *
  20. * <x>_r(void) : Returns the offset for register <x>.
  21. *
  22. * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
  23. *
  24. * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
  25. *
  26. * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
  27. * and masked to place it at field <y> of register <x>. This value
  28. * can be |'d with others to produce a full register value for
  29. * register <x>.
  30. *
  31. * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
  32. * value can be ~'d and then &'d to clear the value of field <y> for
  33. * register <x>.
  34. *
  35. * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
  36. * to place it at field <y> of register <x>. This value can be |'d
  37. * with others to produce a full register value for <x>.
  38. *
  39. * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
  40. * <x> value 'r' after being shifted to place its LSB at bit 0.
  41. * This value is suitable for direct comparison with other unshifted
  42. * values appropriate for use in field <y> of register <x>.
  43. *
  44. * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
  45. * field <y> of register <x>. This value is suitable for direct
  46. * comparison with unshifted values appropriate for use in field <y>
  47. * of register <x>.
  48. */
  49. #ifndef __hw_host1x01_sync_h__
  50. #define __hw_host1x01_sync_h__
  51. #define REGISTER_STRIDE 4
  52. static inline u32 host1x_sync_syncpt_r(unsigned int id)
  53. {
  54. return 0x400 + id * REGISTER_STRIDE;
  55. }
  56. #define HOST1X_SYNC_SYNCPT(id) \
  57. host1x_sync_syncpt_r(id)
  58. static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id)
  59. {
  60. return 0x40 + id * REGISTER_STRIDE;
  61. }
  62. #define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \
  63. host1x_sync_syncpt_thresh_cpu0_int_status_r(id)
  64. static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id)
  65. {
  66. return 0x60 + id * REGISTER_STRIDE;
  67. }
  68. #define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id) \
  69. host1x_sync_syncpt_thresh_int_disable_r(id)
  70. static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(unsigned int id)
  71. {
  72. return 0x68 + id * REGISTER_STRIDE;
  73. }
  74. #define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id) \
  75. host1x_sync_syncpt_thresh_int_enable_cpu0_r(id)
  76. static inline u32 host1x_sync_usec_clk_r(void)
  77. {
  78. return 0x1a4;
  79. }
  80. #define HOST1X_SYNC_USEC_CLK \
  81. host1x_sync_usec_clk_r()
  82. static inline u32 host1x_sync_ctxsw_timeout_cfg_r(void)
  83. {
  84. return 0x1a8;
  85. }
  86. #define HOST1X_SYNC_CTXSW_TIMEOUT_CFG \
  87. host1x_sync_ctxsw_timeout_cfg_r()
  88. static inline u32 host1x_sync_ip_busy_timeout_r(void)
  89. {
  90. return 0x1bc;
  91. }
  92. #define HOST1X_SYNC_IP_BUSY_TIMEOUT \
  93. host1x_sync_ip_busy_timeout_r()
  94. static inline u32 host1x_sync_syncpt_int_thresh_r(unsigned int id)
  95. {
  96. return 0x500 + id * REGISTER_STRIDE;
  97. }
  98. #define HOST1X_SYNC_SYNCPT_INT_THRESH(id) \
  99. host1x_sync_syncpt_int_thresh_r(id)
  100. static inline u32 host1x_sync_syncpt_base_r(unsigned int id)
  101. {
  102. return 0x600 + id * REGISTER_STRIDE;
  103. }
  104. #define HOST1X_SYNC_SYNCPT_BASE(id) \
  105. host1x_sync_syncpt_base_r(id)
  106. static inline u32 host1x_sync_syncpt_cpu_incr_r(unsigned int id)
  107. {
  108. return 0x700 + id * REGISTER_STRIDE;
  109. }
  110. #define HOST1X_SYNC_SYNCPT_CPU_INCR(id) \
  111. host1x_sync_syncpt_cpu_incr_r(id)
  112. #endif /* __hw_host1x01_sync_h__ */