qla_isr.c 81 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_target.h"
  9. #include <linux/delay.h>
  10. #include <linux/slab.h>
  11. #include <scsi/scsi_tcq.h>
  12. #include <scsi/scsi_bsg_fc.h>
  13. #include <scsi/scsi_eh.h>
  14. static void qla2x00_mbx_completion(scsi_qla_host_t *, uint16_t);
  15. static void qla2x00_status_entry(scsi_qla_host_t *, struct rsp_que *, void *);
  16. static void qla2x00_status_cont_entry(struct rsp_que *, sts_cont_entry_t *);
  17. static void qla2x00_error_entry(scsi_qla_host_t *, struct rsp_que *,
  18. sts_entry_t *);
  19. /**
  20. * qla2100_intr_handler() - Process interrupts for the ISP2100 and ISP2200.
  21. * @irq:
  22. * @dev_id: SCSI driver HA context
  23. *
  24. * Called by system whenever the host adapter generates an interrupt.
  25. *
  26. * Returns handled flag.
  27. */
  28. irqreturn_t
  29. qla2100_intr_handler(int irq, void *dev_id)
  30. {
  31. scsi_qla_host_t *vha;
  32. struct qla_hw_data *ha;
  33. struct device_reg_2xxx __iomem *reg;
  34. int status;
  35. unsigned long iter;
  36. uint16_t hccr;
  37. uint16_t mb[4];
  38. struct rsp_que *rsp;
  39. unsigned long flags;
  40. rsp = (struct rsp_que *) dev_id;
  41. if (!rsp) {
  42. ql_log(ql_log_info, NULL, 0x505d,
  43. "%s: NULL response queue pointer.\n", __func__);
  44. return (IRQ_NONE);
  45. }
  46. ha = rsp->hw;
  47. reg = &ha->iobase->isp;
  48. status = 0;
  49. spin_lock_irqsave(&ha->hardware_lock, flags);
  50. vha = pci_get_drvdata(ha->pdev);
  51. for (iter = 50; iter--; ) {
  52. hccr = RD_REG_WORD(&reg->hccr);
  53. if (hccr & HCCR_RISC_PAUSE) {
  54. if (pci_channel_offline(ha->pdev))
  55. break;
  56. /*
  57. * Issue a "HARD" reset in order for the RISC interrupt
  58. * bit to be cleared. Schedule a big hammer to get
  59. * out of the RISC PAUSED state.
  60. */
  61. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  62. RD_REG_WORD(&reg->hccr);
  63. ha->isp_ops->fw_dump(vha, 1);
  64. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  65. break;
  66. } else if ((RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) == 0)
  67. break;
  68. if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
  69. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  70. RD_REG_WORD(&reg->hccr);
  71. /* Get mailbox data. */
  72. mb[0] = RD_MAILBOX_REG(ha, reg, 0);
  73. if (mb[0] > 0x3fff && mb[0] < 0x8000) {
  74. qla2x00_mbx_completion(vha, mb[0]);
  75. status |= MBX_INTERRUPT;
  76. } else if (mb[0] > 0x7fff && mb[0] < 0xc000) {
  77. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  78. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  79. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  80. qla2x00_async_event(vha, rsp, mb);
  81. } else {
  82. /*EMPTY*/
  83. ql_dbg(ql_dbg_async, vha, 0x5025,
  84. "Unrecognized interrupt type (%d).\n",
  85. mb[0]);
  86. }
  87. /* Release mailbox registers. */
  88. WRT_REG_WORD(&reg->semaphore, 0);
  89. RD_REG_WORD(&reg->semaphore);
  90. } else {
  91. qla2x00_process_response_queue(rsp);
  92. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  93. RD_REG_WORD(&reg->hccr);
  94. }
  95. }
  96. qla2x00_handle_mbx_completion(ha, status);
  97. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  98. return (IRQ_HANDLED);
  99. }
  100. /**
  101. * qla2300_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
  102. * @irq:
  103. * @dev_id: SCSI driver HA context
  104. *
  105. * Called by system whenever the host adapter generates an interrupt.
  106. *
  107. * Returns handled flag.
  108. */
  109. irqreturn_t
  110. qla2300_intr_handler(int irq, void *dev_id)
  111. {
  112. scsi_qla_host_t *vha;
  113. struct device_reg_2xxx __iomem *reg;
  114. int status;
  115. unsigned long iter;
  116. uint32_t stat;
  117. uint16_t hccr;
  118. uint16_t mb[4];
  119. struct rsp_que *rsp;
  120. struct qla_hw_data *ha;
  121. unsigned long flags;
  122. rsp = (struct rsp_que *) dev_id;
  123. if (!rsp) {
  124. ql_log(ql_log_info, NULL, 0x5058,
  125. "%s: NULL response queue pointer.\n", __func__);
  126. return (IRQ_NONE);
  127. }
  128. ha = rsp->hw;
  129. reg = &ha->iobase->isp;
  130. status = 0;
  131. spin_lock_irqsave(&ha->hardware_lock, flags);
  132. vha = pci_get_drvdata(ha->pdev);
  133. for (iter = 50; iter--; ) {
  134. stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
  135. if (stat & HSR_RISC_PAUSED) {
  136. if (unlikely(pci_channel_offline(ha->pdev)))
  137. break;
  138. hccr = RD_REG_WORD(&reg->hccr);
  139. if (hccr & (BIT_15 | BIT_13 | BIT_11 | BIT_8))
  140. ql_log(ql_log_warn, vha, 0x5026,
  141. "Parity error -- HCCR=%x, Dumping "
  142. "firmware.\n", hccr);
  143. else
  144. ql_log(ql_log_warn, vha, 0x5027,
  145. "RISC paused -- HCCR=%x, Dumping "
  146. "firmware.\n", hccr);
  147. /*
  148. * Issue a "HARD" reset in order for the RISC
  149. * interrupt bit to be cleared. Schedule a big
  150. * hammer to get out of the RISC PAUSED state.
  151. */
  152. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  153. RD_REG_WORD(&reg->hccr);
  154. ha->isp_ops->fw_dump(vha, 1);
  155. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  156. break;
  157. } else if ((stat & HSR_RISC_INT) == 0)
  158. break;
  159. switch (stat & 0xff) {
  160. case 0x1:
  161. case 0x2:
  162. case 0x10:
  163. case 0x11:
  164. qla2x00_mbx_completion(vha, MSW(stat));
  165. status |= MBX_INTERRUPT;
  166. /* Release mailbox registers. */
  167. WRT_REG_WORD(&reg->semaphore, 0);
  168. break;
  169. case 0x12:
  170. mb[0] = MSW(stat);
  171. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  172. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  173. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  174. qla2x00_async_event(vha, rsp, mb);
  175. break;
  176. case 0x13:
  177. qla2x00_process_response_queue(rsp);
  178. break;
  179. case 0x15:
  180. mb[0] = MBA_CMPLT_1_16BIT;
  181. mb[1] = MSW(stat);
  182. qla2x00_async_event(vha, rsp, mb);
  183. break;
  184. case 0x16:
  185. mb[0] = MBA_SCSI_COMPLETION;
  186. mb[1] = MSW(stat);
  187. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  188. qla2x00_async_event(vha, rsp, mb);
  189. break;
  190. default:
  191. ql_dbg(ql_dbg_async, vha, 0x5028,
  192. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  193. break;
  194. }
  195. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  196. RD_REG_WORD_RELAXED(&reg->hccr);
  197. }
  198. qla2x00_handle_mbx_completion(ha, status);
  199. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  200. return (IRQ_HANDLED);
  201. }
  202. /**
  203. * qla2x00_mbx_completion() - Process mailbox command completions.
  204. * @ha: SCSI driver HA context
  205. * @mb0: Mailbox0 register
  206. */
  207. static void
  208. qla2x00_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  209. {
  210. uint16_t cnt;
  211. uint32_t mboxes;
  212. uint16_t __iomem *wptr;
  213. struct qla_hw_data *ha = vha->hw;
  214. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  215. /* Read all mbox registers? */
  216. mboxes = (1 << ha->mbx_count) - 1;
  217. if (!ha->mcp)
  218. ql_dbg(ql_dbg_async, vha, 0x5001, "MBX pointer ERROR.\n");
  219. else
  220. mboxes = ha->mcp->in_mb;
  221. /* Load return mailbox registers. */
  222. ha->flags.mbox_int = 1;
  223. ha->mailbox_out[0] = mb0;
  224. mboxes >>= 1;
  225. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 1);
  226. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  227. if (IS_QLA2200(ha) && cnt == 8)
  228. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 8);
  229. if ((cnt == 4 || cnt == 5) && (mboxes & BIT_0))
  230. ha->mailbox_out[cnt] = qla2x00_debounce_register(wptr);
  231. else if (mboxes & BIT_0)
  232. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  233. wptr++;
  234. mboxes >>= 1;
  235. }
  236. }
  237. static void
  238. qla81xx_idc_event(scsi_qla_host_t *vha, uint16_t aen, uint16_t descr)
  239. {
  240. static char *event[] =
  241. { "Complete", "Request Notification", "Time Extension" };
  242. int rval;
  243. struct device_reg_24xx __iomem *reg24 = &vha->hw->iobase->isp24;
  244. uint16_t __iomem *wptr;
  245. uint16_t cnt, timeout, mb[QLA_IDC_ACK_REGS];
  246. /* Seed data -- mailbox1 -> mailbox7. */
  247. wptr = (uint16_t __iomem *)&reg24->mailbox1;
  248. for (cnt = 0; cnt < QLA_IDC_ACK_REGS; cnt++, wptr++)
  249. mb[cnt] = RD_REG_WORD(wptr);
  250. ql_dbg(ql_dbg_async, vha, 0x5021,
  251. "Inter-Driver Communication %s -- "
  252. "%04x %04x %04x %04x %04x %04x %04x.\n",
  253. event[aen & 0xff], mb[0], mb[1], mb[2], mb[3],
  254. mb[4], mb[5], mb[6]);
  255. if ((aen == MBA_IDC_COMPLETE && mb[1] >> 15)) {
  256. vha->hw->flags.idc_compl_status = 1;
  257. if (vha->hw->notify_dcbx_comp)
  258. complete(&vha->hw->dcbx_comp);
  259. }
  260. /* Acknowledgement needed? [Notify && non-zero timeout]. */
  261. timeout = (descr >> 8) & 0xf;
  262. if (aen != MBA_IDC_NOTIFY || !timeout)
  263. return;
  264. ql_dbg(ql_dbg_async, vha, 0x5022,
  265. "%lu Inter-Driver Communication %s -- ACK timeout=%d.\n",
  266. vha->host_no, event[aen & 0xff], timeout);
  267. rval = qla2x00_post_idc_ack_work(vha, mb);
  268. if (rval != QLA_SUCCESS)
  269. ql_log(ql_log_warn, vha, 0x5023,
  270. "IDC failed to post ACK.\n");
  271. }
  272. #define LS_UNKNOWN 2
  273. const char *
  274. qla2x00_get_link_speed_str(struct qla_hw_data *ha, uint16_t speed)
  275. {
  276. static const char * const link_speeds[] = {
  277. "1", "2", "?", "4", "8", "16", "10"
  278. };
  279. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  280. return link_speeds[0];
  281. else if (speed == 0x13)
  282. return link_speeds[6];
  283. else if (speed < 6)
  284. return link_speeds[speed];
  285. else
  286. return link_speeds[LS_UNKNOWN];
  287. }
  288. static void
  289. qla83xx_handle_8200_aen(scsi_qla_host_t *vha, uint16_t *mb)
  290. {
  291. struct qla_hw_data *ha = vha->hw;
  292. /*
  293. * 8200 AEN Interpretation:
  294. * mb[0] = AEN code
  295. * mb[1] = AEN Reason code
  296. * mb[2] = LSW of Peg-Halt Status-1 Register
  297. * mb[6] = MSW of Peg-Halt Status-1 Register
  298. * mb[3] = LSW of Peg-Halt Status-2 register
  299. * mb[7] = MSW of Peg-Halt Status-2 register
  300. * mb[4] = IDC Device-State Register value
  301. * mb[5] = IDC Driver-Presence Register value
  302. */
  303. ql_dbg(ql_dbg_async, vha, 0x506b, "AEN Code: mb[0] = 0x%x AEN reason: "
  304. "mb[1] = 0x%x PH-status1: mb[2] = 0x%x PH-status1: mb[6] = 0x%x.\n",
  305. mb[0], mb[1], mb[2], mb[6]);
  306. ql_dbg(ql_dbg_async, vha, 0x506c, "PH-status2: mb[3] = 0x%x "
  307. "PH-status2: mb[7] = 0x%x Device-State: mb[4] = 0x%x "
  308. "Drv-Presence: mb[5] = 0x%x.\n", mb[3], mb[7], mb[4], mb[5]);
  309. if (mb[1] & (IDC_PEG_HALT_STATUS_CHANGE | IDC_NIC_FW_REPORTED_FAILURE |
  310. IDC_HEARTBEAT_FAILURE)) {
  311. ha->flags.nic_core_hung = 1;
  312. ql_log(ql_log_warn, vha, 0x5060,
  313. "83XX: F/W Error Reported: Check if reset required.\n");
  314. if (mb[1] & IDC_PEG_HALT_STATUS_CHANGE) {
  315. uint32_t protocol_engine_id, fw_err_code, err_level;
  316. /*
  317. * IDC_PEG_HALT_STATUS_CHANGE interpretation:
  318. * - PEG-Halt Status-1 Register:
  319. * (LSW = mb[2], MSW = mb[6])
  320. * Bits 0-7 = protocol-engine ID
  321. * Bits 8-28 = f/w error code
  322. * Bits 29-31 = Error-level
  323. * Error-level 0x1 = Non-Fatal error
  324. * Error-level 0x2 = Recoverable Fatal error
  325. * Error-level 0x4 = UnRecoverable Fatal error
  326. * - PEG-Halt Status-2 Register:
  327. * (LSW = mb[3], MSW = mb[7])
  328. */
  329. protocol_engine_id = (mb[2] & 0xff);
  330. fw_err_code = (((mb[2] & 0xff00) >> 8) |
  331. ((mb[6] & 0x1fff) << 8));
  332. err_level = ((mb[6] & 0xe000) >> 13);
  333. ql_log(ql_log_warn, vha, 0x5061, "PegHalt Status-1 "
  334. "Register: protocol_engine_id=0x%x "
  335. "fw_err_code=0x%x err_level=0x%x.\n",
  336. protocol_engine_id, fw_err_code, err_level);
  337. ql_log(ql_log_warn, vha, 0x5062, "PegHalt Status-2 "
  338. "Register: 0x%x%x.\n", mb[7], mb[3]);
  339. if (err_level == ERR_LEVEL_NON_FATAL) {
  340. ql_log(ql_log_warn, vha, 0x5063,
  341. "Not a fatal error, f/w has recovered "
  342. "iteself.\n");
  343. } else if (err_level == ERR_LEVEL_RECOVERABLE_FATAL) {
  344. ql_log(ql_log_fatal, vha, 0x5064,
  345. "Recoverable Fatal error: Chip reset "
  346. "required.\n");
  347. qla83xx_schedule_work(vha,
  348. QLA83XX_NIC_CORE_RESET);
  349. } else if (err_level == ERR_LEVEL_UNRECOVERABLE_FATAL) {
  350. ql_log(ql_log_fatal, vha, 0x5065,
  351. "Unrecoverable Fatal error: Set FAILED "
  352. "state, reboot required.\n");
  353. qla83xx_schedule_work(vha,
  354. QLA83XX_NIC_CORE_UNRECOVERABLE);
  355. }
  356. }
  357. if (mb[1] & IDC_NIC_FW_REPORTED_FAILURE) {
  358. uint16_t peg_fw_state, nw_interface_link_up;
  359. uint16_t nw_interface_signal_detect, sfp_status;
  360. uint16_t htbt_counter, htbt_monitor_enable;
  361. uint16_t sfp_additonal_info, sfp_multirate;
  362. uint16_t sfp_tx_fault, link_speed, dcbx_status;
  363. /*
  364. * IDC_NIC_FW_REPORTED_FAILURE interpretation:
  365. * - PEG-to-FC Status Register:
  366. * (LSW = mb[2], MSW = mb[6])
  367. * Bits 0-7 = Peg-Firmware state
  368. * Bit 8 = N/W Interface Link-up
  369. * Bit 9 = N/W Interface signal detected
  370. * Bits 10-11 = SFP Status
  371. * SFP Status 0x0 = SFP+ transceiver not expected
  372. * SFP Status 0x1 = SFP+ transceiver not present
  373. * SFP Status 0x2 = SFP+ transceiver invalid
  374. * SFP Status 0x3 = SFP+ transceiver present and
  375. * valid
  376. * Bits 12-14 = Heartbeat Counter
  377. * Bit 15 = Heartbeat Monitor Enable
  378. * Bits 16-17 = SFP Additional Info
  379. * SFP info 0x0 = Unregocnized transceiver for
  380. * Ethernet
  381. * SFP info 0x1 = SFP+ brand validation failed
  382. * SFP info 0x2 = SFP+ speed validation failed
  383. * SFP info 0x3 = SFP+ access error
  384. * Bit 18 = SFP Multirate
  385. * Bit 19 = SFP Tx Fault
  386. * Bits 20-22 = Link Speed
  387. * Bits 23-27 = Reserved
  388. * Bits 28-30 = DCBX Status
  389. * DCBX Status 0x0 = DCBX Disabled
  390. * DCBX Status 0x1 = DCBX Enabled
  391. * DCBX Status 0x2 = DCBX Exchange error
  392. * Bit 31 = Reserved
  393. */
  394. peg_fw_state = (mb[2] & 0x00ff);
  395. nw_interface_link_up = ((mb[2] & 0x0100) >> 8);
  396. nw_interface_signal_detect = ((mb[2] & 0x0200) >> 9);
  397. sfp_status = ((mb[2] & 0x0c00) >> 10);
  398. htbt_counter = ((mb[2] & 0x7000) >> 12);
  399. htbt_monitor_enable = ((mb[2] & 0x8000) >> 15);
  400. sfp_additonal_info = (mb[6] & 0x0003);
  401. sfp_multirate = ((mb[6] & 0x0004) >> 2);
  402. sfp_tx_fault = ((mb[6] & 0x0008) >> 3);
  403. link_speed = ((mb[6] & 0x0070) >> 4);
  404. dcbx_status = ((mb[6] & 0x7000) >> 12);
  405. ql_log(ql_log_warn, vha, 0x5066,
  406. "Peg-to-Fc Status Register:\n"
  407. "peg_fw_state=0x%x, nw_interface_link_up=0x%x, "
  408. "nw_interface_signal_detect=0x%x"
  409. "\nsfp_statis=0x%x.\n ", peg_fw_state,
  410. nw_interface_link_up, nw_interface_signal_detect,
  411. sfp_status);
  412. ql_log(ql_log_warn, vha, 0x5067,
  413. "htbt_counter=0x%x, htbt_monitor_enable=0x%x, "
  414. "sfp_additonal_info=0x%x, sfp_multirate=0x%x.\n ",
  415. htbt_counter, htbt_monitor_enable,
  416. sfp_additonal_info, sfp_multirate);
  417. ql_log(ql_log_warn, vha, 0x5068,
  418. "sfp_tx_fault=0x%x, link_state=0x%x, "
  419. "dcbx_status=0x%x.\n", sfp_tx_fault, link_speed,
  420. dcbx_status);
  421. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  422. }
  423. if (mb[1] & IDC_HEARTBEAT_FAILURE) {
  424. ql_log(ql_log_warn, vha, 0x5069,
  425. "Heartbeat Failure encountered, chip reset "
  426. "required.\n");
  427. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  428. }
  429. }
  430. if (mb[1] & IDC_DEVICE_STATE_CHANGE) {
  431. ql_log(ql_log_info, vha, 0x506a,
  432. "IDC Device-State changed = 0x%x.\n", mb[4]);
  433. if (ha->flags.nic_core_reset_owner)
  434. return;
  435. qla83xx_schedule_work(vha, MBA_IDC_AEN);
  436. }
  437. }
  438. int
  439. qla2x00_is_a_vp_did(scsi_qla_host_t *vha, uint32_t rscn_entry)
  440. {
  441. struct qla_hw_data *ha = vha->hw;
  442. scsi_qla_host_t *vp;
  443. uint32_t vp_did;
  444. unsigned long flags;
  445. int ret = 0;
  446. if (!ha->num_vhosts)
  447. return ret;
  448. spin_lock_irqsave(&ha->vport_slock, flags);
  449. list_for_each_entry(vp, &ha->vp_list, list) {
  450. vp_did = vp->d_id.b24;
  451. if (vp_did == rscn_entry) {
  452. ret = 1;
  453. break;
  454. }
  455. }
  456. spin_unlock_irqrestore(&ha->vport_slock, flags);
  457. return ret;
  458. }
  459. /**
  460. * qla2x00_async_event() - Process aynchronous events.
  461. * @ha: SCSI driver HA context
  462. * @mb: Mailbox registers (0 - 3)
  463. */
  464. void
  465. qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb)
  466. {
  467. uint16_t handle_cnt;
  468. uint16_t cnt, mbx;
  469. uint32_t handles[5];
  470. struct qla_hw_data *ha = vha->hw;
  471. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  472. struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
  473. struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
  474. uint32_t rscn_entry, host_pid;
  475. unsigned long flags;
  476. /* Setup to process RIO completion. */
  477. handle_cnt = 0;
  478. if (IS_CNA_CAPABLE(ha))
  479. goto skip_rio;
  480. switch (mb[0]) {
  481. case MBA_SCSI_COMPLETION:
  482. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  483. handle_cnt = 1;
  484. break;
  485. case MBA_CMPLT_1_16BIT:
  486. handles[0] = mb[1];
  487. handle_cnt = 1;
  488. mb[0] = MBA_SCSI_COMPLETION;
  489. break;
  490. case MBA_CMPLT_2_16BIT:
  491. handles[0] = mb[1];
  492. handles[1] = mb[2];
  493. handle_cnt = 2;
  494. mb[0] = MBA_SCSI_COMPLETION;
  495. break;
  496. case MBA_CMPLT_3_16BIT:
  497. handles[0] = mb[1];
  498. handles[1] = mb[2];
  499. handles[2] = mb[3];
  500. handle_cnt = 3;
  501. mb[0] = MBA_SCSI_COMPLETION;
  502. break;
  503. case MBA_CMPLT_4_16BIT:
  504. handles[0] = mb[1];
  505. handles[1] = mb[2];
  506. handles[2] = mb[3];
  507. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  508. handle_cnt = 4;
  509. mb[0] = MBA_SCSI_COMPLETION;
  510. break;
  511. case MBA_CMPLT_5_16BIT:
  512. handles[0] = mb[1];
  513. handles[1] = mb[2];
  514. handles[2] = mb[3];
  515. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  516. handles[4] = (uint32_t)RD_MAILBOX_REG(ha, reg, 7);
  517. handle_cnt = 5;
  518. mb[0] = MBA_SCSI_COMPLETION;
  519. break;
  520. case MBA_CMPLT_2_32BIT:
  521. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  522. handles[1] = le32_to_cpu(
  523. ((uint32_t)(RD_MAILBOX_REG(ha, reg, 7) << 16)) |
  524. RD_MAILBOX_REG(ha, reg, 6));
  525. handle_cnt = 2;
  526. mb[0] = MBA_SCSI_COMPLETION;
  527. break;
  528. default:
  529. break;
  530. }
  531. skip_rio:
  532. switch (mb[0]) {
  533. case MBA_SCSI_COMPLETION: /* Fast Post */
  534. if (!vha->flags.online)
  535. break;
  536. for (cnt = 0; cnt < handle_cnt; cnt++)
  537. qla2x00_process_completed_request(vha, rsp->req,
  538. handles[cnt]);
  539. break;
  540. case MBA_RESET: /* Reset */
  541. ql_dbg(ql_dbg_async, vha, 0x5002,
  542. "Asynchronous RESET.\n");
  543. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  544. break;
  545. case MBA_SYSTEM_ERR: /* System Error */
  546. mbx = (IS_QLA81XX(ha) || IS_QLA83XX(ha)) ?
  547. RD_REG_WORD(&reg24->mailbox7) : 0;
  548. ql_log(ql_log_warn, vha, 0x5003,
  549. "ISP System Error - mbx1=%xh mbx2=%xh mbx3=%xh "
  550. "mbx7=%xh.\n", mb[1], mb[2], mb[3], mbx);
  551. ha->isp_ops->fw_dump(vha, 1);
  552. if (IS_FWI2_CAPABLE(ha)) {
  553. if (mb[1] == 0 && mb[2] == 0) {
  554. ql_log(ql_log_fatal, vha, 0x5004,
  555. "Unrecoverable Hardware Error: adapter "
  556. "marked OFFLINE!\n");
  557. vha->flags.online = 0;
  558. vha->device_flags |= DFLG_DEV_FAILED;
  559. } else {
  560. /* Check to see if MPI timeout occurred */
  561. if ((mbx & MBX_3) && (ha->flags.port0))
  562. set_bit(MPI_RESET_NEEDED,
  563. &vha->dpc_flags);
  564. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  565. }
  566. } else if (mb[1] == 0) {
  567. ql_log(ql_log_fatal, vha, 0x5005,
  568. "Unrecoverable Hardware Error: adapter marked "
  569. "OFFLINE!\n");
  570. vha->flags.online = 0;
  571. vha->device_flags |= DFLG_DEV_FAILED;
  572. } else
  573. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  574. break;
  575. case MBA_REQ_TRANSFER_ERR: /* Request Transfer Error */
  576. ql_log(ql_log_warn, vha, 0x5006,
  577. "ISP Request Transfer Error (%x).\n", mb[1]);
  578. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  579. break;
  580. case MBA_RSP_TRANSFER_ERR: /* Response Transfer Error */
  581. ql_log(ql_log_warn, vha, 0x5007,
  582. "ISP Response Transfer Error.\n");
  583. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  584. break;
  585. case MBA_WAKEUP_THRES: /* Request Queue Wake-up */
  586. ql_dbg(ql_dbg_async, vha, 0x5008,
  587. "Asynchronous WAKEUP_THRES.\n");
  588. break;
  589. case MBA_LIP_OCCURRED: /* Loop Initialization Procedure */
  590. ql_dbg(ql_dbg_async, vha, 0x5009,
  591. "LIP occurred (%x).\n", mb[1]);
  592. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  593. atomic_set(&vha->loop_state, LOOP_DOWN);
  594. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  595. qla2x00_mark_all_devices_lost(vha, 1);
  596. }
  597. if (vha->vp_idx) {
  598. atomic_set(&vha->vp_state, VP_FAILED);
  599. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  600. }
  601. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  602. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  603. vha->flags.management_server_logged_in = 0;
  604. qla2x00_post_aen_work(vha, FCH_EVT_LIP, mb[1]);
  605. break;
  606. case MBA_LOOP_UP: /* Loop Up Event */
  607. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  608. ha->link_data_rate = PORT_SPEED_1GB;
  609. else
  610. ha->link_data_rate = mb[1];
  611. ql_dbg(ql_dbg_async, vha, 0x500a,
  612. "LOOP UP detected (%s Gbps).\n",
  613. qla2x00_get_link_speed_str(ha, ha->link_data_rate));
  614. vha->flags.management_server_logged_in = 0;
  615. qla2x00_post_aen_work(vha, FCH_EVT_LINKUP, ha->link_data_rate);
  616. break;
  617. case MBA_LOOP_DOWN: /* Loop Down Event */
  618. mbx = (IS_QLA81XX(ha) || IS_QLA8031(ha))
  619. ? RD_REG_WORD(&reg24->mailbox4) : 0;
  620. mbx = (IS_P3P_TYPE(ha)) ? RD_REG_WORD(&reg82->mailbox_out[4])
  621. : mbx;
  622. ql_dbg(ql_dbg_async, vha, 0x500b,
  623. "LOOP DOWN detected (%x %x %x %x).\n",
  624. mb[1], mb[2], mb[3], mbx);
  625. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  626. atomic_set(&vha->loop_state, LOOP_DOWN);
  627. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  628. vha->device_flags |= DFLG_NO_CABLE;
  629. qla2x00_mark_all_devices_lost(vha, 1);
  630. }
  631. if (vha->vp_idx) {
  632. atomic_set(&vha->vp_state, VP_FAILED);
  633. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  634. }
  635. vha->flags.management_server_logged_in = 0;
  636. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  637. qla2x00_post_aen_work(vha, FCH_EVT_LINKDOWN, 0);
  638. break;
  639. case MBA_LIP_RESET: /* LIP reset occurred */
  640. ql_dbg(ql_dbg_async, vha, 0x500c,
  641. "LIP reset occurred (%x).\n", mb[1]);
  642. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  643. atomic_set(&vha->loop_state, LOOP_DOWN);
  644. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  645. qla2x00_mark_all_devices_lost(vha, 1);
  646. }
  647. if (vha->vp_idx) {
  648. atomic_set(&vha->vp_state, VP_FAILED);
  649. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  650. }
  651. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  652. ha->operating_mode = LOOP;
  653. vha->flags.management_server_logged_in = 0;
  654. qla2x00_post_aen_work(vha, FCH_EVT_LIPRESET, mb[1]);
  655. break;
  656. /* case MBA_DCBX_COMPLETE: */
  657. case MBA_POINT_TO_POINT: /* Point-to-Point */
  658. if (IS_QLA2100(ha))
  659. break;
  660. if (IS_CNA_CAPABLE(ha)) {
  661. ql_dbg(ql_dbg_async, vha, 0x500d,
  662. "DCBX Completed -- %04x %04x %04x.\n",
  663. mb[1], mb[2], mb[3]);
  664. if (ha->notify_dcbx_comp)
  665. complete(&ha->dcbx_comp);
  666. } else
  667. ql_dbg(ql_dbg_async, vha, 0x500e,
  668. "Asynchronous P2P MODE received.\n");
  669. /*
  670. * Until there's a transition from loop down to loop up, treat
  671. * this as loop down only.
  672. */
  673. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  674. atomic_set(&vha->loop_state, LOOP_DOWN);
  675. if (!atomic_read(&vha->loop_down_timer))
  676. atomic_set(&vha->loop_down_timer,
  677. LOOP_DOWN_TIME);
  678. qla2x00_mark_all_devices_lost(vha, 1);
  679. }
  680. if (vha->vp_idx) {
  681. atomic_set(&vha->vp_state, VP_FAILED);
  682. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  683. }
  684. if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)))
  685. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  686. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  687. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  688. ha->flags.gpsc_supported = 1;
  689. vha->flags.management_server_logged_in = 0;
  690. break;
  691. case MBA_CHG_IN_CONNECTION: /* Change in connection mode */
  692. if (IS_QLA2100(ha))
  693. break;
  694. ql_dbg(ql_dbg_async, vha, 0x500f,
  695. "Configuration change detected: value=%x.\n", mb[1]);
  696. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  697. atomic_set(&vha->loop_state, LOOP_DOWN);
  698. if (!atomic_read(&vha->loop_down_timer))
  699. atomic_set(&vha->loop_down_timer,
  700. LOOP_DOWN_TIME);
  701. qla2x00_mark_all_devices_lost(vha, 1);
  702. }
  703. if (vha->vp_idx) {
  704. atomic_set(&vha->vp_state, VP_FAILED);
  705. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  706. }
  707. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  708. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  709. break;
  710. case MBA_PORT_UPDATE: /* Port database update */
  711. /*
  712. * Handle only global and vn-port update events
  713. *
  714. * Relevant inputs:
  715. * mb[1] = N_Port handle of changed port
  716. * OR 0xffff for global event
  717. * mb[2] = New login state
  718. * 7 = Port logged out
  719. * mb[3] = LSB is vp_idx, 0xff = all vps
  720. *
  721. * Skip processing if:
  722. * Event is global, vp_idx is NOT all vps,
  723. * vp_idx does not match
  724. * Event is not global, vp_idx does not match
  725. */
  726. if (IS_QLA2XXX_MIDTYPE(ha) &&
  727. ((mb[1] == 0xffff && (mb[3] & 0xff) != 0xff) ||
  728. (mb[1] != 0xffff)) && vha->vp_idx != (mb[3] & 0xff))
  729. break;
  730. /* Global event -- port logout or port unavailable. */
  731. if (mb[1] == 0xffff && mb[2] == 0x7) {
  732. ql_dbg(ql_dbg_async, vha, 0x5010,
  733. "Port unavailable %04x %04x %04x.\n",
  734. mb[1], mb[2], mb[3]);
  735. ql_log(ql_log_warn, vha, 0x505e,
  736. "Link is offline.\n");
  737. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  738. atomic_set(&vha->loop_state, LOOP_DOWN);
  739. atomic_set(&vha->loop_down_timer,
  740. LOOP_DOWN_TIME);
  741. vha->device_flags |= DFLG_NO_CABLE;
  742. qla2x00_mark_all_devices_lost(vha, 1);
  743. }
  744. if (vha->vp_idx) {
  745. atomic_set(&vha->vp_state, VP_FAILED);
  746. fc_vport_set_state(vha->fc_vport,
  747. FC_VPORT_FAILED);
  748. qla2x00_mark_all_devices_lost(vha, 1);
  749. }
  750. vha->flags.management_server_logged_in = 0;
  751. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  752. break;
  753. }
  754. /*
  755. * If PORT UPDATE is global (received LIP_OCCURRED/LIP_RESET
  756. * event etc. earlier indicating loop is down) then process
  757. * it. Otherwise ignore it and Wait for RSCN to come in.
  758. */
  759. atomic_set(&vha->loop_down_timer, 0);
  760. if (mb[1] != 0xffff || (mb[2] != 0x6 && mb[2] != 0x4)) {
  761. ql_dbg(ql_dbg_async, vha, 0x5011,
  762. "Asynchronous PORT UPDATE ignored %04x/%04x/%04x.\n",
  763. mb[1], mb[2], mb[3]);
  764. qlt_async_event(mb[0], vha, mb);
  765. break;
  766. }
  767. ql_dbg(ql_dbg_async, vha, 0x5012,
  768. "Port database changed %04x %04x %04x.\n",
  769. mb[1], mb[2], mb[3]);
  770. ql_log(ql_log_warn, vha, 0x505f,
  771. "Link is operational (%s Gbps).\n",
  772. qla2x00_get_link_speed_str(ha, ha->link_data_rate));
  773. /*
  774. * Mark all devices as missing so we will login again.
  775. */
  776. atomic_set(&vha->loop_state, LOOP_UP);
  777. qla2x00_mark_all_devices_lost(vha, 1);
  778. if (vha->vp_idx == 0 && !qla_ini_mode_enabled(vha))
  779. set_bit(SCR_PENDING, &vha->dpc_flags);
  780. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  781. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  782. qlt_async_event(mb[0], vha, mb);
  783. break;
  784. case MBA_RSCN_UPDATE: /* State Change Registration */
  785. /* Check if the Vport has issued a SCR */
  786. if (vha->vp_idx && test_bit(VP_SCR_NEEDED, &vha->vp_flags))
  787. break;
  788. /* Only handle SCNs for our Vport index. */
  789. if (ha->flags.npiv_supported && vha->vp_idx != (mb[3] & 0xff))
  790. break;
  791. ql_dbg(ql_dbg_async, vha, 0x5013,
  792. "RSCN database changed -- %04x %04x %04x.\n",
  793. mb[1], mb[2], mb[3]);
  794. rscn_entry = ((mb[1] & 0xff) << 16) | mb[2];
  795. host_pid = (vha->d_id.b.domain << 16) | (vha->d_id.b.area << 8)
  796. | vha->d_id.b.al_pa;
  797. if (rscn_entry == host_pid) {
  798. ql_dbg(ql_dbg_async, vha, 0x5014,
  799. "Ignoring RSCN update to local host "
  800. "port ID (%06x).\n", host_pid);
  801. break;
  802. }
  803. /* Ignore reserved bits from RSCN-payload. */
  804. rscn_entry = ((mb[1] & 0x3ff) << 16) | mb[2];
  805. /* Skip RSCNs for virtual ports on the same physical port */
  806. if (qla2x00_is_a_vp_did(vha, rscn_entry))
  807. break;
  808. atomic_set(&vha->loop_down_timer, 0);
  809. vha->flags.management_server_logged_in = 0;
  810. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  811. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  812. qla2x00_post_aen_work(vha, FCH_EVT_RSCN, rscn_entry);
  813. break;
  814. /* case MBA_RIO_RESPONSE: */
  815. case MBA_ZIO_RESPONSE:
  816. ql_dbg(ql_dbg_async, vha, 0x5015,
  817. "[R|Z]IO update completion.\n");
  818. if (IS_FWI2_CAPABLE(ha))
  819. qla24xx_process_response_queue(vha, rsp);
  820. else
  821. qla2x00_process_response_queue(rsp);
  822. break;
  823. case MBA_DISCARD_RND_FRAME:
  824. ql_dbg(ql_dbg_async, vha, 0x5016,
  825. "Discard RND Frame -- %04x %04x %04x.\n",
  826. mb[1], mb[2], mb[3]);
  827. break;
  828. case MBA_TRACE_NOTIFICATION:
  829. ql_dbg(ql_dbg_async, vha, 0x5017,
  830. "Trace Notification -- %04x %04x.\n", mb[1], mb[2]);
  831. break;
  832. case MBA_ISP84XX_ALERT:
  833. ql_dbg(ql_dbg_async, vha, 0x5018,
  834. "ISP84XX Alert Notification -- %04x %04x %04x.\n",
  835. mb[1], mb[2], mb[3]);
  836. spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
  837. switch (mb[1]) {
  838. case A84_PANIC_RECOVERY:
  839. ql_log(ql_log_info, vha, 0x5019,
  840. "Alert 84XX: panic recovery %04x %04x.\n",
  841. mb[2], mb[3]);
  842. break;
  843. case A84_OP_LOGIN_COMPLETE:
  844. ha->cs84xx->op_fw_version = mb[3] << 16 | mb[2];
  845. ql_log(ql_log_info, vha, 0x501a,
  846. "Alert 84XX: firmware version %x.\n",
  847. ha->cs84xx->op_fw_version);
  848. break;
  849. case A84_DIAG_LOGIN_COMPLETE:
  850. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  851. ql_log(ql_log_info, vha, 0x501b,
  852. "Alert 84XX: diagnostic firmware version %x.\n",
  853. ha->cs84xx->diag_fw_version);
  854. break;
  855. case A84_GOLD_LOGIN_COMPLETE:
  856. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  857. ha->cs84xx->fw_update = 1;
  858. ql_log(ql_log_info, vha, 0x501c,
  859. "Alert 84XX: gold firmware version %x.\n",
  860. ha->cs84xx->gold_fw_version);
  861. break;
  862. default:
  863. ql_log(ql_log_warn, vha, 0x501d,
  864. "Alert 84xx: Invalid Alert %04x %04x %04x.\n",
  865. mb[1], mb[2], mb[3]);
  866. }
  867. spin_unlock_irqrestore(&ha->cs84xx->access_lock, flags);
  868. break;
  869. case MBA_DCBX_START:
  870. ql_dbg(ql_dbg_async, vha, 0x501e,
  871. "DCBX Started -- %04x %04x %04x.\n",
  872. mb[1], mb[2], mb[3]);
  873. break;
  874. case MBA_DCBX_PARAM_UPDATE:
  875. ql_dbg(ql_dbg_async, vha, 0x501f,
  876. "DCBX Parameters Updated -- %04x %04x %04x.\n",
  877. mb[1], mb[2], mb[3]);
  878. break;
  879. case MBA_FCF_CONF_ERR:
  880. ql_dbg(ql_dbg_async, vha, 0x5020,
  881. "FCF Configuration Error -- %04x %04x %04x.\n",
  882. mb[1], mb[2], mb[3]);
  883. break;
  884. case MBA_IDC_NOTIFY:
  885. if (IS_QLA8031(vha->hw) || IS_QLA8044(ha)) {
  886. mb[4] = RD_REG_WORD(&reg24->mailbox4);
  887. if (((mb[2] & 0x7fff) == MBC_PORT_RESET ||
  888. (mb[2] & 0x7fff) == MBC_SET_PORT_CONFIG) &&
  889. (mb[4] & INTERNAL_LOOPBACK_MASK) != 0) {
  890. set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
  891. /*
  892. * Extend loop down timer since port is active.
  893. */
  894. if (atomic_read(&vha->loop_state) == LOOP_DOWN)
  895. atomic_set(&vha->loop_down_timer,
  896. LOOP_DOWN_TIME);
  897. qla2xxx_wake_dpc(vha);
  898. }
  899. }
  900. case MBA_IDC_COMPLETE:
  901. if (ha->notify_lb_portup_comp)
  902. complete(&ha->lb_portup_comp);
  903. /* Fallthru */
  904. case MBA_IDC_TIME_EXT:
  905. if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) ||
  906. IS_QLA8044(ha))
  907. qla81xx_idc_event(vha, mb[0], mb[1]);
  908. break;
  909. case MBA_IDC_AEN:
  910. mb[4] = RD_REG_WORD(&reg24->mailbox4);
  911. mb[5] = RD_REG_WORD(&reg24->mailbox5);
  912. mb[6] = RD_REG_WORD(&reg24->mailbox6);
  913. mb[7] = RD_REG_WORD(&reg24->mailbox7);
  914. qla83xx_handle_8200_aen(vha, mb);
  915. break;
  916. default:
  917. ql_dbg(ql_dbg_async, vha, 0x5057,
  918. "Unknown AEN:%04x %04x %04x %04x\n",
  919. mb[0], mb[1], mb[2], mb[3]);
  920. }
  921. qlt_async_event(mb[0], vha, mb);
  922. if (!vha->vp_idx && ha->num_vhosts)
  923. qla2x00_alert_all_vps(rsp, mb);
  924. }
  925. /**
  926. * qla2x00_process_completed_request() - Process a Fast Post response.
  927. * @ha: SCSI driver HA context
  928. * @index: SRB index
  929. */
  930. void
  931. qla2x00_process_completed_request(struct scsi_qla_host *vha,
  932. struct req_que *req, uint32_t index)
  933. {
  934. srb_t *sp;
  935. struct qla_hw_data *ha = vha->hw;
  936. /* Validate handle. */
  937. if (index >= req->num_outstanding_cmds) {
  938. ql_log(ql_log_warn, vha, 0x3014,
  939. "Invalid SCSI command index (%x).\n", index);
  940. if (IS_P3P_TYPE(ha))
  941. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  942. else
  943. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  944. return;
  945. }
  946. sp = req->outstanding_cmds[index];
  947. if (sp) {
  948. /* Free outstanding command slot. */
  949. req->outstanding_cmds[index] = NULL;
  950. /* Save ISP completion status */
  951. sp->done(ha, sp, DID_OK << 16);
  952. } else {
  953. ql_log(ql_log_warn, vha, 0x3016, "Invalid SCSI SRB.\n");
  954. if (IS_P3P_TYPE(ha))
  955. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  956. else
  957. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  958. }
  959. }
  960. srb_t *
  961. qla2x00_get_sp_from_handle(scsi_qla_host_t *vha, const char *func,
  962. struct req_que *req, void *iocb)
  963. {
  964. struct qla_hw_data *ha = vha->hw;
  965. sts_entry_t *pkt = iocb;
  966. srb_t *sp = NULL;
  967. uint16_t index;
  968. index = LSW(pkt->handle);
  969. if (index >= req->num_outstanding_cmds) {
  970. ql_log(ql_log_warn, vha, 0x5031,
  971. "Invalid command index (%x).\n", index);
  972. if (IS_P3P_TYPE(ha))
  973. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  974. else
  975. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  976. goto done;
  977. }
  978. sp = req->outstanding_cmds[index];
  979. if (!sp) {
  980. ql_log(ql_log_warn, vha, 0x5032,
  981. "Invalid completion handle (%x) -- timed-out.\n", index);
  982. return sp;
  983. }
  984. if (sp->handle != index) {
  985. ql_log(ql_log_warn, vha, 0x5033,
  986. "SRB handle (%x) mismatch %x.\n", sp->handle, index);
  987. return NULL;
  988. }
  989. req->outstanding_cmds[index] = NULL;
  990. done:
  991. return sp;
  992. }
  993. static void
  994. qla2x00_mbx_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  995. struct mbx_entry *mbx)
  996. {
  997. const char func[] = "MBX-IOCB";
  998. const char *type;
  999. fc_port_t *fcport;
  1000. srb_t *sp;
  1001. struct srb_iocb *lio;
  1002. uint16_t *data;
  1003. uint16_t status;
  1004. sp = qla2x00_get_sp_from_handle(vha, func, req, mbx);
  1005. if (!sp)
  1006. return;
  1007. lio = &sp->u.iocb_cmd;
  1008. type = sp->name;
  1009. fcport = sp->fcport;
  1010. data = lio->u.logio.data;
  1011. data[0] = MBS_COMMAND_ERROR;
  1012. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  1013. QLA_LOGIO_LOGIN_RETRIED : 0;
  1014. if (mbx->entry_status) {
  1015. ql_dbg(ql_dbg_async, vha, 0x5043,
  1016. "Async-%s error entry - hdl=%x portid=%02x%02x%02x "
  1017. "entry-status=%x status=%x state-flag=%x "
  1018. "status-flags=%x.\n", type, sp->handle,
  1019. fcport->d_id.b.domain, fcport->d_id.b.area,
  1020. fcport->d_id.b.al_pa, mbx->entry_status,
  1021. le16_to_cpu(mbx->status), le16_to_cpu(mbx->state_flags),
  1022. le16_to_cpu(mbx->status_flags));
  1023. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5029,
  1024. (uint8_t *)mbx, sizeof(*mbx));
  1025. goto logio_done;
  1026. }
  1027. status = le16_to_cpu(mbx->status);
  1028. if (status == 0x30 && sp->type == SRB_LOGIN_CMD &&
  1029. le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE)
  1030. status = 0;
  1031. if (!status && le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE) {
  1032. ql_dbg(ql_dbg_async, vha, 0x5045,
  1033. "Async-%s complete - hdl=%x portid=%02x%02x%02x mbx1=%x.\n",
  1034. type, sp->handle, fcport->d_id.b.domain,
  1035. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1036. le16_to_cpu(mbx->mb1));
  1037. data[0] = MBS_COMMAND_COMPLETE;
  1038. if (sp->type == SRB_LOGIN_CMD) {
  1039. fcport->port_type = FCT_TARGET;
  1040. if (le16_to_cpu(mbx->mb1) & BIT_0)
  1041. fcport->port_type = FCT_INITIATOR;
  1042. else if (le16_to_cpu(mbx->mb1) & BIT_1)
  1043. fcport->flags |= FCF_FCP2_DEVICE;
  1044. }
  1045. goto logio_done;
  1046. }
  1047. data[0] = le16_to_cpu(mbx->mb0);
  1048. switch (data[0]) {
  1049. case MBS_PORT_ID_USED:
  1050. data[1] = le16_to_cpu(mbx->mb1);
  1051. break;
  1052. case MBS_LOOP_ID_USED:
  1053. break;
  1054. default:
  1055. data[0] = MBS_COMMAND_ERROR;
  1056. break;
  1057. }
  1058. ql_log(ql_log_warn, vha, 0x5046,
  1059. "Async-%s failed - hdl=%x portid=%02x%02x%02x status=%x "
  1060. "mb0=%x mb1=%x mb2=%x mb6=%x mb7=%x.\n", type, sp->handle,
  1061. fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1062. status, le16_to_cpu(mbx->mb0), le16_to_cpu(mbx->mb1),
  1063. le16_to_cpu(mbx->mb2), le16_to_cpu(mbx->mb6),
  1064. le16_to_cpu(mbx->mb7));
  1065. logio_done:
  1066. sp->done(vha, sp, 0);
  1067. }
  1068. static void
  1069. qla2x00_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1070. sts_entry_t *pkt, int iocb_type)
  1071. {
  1072. const char func[] = "CT_IOCB";
  1073. const char *type;
  1074. srb_t *sp;
  1075. struct fc_bsg_job *bsg_job;
  1076. uint16_t comp_status;
  1077. int res;
  1078. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1079. if (!sp)
  1080. return;
  1081. bsg_job = sp->u.bsg_job;
  1082. type = "ct pass-through";
  1083. comp_status = le16_to_cpu(pkt->comp_status);
  1084. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1085. * fc payload to the caller
  1086. */
  1087. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1088. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1089. if (comp_status != CS_COMPLETE) {
  1090. if (comp_status == CS_DATA_UNDERRUN) {
  1091. res = DID_OK << 16;
  1092. bsg_job->reply->reply_payload_rcv_len =
  1093. le16_to_cpu(((sts_entry_t *)pkt)->rsp_info_len);
  1094. ql_log(ql_log_warn, vha, 0x5048,
  1095. "CT pass-through-%s error "
  1096. "comp_status-status=0x%x total_byte = 0x%x.\n",
  1097. type, comp_status,
  1098. bsg_job->reply->reply_payload_rcv_len);
  1099. } else {
  1100. ql_log(ql_log_warn, vha, 0x5049,
  1101. "CT pass-through-%s error "
  1102. "comp_status-status=0x%x.\n", type, comp_status);
  1103. res = DID_ERROR << 16;
  1104. bsg_job->reply->reply_payload_rcv_len = 0;
  1105. }
  1106. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5035,
  1107. (uint8_t *)pkt, sizeof(*pkt));
  1108. } else {
  1109. res = DID_OK << 16;
  1110. bsg_job->reply->reply_payload_rcv_len =
  1111. bsg_job->reply_payload.payload_len;
  1112. bsg_job->reply_len = 0;
  1113. }
  1114. sp->done(vha, sp, res);
  1115. }
  1116. static void
  1117. qla24xx_els_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1118. struct sts_entry_24xx *pkt, int iocb_type)
  1119. {
  1120. const char func[] = "ELS_CT_IOCB";
  1121. const char *type;
  1122. srb_t *sp;
  1123. struct fc_bsg_job *bsg_job;
  1124. uint16_t comp_status;
  1125. uint32_t fw_status[3];
  1126. uint8_t* fw_sts_ptr;
  1127. int res;
  1128. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1129. if (!sp)
  1130. return;
  1131. bsg_job = sp->u.bsg_job;
  1132. type = NULL;
  1133. switch (sp->type) {
  1134. case SRB_ELS_CMD_RPT:
  1135. case SRB_ELS_CMD_HST:
  1136. type = "els";
  1137. break;
  1138. case SRB_CT_CMD:
  1139. type = "ct pass-through";
  1140. break;
  1141. default:
  1142. ql_dbg(ql_dbg_user, vha, 0x503e,
  1143. "Unrecognized SRB: (%p) type=%d.\n", sp, sp->type);
  1144. return;
  1145. }
  1146. comp_status = fw_status[0] = le16_to_cpu(pkt->comp_status);
  1147. fw_status[1] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_1);
  1148. fw_status[2] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_2);
  1149. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1150. * fc payload to the caller
  1151. */
  1152. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1153. bsg_job->reply_len = sizeof(struct fc_bsg_reply) + sizeof(fw_status);
  1154. if (comp_status != CS_COMPLETE) {
  1155. if (comp_status == CS_DATA_UNDERRUN) {
  1156. res = DID_OK << 16;
  1157. bsg_job->reply->reply_payload_rcv_len =
  1158. le16_to_cpu(((struct els_sts_entry_24xx *)pkt)->total_byte_count);
  1159. ql_dbg(ql_dbg_user, vha, 0x503f,
  1160. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1161. "error subcode 1=0x%x error subcode 2=0x%x total_byte = 0x%x.\n",
  1162. type, sp->handle, comp_status, fw_status[1], fw_status[2],
  1163. le16_to_cpu(((struct els_sts_entry_24xx *)
  1164. pkt)->total_byte_count));
  1165. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  1166. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  1167. }
  1168. else {
  1169. ql_dbg(ql_dbg_user, vha, 0x5040,
  1170. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1171. "error subcode 1=0x%x error subcode 2=0x%x.\n",
  1172. type, sp->handle, comp_status,
  1173. le16_to_cpu(((struct els_sts_entry_24xx *)
  1174. pkt)->error_subcode_1),
  1175. le16_to_cpu(((struct els_sts_entry_24xx *)
  1176. pkt)->error_subcode_2));
  1177. res = DID_ERROR << 16;
  1178. bsg_job->reply->reply_payload_rcv_len = 0;
  1179. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  1180. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  1181. }
  1182. ql_dump_buffer(ql_dbg_user + ql_dbg_buffer, vha, 0x5056,
  1183. (uint8_t *)pkt, sizeof(*pkt));
  1184. }
  1185. else {
  1186. res = DID_OK << 16;
  1187. bsg_job->reply->reply_payload_rcv_len = bsg_job->reply_payload.payload_len;
  1188. bsg_job->reply_len = 0;
  1189. }
  1190. sp->done(vha, sp, res);
  1191. }
  1192. static void
  1193. qla24xx_logio_entry(scsi_qla_host_t *vha, struct req_que *req,
  1194. struct logio_entry_24xx *logio)
  1195. {
  1196. const char func[] = "LOGIO-IOCB";
  1197. const char *type;
  1198. fc_port_t *fcport;
  1199. srb_t *sp;
  1200. struct srb_iocb *lio;
  1201. uint16_t *data;
  1202. uint32_t iop[2];
  1203. sp = qla2x00_get_sp_from_handle(vha, func, req, logio);
  1204. if (!sp)
  1205. return;
  1206. lio = &sp->u.iocb_cmd;
  1207. type = sp->name;
  1208. fcport = sp->fcport;
  1209. data = lio->u.logio.data;
  1210. data[0] = MBS_COMMAND_ERROR;
  1211. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  1212. QLA_LOGIO_LOGIN_RETRIED : 0;
  1213. if (logio->entry_status) {
  1214. ql_log(ql_log_warn, fcport->vha, 0x5034,
  1215. "Async-%s error entry - hdl=%x"
  1216. "portid=%02x%02x%02x entry-status=%x.\n",
  1217. type, sp->handle, fcport->d_id.b.domain,
  1218. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1219. logio->entry_status);
  1220. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x504d,
  1221. (uint8_t *)logio, sizeof(*logio));
  1222. goto logio_done;
  1223. }
  1224. if (le16_to_cpu(logio->comp_status) == CS_COMPLETE) {
  1225. ql_dbg(ql_dbg_async, fcport->vha, 0x5036,
  1226. "Async-%s complete - hdl=%x portid=%02x%02x%02x "
  1227. "iop0=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1228. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1229. le32_to_cpu(logio->io_parameter[0]));
  1230. data[0] = MBS_COMMAND_COMPLETE;
  1231. if (sp->type != SRB_LOGIN_CMD)
  1232. goto logio_done;
  1233. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1234. if (iop[0] & BIT_4) {
  1235. fcport->port_type = FCT_TARGET;
  1236. if (iop[0] & BIT_8)
  1237. fcport->flags |= FCF_FCP2_DEVICE;
  1238. } else if (iop[0] & BIT_5)
  1239. fcport->port_type = FCT_INITIATOR;
  1240. if (iop[0] & BIT_7)
  1241. fcport->flags |= FCF_CONF_COMP_SUPPORTED;
  1242. if (logio->io_parameter[7] || logio->io_parameter[8])
  1243. fcport->supported_classes |= FC_COS_CLASS2;
  1244. if (logio->io_parameter[9] || logio->io_parameter[10])
  1245. fcport->supported_classes |= FC_COS_CLASS3;
  1246. goto logio_done;
  1247. }
  1248. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1249. iop[1] = le32_to_cpu(logio->io_parameter[1]);
  1250. switch (iop[0]) {
  1251. case LSC_SCODE_PORTID_USED:
  1252. data[0] = MBS_PORT_ID_USED;
  1253. data[1] = LSW(iop[1]);
  1254. break;
  1255. case LSC_SCODE_NPORT_USED:
  1256. data[0] = MBS_LOOP_ID_USED;
  1257. break;
  1258. default:
  1259. data[0] = MBS_COMMAND_ERROR;
  1260. break;
  1261. }
  1262. ql_dbg(ql_dbg_async, fcport->vha, 0x5037,
  1263. "Async-%s failed - hdl=%x portid=%02x%02x%02x comp=%x "
  1264. "iop0=%x iop1=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1265. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1266. le16_to_cpu(logio->comp_status),
  1267. le32_to_cpu(logio->io_parameter[0]),
  1268. le32_to_cpu(logio->io_parameter[1]));
  1269. logio_done:
  1270. sp->done(vha, sp, 0);
  1271. }
  1272. static void
  1273. qla24xx_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1274. struct tsk_mgmt_entry *tsk)
  1275. {
  1276. const char func[] = "TMF-IOCB";
  1277. const char *type;
  1278. fc_port_t *fcport;
  1279. srb_t *sp;
  1280. struct srb_iocb *iocb;
  1281. struct sts_entry_24xx *sts = (struct sts_entry_24xx *)tsk;
  1282. int error = 1;
  1283. sp = qla2x00_get_sp_from_handle(vha, func, req, tsk);
  1284. if (!sp)
  1285. return;
  1286. iocb = &sp->u.iocb_cmd;
  1287. type = sp->name;
  1288. fcport = sp->fcport;
  1289. if (sts->entry_status) {
  1290. ql_log(ql_log_warn, fcport->vha, 0x5038,
  1291. "Async-%s error - hdl=%x entry-status(%x).\n",
  1292. type, sp->handle, sts->entry_status);
  1293. } else if (sts->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1294. ql_log(ql_log_warn, fcport->vha, 0x5039,
  1295. "Async-%s error - hdl=%x completion status(%x).\n",
  1296. type, sp->handle, sts->comp_status);
  1297. } else if (!(le16_to_cpu(sts->scsi_status) &
  1298. SS_RESPONSE_INFO_LEN_VALID)) {
  1299. ql_log(ql_log_warn, fcport->vha, 0x503a,
  1300. "Async-%s error - hdl=%x no response info(%x).\n",
  1301. type, sp->handle, sts->scsi_status);
  1302. } else if (le32_to_cpu(sts->rsp_data_len) < 4) {
  1303. ql_log(ql_log_warn, fcport->vha, 0x503b,
  1304. "Async-%s error - hdl=%x not enough response(%d).\n",
  1305. type, sp->handle, sts->rsp_data_len);
  1306. } else if (sts->data[3]) {
  1307. ql_log(ql_log_warn, fcport->vha, 0x503c,
  1308. "Async-%s error - hdl=%x response(%x).\n",
  1309. type, sp->handle, sts->data[3]);
  1310. } else {
  1311. error = 0;
  1312. }
  1313. if (error) {
  1314. iocb->u.tmf.data = error;
  1315. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5055,
  1316. (uint8_t *)sts, sizeof(*sts));
  1317. }
  1318. sp->done(vha, sp, 0);
  1319. }
  1320. /**
  1321. * qla2x00_process_response_queue() - Process response queue entries.
  1322. * @ha: SCSI driver HA context
  1323. */
  1324. void
  1325. qla2x00_process_response_queue(struct rsp_que *rsp)
  1326. {
  1327. struct scsi_qla_host *vha;
  1328. struct qla_hw_data *ha = rsp->hw;
  1329. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1330. sts_entry_t *pkt;
  1331. uint16_t handle_cnt;
  1332. uint16_t cnt;
  1333. vha = pci_get_drvdata(ha->pdev);
  1334. if (!vha->flags.online)
  1335. return;
  1336. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  1337. pkt = (sts_entry_t *)rsp->ring_ptr;
  1338. rsp->ring_index++;
  1339. if (rsp->ring_index == rsp->length) {
  1340. rsp->ring_index = 0;
  1341. rsp->ring_ptr = rsp->ring;
  1342. } else {
  1343. rsp->ring_ptr++;
  1344. }
  1345. if (pkt->entry_status != 0) {
  1346. qla2x00_error_entry(vha, rsp, pkt);
  1347. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1348. wmb();
  1349. continue;
  1350. }
  1351. switch (pkt->entry_type) {
  1352. case STATUS_TYPE:
  1353. qla2x00_status_entry(vha, rsp, pkt);
  1354. break;
  1355. case STATUS_TYPE_21:
  1356. handle_cnt = ((sts21_entry_t *)pkt)->handle_count;
  1357. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1358. qla2x00_process_completed_request(vha, rsp->req,
  1359. ((sts21_entry_t *)pkt)->handle[cnt]);
  1360. }
  1361. break;
  1362. case STATUS_TYPE_22:
  1363. handle_cnt = ((sts22_entry_t *)pkt)->handle_count;
  1364. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1365. qla2x00_process_completed_request(vha, rsp->req,
  1366. ((sts22_entry_t *)pkt)->handle[cnt]);
  1367. }
  1368. break;
  1369. case STATUS_CONT_TYPE:
  1370. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  1371. break;
  1372. case MBX_IOCB_TYPE:
  1373. qla2x00_mbx_iocb_entry(vha, rsp->req,
  1374. (struct mbx_entry *)pkt);
  1375. break;
  1376. case CT_IOCB_TYPE:
  1377. qla2x00_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  1378. break;
  1379. default:
  1380. /* Type Not Supported. */
  1381. ql_log(ql_log_warn, vha, 0x504a,
  1382. "Received unknown response pkt type %x "
  1383. "entry status=%x.\n",
  1384. pkt->entry_type, pkt->entry_status);
  1385. break;
  1386. }
  1387. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1388. wmb();
  1389. }
  1390. /* Adjust ring index */
  1391. WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), rsp->ring_index);
  1392. }
  1393. static inline void
  1394. qla2x00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
  1395. uint32_t sense_len, struct rsp_que *rsp, int res)
  1396. {
  1397. struct scsi_qla_host *vha = sp->fcport->vha;
  1398. struct scsi_cmnd *cp = GET_CMD_SP(sp);
  1399. uint32_t track_sense_len;
  1400. if (sense_len >= SCSI_SENSE_BUFFERSIZE)
  1401. sense_len = SCSI_SENSE_BUFFERSIZE;
  1402. SET_CMD_SENSE_LEN(sp, sense_len);
  1403. SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
  1404. track_sense_len = sense_len;
  1405. if (sense_len > par_sense_len)
  1406. sense_len = par_sense_len;
  1407. memcpy(cp->sense_buffer, sense_data, sense_len);
  1408. SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
  1409. track_sense_len -= sense_len;
  1410. SET_CMD_SENSE_LEN(sp, track_sense_len);
  1411. if (track_sense_len != 0) {
  1412. rsp->status_srb = sp;
  1413. cp->result = res;
  1414. }
  1415. if (sense_len) {
  1416. ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x301c,
  1417. "Check condition Sense data, nexus%ld:%d:%d cmd=%p.\n",
  1418. sp->fcport->vha->host_no, cp->device->id, cp->device->lun,
  1419. cp);
  1420. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302b,
  1421. cp->sense_buffer, sense_len);
  1422. }
  1423. }
  1424. struct scsi_dif_tuple {
  1425. __be16 guard; /* Checksum */
  1426. __be16 app_tag; /* APPL identifier */
  1427. __be32 ref_tag; /* Target LBA or indirect LBA */
  1428. };
  1429. /*
  1430. * Checks the guard or meta-data for the type of error
  1431. * detected by the HBA. In case of errors, we set the
  1432. * ASC/ASCQ fields in the sense buffer with ILLEGAL_REQUEST
  1433. * to indicate to the kernel that the HBA detected error.
  1434. */
  1435. static inline int
  1436. qla2x00_handle_dif_error(srb_t *sp, struct sts_entry_24xx *sts24)
  1437. {
  1438. struct scsi_qla_host *vha = sp->fcport->vha;
  1439. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  1440. uint8_t *ap = &sts24->data[12];
  1441. uint8_t *ep = &sts24->data[20];
  1442. uint32_t e_ref_tag, a_ref_tag;
  1443. uint16_t e_app_tag, a_app_tag;
  1444. uint16_t e_guard, a_guard;
  1445. /*
  1446. * swab32 of the "data" field in the beginning of qla2x00_status_entry()
  1447. * would make guard field appear at offset 2
  1448. */
  1449. a_guard = le16_to_cpu(*(uint16_t *)(ap + 2));
  1450. a_app_tag = le16_to_cpu(*(uint16_t *)(ap + 0));
  1451. a_ref_tag = le32_to_cpu(*(uint32_t *)(ap + 4));
  1452. e_guard = le16_to_cpu(*(uint16_t *)(ep + 2));
  1453. e_app_tag = le16_to_cpu(*(uint16_t *)(ep + 0));
  1454. e_ref_tag = le32_to_cpu(*(uint32_t *)(ep + 4));
  1455. ql_dbg(ql_dbg_io, vha, 0x3023,
  1456. "iocb(s) %p Returned STATUS.\n", sts24);
  1457. ql_dbg(ql_dbg_io, vha, 0x3024,
  1458. "DIF ERROR in cmd 0x%x lba 0x%llx act ref"
  1459. " tag=0x%x, exp ref_tag=0x%x, act app tag=0x%x, exp app"
  1460. " tag=0x%x, act guard=0x%x, exp guard=0x%x.\n",
  1461. cmd->cmnd[0], (u64)scsi_get_lba(cmd), a_ref_tag, e_ref_tag,
  1462. a_app_tag, e_app_tag, a_guard, e_guard);
  1463. /*
  1464. * Ignore sector if:
  1465. * For type 3: ref & app tag is all 'f's
  1466. * For type 0,1,2: app tag is all 'f's
  1467. */
  1468. if ((a_app_tag == 0xffff) &&
  1469. ((scsi_get_prot_type(cmd) != SCSI_PROT_DIF_TYPE3) ||
  1470. (a_ref_tag == 0xffffffff))) {
  1471. uint32_t blocks_done, resid;
  1472. sector_t lba_s = scsi_get_lba(cmd);
  1473. /* 2TB boundary case covered automatically with this */
  1474. blocks_done = e_ref_tag - (uint32_t)lba_s + 1;
  1475. resid = scsi_bufflen(cmd) - (blocks_done *
  1476. cmd->device->sector_size);
  1477. scsi_set_resid(cmd, resid);
  1478. cmd->result = DID_OK << 16;
  1479. /* Update protection tag */
  1480. if (scsi_prot_sg_count(cmd)) {
  1481. uint32_t i, j = 0, k = 0, num_ent;
  1482. struct scatterlist *sg;
  1483. struct sd_dif_tuple *spt;
  1484. /* Patch the corresponding protection tags */
  1485. scsi_for_each_prot_sg(cmd, sg,
  1486. scsi_prot_sg_count(cmd), i) {
  1487. num_ent = sg_dma_len(sg) / 8;
  1488. if (k + num_ent < blocks_done) {
  1489. k += num_ent;
  1490. continue;
  1491. }
  1492. j = blocks_done - k - 1;
  1493. k = blocks_done;
  1494. break;
  1495. }
  1496. if (k != blocks_done) {
  1497. ql_log(ql_log_warn, vha, 0x302f,
  1498. "unexpected tag values tag:lba=%x:%llx)\n",
  1499. e_ref_tag, (unsigned long long)lba_s);
  1500. return 1;
  1501. }
  1502. spt = page_address(sg_page(sg)) + sg->offset;
  1503. spt += j;
  1504. spt->app_tag = 0xffff;
  1505. if (scsi_get_prot_type(cmd) == SCSI_PROT_DIF_TYPE3)
  1506. spt->ref_tag = 0xffffffff;
  1507. }
  1508. return 0;
  1509. }
  1510. /* check guard */
  1511. if (e_guard != a_guard) {
  1512. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1513. 0x10, 0x1);
  1514. set_driver_byte(cmd, DRIVER_SENSE);
  1515. set_host_byte(cmd, DID_ABORT);
  1516. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1517. return 1;
  1518. }
  1519. /* check ref tag */
  1520. if (e_ref_tag != a_ref_tag) {
  1521. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1522. 0x10, 0x3);
  1523. set_driver_byte(cmd, DRIVER_SENSE);
  1524. set_host_byte(cmd, DID_ABORT);
  1525. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1526. return 1;
  1527. }
  1528. /* check appl tag */
  1529. if (e_app_tag != a_app_tag) {
  1530. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1531. 0x10, 0x2);
  1532. set_driver_byte(cmd, DRIVER_SENSE);
  1533. set_host_byte(cmd, DID_ABORT);
  1534. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1535. return 1;
  1536. }
  1537. return 1;
  1538. }
  1539. static void
  1540. qla25xx_process_bidir_status_iocb(scsi_qla_host_t *vha, void *pkt,
  1541. struct req_que *req, uint32_t index)
  1542. {
  1543. struct qla_hw_data *ha = vha->hw;
  1544. srb_t *sp;
  1545. uint16_t comp_status;
  1546. uint16_t scsi_status;
  1547. uint16_t thread_id;
  1548. uint32_t rval = EXT_STATUS_OK;
  1549. struct fc_bsg_job *bsg_job = NULL;
  1550. sts_entry_t *sts;
  1551. struct sts_entry_24xx *sts24;
  1552. sts = (sts_entry_t *) pkt;
  1553. sts24 = (struct sts_entry_24xx *) pkt;
  1554. /* Validate handle. */
  1555. if (index >= req->num_outstanding_cmds) {
  1556. ql_log(ql_log_warn, vha, 0x70af,
  1557. "Invalid SCSI completion handle 0x%x.\n", index);
  1558. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1559. return;
  1560. }
  1561. sp = req->outstanding_cmds[index];
  1562. if (sp) {
  1563. /* Free outstanding command slot. */
  1564. req->outstanding_cmds[index] = NULL;
  1565. bsg_job = sp->u.bsg_job;
  1566. } else {
  1567. ql_log(ql_log_warn, vha, 0x70b0,
  1568. "Req:%d: Invalid ISP SCSI completion handle(0x%x)\n",
  1569. req->id, index);
  1570. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1571. return;
  1572. }
  1573. if (IS_FWI2_CAPABLE(ha)) {
  1574. comp_status = le16_to_cpu(sts24->comp_status);
  1575. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1576. } else {
  1577. comp_status = le16_to_cpu(sts->comp_status);
  1578. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1579. }
  1580. thread_id = bsg_job->request->rqst_data.h_vendor.vendor_cmd[1];
  1581. switch (comp_status) {
  1582. case CS_COMPLETE:
  1583. if (scsi_status == 0) {
  1584. bsg_job->reply->reply_payload_rcv_len =
  1585. bsg_job->reply_payload.payload_len;
  1586. rval = EXT_STATUS_OK;
  1587. }
  1588. goto done;
  1589. case CS_DATA_OVERRUN:
  1590. ql_dbg(ql_dbg_user, vha, 0x70b1,
  1591. "Command completed with date overrun thread_id=%d\n",
  1592. thread_id);
  1593. rval = EXT_STATUS_DATA_OVERRUN;
  1594. break;
  1595. case CS_DATA_UNDERRUN:
  1596. ql_dbg(ql_dbg_user, vha, 0x70b2,
  1597. "Command completed with date underrun thread_id=%d\n",
  1598. thread_id);
  1599. rval = EXT_STATUS_DATA_UNDERRUN;
  1600. break;
  1601. case CS_BIDIR_RD_OVERRUN:
  1602. ql_dbg(ql_dbg_user, vha, 0x70b3,
  1603. "Command completed with read data overrun thread_id=%d\n",
  1604. thread_id);
  1605. rval = EXT_STATUS_DATA_OVERRUN;
  1606. break;
  1607. case CS_BIDIR_RD_WR_OVERRUN:
  1608. ql_dbg(ql_dbg_user, vha, 0x70b4,
  1609. "Command completed with read and write data overrun "
  1610. "thread_id=%d\n", thread_id);
  1611. rval = EXT_STATUS_DATA_OVERRUN;
  1612. break;
  1613. case CS_BIDIR_RD_OVERRUN_WR_UNDERRUN:
  1614. ql_dbg(ql_dbg_user, vha, 0x70b5,
  1615. "Command completed with read data over and write data "
  1616. "underrun thread_id=%d\n", thread_id);
  1617. rval = EXT_STATUS_DATA_OVERRUN;
  1618. break;
  1619. case CS_BIDIR_RD_UNDERRUN:
  1620. ql_dbg(ql_dbg_user, vha, 0x70b6,
  1621. "Command completed with read data data underrun "
  1622. "thread_id=%d\n", thread_id);
  1623. rval = EXT_STATUS_DATA_UNDERRUN;
  1624. break;
  1625. case CS_BIDIR_RD_UNDERRUN_WR_OVERRUN:
  1626. ql_dbg(ql_dbg_user, vha, 0x70b7,
  1627. "Command completed with read data under and write data "
  1628. "overrun thread_id=%d\n", thread_id);
  1629. rval = EXT_STATUS_DATA_UNDERRUN;
  1630. break;
  1631. case CS_BIDIR_RD_WR_UNDERRUN:
  1632. ql_dbg(ql_dbg_user, vha, 0x70b8,
  1633. "Command completed with read and write data underrun "
  1634. "thread_id=%d\n", thread_id);
  1635. rval = EXT_STATUS_DATA_UNDERRUN;
  1636. break;
  1637. case CS_BIDIR_DMA:
  1638. ql_dbg(ql_dbg_user, vha, 0x70b9,
  1639. "Command completed with data DMA error thread_id=%d\n",
  1640. thread_id);
  1641. rval = EXT_STATUS_DMA_ERR;
  1642. break;
  1643. case CS_TIMEOUT:
  1644. ql_dbg(ql_dbg_user, vha, 0x70ba,
  1645. "Command completed with timeout thread_id=%d\n",
  1646. thread_id);
  1647. rval = EXT_STATUS_TIMEOUT;
  1648. break;
  1649. default:
  1650. ql_dbg(ql_dbg_user, vha, 0x70bb,
  1651. "Command completed with completion status=0x%x "
  1652. "thread_id=%d\n", comp_status, thread_id);
  1653. rval = EXT_STATUS_ERR;
  1654. break;
  1655. }
  1656. bsg_job->reply->reply_payload_rcv_len = 0;
  1657. done:
  1658. /* Return the vendor specific reply to API */
  1659. bsg_job->reply->reply_data.vendor_reply.vendor_rsp[0] = rval;
  1660. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1661. /* Always return DID_OK, bsg will send the vendor specific response
  1662. * in this case only */
  1663. sp->done(vha, sp, (DID_OK << 6));
  1664. }
  1665. /**
  1666. * qla2x00_status_entry() - Process a Status IOCB entry.
  1667. * @ha: SCSI driver HA context
  1668. * @pkt: Entry pointer
  1669. */
  1670. static void
  1671. qla2x00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
  1672. {
  1673. srb_t *sp;
  1674. fc_port_t *fcport;
  1675. struct scsi_cmnd *cp;
  1676. sts_entry_t *sts;
  1677. struct sts_entry_24xx *sts24;
  1678. uint16_t comp_status;
  1679. uint16_t scsi_status;
  1680. uint16_t ox_id;
  1681. uint8_t lscsi_status;
  1682. int32_t resid;
  1683. uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
  1684. fw_resid_len;
  1685. uint8_t *rsp_info, *sense_data;
  1686. struct qla_hw_data *ha = vha->hw;
  1687. uint32_t handle;
  1688. uint16_t que;
  1689. struct req_que *req;
  1690. int logit = 1;
  1691. int res = 0;
  1692. uint16_t state_flags = 0;
  1693. sts = (sts_entry_t *) pkt;
  1694. sts24 = (struct sts_entry_24xx *) pkt;
  1695. if (IS_FWI2_CAPABLE(ha)) {
  1696. comp_status = le16_to_cpu(sts24->comp_status);
  1697. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1698. state_flags = le16_to_cpu(sts24->state_flags);
  1699. } else {
  1700. comp_status = le16_to_cpu(sts->comp_status);
  1701. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1702. }
  1703. handle = (uint32_t) LSW(sts->handle);
  1704. que = MSW(sts->handle);
  1705. req = ha->req_q_map[que];
  1706. /* Validate handle. */
  1707. if (handle < req->num_outstanding_cmds)
  1708. sp = req->outstanding_cmds[handle];
  1709. else
  1710. sp = NULL;
  1711. if (sp == NULL) {
  1712. ql_dbg(ql_dbg_io, vha, 0x3017,
  1713. "Invalid status handle (0x%x).\n", sts->handle);
  1714. if (IS_P3P_TYPE(ha))
  1715. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1716. else
  1717. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1718. qla2xxx_wake_dpc(vha);
  1719. return;
  1720. }
  1721. if (unlikely((state_flags & BIT_1) && (sp->type == SRB_BIDI_CMD))) {
  1722. qla25xx_process_bidir_status_iocb(vha, pkt, req, handle);
  1723. return;
  1724. }
  1725. /* Fast path completion. */
  1726. if (comp_status == CS_COMPLETE && scsi_status == 0) {
  1727. qla2x00_do_host_ramp_up(vha);
  1728. qla2x00_process_completed_request(vha, req, handle);
  1729. return;
  1730. }
  1731. req->outstanding_cmds[handle] = NULL;
  1732. cp = GET_CMD_SP(sp);
  1733. if (cp == NULL) {
  1734. ql_dbg(ql_dbg_io, vha, 0x3018,
  1735. "Command already returned (0x%x/%p).\n",
  1736. sts->handle, sp);
  1737. return;
  1738. }
  1739. lscsi_status = scsi_status & STATUS_MASK;
  1740. fcport = sp->fcport;
  1741. ox_id = 0;
  1742. sense_len = par_sense_len = rsp_info_len = resid_len =
  1743. fw_resid_len = 0;
  1744. if (IS_FWI2_CAPABLE(ha)) {
  1745. if (scsi_status & SS_SENSE_LEN_VALID)
  1746. sense_len = le32_to_cpu(sts24->sense_len);
  1747. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1748. rsp_info_len = le32_to_cpu(sts24->rsp_data_len);
  1749. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER))
  1750. resid_len = le32_to_cpu(sts24->rsp_residual_count);
  1751. if (comp_status == CS_DATA_UNDERRUN)
  1752. fw_resid_len = le32_to_cpu(sts24->residual_len);
  1753. rsp_info = sts24->data;
  1754. sense_data = sts24->data;
  1755. host_to_fcp_swap(sts24->data, sizeof(sts24->data));
  1756. ox_id = le16_to_cpu(sts24->ox_id);
  1757. par_sense_len = sizeof(sts24->data);
  1758. } else {
  1759. if (scsi_status & SS_SENSE_LEN_VALID)
  1760. sense_len = le16_to_cpu(sts->req_sense_length);
  1761. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1762. rsp_info_len = le16_to_cpu(sts->rsp_info_len);
  1763. resid_len = le32_to_cpu(sts->residual_length);
  1764. rsp_info = sts->rsp_info;
  1765. sense_data = sts->req_sense_data;
  1766. par_sense_len = sizeof(sts->req_sense_data);
  1767. }
  1768. /* Check for any FCP transport errors. */
  1769. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID) {
  1770. /* Sense data lies beyond any FCP RESPONSE data. */
  1771. if (IS_FWI2_CAPABLE(ha)) {
  1772. sense_data += rsp_info_len;
  1773. par_sense_len -= rsp_info_len;
  1774. }
  1775. if (rsp_info_len > 3 && rsp_info[3]) {
  1776. ql_dbg(ql_dbg_io, fcport->vha, 0x3019,
  1777. "FCP I/O protocol failure (0x%x/0x%x).\n",
  1778. rsp_info_len, rsp_info[3]);
  1779. res = DID_BUS_BUSY << 16;
  1780. goto out;
  1781. }
  1782. }
  1783. /* Check for overrun. */
  1784. if (IS_FWI2_CAPABLE(ha) && comp_status == CS_COMPLETE &&
  1785. scsi_status & SS_RESIDUAL_OVER)
  1786. comp_status = CS_DATA_OVERRUN;
  1787. /*
  1788. * Based on Host and scsi status generate status code for Linux
  1789. */
  1790. switch (comp_status) {
  1791. case CS_COMPLETE:
  1792. case CS_QUEUE_FULL:
  1793. if (scsi_status == 0) {
  1794. res = DID_OK << 16;
  1795. break;
  1796. }
  1797. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER)) {
  1798. resid = resid_len;
  1799. scsi_set_resid(cp, resid);
  1800. if (!lscsi_status &&
  1801. ((unsigned)(scsi_bufflen(cp) - resid) <
  1802. cp->underflow)) {
  1803. ql_dbg(ql_dbg_io, fcport->vha, 0x301a,
  1804. "Mid-layer underflow "
  1805. "detected (0x%x of 0x%x bytes).\n",
  1806. resid, scsi_bufflen(cp));
  1807. res = DID_ERROR << 16;
  1808. break;
  1809. }
  1810. }
  1811. res = DID_OK << 16 | lscsi_status;
  1812. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  1813. ql_dbg(ql_dbg_io, fcport->vha, 0x301b,
  1814. "QUEUE FULL detected.\n");
  1815. break;
  1816. }
  1817. logit = 0;
  1818. if (lscsi_status != SS_CHECK_CONDITION)
  1819. break;
  1820. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  1821. if (!(scsi_status & SS_SENSE_LEN_VALID))
  1822. break;
  1823. qla2x00_handle_sense(sp, sense_data, par_sense_len, sense_len,
  1824. rsp, res);
  1825. break;
  1826. case CS_DATA_UNDERRUN:
  1827. /* Use F/W calculated residual length. */
  1828. resid = IS_FWI2_CAPABLE(ha) ? fw_resid_len : resid_len;
  1829. scsi_set_resid(cp, resid);
  1830. if (scsi_status & SS_RESIDUAL_UNDER) {
  1831. if (IS_FWI2_CAPABLE(ha) && fw_resid_len != resid_len) {
  1832. ql_dbg(ql_dbg_io, fcport->vha, 0x301d,
  1833. "Dropped frame(s) detected "
  1834. "(0x%x of 0x%x bytes).\n",
  1835. resid, scsi_bufflen(cp));
  1836. res = DID_ERROR << 16 | lscsi_status;
  1837. goto check_scsi_status;
  1838. }
  1839. if (!lscsi_status &&
  1840. ((unsigned)(scsi_bufflen(cp) - resid) <
  1841. cp->underflow)) {
  1842. ql_dbg(ql_dbg_io, fcport->vha, 0x301e,
  1843. "Mid-layer underflow "
  1844. "detected (0x%x of 0x%x bytes).\n",
  1845. resid, scsi_bufflen(cp));
  1846. res = DID_ERROR << 16;
  1847. break;
  1848. }
  1849. } else if (lscsi_status != SAM_STAT_TASK_SET_FULL &&
  1850. lscsi_status != SAM_STAT_BUSY) {
  1851. /*
  1852. * scsi status of task set and busy are considered to be
  1853. * task not completed.
  1854. */
  1855. ql_dbg(ql_dbg_io, fcport->vha, 0x301f,
  1856. "Dropped frame(s) detected (0x%x "
  1857. "of 0x%x bytes).\n", resid,
  1858. scsi_bufflen(cp));
  1859. res = DID_ERROR << 16 | lscsi_status;
  1860. goto check_scsi_status;
  1861. } else {
  1862. ql_dbg(ql_dbg_io, fcport->vha, 0x3030,
  1863. "scsi_status: 0x%x, lscsi_status: 0x%x\n",
  1864. scsi_status, lscsi_status);
  1865. }
  1866. res = DID_OK << 16 | lscsi_status;
  1867. logit = 0;
  1868. check_scsi_status:
  1869. /*
  1870. * Check to see if SCSI Status is non zero. If so report SCSI
  1871. * Status.
  1872. */
  1873. if (lscsi_status != 0) {
  1874. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  1875. ql_dbg(ql_dbg_io, fcport->vha, 0x3020,
  1876. "QUEUE FULL detected.\n");
  1877. logit = 1;
  1878. break;
  1879. }
  1880. if (lscsi_status != SS_CHECK_CONDITION)
  1881. break;
  1882. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  1883. if (!(scsi_status & SS_SENSE_LEN_VALID))
  1884. break;
  1885. qla2x00_handle_sense(sp, sense_data, par_sense_len,
  1886. sense_len, rsp, res);
  1887. }
  1888. break;
  1889. case CS_PORT_LOGGED_OUT:
  1890. case CS_PORT_CONFIG_CHG:
  1891. case CS_PORT_BUSY:
  1892. case CS_INCOMPLETE:
  1893. case CS_PORT_UNAVAILABLE:
  1894. case CS_TIMEOUT:
  1895. case CS_RESET:
  1896. /*
  1897. * We are going to have the fc class block the rport
  1898. * while we try to recover so instruct the mid layer
  1899. * to requeue until the class decides how to handle this.
  1900. */
  1901. res = DID_TRANSPORT_DISRUPTED << 16;
  1902. if (comp_status == CS_TIMEOUT) {
  1903. if (IS_FWI2_CAPABLE(ha))
  1904. break;
  1905. else if ((le16_to_cpu(sts->status_flags) &
  1906. SF_LOGOUT_SENT) == 0)
  1907. break;
  1908. }
  1909. ql_dbg(ql_dbg_io, fcport->vha, 0x3021,
  1910. "Port down status: port-state=0x%x.\n",
  1911. atomic_read(&fcport->state));
  1912. if (atomic_read(&fcport->state) == FCS_ONLINE)
  1913. qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
  1914. break;
  1915. case CS_ABORTED:
  1916. res = DID_RESET << 16;
  1917. break;
  1918. case CS_DIF_ERROR:
  1919. logit = qla2x00_handle_dif_error(sp, sts24);
  1920. res = cp->result;
  1921. break;
  1922. case CS_TRANSPORT:
  1923. res = DID_ERROR << 16;
  1924. if (!IS_PI_SPLIT_DET_CAPABLE(ha))
  1925. break;
  1926. if (state_flags & BIT_4)
  1927. scmd_printk(KERN_WARNING, cp,
  1928. "Unsupported device '%s' found.\n",
  1929. cp->device->vendor);
  1930. break;
  1931. default:
  1932. res = DID_ERROR << 16;
  1933. break;
  1934. }
  1935. out:
  1936. if (logit)
  1937. ql_dbg(ql_dbg_io, fcport->vha, 0x3022,
  1938. "FCP command status: 0x%x-0x%x (0x%x) nexus=%ld:%d:%d "
  1939. "portid=%02x%02x%02x oxid=0x%x cdb=%10phN len=0x%x "
  1940. "rsp_info=0x%x resid=0x%x fw_resid=0x%x.\n",
  1941. comp_status, scsi_status, res, vha->host_no,
  1942. cp->device->id, cp->device->lun, fcport->d_id.b.domain,
  1943. fcport->d_id.b.area, fcport->d_id.b.al_pa, ox_id,
  1944. cp->cmnd, scsi_bufflen(cp), rsp_info_len,
  1945. resid_len, fw_resid_len);
  1946. if (!res)
  1947. qla2x00_do_host_ramp_up(vha);
  1948. if (rsp->status_srb == NULL)
  1949. sp->done(ha, sp, res);
  1950. }
  1951. /**
  1952. * qla2x00_status_cont_entry() - Process a Status Continuations entry.
  1953. * @ha: SCSI driver HA context
  1954. * @pkt: Entry pointer
  1955. *
  1956. * Extended sense data.
  1957. */
  1958. static void
  1959. qla2x00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
  1960. {
  1961. uint8_t sense_sz = 0;
  1962. struct qla_hw_data *ha = rsp->hw;
  1963. struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
  1964. srb_t *sp = rsp->status_srb;
  1965. struct scsi_cmnd *cp;
  1966. uint32_t sense_len;
  1967. uint8_t *sense_ptr;
  1968. if (!sp || !GET_CMD_SENSE_LEN(sp))
  1969. return;
  1970. sense_len = GET_CMD_SENSE_LEN(sp);
  1971. sense_ptr = GET_CMD_SENSE_PTR(sp);
  1972. cp = GET_CMD_SP(sp);
  1973. if (cp == NULL) {
  1974. ql_log(ql_log_warn, vha, 0x3025,
  1975. "cmd is NULL: already returned to OS (sp=%p).\n", sp);
  1976. rsp->status_srb = NULL;
  1977. return;
  1978. }
  1979. if (sense_len > sizeof(pkt->data))
  1980. sense_sz = sizeof(pkt->data);
  1981. else
  1982. sense_sz = sense_len;
  1983. /* Move sense data. */
  1984. if (IS_FWI2_CAPABLE(ha))
  1985. host_to_fcp_swap(pkt->data, sizeof(pkt->data));
  1986. memcpy(sense_ptr, pkt->data, sense_sz);
  1987. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302c,
  1988. sense_ptr, sense_sz);
  1989. sense_len -= sense_sz;
  1990. sense_ptr += sense_sz;
  1991. SET_CMD_SENSE_PTR(sp, sense_ptr);
  1992. SET_CMD_SENSE_LEN(sp, sense_len);
  1993. /* Place command on done queue. */
  1994. if (sense_len == 0) {
  1995. rsp->status_srb = NULL;
  1996. sp->done(ha, sp, cp->result);
  1997. }
  1998. }
  1999. /**
  2000. * qla2x00_error_entry() - Process an error entry.
  2001. * @ha: SCSI driver HA context
  2002. * @pkt: Entry pointer
  2003. */
  2004. static void
  2005. qla2x00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, sts_entry_t *pkt)
  2006. {
  2007. srb_t *sp;
  2008. struct qla_hw_data *ha = vha->hw;
  2009. const char func[] = "ERROR-IOCB";
  2010. uint16_t que = MSW(pkt->handle);
  2011. struct req_que *req = NULL;
  2012. int res = DID_ERROR << 16;
  2013. ql_dbg(ql_dbg_async, vha, 0x502a,
  2014. "type of error status in response: 0x%x\n", pkt->entry_status);
  2015. if (que >= ha->max_req_queues || !ha->req_q_map[que])
  2016. goto fatal;
  2017. req = ha->req_q_map[que];
  2018. if (pkt->entry_status & RF_BUSY)
  2019. res = DID_BUS_BUSY << 16;
  2020. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  2021. if (sp) {
  2022. sp->done(ha, sp, res);
  2023. return;
  2024. }
  2025. fatal:
  2026. ql_log(ql_log_warn, vha, 0x5030,
  2027. "Error entry - invalid handle/queue.\n");
  2028. if (IS_P3P_TYPE(ha))
  2029. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  2030. else
  2031. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2032. qla2xxx_wake_dpc(vha);
  2033. }
  2034. /**
  2035. * qla24xx_mbx_completion() - Process mailbox command completions.
  2036. * @ha: SCSI driver HA context
  2037. * @mb0: Mailbox0 register
  2038. */
  2039. static void
  2040. qla24xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  2041. {
  2042. uint16_t cnt;
  2043. uint32_t mboxes;
  2044. uint16_t __iomem *wptr;
  2045. struct qla_hw_data *ha = vha->hw;
  2046. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2047. /* Read all mbox registers? */
  2048. mboxes = (1 << ha->mbx_count) - 1;
  2049. if (!ha->mcp)
  2050. ql_dbg(ql_dbg_async, vha, 0x504e, "MBX pointer ERROR.\n");
  2051. else
  2052. mboxes = ha->mcp->in_mb;
  2053. /* Load return mailbox registers. */
  2054. ha->flags.mbox_int = 1;
  2055. ha->mailbox_out[0] = mb0;
  2056. mboxes >>= 1;
  2057. wptr = (uint16_t __iomem *)&reg->mailbox1;
  2058. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  2059. if (mboxes & BIT_0)
  2060. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  2061. mboxes >>= 1;
  2062. wptr++;
  2063. }
  2064. }
  2065. /**
  2066. * qla24xx_process_response_queue() - Process response queue entries.
  2067. * @ha: SCSI driver HA context
  2068. */
  2069. void qla24xx_process_response_queue(struct scsi_qla_host *vha,
  2070. struct rsp_que *rsp)
  2071. {
  2072. struct sts_entry_24xx *pkt;
  2073. struct qla_hw_data *ha = vha->hw;
  2074. if (!vha->flags.online)
  2075. return;
  2076. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  2077. pkt = (struct sts_entry_24xx *)rsp->ring_ptr;
  2078. rsp->ring_index++;
  2079. if (rsp->ring_index == rsp->length) {
  2080. rsp->ring_index = 0;
  2081. rsp->ring_ptr = rsp->ring;
  2082. } else {
  2083. rsp->ring_ptr++;
  2084. }
  2085. if (pkt->entry_status != 0) {
  2086. qla2x00_error_entry(vha, rsp, (sts_entry_t *) pkt);
  2087. (void)qlt_24xx_process_response_error(vha, pkt);
  2088. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2089. wmb();
  2090. continue;
  2091. }
  2092. switch (pkt->entry_type) {
  2093. case STATUS_TYPE:
  2094. qla2x00_status_entry(vha, rsp, pkt);
  2095. break;
  2096. case STATUS_CONT_TYPE:
  2097. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  2098. break;
  2099. case VP_RPT_ID_IOCB_TYPE:
  2100. qla24xx_report_id_acquisition(vha,
  2101. (struct vp_rpt_id_entry_24xx *)pkt);
  2102. break;
  2103. case LOGINOUT_PORT_IOCB_TYPE:
  2104. qla24xx_logio_entry(vha, rsp->req,
  2105. (struct logio_entry_24xx *)pkt);
  2106. break;
  2107. case TSK_MGMT_IOCB_TYPE:
  2108. qla24xx_tm_iocb_entry(vha, rsp->req,
  2109. (struct tsk_mgmt_entry *)pkt);
  2110. break;
  2111. case CT_IOCB_TYPE:
  2112. qla24xx_els_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  2113. break;
  2114. case ELS_IOCB_TYPE:
  2115. qla24xx_els_ct_entry(vha, rsp->req, pkt, ELS_IOCB_TYPE);
  2116. break;
  2117. case ABTS_RECV_24XX:
  2118. /* ensure that the ATIO queue is empty */
  2119. qlt_24xx_process_atio_queue(vha);
  2120. case ABTS_RESP_24XX:
  2121. case CTIO_TYPE7:
  2122. case NOTIFY_ACK_TYPE:
  2123. qlt_response_pkt_all_vps(vha, (response_t *)pkt);
  2124. break;
  2125. case MARKER_TYPE:
  2126. /* Do nothing in this case, this check is to prevent it
  2127. * from falling into default case
  2128. */
  2129. break;
  2130. default:
  2131. /* Type Not Supported. */
  2132. ql_dbg(ql_dbg_async, vha, 0x5042,
  2133. "Received unknown response pkt type %x "
  2134. "entry status=%x.\n",
  2135. pkt->entry_type, pkt->entry_status);
  2136. break;
  2137. }
  2138. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2139. wmb();
  2140. }
  2141. /* Adjust ring index */
  2142. if (IS_P3P_TYPE(ha)) {
  2143. struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
  2144. WRT_REG_DWORD(&reg->rsp_q_out[0], rsp->ring_index);
  2145. } else
  2146. WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
  2147. }
  2148. static void
  2149. qla2xxx_check_risc_status(scsi_qla_host_t *vha)
  2150. {
  2151. int rval;
  2152. uint32_t cnt;
  2153. struct qla_hw_data *ha = vha->hw;
  2154. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2155. if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
  2156. return;
  2157. rval = QLA_SUCCESS;
  2158. WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
  2159. RD_REG_DWORD(&reg->iobase_addr);
  2160. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2161. for (cnt = 10000; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2162. rval == QLA_SUCCESS; cnt--) {
  2163. if (cnt) {
  2164. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2165. udelay(10);
  2166. } else
  2167. rval = QLA_FUNCTION_TIMEOUT;
  2168. }
  2169. if (rval == QLA_SUCCESS)
  2170. goto next_test;
  2171. rval = QLA_SUCCESS;
  2172. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2173. for (cnt = 100; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2174. rval == QLA_SUCCESS; cnt--) {
  2175. if (cnt) {
  2176. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2177. udelay(10);
  2178. } else
  2179. rval = QLA_FUNCTION_TIMEOUT;
  2180. }
  2181. if (rval != QLA_SUCCESS)
  2182. goto done;
  2183. next_test:
  2184. if (RD_REG_DWORD(&reg->iobase_c8) & BIT_3)
  2185. ql_log(ql_log_info, vha, 0x504c,
  2186. "Additional code -- 0x55AA.\n");
  2187. done:
  2188. WRT_REG_DWORD(&reg->iobase_window, 0x0000);
  2189. RD_REG_DWORD(&reg->iobase_window);
  2190. }
  2191. /**
  2192. * qla24xx_intr_handler() - Process interrupts for the ISP23xx and ISP24xx.
  2193. * @irq:
  2194. * @dev_id: SCSI driver HA context
  2195. *
  2196. * Called by system whenever the host adapter generates an interrupt.
  2197. *
  2198. * Returns handled flag.
  2199. */
  2200. irqreturn_t
  2201. qla24xx_intr_handler(int irq, void *dev_id)
  2202. {
  2203. scsi_qla_host_t *vha;
  2204. struct qla_hw_data *ha;
  2205. struct device_reg_24xx __iomem *reg;
  2206. int status;
  2207. unsigned long iter;
  2208. uint32_t stat;
  2209. uint32_t hccr;
  2210. uint16_t mb[8];
  2211. struct rsp_que *rsp;
  2212. unsigned long flags;
  2213. rsp = (struct rsp_que *) dev_id;
  2214. if (!rsp) {
  2215. ql_log(ql_log_info, NULL, 0x5059,
  2216. "%s: NULL response queue pointer.\n", __func__);
  2217. return IRQ_NONE;
  2218. }
  2219. ha = rsp->hw;
  2220. reg = &ha->iobase->isp24;
  2221. status = 0;
  2222. if (unlikely(pci_channel_offline(ha->pdev)))
  2223. return IRQ_HANDLED;
  2224. spin_lock_irqsave(&ha->hardware_lock, flags);
  2225. vha = pci_get_drvdata(ha->pdev);
  2226. for (iter = 50; iter--; ) {
  2227. stat = RD_REG_DWORD(&reg->host_status);
  2228. if (stat & HSRX_RISC_PAUSED) {
  2229. if (unlikely(pci_channel_offline(ha->pdev)))
  2230. break;
  2231. hccr = RD_REG_DWORD(&reg->hccr);
  2232. ql_log(ql_log_warn, vha, 0x504b,
  2233. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2234. hccr);
  2235. qla2xxx_check_risc_status(vha);
  2236. ha->isp_ops->fw_dump(vha, 1);
  2237. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2238. break;
  2239. } else if ((stat & HSRX_RISC_INT) == 0)
  2240. break;
  2241. switch (stat & 0xff) {
  2242. case INTR_ROM_MB_SUCCESS:
  2243. case INTR_ROM_MB_FAILED:
  2244. case INTR_MB_SUCCESS:
  2245. case INTR_MB_FAILED:
  2246. qla24xx_mbx_completion(vha, MSW(stat));
  2247. status |= MBX_INTERRUPT;
  2248. break;
  2249. case INTR_ASYNC_EVENT:
  2250. mb[0] = MSW(stat);
  2251. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2252. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2253. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2254. qla2x00_async_event(vha, rsp, mb);
  2255. break;
  2256. case INTR_RSP_QUE_UPDATE:
  2257. case INTR_RSP_QUE_UPDATE_83XX:
  2258. qla24xx_process_response_queue(vha, rsp);
  2259. break;
  2260. case INTR_ATIO_QUE_UPDATE:
  2261. qlt_24xx_process_atio_queue(vha);
  2262. break;
  2263. case INTR_ATIO_RSP_QUE_UPDATE:
  2264. qlt_24xx_process_atio_queue(vha);
  2265. qla24xx_process_response_queue(vha, rsp);
  2266. break;
  2267. default:
  2268. ql_dbg(ql_dbg_async, vha, 0x504f,
  2269. "Unrecognized interrupt type (%d).\n", stat * 0xff);
  2270. break;
  2271. }
  2272. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2273. RD_REG_DWORD_RELAXED(&reg->hccr);
  2274. if (unlikely(IS_QLA83XX(ha) && (ha->pdev->revision == 1)))
  2275. ndelay(3500);
  2276. }
  2277. qla2x00_handle_mbx_completion(ha, status);
  2278. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2279. return IRQ_HANDLED;
  2280. }
  2281. static irqreturn_t
  2282. qla24xx_msix_rsp_q(int irq, void *dev_id)
  2283. {
  2284. struct qla_hw_data *ha;
  2285. struct rsp_que *rsp;
  2286. struct device_reg_24xx __iomem *reg;
  2287. struct scsi_qla_host *vha;
  2288. unsigned long flags;
  2289. rsp = (struct rsp_que *) dev_id;
  2290. if (!rsp) {
  2291. ql_log(ql_log_info, NULL, 0x505a,
  2292. "%s: NULL response queue pointer.\n", __func__);
  2293. return IRQ_NONE;
  2294. }
  2295. ha = rsp->hw;
  2296. reg = &ha->iobase->isp24;
  2297. spin_lock_irqsave(&ha->hardware_lock, flags);
  2298. vha = pci_get_drvdata(ha->pdev);
  2299. qla24xx_process_response_queue(vha, rsp);
  2300. if (!ha->flags.disable_msix_handshake) {
  2301. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2302. RD_REG_DWORD_RELAXED(&reg->hccr);
  2303. }
  2304. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2305. return IRQ_HANDLED;
  2306. }
  2307. static irqreturn_t
  2308. qla25xx_msix_rsp_q(int irq, void *dev_id)
  2309. {
  2310. struct qla_hw_data *ha;
  2311. struct rsp_que *rsp;
  2312. struct device_reg_24xx __iomem *reg;
  2313. unsigned long flags;
  2314. rsp = (struct rsp_que *) dev_id;
  2315. if (!rsp) {
  2316. ql_log(ql_log_info, NULL, 0x505b,
  2317. "%s: NULL response queue pointer.\n", __func__);
  2318. return IRQ_NONE;
  2319. }
  2320. ha = rsp->hw;
  2321. /* Clear the interrupt, if enabled, for this response queue */
  2322. if (!ha->flags.disable_msix_handshake) {
  2323. reg = &ha->iobase->isp24;
  2324. spin_lock_irqsave(&ha->hardware_lock, flags);
  2325. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2326. RD_REG_DWORD_RELAXED(&reg->hccr);
  2327. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2328. }
  2329. queue_work_on((int) (rsp->id - 1), ha->wq, &rsp->q_work);
  2330. return IRQ_HANDLED;
  2331. }
  2332. static irqreturn_t
  2333. qla24xx_msix_default(int irq, void *dev_id)
  2334. {
  2335. scsi_qla_host_t *vha;
  2336. struct qla_hw_data *ha;
  2337. struct rsp_que *rsp;
  2338. struct device_reg_24xx __iomem *reg;
  2339. int status;
  2340. uint32_t stat;
  2341. uint32_t hccr;
  2342. uint16_t mb[8];
  2343. unsigned long flags;
  2344. rsp = (struct rsp_que *) dev_id;
  2345. if (!rsp) {
  2346. ql_log(ql_log_info, NULL, 0x505c,
  2347. "%s: NULL response queue pointer.\n", __func__);
  2348. return IRQ_NONE;
  2349. }
  2350. ha = rsp->hw;
  2351. reg = &ha->iobase->isp24;
  2352. status = 0;
  2353. spin_lock_irqsave(&ha->hardware_lock, flags);
  2354. vha = pci_get_drvdata(ha->pdev);
  2355. do {
  2356. stat = RD_REG_DWORD(&reg->host_status);
  2357. if (stat & HSRX_RISC_PAUSED) {
  2358. if (unlikely(pci_channel_offline(ha->pdev)))
  2359. break;
  2360. hccr = RD_REG_DWORD(&reg->hccr);
  2361. ql_log(ql_log_info, vha, 0x5050,
  2362. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2363. hccr);
  2364. qla2xxx_check_risc_status(vha);
  2365. ha->isp_ops->fw_dump(vha, 1);
  2366. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2367. break;
  2368. } else if ((stat & HSRX_RISC_INT) == 0)
  2369. break;
  2370. switch (stat & 0xff) {
  2371. case INTR_ROM_MB_SUCCESS:
  2372. case INTR_ROM_MB_FAILED:
  2373. case INTR_MB_SUCCESS:
  2374. case INTR_MB_FAILED:
  2375. qla24xx_mbx_completion(vha, MSW(stat));
  2376. status |= MBX_INTERRUPT;
  2377. break;
  2378. case INTR_ASYNC_EVENT:
  2379. mb[0] = MSW(stat);
  2380. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2381. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2382. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2383. qla2x00_async_event(vha, rsp, mb);
  2384. break;
  2385. case INTR_RSP_QUE_UPDATE:
  2386. case INTR_RSP_QUE_UPDATE_83XX:
  2387. qla24xx_process_response_queue(vha, rsp);
  2388. break;
  2389. case INTR_ATIO_QUE_UPDATE:
  2390. qlt_24xx_process_atio_queue(vha);
  2391. break;
  2392. case INTR_ATIO_RSP_QUE_UPDATE:
  2393. qlt_24xx_process_atio_queue(vha);
  2394. qla24xx_process_response_queue(vha, rsp);
  2395. break;
  2396. default:
  2397. ql_dbg(ql_dbg_async, vha, 0x5051,
  2398. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  2399. break;
  2400. }
  2401. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2402. } while (0);
  2403. qla2x00_handle_mbx_completion(ha, status);
  2404. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2405. return IRQ_HANDLED;
  2406. }
  2407. /* Interrupt handling helpers. */
  2408. struct qla_init_msix_entry {
  2409. const char *name;
  2410. irq_handler_t handler;
  2411. };
  2412. static struct qla_init_msix_entry msix_entries[3] = {
  2413. { "qla2xxx (default)", qla24xx_msix_default },
  2414. { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
  2415. { "qla2xxx (multiq)", qla25xx_msix_rsp_q },
  2416. };
  2417. static struct qla_init_msix_entry qla82xx_msix_entries[2] = {
  2418. { "qla2xxx (default)", qla82xx_msix_default },
  2419. { "qla2xxx (rsp_q)", qla82xx_msix_rsp_q },
  2420. };
  2421. static struct qla_init_msix_entry qla83xx_msix_entries[3] = {
  2422. { "qla2xxx (default)", qla24xx_msix_default },
  2423. { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
  2424. { "qla2xxx (atio_q)", qla83xx_msix_atio_q },
  2425. };
  2426. static void
  2427. qla24xx_disable_msix(struct qla_hw_data *ha)
  2428. {
  2429. int i;
  2430. struct qla_msix_entry *qentry;
  2431. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2432. for (i = 0; i < ha->msix_count; i++) {
  2433. qentry = &ha->msix_entries[i];
  2434. if (qentry->have_irq)
  2435. free_irq(qentry->vector, qentry->rsp);
  2436. }
  2437. pci_disable_msix(ha->pdev);
  2438. kfree(ha->msix_entries);
  2439. ha->msix_entries = NULL;
  2440. ha->flags.msix_enabled = 0;
  2441. ql_dbg(ql_dbg_init, vha, 0x0042,
  2442. "Disabled the MSI.\n");
  2443. }
  2444. static int
  2445. qla24xx_enable_msix(struct qla_hw_data *ha, struct rsp_que *rsp)
  2446. {
  2447. #define MIN_MSIX_COUNT 2
  2448. int i, ret;
  2449. struct msix_entry *entries;
  2450. struct qla_msix_entry *qentry;
  2451. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2452. entries = kzalloc(sizeof(struct msix_entry) * ha->msix_count,
  2453. GFP_KERNEL);
  2454. if (!entries) {
  2455. ql_log(ql_log_warn, vha, 0x00bc,
  2456. "Failed to allocate memory for msix_entry.\n");
  2457. return -ENOMEM;
  2458. }
  2459. for (i = 0; i < ha->msix_count; i++)
  2460. entries[i].entry = i;
  2461. ret = pci_enable_msix(ha->pdev, entries, ha->msix_count);
  2462. if (ret) {
  2463. if (ret < MIN_MSIX_COUNT)
  2464. goto msix_failed;
  2465. ql_log(ql_log_warn, vha, 0x00c6,
  2466. "MSI-X: Failed to enable support "
  2467. "-- %d/%d\n Retry with %d vectors.\n",
  2468. ha->msix_count, ret, ret);
  2469. ha->msix_count = ret;
  2470. ret = pci_enable_msix(ha->pdev, entries, ha->msix_count);
  2471. if (ret) {
  2472. msix_failed:
  2473. ql_log(ql_log_fatal, vha, 0x00c7,
  2474. "MSI-X: Failed to enable support, "
  2475. "giving up -- %d/%d.\n",
  2476. ha->msix_count, ret);
  2477. goto msix_out;
  2478. }
  2479. ha->max_rsp_queues = ha->msix_count - 1;
  2480. }
  2481. ha->msix_entries = kzalloc(sizeof(struct qla_msix_entry) *
  2482. ha->msix_count, GFP_KERNEL);
  2483. if (!ha->msix_entries) {
  2484. ql_log(ql_log_fatal, vha, 0x00c8,
  2485. "Failed to allocate memory for ha->msix_entries.\n");
  2486. ret = -ENOMEM;
  2487. goto msix_out;
  2488. }
  2489. ha->flags.msix_enabled = 1;
  2490. for (i = 0; i < ha->msix_count; i++) {
  2491. qentry = &ha->msix_entries[i];
  2492. qentry->vector = entries[i].vector;
  2493. qentry->entry = entries[i].entry;
  2494. qentry->have_irq = 0;
  2495. qentry->rsp = NULL;
  2496. }
  2497. /* Enable MSI-X vectors for the base queue */
  2498. for (i = 0; i < ha->msix_count; i++) {
  2499. qentry = &ha->msix_entries[i];
  2500. if (QLA_TGT_MODE_ENABLED() && IS_ATIO_MSIX_CAPABLE(ha)) {
  2501. ret = request_irq(qentry->vector,
  2502. qla83xx_msix_entries[i].handler,
  2503. 0, qla83xx_msix_entries[i].name, rsp);
  2504. } else if (IS_P3P_TYPE(ha)) {
  2505. ret = request_irq(qentry->vector,
  2506. qla82xx_msix_entries[i].handler,
  2507. 0, qla82xx_msix_entries[i].name, rsp);
  2508. } else {
  2509. ret = request_irq(qentry->vector,
  2510. msix_entries[i].handler,
  2511. 0, msix_entries[i].name, rsp);
  2512. }
  2513. if (ret) {
  2514. ql_log(ql_log_fatal, vha, 0x00cb,
  2515. "MSI-X: unable to register handler -- %x/%d.\n",
  2516. qentry->vector, ret);
  2517. qla24xx_disable_msix(ha);
  2518. ha->mqenable = 0;
  2519. goto msix_out;
  2520. }
  2521. qentry->have_irq = 1;
  2522. qentry->rsp = rsp;
  2523. rsp->msix = qentry;
  2524. }
  2525. /* Enable MSI-X vector for response queue update for queue 0 */
  2526. if (IS_QLA83XX(ha)) {
  2527. if (ha->msixbase && ha->mqiobase &&
  2528. (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2529. ha->mqenable = 1;
  2530. } else
  2531. if (ha->mqiobase
  2532. && (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2533. ha->mqenable = 1;
  2534. ql_dbg(ql_dbg_multiq, vha, 0xc005,
  2535. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2536. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2537. ql_dbg(ql_dbg_init, vha, 0x0055,
  2538. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2539. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2540. msix_out:
  2541. kfree(entries);
  2542. return ret;
  2543. }
  2544. int
  2545. qla2x00_request_irqs(struct qla_hw_data *ha, struct rsp_que *rsp)
  2546. {
  2547. int ret;
  2548. device_reg_t __iomem *reg = ha->iobase;
  2549. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2550. /* If possible, enable MSI-X. */
  2551. if (!IS_QLA2432(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2552. !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha) && !IS_QLAFX00(ha))
  2553. goto skip_msi;
  2554. if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
  2555. (ha->pdev->subsystem_device == 0x7040 ||
  2556. ha->pdev->subsystem_device == 0x7041 ||
  2557. ha->pdev->subsystem_device == 0x1705)) {
  2558. ql_log(ql_log_warn, vha, 0x0034,
  2559. "MSI-X: Unsupported ISP 2432 SSVID/SSDID (0x%X,0x%X).\n",
  2560. ha->pdev->subsystem_vendor,
  2561. ha->pdev->subsystem_device);
  2562. goto skip_msi;
  2563. }
  2564. if (IS_QLA2432(ha) && (ha->pdev->revision < QLA_MSIX_CHIP_REV_24XX)) {
  2565. ql_log(ql_log_warn, vha, 0x0035,
  2566. "MSI-X; Unsupported ISP2432 (0x%X, 0x%X).\n",
  2567. ha->pdev->revision, QLA_MSIX_CHIP_REV_24XX);
  2568. goto skip_msix;
  2569. }
  2570. ret = qla24xx_enable_msix(ha, rsp);
  2571. if (!ret) {
  2572. ql_dbg(ql_dbg_init, vha, 0x0036,
  2573. "MSI-X: Enabled (0x%X, 0x%X).\n",
  2574. ha->chip_revision, ha->fw_attributes);
  2575. goto clear_risc_ints;
  2576. }
  2577. ql_log(ql_log_info, vha, 0x0037,
  2578. "MSI-X Falling back-to MSI mode -%d.\n", ret);
  2579. skip_msix:
  2580. if (!IS_QLA24XX(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2581. !IS_QLA8001(ha) && !IS_P3P_TYPE(ha) && !IS_QLAFX00(ha))
  2582. goto skip_msi;
  2583. ret = pci_enable_msi(ha->pdev);
  2584. if (!ret) {
  2585. ql_dbg(ql_dbg_init, vha, 0x0038,
  2586. "MSI: Enabled.\n");
  2587. ha->flags.msi_enabled = 1;
  2588. } else
  2589. ql_log(ql_log_warn, vha, 0x0039,
  2590. "MSI-X; Falling back-to INTa mode -- %d.\n", ret);
  2591. /* Skip INTx on ISP82xx. */
  2592. if (!ha->flags.msi_enabled && IS_QLA82XX(ha))
  2593. return QLA_FUNCTION_FAILED;
  2594. skip_msi:
  2595. ret = request_irq(ha->pdev->irq, ha->isp_ops->intr_handler,
  2596. ha->flags.msi_enabled ? 0 : IRQF_SHARED,
  2597. QLA2XXX_DRIVER_NAME, rsp);
  2598. if (ret) {
  2599. ql_log(ql_log_warn, vha, 0x003a,
  2600. "Failed to reserve interrupt %d already in use.\n",
  2601. ha->pdev->irq);
  2602. goto fail;
  2603. } else if (!ha->flags.msi_enabled) {
  2604. ql_dbg(ql_dbg_init, vha, 0x0125,
  2605. "INTa mode: Enabled.\n");
  2606. ha->flags.mr_intr_valid = 1;
  2607. }
  2608. clear_risc_ints:
  2609. spin_lock_irq(&ha->hardware_lock);
  2610. if (!IS_FWI2_CAPABLE(ha))
  2611. WRT_REG_WORD(&reg->isp.semaphore, 0);
  2612. spin_unlock_irq(&ha->hardware_lock);
  2613. fail:
  2614. return ret;
  2615. }
  2616. void
  2617. qla2x00_free_irqs(scsi_qla_host_t *vha)
  2618. {
  2619. struct qla_hw_data *ha = vha->hw;
  2620. struct rsp_que *rsp;
  2621. /*
  2622. * We need to check that ha->rsp_q_map is valid in case we are called
  2623. * from a probe failure context.
  2624. */
  2625. if (!ha->rsp_q_map || !ha->rsp_q_map[0])
  2626. return;
  2627. rsp = ha->rsp_q_map[0];
  2628. if (ha->flags.msix_enabled)
  2629. qla24xx_disable_msix(ha);
  2630. else if (ha->flags.msi_enabled) {
  2631. free_irq(ha->pdev->irq, rsp);
  2632. pci_disable_msi(ha->pdev);
  2633. } else
  2634. free_irq(ha->pdev->irq, rsp);
  2635. }
  2636. int qla25xx_request_irq(struct rsp_que *rsp)
  2637. {
  2638. struct qla_hw_data *ha = rsp->hw;
  2639. struct qla_init_msix_entry *intr = &msix_entries[2];
  2640. struct qla_msix_entry *msix = rsp->msix;
  2641. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2642. int ret;
  2643. ret = request_irq(msix->vector, intr->handler, 0, intr->name, rsp);
  2644. if (ret) {
  2645. ql_log(ql_log_fatal, vha, 0x00e6,
  2646. "MSI-X: Unable to register handler -- %x/%d.\n",
  2647. msix->vector, ret);
  2648. return ret;
  2649. }
  2650. msix->have_irq = 1;
  2651. msix->rsp = rsp;
  2652. return ret;
  2653. }