pasemi_mac.c 38 KB

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  1. /*
  2. * Copyright (C) 2006-2007 PA Semi, Inc
  3. *
  4. * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/init.h>
  20. #include <linux/module.h>
  21. #include <linux/pci.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/dmaengine.h>
  24. #include <linux/delay.h>
  25. #include <linux/netdevice.h>
  26. #include <linux/etherdevice.h>
  27. #include <asm/dma-mapping.h>
  28. #include <linux/in.h>
  29. #include <linux/skbuff.h>
  30. #include <linux/ip.h>
  31. #include <linux/tcp.h>
  32. #include <net/checksum.h>
  33. #include <linux/inet_lro.h>
  34. #include <asm/irq.h>
  35. #include <asm/firmware.h>
  36. #include <asm/pasemi_dma.h>
  37. #include "pasemi_mac.h"
  38. /* We have our own align, since ppc64 in general has it at 0 because
  39. * of design flaws in some of the server bridge chips. However, for
  40. * PWRficient doing the unaligned copies is more expensive than doing
  41. * unaligned DMA, so make sure the data is aligned instead.
  42. */
  43. #define LOCAL_SKB_ALIGN 2
  44. /* TODO list
  45. *
  46. * - Multicast support
  47. * - Large MTU support
  48. * - SW LRO
  49. * - Multiqueue RX/TX
  50. */
  51. /* Must be a power of two */
  52. #define RX_RING_SIZE 2048
  53. #define TX_RING_SIZE 4096
  54. #define LRO_MAX_AGGR 64
  55. #define DEFAULT_MSG_ENABLE \
  56. (NETIF_MSG_DRV | \
  57. NETIF_MSG_PROBE | \
  58. NETIF_MSG_LINK | \
  59. NETIF_MSG_TIMER | \
  60. NETIF_MSG_IFDOWN | \
  61. NETIF_MSG_IFUP | \
  62. NETIF_MSG_RX_ERR | \
  63. NETIF_MSG_TX_ERR)
  64. #define TX_DESC(tx, num) ((tx)->chan.ring_virt[(num) & (TX_RING_SIZE-1)])
  65. #define TX_DESC_INFO(tx, num) ((tx)->ring_info[(num) & (TX_RING_SIZE-1)])
  66. #define RX_DESC(rx, num) ((rx)->chan.ring_virt[(num) & (RX_RING_SIZE-1)])
  67. #define RX_DESC_INFO(rx, num) ((rx)->ring_info[(num) & (RX_RING_SIZE-1)])
  68. #define RX_BUFF(rx, num) ((rx)->buffers[(num) & (RX_RING_SIZE-1)])
  69. #define RING_USED(ring) (((ring)->next_to_fill - (ring)->next_to_clean) \
  70. & ((ring)->size - 1))
  71. #define RING_AVAIL(ring) ((ring->size) - RING_USED(ring))
  72. #define BUF_SIZE 1646 /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
  73. MODULE_LICENSE("GPL");
  74. MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
  75. MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver");
  76. static int debug = -1; /* -1 == use DEFAULT_MSG_ENABLE as value */
  77. module_param(debug, int, 0);
  78. MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value");
  79. static int translation_enabled(void)
  80. {
  81. #if defined(CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE)
  82. return 1;
  83. #else
  84. return firmware_has_feature(FW_FEATURE_LPAR);
  85. #endif
  86. }
  87. static void write_iob_reg(unsigned int reg, unsigned int val)
  88. {
  89. pasemi_write_iob_reg(reg, val);
  90. }
  91. static unsigned int read_mac_reg(const struct pasemi_mac *mac, unsigned int reg)
  92. {
  93. return pasemi_read_mac_reg(mac->dma_if, reg);
  94. }
  95. static void write_mac_reg(const struct pasemi_mac *mac, unsigned int reg,
  96. unsigned int val)
  97. {
  98. pasemi_write_mac_reg(mac->dma_if, reg, val);
  99. }
  100. static unsigned int read_dma_reg(unsigned int reg)
  101. {
  102. return pasemi_read_dma_reg(reg);
  103. }
  104. static void write_dma_reg(unsigned int reg, unsigned int val)
  105. {
  106. pasemi_write_dma_reg(reg, val);
  107. }
  108. static struct pasemi_mac_rxring *rx_ring(const struct pasemi_mac *mac)
  109. {
  110. return mac->rx;
  111. }
  112. static struct pasemi_mac_txring *tx_ring(const struct pasemi_mac *mac)
  113. {
  114. return mac->tx;
  115. }
  116. static inline void prefetch_skb(const struct sk_buff *skb)
  117. {
  118. const void *d = skb;
  119. prefetch(d);
  120. prefetch(d+64);
  121. prefetch(d+128);
  122. prefetch(d+192);
  123. }
  124. static int mac_to_intf(struct pasemi_mac *mac)
  125. {
  126. struct pci_dev *pdev = mac->pdev;
  127. u32 tmp;
  128. int nintf, off, i, j;
  129. int devfn = pdev->devfn;
  130. tmp = read_dma_reg(PAS_DMA_CAP_IFI);
  131. nintf = (tmp & PAS_DMA_CAP_IFI_NIN_M) >> PAS_DMA_CAP_IFI_NIN_S;
  132. off = (tmp & PAS_DMA_CAP_IFI_IOFF_M) >> PAS_DMA_CAP_IFI_IOFF_S;
  133. /* IOFF contains the offset to the registers containing the
  134. * DMA interface-to-MAC-pci-id mappings, and NIN contains number
  135. * of total interfaces. Each register contains 4 devfns.
  136. * Just do a linear search until we find the devfn of the MAC
  137. * we're trying to look up.
  138. */
  139. for (i = 0; i < (nintf+3)/4; i++) {
  140. tmp = read_dma_reg(off+4*i);
  141. for (j = 0; j < 4; j++) {
  142. if (((tmp >> (8*j)) & 0xff) == devfn)
  143. return i*4 + j;
  144. }
  145. }
  146. return -1;
  147. }
  148. static int pasemi_get_mac_addr(struct pasemi_mac *mac)
  149. {
  150. struct pci_dev *pdev = mac->pdev;
  151. struct device_node *dn = pci_device_to_OF_node(pdev);
  152. int len;
  153. const u8 *maddr;
  154. u8 addr[6];
  155. if (!dn) {
  156. dev_dbg(&pdev->dev,
  157. "No device node for mac, not configuring\n");
  158. return -ENOENT;
  159. }
  160. maddr = of_get_property(dn, "local-mac-address", &len);
  161. if (maddr && len == 6) {
  162. memcpy(mac->mac_addr, maddr, 6);
  163. return 0;
  164. }
  165. /* Some old versions of firmware mistakenly uses mac-address
  166. * (and as a string) instead of a byte array in local-mac-address.
  167. */
  168. if (maddr == NULL)
  169. maddr = of_get_property(dn, "mac-address", NULL);
  170. if (maddr == NULL) {
  171. dev_warn(&pdev->dev,
  172. "no mac address in device tree, not configuring\n");
  173. return -ENOENT;
  174. }
  175. if (sscanf(maddr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &addr[0],
  176. &addr[1], &addr[2], &addr[3], &addr[4], &addr[5]) != 6) {
  177. dev_warn(&pdev->dev,
  178. "can't parse mac address, not configuring\n");
  179. return -EINVAL;
  180. }
  181. memcpy(mac->mac_addr, addr, 6);
  182. return 0;
  183. }
  184. static int get_skb_hdr(struct sk_buff *skb, void **iphdr,
  185. void **tcph, u64 *hdr_flags, void *data)
  186. {
  187. u64 macrx = (u64) data;
  188. unsigned int ip_len;
  189. struct iphdr *iph;
  190. /* IPv4 header checksum failed */
  191. if ((macrx & XCT_MACRX_HTY_M) != XCT_MACRX_HTY_IPV4_OK)
  192. return -1;
  193. /* non tcp packet */
  194. skb_reset_network_header(skb);
  195. iph = ip_hdr(skb);
  196. if (iph->protocol != IPPROTO_TCP)
  197. return -1;
  198. ip_len = ip_hdrlen(skb);
  199. skb_set_transport_header(skb, ip_len);
  200. *tcph = tcp_hdr(skb);
  201. /* check if ip header and tcp header are complete */
  202. if (iph->tot_len < ip_len + tcp_hdrlen(skb))
  203. return -1;
  204. *hdr_flags = LRO_IPV4 | LRO_TCP;
  205. *iphdr = iph;
  206. return 0;
  207. }
  208. static int pasemi_mac_unmap_tx_skb(struct pasemi_mac *mac,
  209. const int nfrags,
  210. struct sk_buff *skb,
  211. const dma_addr_t *dmas)
  212. {
  213. int f;
  214. struct pci_dev *pdev = mac->dma_pdev;
  215. pci_unmap_single(pdev, dmas[0], skb_headlen(skb), PCI_DMA_TODEVICE);
  216. for (f = 0; f < nfrags; f++) {
  217. skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
  218. pci_unmap_page(pdev, dmas[f+1], frag->size, PCI_DMA_TODEVICE);
  219. }
  220. dev_kfree_skb_irq(skb);
  221. /* Freed descriptor slot + main SKB ptr + nfrags additional ptrs,
  222. * aligned up to a power of 2
  223. */
  224. return (nfrags + 3) & ~1;
  225. }
  226. static int pasemi_mac_setup_rx_resources(const struct net_device *dev)
  227. {
  228. struct pasemi_mac_rxring *ring;
  229. struct pasemi_mac *mac = netdev_priv(dev);
  230. int chno;
  231. unsigned int cfg;
  232. ring = pasemi_dma_alloc_chan(RXCHAN, sizeof(struct pasemi_mac_rxring),
  233. offsetof(struct pasemi_mac_rxring, chan));
  234. if (!ring) {
  235. dev_err(&mac->pdev->dev, "Can't allocate RX channel\n");
  236. goto out_chan;
  237. }
  238. chno = ring->chan.chno;
  239. spin_lock_init(&ring->lock);
  240. ring->size = RX_RING_SIZE;
  241. ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
  242. RX_RING_SIZE, GFP_KERNEL);
  243. if (!ring->ring_info)
  244. goto out_ring_info;
  245. /* Allocate descriptors */
  246. if (pasemi_dma_alloc_ring(&ring->chan, RX_RING_SIZE))
  247. goto out_ring_desc;
  248. ring->buffers = dma_alloc_coherent(&mac->dma_pdev->dev,
  249. RX_RING_SIZE * sizeof(u64),
  250. &ring->buf_dma, GFP_KERNEL);
  251. if (!ring->buffers)
  252. goto out_ring_desc;
  253. memset(ring->buffers, 0, RX_RING_SIZE * sizeof(u64));
  254. write_dma_reg(PAS_DMA_RXCHAN_BASEL(chno),
  255. PAS_DMA_RXCHAN_BASEL_BRBL(ring->chan.ring_dma));
  256. write_dma_reg(PAS_DMA_RXCHAN_BASEU(chno),
  257. PAS_DMA_RXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32) |
  258. PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 3));
  259. cfg = PAS_DMA_RXCHAN_CFG_HBU(2);
  260. if (translation_enabled())
  261. cfg |= PAS_DMA_RXCHAN_CFG_CTR;
  262. write_dma_reg(PAS_DMA_RXCHAN_CFG(chno), cfg);
  263. write_dma_reg(PAS_DMA_RXINT_BASEL(mac->dma_if),
  264. PAS_DMA_RXINT_BASEL_BRBL(ring->buf_dma));
  265. write_dma_reg(PAS_DMA_RXINT_BASEU(mac->dma_if),
  266. PAS_DMA_RXINT_BASEU_BRBH(ring->buf_dma >> 32) |
  267. PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3));
  268. cfg = PAS_DMA_RXINT_CFG_DHL(2) | PAS_DMA_RXINT_CFG_L2 |
  269. PAS_DMA_RXINT_CFG_LW | PAS_DMA_RXINT_CFG_RBP |
  270. PAS_DMA_RXINT_CFG_HEN;
  271. if (translation_enabled())
  272. cfg |= PAS_DMA_RXINT_CFG_ITRR | PAS_DMA_RXINT_CFG_ITR;
  273. write_dma_reg(PAS_DMA_RXINT_CFG(mac->dma_if), cfg);
  274. ring->next_to_fill = 0;
  275. ring->next_to_clean = 0;
  276. ring->mac = mac;
  277. mac->rx = ring;
  278. return 0;
  279. out_ring_desc:
  280. kfree(ring->ring_info);
  281. out_ring_info:
  282. pasemi_dma_free_chan(&ring->chan);
  283. out_chan:
  284. return -ENOMEM;
  285. }
  286. static struct pasemi_mac_txring *
  287. pasemi_mac_setup_tx_resources(const struct net_device *dev)
  288. {
  289. struct pasemi_mac *mac = netdev_priv(dev);
  290. u32 val;
  291. struct pasemi_mac_txring *ring;
  292. unsigned int cfg;
  293. int chno;
  294. ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_txring),
  295. offsetof(struct pasemi_mac_txring, chan));
  296. if (!ring) {
  297. dev_err(&mac->pdev->dev, "Can't allocate TX channel\n");
  298. goto out_chan;
  299. }
  300. chno = ring->chan.chno;
  301. spin_lock_init(&ring->lock);
  302. ring->size = TX_RING_SIZE;
  303. ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
  304. TX_RING_SIZE, GFP_KERNEL);
  305. if (!ring->ring_info)
  306. goto out_ring_info;
  307. /* Allocate descriptors */
  308. if (pasemi_dma_alloc_ring(&ring->chan, TX_RING_SIZE))
  309. goto out_ring_desc;
  310. write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno),
  311. PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma));
  312. val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32);
  313. val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 3);
  314. write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val);
  315. cfg = PAS_DMA_TXCHAN_CFG_TY_IFACE |
  316. PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) |
  317. PAS_DMA_TXCHAN_CFG_UP |
  318. PAS_DMA_TXCHAN_CFG_WT(2);
  319. if (translation_enabled())
  320. cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR;
  321. write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg);
  322. ring->next_to_fill = 0;
  323. ring->next_to_clean = 0;
  324. ring->mac = mac;
  325. return ring;
  326. out_ring_desc:
  327. kfree(ring->ring_info);
  328. out_ring_info:
  329. pasemi_dma_free_chan(&ring->chan);
  330. out_chan:
  331. return NULL;
  332. }
  333. static void pasemi_mac_free_tx_resources(struct pasemi_mac *mac)
  334. {
  335. struct pasemi_mac_txring *txring = tx_ring(mac);
  336. unsigned int i, j;
  337. struct pasemi_mac_buffer *info;
  338. dma_addr_t dmas[MAX_SKB_FRAGS+1];
  339. int freed, nfrags;
  340. int start, limit;
  341. start = txring->next_to_clean;
  342. limit = txring->next_to_fill;
  343. /* Compensate for when fill has wrapped and clean has not */
  344. if (start > limit)
  345. limit += TX_RING_SIZE;
  346. for (i = start; i < limit; i += freed) {
  347. info = &txring->ring_info[(i+1) & (TX_RING_SIZE-1)];
  348. if (info->dma && info->skb) {
  349. nfrags = skb_shinfo(info->skb)->nr_frags;
  350. for (j = 0; j <= nfrags; j++)
  351. dmas[j] = txring->ring_info[(i+1+j) &
  352. (TX_RING_SIZE-1)].dma;
  353. freed = pasemi_mac_unmap_tx_skb(mac, nfrags,
  354. info->skb, dmas);
  355. } else
  356. freed = 2;
  357. }
  358. kfree(txring->ring_info);
  359. pasemi_dma_free_chan(&txring->chan);
  360. }
  361. static void pasemi_mac_free_rx_resources(struct pasemi_mac *mac)
  362. {
  363. struct pasemi_mac_rxring *rx = rx_ring(mac);
  364. unsigned int i;
  365. struct pasemi_mac_buffer *info;
  366. for (i = 0; i < RX_RING_SIZE; i++) {
  367. info = &RX_DESC_INFO(rx, i);
  368. if (info->skb && info->dma) {
  369. pci_unmap_single(mac->dma_pdev,
  370. info->dma,
  371. info->skb->len,
  372. PCI_DMA_FROMDEVICE);
  373. dev_kfree_skb_any(info->skb);
  374. }
  375. info->dma = 0;
  376. info->skb = NULL;
  377. }
  378. for (i = 0; i < RX_RING_SIZE; i++)
  379. RX_DESC(rx, i) = 0;
  380. dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64),
  381. rx_ring(mac)->buffers, rx_ring(mac)->buf_dma);
  382. kfree(rx_ring(mac)->ring_info);
  383. pasemi_dma_free_chan(&rx_ring(mac)->chan);
  384. mac->rx = NULL;
  385. }
  386. static void pasemi_mac_replenish_rx_ring(const struct net_device *dev,
  387. const int limit)
  388. {
  389. const struct pasemi_mac *mac = netdev_priv(dev);
  390. struct pasemi_mac_rxring *rx = rx_ring(mac);
  391. int fill, count;
  392. if (limit <= 0)
  393. return;
  394. fill = rx_ring(mac)->next_to_fill;
  395. for (count = 0; count < limit; count++) {
  396. struct pasemi_mac_buffer *info = &RX_DESC_INFO(rx, fill);
  397. u64 *buff = &RX_BUFF(rx, fill);
  398. struct sk_buff *skb;
  399. dma_addr_t dma;
  400. /* Entry in use? */
  401. WARN_ON(*buff);
  402. /* skb might still be in there for recycle on short receives */
  403. if (info->skb)
  404. skb = info->skb;
  405. else {
  406. skb = dev_alloc_skb(BUF_SIZE);
  407. skb_reserve(skb, LOCAL_SKB_ALIGN);
  408. }
  409. if (unlikely(!skb))
  410. break;
  411. dma = pci_map_single(mac->dma_pdev, skb->data,
  412. BUF_SIZE - LOCAL_SKB_ALIGN,
  413. PCI_DMA_FROMDEVICE);
  414. if (unlikely(dma_mapping_error(dma))) {
  415. dev_kfree_skb_irq(info->skb);
  416. break;
  417. }
  418. info->skb = skb;
  419. info->dma = dma;
  420. *buff = XCT_RXB_LEN(BUF_SIZE) | XCT_RXB_ADDR(dma);
  421. fill++;
  422. }
  423. wmb();
  424. write_dma_reg(PAS_DMA_RXINT_INCR(mac->dma_if), count);
  425. rx_ring(mac)->next_to_fill = (rx_ring(mac)->next_to_fill + count) &
  426. (RX_RING_SIZE - 1);
  427. }
  428. static void pasemi_mac_restart_rx_intr(const struct pasemi_mac *mac)
  429. {
  430. struct pasemi_mac_rxring *rx = rx_ring(mac);
  431. unsigned int reg, pcnt;
  432. /* Re-enable packet count interrupts: finally
  433. * ack the packet count interrupt we got in rx_intr.
  434. */
  435. pcnt = *rx->chan.status & PAS_STATUS_PCNT_M;
  436. reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC;
  437. if (*rx->chan.status & PAS_STATUS_TIMER)
  438. reg |= PAS_IOB_DMA_RXCH_RESET_TINTC;
  439. write_iob_reg(PAS_IOB_DMA_RXCH_RESET(mac->rx->chan.chno), reg);
  440. }
  441. static void pasemi_mac_restart_tx_intr(const struct pasemi_mac *mac)
  442. {
  443. unsigned int reg, pcnt;
  444. /* Re-enable packet count interrupts */
  445. pcnt = *tx_ring(mac)->chan.status & PAS_STATUS_PCNT_M;
  446. reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC;
  447. write_iob_reg(PAS_IOB_DMA_TXCH_RESET(tx_ring(mac)->chan.chno), reg);
  448. }
  449. static inline void pasemi_mac_rx_error(const struct pasemi_mac *mac,
  450. const u64 macrx)
  451. {
  452. unsigned int rcmdsta, ccmdsta;
  453. struct pasemi_dmachan *chan = &rx_ring(mac)->chan;
  454. if (!netif_msg_rx_err(mac))
  455. return;
  456. rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
  457. ccmdsta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(chan->chno));
  458. printk(KERN_ERR "pasemi_mac: rx error. macrx %016lx, rx status %lx\n",
  459. macrx, *chan->status);
  460. printk(KERN_ERR "pasemi_mac: rcmdsta %08x ccmdsta %08x\n",
  461. rcmdsta, ccmdsta);
  462. }
  463. static inline void pasemi_mac_tx_error(const struct pasemi_mac *mac,
  464. const u64 mactx)
  465. {
  466. unsigned int cmdsta;
  467. struct pasemi_dmachan *chan = &tx_ring(mac)->chan;
  468. if (!netif_msg_tx_err(mac))
  469. return;
  470. cmdsta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(chan->chno));
  471. printk(KERN_ERR "pasemi_mac: tx error. mactx 0x%016lx, "\
  472. "tx status 0x%016lx\n", mactx, *chan->status);
  473. printk(KERN_ERR "pasemi_mac: tcmdsta 0x%08x\n", cmdsta);
  474. }
  475. static int pasemi_mac_clean_rx(struct pasemi_mac_rxring *rx,
  476. const int limit)
  477. {
  478. const struct pasemi_dmachan *chan = &rx->chan;
  479. struct pasemi_mac *mac = rx->mac;
  480. struct pci_dev *pdev = mac->dma_pdev;
  481. unsigned int n;
  482. int count, buf_index, tot_bytes, packets;
  483. struct pasemi_mac_buffer *info;
  484. struct sk_buff *skb;
  485. unsigned int len;
  486. u64 macrx, eval;
  487. dma_addr_t dma;
  488. tot_bytes = 0;
  489. packets = 0;
  490. spin_lock(&rx->lock);
  491. n = rx->next_to_clean;
  492. prefetch(&RX_DESC(rx, n));
  493. for (count = 0; count < limit; count++) {
  494. macrx = RX_DESC(rx, n);
  495. prefetch(&RX_DESC(rx, n+4));
  496. if ((macrx & XCT_MACRX_E) ||
  497. (*chan->status & PAS_STATUS_ERROR))
  498. pasemi_mac_rx_error(mac, macrx);
  499. if (!(macrx & XCT_MACRX_O))
  500. break;
  501. info = NULL;
  502. BUG_ON(!(macrx & XCT_MACRX_RR_8BRES));
  503. eval = (RX_DESC(rx, n+1) & XCT_RXRES_8B_EVAL_M) >>
  504. XCT_RXRES_8B_EVAL_S;
  505. buf_index = eval-1;
  506. dma = (RX_DESC(rx, n+2) & XCT_PTR_ADDR_M);
  507. info = &RX_DESC_INFO(rx, buf_index);
  508. skb = info->skb;
  509. prefetch_skb(skb);
  510. len = (macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S;
  511. pci_unmap_single(pdev, dma, BUF_SIZE-LOCAL_SKB_ALIGN,
  512. PCI_DMA_FROMDEVICE);
  513. if (macrx & XCT_MACRX_CRC) {
  514. /* CRC error flagged */
  515. mac->netdev->stats.rx_errors++;
  516. mac->netdev->stats.rx_crc_errors++;
  517. /* No need to free skb, it'll be reused */
  518. goto next;
  519. }
  520. if (len < 256) {
  521. struct sk_buff *new_skb;
  522. new_skb = netdev_alloc_skb(mac->netdev,
  523. len + LOCAL_SKB_ALIGN);
  524. if (new_skb) {
  525. skb_reserve(new_skb, LOCAL_SKB_ALIGN);
  526. memcpy(new_skb->data, skb->data, len);
  527. /* save the skb in buffer_info as good */
  528. skb = new_skb;
  529. }
  530. /* else just continue with the old one */
  531. } else
  532. info->skb = NULL;
  533. info->dma = 0;
  534. if (likely((macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK)) {
  535. skb->ip_summed = CHECKSUM_UNNECESSARY;
  536. skb->csum = (macrx & XCT_MACRX_CSUM_M) >>
  537. XCT_MACRX_CSUM_S;
  538. } else
  539. skb->ip_summed = CHECKSUM_NONE;
  540. packets++;
  541. tot_bytes += len;
  542. /* Don't include CRC */
  543. skb_put(skb, len-4);
  544. skb->protocol = eth_type_trans(skb, mac->netdev);
  545. lro_receive_skb(&mac->lro_mgr, skb, (void *)macrx);
  546. next:
  547. RX_DESC(rx, n) = 0;
  548. RX_DESC(rx, n+1) = 0;
  549. /* Need to zero it out since hardware doesn't, since the
  550. * replenish loop uses it to tell when it's done.
  551. */
  552. RX_BUFF(rx, buf_index) = 0;
  553. n += 4;
  554. }
  555. if (n > RX_RING_SIZE) {
  556. /* Errata 5971 workaround: L2 target of headers */
  557. write_iob_reg(PAS_IOB_COM_PKTHDRCNT, 0);
  558. n &= (RX_RING_SIZE-1);
  559. }
  560. rx_ring(mac)->next_to_clean = n;
  561. lro_flush_all(&mac->lro_mgr);
  562. /* Increase is in number of 16-byte entries, and since each descriptor
  563. * with an 8BRES takes up 3x8 bytes (padded to 4x8), increase with
  564. * count*2.
  565. */
  566. write_dma_reg(PAS_DMA_RXCHAN_INCR(mac->rx->chan.chno), count << 1);
  567. pasemi_mac_replenish_rx_ring(mac->netdev, count);
  568. mac->netdev->stats.rx_bytes += tot_bytes;
  569. mac->netdev->stats.rx_packets += packets;
  570. spin_unlock(&rx_ring(mac)->lock);
  571. return count;
  572. }
  573. /* Can't make this too large or we blow the kernel stack limits */
  574. #define TX_CLEAN_BATCHSIZE (128/MAX_SKB_FRAGS)
  575. static int pasemi_mac_clean_tx(struct pasemi_mac_txring *txring)
  576. {
  577. struct pasemi_dmachan *chan = &txring->chan;
  578. struct pasemi_mac *mac = txring->mac;
  579. int i, j;
  580. unsigned int start, descr_count, buf_count, batch_limit;
  581. unsigned int ring_limit;
  582. unsigned int total_count;
  583. unsigned long flags;
  584. struct sk_buff *skbs[TX_CLEAN_BATCHSIZE];
  585. dma_addr_t dmas[TX_CLEAN_BATCHSIZE][MAX_SKB_FRAGS+1];
  586. int nf[TX_CLEAN_BATCHSIZE];
  587. int nr_frags;
  588. total_count = 0;
  589. batch_limit = TX_CLEAN_BATCHSIZE;
  590. restart:
  591. spin_lock_irqsave(&txring->lock, flags);
  592. start = txring->next_to_clean;
  593. ring_limit = txring->next_to_fill;
  594. prefetch(&TX_DESC_INFO(txring, start+1).skb);
  595. /* Compensate for when fill has wrapped but clean has not */
  596. if (start > ring_limit)
  597. ring_limit += TX_RING_SIZE;
  598. buf_count = 0;
  599. descr_count = 0;
  600. for (i = start;
  601. descr_count < batch_limit && i < ring_limit;
  602. i += buf_count) {
  603. u64 mactx = TX_DESC(txring, i);
  604. struct sk_buff *skb;
  605. skb = TX_DESC_INFO(txring, i+1).skb;
  606. nr_frags = TX_DESC_INFO(txring, i).dma;
  607. if ((mactx & XCT_MACTX_E) ||
  608. (*chan->status & PAS_STATUS_ERROR))
  609. pasemi_mac_tx_error(mac, mactx);
  610. if (unlikely(mactx & XCT_MACTX_O))
  611. /* Not yet transmitted */
  612. break;
  613. buf_count = 2 + nr_frags;
  614. /* Since we always fill with an even number of entries, make
  615. * sure we skip any unused one at the end as well.
  616. */
  617. if (buf_count & 1)
  618. buf_count++;
  619. for (j = 0; j <= nr_frags; j++)
  620. dmas[descr_count][j] = TX_DESC_INFO(txring, i+1+j).dma;
  621. skbs[descr_count] = skb;
  622. nf[descr_count] = nr_frags;
  623. TX_DESC(txring, i) = 0;
  624. TX_DESC(txring, i+1) = 0;
  625. descr_count++;
  626. }
  627. txring->next_to_clean = i & (TX_RING_SIZE-1);
  628. spin_unlock_irqrestore(&txring->lock, flags);
  629. netif_wake_queue(mac->netdev);
  630. for (i = 0; i < descr_count; i++)
  631. pasemi_mac_unmap_tx_skb(mac, nf[i], skbs[i], dmas[i]);
  632. total_count += descr_count;
  633. /* If the batch was full, try to clean more */
  634. if (descr_count == batch_limit)
  635. goto restart;
  636. return total_count;
  637. }
  638. static irqreturn_t pasemi_mac_rx_intr(int irq, void *data)
  639. {
  640. const struct pasemi_mac_rxring *rxring = data;
  641. struct pasemi_mac *mac = rxring->mac;
  642. struct net_device *dev = mac->netdev;
  643. const struct pasemi_dmachan *chan = &rxring->chan;
  644. unsigned int reg;
  645. if (!(*chan->status & PAS_STATUS_CAUSE_M))
  646. return IRQ_NONE;
  647. /* Don't reset packet count so it won't fire again but clear
  648. * all others.
  649. */
  650. reg = 0;
  651. if (*chan->status & PAS_STATUS_SOFT)
  652. reg |= PAS_IOB_DMA_RXCH_RESET_SINTC;
  653. if (*chan->status & PAS_STATUS_ERROR)
  654. reg |= PAS_IOB_DMA_RXCH_RESET_DINTC;
  655. netif_rx_schedule(dev, &mac->napi);
  656. write_iob_reg(PAS_IOB_DMA_RXCH_RESET(chan->chno), reg);
  657. return IRQ_HANDLED;
  658. }
  659. #define TX_CLEAN_INTERVAL HZ
  660. static void pasemi_mac_tx_timer(unsigned long data)
  661. {
  662. struct pasemi_mac_txring *txring = (struct pasemi_mac_txring *)data;
  663. struct pasemi_mac *mac = txring->mac;
  664. pasemi_mac_clean_tx(txring);
  665. mod_timer(&txring->clean_timer, jiffies + TX_CLEAN_INTERVAL);
  666. pasemi_mac_restart_tx_intr(mac);
  667. }
  668. static irqreturn_t pasemi_mac_tx_intr(int irq, void *data)
  669. {
  670. struct pasemi_mac_txring *txring = data;
  671. const struct pasemi_dmachan *chan = &txring->chan;
  672. struct pasemi_mac *mac = txring->mac;
  673. unsigned int reg;
  674. if (!(*chan->status & PAS_STATUS_CAUSE_M))
  675. return IRQ_NONE;
  676. reg = 0;
  677. if (*chan->status & PAS_STATUS_SOFT)
  678. reg |= PAS_IOB_DMA_TXCH_RESET_SINTC;
  679. if (*chan->status & PAS_STATUS_ERROR)
  680. reg |= PAS_IOB_DMA_TXCH_RESET_DINTC;
  681. mod_timer(&txring->clean_timer, jiffies + (TX_CLEAN_INTERVAL)*2);
  682. netif_rx_schedule(mac->netdev, &mac->napi);
  683. if (reg)
  684. write_iob_reg(PAS_IOB_DMA_TXCH_RESET(chan->chno), reg);
  685. return IRQ_HANDLED;
  686. }
  687. static void pasemi_adjust_link(struct net_device *dev)
  688. {
  689. struct pasemi_mac *mac = netdev_priv(dev);
  690. int msg;
  691. unsigned int flags;
  692. unsigned int new_flags;
  693. if (!mac->phydev->link) {
  694. /* If no link, MAC speed settings don't matter. Just report
  695. * link down and return.
  696. */
  697. if (mac->link && netif_msg_link(mac))
  698. printk(KERN_INFO "%s: Link is down.\n", dev->name);
  699. netif_carrier_off(dev);
  700. mac->link = 0;
  701. return;
  702. } else
  703. netif_carrier_on(dev);
  704. flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
  705. new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M |
  706. PAS_MAC_CFG_PCFG_TSR_M);
  707. if (!mac->phydev->duplex)
  708. new_flags |= PAS_MAC_CFG_PCFG_HD;
  709. switch (mac->phydev->speed) {
  710. case 1000:
  711. new_flags |= PAS_MAC_CFG_PCFG_SPD_1G |
  712. PAS_MAC_CFG_PCFG_TSR_1G;
  713. break;
  714. case 100:
  715. new_flags |= PAS_MAC_CFG_PCFG_SPD_100M |
  716. PAS_MAC_CFG_PCFG_TSR_100M;
  717. break;
  718. case 10:
  719. new_flags |= PAS_MAC_CFG_PCFG_SPD_10M |
  720. PAS_MAC_CFG_PCFG_TSR_10M;
  721. break;
  722. default:
  723. printk("Unsupported speed %d\n", mac->phydev->speed);
  724. }
  725. /* Print on link or speed/duplex change */
  726. msg = mac->link != mac->phydev->link || flags != new_flags;
  727. mac->duplex = mac->phydev->duplex;
  728. mac->speed = mac->phydev->speed;
  729. mac->link = mac->phydev->link;
  730. if (new_flags != flags)
  731. write_mac_reg(mac, PAS_MAC_CFG_PCFG, new_flags);
  732. if (msg && netif_msg_link(mac))
  733. printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n",
  734. dev->name, mac->speed, mac->duplex ? "full" : "half");
  735. }
  736. static int pasemi_mac_phy_init(struct net_device *dev)
  737. {
  738. struct pasemi_mac *mac = netdev_priv(dev);
  739. struct device_node *dn, *phy_dn;
  740. struct phy_device *phydev;
  741. unsigned int phy_id;
  742. const phandle *ph;
  743. const unsigned int *prop;
  744. struct resource r;
  745. int ret;
  746. dn = pci_device_to_OF_node(mac->pdev);
  747. ph = of_get_property(dn, "phy-handle", NULL);
  748. if (!ph)
  749. return -ENODEV;
  750. phy_dn = of_find_node_by_phandle(*ph);
  751. prop = of_get_property(phy_dn, "reg", NULL);
  752. ret = of_address_to_resource(phy_dn->parent, 0, &r);
  753. if (ret)
  754. goto err;
  755. phy_id = *prop;
  756. snprintf(mac->phy_id, BUS_ID_SIZE, PHY_ID_FMT, (int)r.start, phy_id);
  757. of_node_put(phy_dn);
  758. mac->link = 0;
  759. mac->speed = 0;
  760. mac->duplex = -1;
  761. phydev = phy_connect(dev, mac->phy_id, &pasemi_adjust_link, 0, PHY_INTERFACE_MODE_SGMII);
  762. if (IS_ERR(phydev)) {
  763. printk(KERN_ERR "%s: Could not attach to phy\n", dev->name);
  764. return PTR_ERR(phydev);
  765. }
  766. mac->phydev = phydev;
  767. return 0;
  768. err:
  769. of_node_put(phy_dn);
  770. return -ENODEV;
  771. }
  772. static int pasemi_mac_open(struct net_device *dev)
  773. {
  774. struct pasemi_mac *mac = netdev_priv(dev);
  775. unsigned int flags;
  776. int ret;
  777. /* enable rx section */
  778. write_dma_reg(PAS_DMA_COM_RXCMD, PAS_DMA_COM_RXCMD_EN);
  779. /* enable tx section */
  780. write_dma_reg(PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN);
  781. flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) |
  782. PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) |
  783. PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12);
  784. write_mac_reg(mac, PAS_MAC_CFG_TXP, flags);
  785. ret = pasemi_mac_setup_rx_resources(dev);
  786. if (ret)
  787. goto out_rx_resources;
  788. mac->tx = pasemi_mac_setup_tx_resources(dev);
  789. if (!mac->tx)
  790. goto out_tx_ring;
  791. /* 0x3ff with 33MHz clock is about 31us */
  792. write_iob_reg(PAS_IOB_DMA_COM_TIMEOUTCFG,
  793. PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0x3ff));
  794. write_iob_reg(PAS_IOB_DMA_RXCH_CFG(mac->rx->chan.chno),
  795. PAS_IOB_DMA_RXCH_CFG_CNTTH(256));
  796. write_iob_reg(PAS_IOB_DMA_TXCH_CFG(mac->tx->chan.chno),
  797. PAS_IOB_DMA_TXCH_CFG_CNTTH(32));
  798. write_mac_reg(mac, PAS_MAC_IPC_CHNL,
  799. PAS_MAC_IPC_CHNL_DCHNO(mac->rx->chan.chno) |
  800. PAS_MAC_IPC_CHNL_BCH(mac->rx->chan.chno));
  801. /* enable rx if */
  802. write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
  803. PAS_DMA_RXINT_RCMDSTA_EN |
  804. PAS_DMA_RXINT_RCMDSTA_DROPS_M |
  805. PAS_DMA_RXINT_RCMDSTA_BP |
  806. PAS_DMA_RXINT_RCMDSTA_OO |
  807. PAS_DMA_RXINT_RCMDSTA_BT);
  808. /* enable rx channel */
  809. pasemi_dma_start_chan(&rx_ring(mac)->chan, PAS_DMA_RXCHAN_CCMDSTA_DU |
  810. PAS_DMA_RXCHAN_CCMDSTA_OD |
  811. PAS_DMA_RXCHAN_CCMDSTA_FD |
  812. PAS_DMA_RXCHAN_CCMDSTA_DT);
  813. /* enable tx channel */
  814. pasemi_dma_start_chan(&tx_ring(mac)->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ |
  815. PAS_DMA_TXCHAN_TCMDSTA_DB |
  816. PAS_DMA_TXCHAN_TCMDSTA_DE |
  817. PAS_DMA_TXCHAN_TCMDSTA_DA);
  818. pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE);
  819. write_dma_reg(PAS_DMA_RXCHAN_INCR(rx_ring(mac)->chan.chno),
  820. RX_RING_SIZE>>1);
  821. /* Clear out any residual packet count state from firmware */
  822. pasemi_mac_restart_rx_intr(mac);
  823. pasemi_mac_restart_tx_intr(mac);
  824. flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PE |
  825. PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE;
  826. if (mac->type == MAC_TYPE_GMAC)
  827. flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G;
  828. else
  829. flags |= PAS_MAC_CFG_PCFG_TSR_10G | PAS_MAC_CFG_PCFG_SPD_10G;
  830. /* Enable interface in MAC */
  831. write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
  832. ret = pasemi_mac_phy_init(dev);
  833. /* Some configs don't have PHYs (XAUI etc), so don't complain about
  834. * failed init due to -ENODEV.
  835. */
  836. if (ret && ret != -ENODEV)
  837. dev_warn(&mac->pdev->dev, "phy init failed: %d\n", ret);
  838. netif_start_queue(dev);
  839. napi_enable(&mac->napi);
  840. snprintf(mac->tx_irq_name, sizeof(mac->tx_irq_name), "%s tx",
  841. dev->name);
  842. ret = request_irq(mac->tx->chan.irq, &pasemi_mac_tx_intr, IRQF_DISABLED,
  843. mac->tx_irq_name, mac->tx);
  844. if (ret) {
  845. dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
  846. mac->tx->chan.irq, ret);
  847. goto out_tx_int;
  848. }
  849. snprintf(mac->rx_irq_name, sizeof(mac->rx_irq_name), "%s rx",
  850. dev->name);
  851. ret = request_irq(mac->rx->chan.irq, &pasemi_mac_rx_intr, IRQF_DISABLED,
  852. mac->rx_irq_name, mac->rx);
  853. if (ret) {
  854. dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
  855. mac->rx->chan.irq, ret);
  856. goto out_rx_int;
  857. }
  858. if (mac->phydev)
  859. phy_start(mac->phydev);
  860. init_timer(&mac->tx->clean_timer);
  861. mac->tx->clean_timer.function = pasemi_mac_tx_timer;
  862. mac->tx->clean_timer.data = (unsigned long)mac->tx;
  863. mac->tx->clean_timer.expires = jiffies+HZ;
  864. add_timer(&mac->tx->clean_timer);
  865. return 0;
  866. out_rx_int:
  867. free_irq(mac->tx->chan.irq, mac->tx);
  868. out_tx_int:
  869. napi_disable(&mac->napi);
  870. netif_stop_queue(dev);
  871. out_tx_ring:
  872. if (mac->tx)
  873. pasemi_mac_free_tx_resources(mac);
  874. pasemi_mac_free_rx_resources(mac);
  875. out_rx_resources:
  876. return ret;
  877. }
  878. #define MAX_RETRIES 5000
  879. static int pasemi_mac_close(struct net_device *dev)
  880. {
  881. struct pasemi_mac *mac = netdev_priv(dev);
  882. unsigned int sta;
  883. int retries;
  884. int rxch, txch;
  885. rxch = rx_ring(mac)->chan.chno;
  886. txch = tx_ring(mac)->chan.chno;
  887. if (mac->phydev) {
  888. phy_stop(mac->phydev);
  889. phy_disconnect(mac->phydev);
  890. }
  891. del_timer_sync(&mac->tx->clean_timer);
  892. netif_stop_queue(dev);
  893. napi_disable(&mac->napi);
  894. sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
  895. if (sta & (PAS_DMA_RXINT_RCMDSTA_BP |
  896. PAS_DMA_RXINT_RCMDSTA_OO |
  897. PAS_DMA_RXINT_RCMDSTA_BT))
  898. printk(KERN_DEBUG "pasemi_mac: rcmdsta error: 0x%08x\n", sta);
  899. sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch));
  900. if (sta & (PAS_DMA_RXCHAN_CCMDSTA_DU |
  901. PAS_DMA_RXCHAN_CCMDSTA_OD |
  902. PAS_DMA_RXCHAN_CCMDSTA_FD |
  903. PAS_DMA_RXCHAN_CCMDSTA_DT))
  904. printk(KERN_DEBUG "pasemi_mac: ccmdsta error: 0x%08x\n", sta);
  905. sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch));
  906. if (sta & (PAS_DMA_TXCHAN_TCMDSTA_SZ | PAS_DMA_TXCHAN_TCMDSTA_DB |
  907. PAS_DMA_TXCHAN_TCMDSTA_DE | PAS_DMA_TXCHAN_TCMDSTA_DA))
  908. printk(KERN_DEBUG "pasemi_mac: tcmdsta error: 0x%08x\n", sta);
  909. /* Clean out any pending buffers */
  910. pasemi_mac_clean_tx(tx_ring(mac));
  911. pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE);
  912. /* Disable interface */
  913. write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch),
  914. PAS_DMA_TXCHAN_TCMDSTA_ST);
  915. write_dma_reg( PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
  916. PAS_DMA_RXINT_RCMDSTA_ST);
  917. write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch),
  918. PAS_DMA_RXCHAN_CCMDSTA_ST);
  919. for (retries = 0; retries < MAX_RETRIES; retries++) {
  920. sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(rxch));
  921. if (!(sta & PAS_DMA_TXCHAN_TCMDSTA_ACT))
  922. break;
  923. cond_resched();
  924. }
  925. if (sta & PAS_DMA_TXCHAN_TCMDSTA_ACT)
  926. dev_err(&mac->dma_pdev->dev, "Failed to stop tx channel\n");
  927. for (retries = 0; retries < MAX_RETRIES; retries++) {
  928. sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch));
  929. if (!(sta & PAS_DMA_RXCHAN_CCMDSTA_ACT))
  930. break;
  931. cond_resched();
  932. }
  933. if (sta & PAS_DMA_RXCHAN_CCMDSTA_ACT)
  934. dev_err(&mac->dma_pdev->dev, "Failed to stop rx channel\n");
  935. for (retries = 0; retries < MAX_RETRIES; retries++) {
  936. sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
  937. if (!(sta & PAS_DMA_RXINT_RCMDSTA_ACT))
  938. break;
  939. cond_resched();
  940. }
  941. if (sta & PAS_DMA_RXINT_RCMDSTA_ACT)
  942. dev_err(&mac->dma_pdev->dev, "Failed to stop rx interface\n");
  943. /* Then, disable the channel. This must be done separately from
  944. * stopping, since you can't disable when active.
  945. */
  946. write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch), 0);
  947. write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch), 0);
  948. write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0);
  949. free_irq(mac->tx->chan.irq, mac->tx);
  950. free_irq(mac->rx->chan.irq, mac->rx);
  951. /* Free resources */
  952. pasemi_mac_free_rx_resources(mac);
  953. pasemi_mac_free_tx_resources(mac);
  954. return 0;
  955. }
  956. static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev)
  957. {
  958. struct pasemi_mac *mac = netdev_priv(dev);
  959. struct pasemi_mac_txring *txring;
  960. u64 dflags, mactx;
  961. dma_addr_t map[MAX_SKB_FRAGS+1];
  962. unsigned int map_size[MAX_SKB_FRAGS+1];
  963. unsigned long flags;
  964. int i, nfrags;
  965. int fill;
  966. dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_CRC_PAD;
  967. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  968. const unsigned char *nh = skb_network_header(skb);
  969. switch (ip_hdr(skb)->protocol) {
  970. case IPPROTO_TCP:
  971. dflags |= XCT_MACTX_CSUM_TCP;
  972. dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
  973. dflags |= XCT_MACTX_IPO(nh - skb->data);
  974. break;
  975. case IPPROTO_UDP:
  976. dflags |= XCT_MACTX_CSUM_UDP;
  977. dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
  978. dflags |= XCT_MACTX_IPO(nh - skb->data);
  979. break;
  980. }
  981. }
  982. nfrags = skb_shinfo(skb)->nr_frags;
  983. map[0] = pci_map_single(mac->dma_pdev, skb->data, skb_headlen(skb),
  984. PCI_DMA_TODEVICE);
  985. map_size[0] = skb_headlen(skb);
  986. if (dma_mapping_error(map[0]))
  987. goto out_err_nolock;
  988. for (i = 0; i < nfrags; i++) {
  989. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  990. map[i+1] = pci_map_page(mac->dma_pdev, frag->page,
  991. frag->page_offset, frag->size,
  992. PCI_DMA_TODEVICE);
  993. map_size[i+1] = frag->size;
  994. if (dma_mapping_error(map[i+1])) {
  995. nfrags = i;
  996. goto out_err_nolock;
  997. }
  998. }
  999. mactx = dflags | XCT_MACTX_LLEN(skb->len);
  1000. txring = tx_ring(mac);
  1001. spin_lock_irqsave(&txring->lock, flags);
  1002. fill = txring->next_to_fill;
  1003. /* Avoid stepping on the same cache line that the DMA controller
  1004. * is currently about to send, so leave at least 8 words available.
  1005. * Total free space needed is mactx + fragments + 8
  1006. */
  1007. if (RING_AVAIL(txring) < nfrags + 10) {
  1008. /* no room -- stop the queue and wait for tx intr */
  1009. netif_stop_queue(dev);
  1010. goto out_err;
  1011. }
  1012. TX_DESC(txring, fill) = mactx;
  1013. TX_DESC_INFO(txring, fill).dma = nfrags;
  1014. fill++;
  1015. TX_DESC_INFO(txring, fill).skb = skb;
  1016. for (i = 0; i <= nfrags; i++) {
  1017. TX_DESC(txring, fill+i) =
  1018. XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]);
  1019. TX_DESC_INFO(txring, fill+i).dma = map[i];
  1020. }
  1021. /* We have to add an even number of 8-byte entries to the ring
  1022. * even if the last one is unused. That means always an odd number
  1023. * of pointers + one mactx descriptor.
  1024. */
  1025. if (nfrags & 1)
  1026. nfrags++;
  1027. txring->next_to_fill = (fill + nfrags + 1) & (TX_RING_SIZE-1);
  1028. dev->stats.tx_packets++;
  1029. dev->stats.tx_bytes += skb->len;
  1030. spin_unlock_irqrestore(&txring->lock, flags);
  1031. write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), (nfrags+2) >> 1);
  1032. return NETDEV_TX_OK;
  1033. out_err:
  1034. spin_unlock_irqrestore(&txring->lock, flags);
  1035. out_err_nolock:
  1036. while (nfrags--)
  1037. pci_unmap_single(mac->dma_pdev, map[nfrags], map_size[nfrags],
  1038. PCI_DMA_TODEVICE);
  1039. return NETDEV_TX_BUSY;
  1040. }
  1041. static void pasemi_mac_set_rx_mode(struct net_device *dev)
  1042. {
  1043. const struct pasemi_mac *mac = netdev_priv(dev);
  1044. unsigned int flags;
  1045. flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
  1046. /* Set promiscuous */
  1047. if (dev->flags & IFF_PROMISC)
  1048. flags |= PAS_MAC_CFG_PCFG_PR;
  1049. else
  1050. flags &= ~PAS_MAC_CFG_PCFG_PR;
  1051. write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
  1052. }
  1053. static int pasemi_mac_poll(struct napi_struct *napi, int budget)
  1054. {
  1055. struct pasemi_mac *mac = container_of(napi, struct pasemi_mac, napi);
  1056. struct net_device *dev = mac->netdev;
  1057. int pkts;
  1058. pasemi_mac_clean_tx(tx_ring(mac));
  1059. pkts = pasemi_mac_clean_rx(rx_ring(mac), budget);
  1060. if (pkts < budget) {
  1061. /* all done, no more packets present */
  1062. netif_rx_complete(dev, napi);
  1063. pasemi_mac_restart_rx_intr(mac);
  1064. pasemi_mac_restart_tx_intr(mac);
  1065. }
  1066. return pkts;
  1067. }
  1068. static int __devinit
  1069. pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  1070. {
  1071. struct net_device *dev;
  1072. struct pasemi_mac *mac;
  1073. int err;
  1074. DECLARE_MAC_BUF(mac_buf);
  1075. err = pci_enable_device(pdev);
  1076. if (err)
  1077. return err;
  1078. dev = alloc_etherdev(sizeof(struct pasemi_mac));
  1079. if (dev == NULL) {
  1080. dev_err(&pdev->dev,
  1081. "pasemi_mac: Could not allocate ethernet device.\n");
  1082. err = -ENOMEM;
  1083. goto out_disable_device;
  1084. }
  1085. pci_set_drvdata(pdev, dev);
  1086. SET_NETDEV_DEV(dev, &pdev->dev);
  1087. mac = netdev_priv(dev);
  1088. mac->pdev = pdev;
  1089. mac->netdev = dev;
  1090. netif_napi_add(dev, &mac->napi, pasemi_mac_poll, 64);
  1091. dev->features = NETIF_F_IP_CSUM | NETIF_F_LLTX | NETIF_F_SG |
  1092. NETIF_F_HIGHDMA;
  1093. mac->lro_mgr.max_aggr = LRO_MAX_AGGR;
  1094. mac->lro_mgr.max_desc = MAX_LRO_DESCRIPTORS;
  1095. mac->lro_mgr.lro_arr = mac->lro_desc;
  1096. mac->lro_mgr.get_skb_header = get_skb_hdr;
  1097. mac->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID;
  1098. mac->lro_mgr.dev = mac->netdev;
  1099. mac->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
  1100. mac->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
  1101. mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL);
  1102. if (!mac->dma_pdev) {
  1103. dev_err(&mac->pdev->dev, "Can't find DMA Controller\n");
  1104. err = -ENODEV;
  1105. goto out;
  1106. }
  1107. mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
  1108. if (!mac->iob_pdev) {
  1109. dev_err(&mac->pdev->dev, "Can't find I/O Bridge\n");
  1110. err = -ENODEV;
  1111. goto out;
  1112. }
  1113. /* get mac addr from device tree */
  1114. if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) {
  1115. err = -ENODEV;
  1116. goto out;
  1117. }
  1118. memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr));
  1119. mac->dma_if = mac_to_intf(mac);
  1120. if (mac->dma_if < 0) {
  1121. dev_err(&mac->pdev->dev, "Can't map DMA interface\n");
  1122. err = -ENODEV;
  1123. goto out;
  1124. }
  1125. switch (pdev->device) {
  1126. case 0xa005:
  1127. mac->type = MAC_TYPE_GMAC;
  1128. break;
  1129. case 0xa006:
  1130. mac->type = MAC_TYPE_XAUI;
  1131. break;
  1132. default:
  1133. err = -ENODEV;
  1134. goto out;
  1135. }
  1136. dev->open = pasemi_mac_open;
  1137. dev->stop = pasemi_mac_close;
  1138. dev->hard_start_xmit = pasemi_mac_start_tx;
  1139. dev->set_multicast_list = pasemi_mac_set_rx_mode;
  1140. if (err)
  1141. goto out;
  1142. mac->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
  1143. /* Enable most messages by default */
  1144. mac->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
  1145. err = register_netdev(dev);
  1146. if (err) {
  1147. dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n",
  1148. err);
  1149. goto out;
  1150. } else if netif_msg_probe(mac)
  1151. printk(KERN_INFO "%s: PA Semi %s: intf %d, hw addr %s\n",
  1152. dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI",
  1153. mac->dma_if, print_mac(mac_buf, dev->dev_addr));
  1154. return err;
  1155. out:
  1156. if (mac->iob_pdev)
  1157. pci_dev_put(mac->iob_pdev);
  1158. if (mac->dma_pdev)
  1159. pci_dev_put(mac->dma_pdev);
  1160. free_netdev(dev);
  1161. out_disable_device:
  1162. pci_disable_device(pdev);
  1163. return err;
  1164. }
  1165. static void __devexit pasemi_mac_remove(struct pci_dev *pdev)
  1166. {
  1167. struct net_device *netdev = pci_get_drvdata(pdev);
  1168. struct pasemi_mac *mac;
  1169. if (!netdev)
  1170. return;
  1171. mac = netdev_priv(netdev);
  1172. unregister_netdev(netdev);
  1173. pci_disable_device(pdev);
  1174. pci_dev_put(mac->dma_pdev);
  1175. pci_dev_put(mac->iob_pdev);
  1176. pasemi_dma_free_chan(&mac->tx->chan);
  1177. pasemi_dma_free_chan(&mac->rx->chan);
  1178. pci_set_drvdata(pdev, NULL);
  1179. free_netdev(netdev);
  1180. }
  1181. static struct pci_device_id pasemi_mac_pci_tbl[] = {
  1182. { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) },
  1183. { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) },
  1184. { },
  1185. };
  1186. MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl);
  1187. static struct pci_driver pasemi_mac_driver = {
  1188. .name = "pasemi_mac",
  1189. .id_table = pasemi_mac_pci_tbl,
  1190. .probe = pasemi_mac_probe,
  1191. .remove = __devexit_p(pasemi_mac_remove),
  1192. };
  1193. static void __exit pasemi_mac_cleanup_module(void)
  1194. {
  1195. pci_unregister_driver(&pasemi_mac_driver);
  1196. }
  1197. int pasemi_mac_init_module(void)
  1198. {
  1199. int err;
  1200. err = pasemi_dma_init();
  1201. if (err)
  1202. return err;
  1203. return pci_register_driver(&pasemi_mac_driver);
  1204. }
  1205. module_init(pasemi_mac_init_module);
  1206. module_exit(pasemi_mac_cleanup_module);