imx53.dtsi 8.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355
  1. /*
  2. * Copyright 2011 Freescale Semiconductor, Inc.
  3. * Copyright 2011 Linaro Ltd.
  4. *
  5. * The code contained herein is licensed under the GNU General Public
  6. * License. You may obtain a copy of the GNU General Public License
  7. * Version 2 or later at the following locations:
  8. *
  9. * http://www.opensource.org/licenses/gpl-license.html
  10. * http://www.gnu.org/copyleft/gpl.html
  11. */
  12. /include/ "skeleton.dtsi"
  13. / {
  14. aliases {
  15. serial0 = &uart1;
  16. serial1 = &uart2;
  17. serial2 = &uart3;
  18. serial3 = &uart4;
  19. serial4 = &uart5;
  20. gpio0 = &gpio1;
  21. gpio1 = &gpio2;
  22. gpio2 = &gpio3;
  23. gpio3 = &gpio4;
  24. gpio4 = &gpio5;
  25. gpio5 = &gpio6;
  26. gpio6 = &gpio7;
  27. };
  28. tzic: tz-interrupt-controller@0fffc000 {
  29. compatible = "fsl,imx53-tzic", "fsl,tzic";
  30. interrupt-controller;
  31. #interrupt-cells = <1>;
  32. reg = <0x0fffc000 0x4000>;
  33. };
  34. clocks {
  35. #address-cells = <1>;
  36. #size-cells = <0>;
  37. ckil {
  38. compatible = "fsl,imx-ckil", "fixed-clock";
  39. clock-frequency = <32768>;
  40. };
  41. ckih1 {
  42. compatible = "fsl,imx-ckih1", "fixed-clock";
  43. clock-frequency = <22579200>;
  44. };
  45. ckih2 {
  46. compatible = "fsl,imx-ckih2", "fixed-clock";
  47. clock-frequency = <0>;
  48. };
  49. osc {
  50. compatible = "fsl,imx-osc", "fixed-clock";
  51. clock-frequency = <24000000>;
  52. };
  53. };
  54. soc {
  55. #address-cells = <1>;
  56. #size-cells = <1>;
  57. compatible = "simple-bus";
  58. interrupt-parent = <&tzic>;
  59. ranges;
  60. aips@50000000 { /* AIPS1 */
  61. compatible = "fsl,aips-bus", "simple-bus";
  62. #address-cells = <1>;
  63. #size-cells = <1>;
  64. reg = <0x50000000 0x10000000>;
  65. ranges;
  66. spba@50000000 {
  67. compatible = "fsl,spba-bus", "simple-bus";
  68. #address-cells = <1>;
  69. #size-cells = <1>;
  70. reg = <0x50000000 0x40000>;
  71. ranges;
  72. esdhc@50004000 { /* ESDHC1 */
  73. compatible = "fsl,imx53-esdhc";
  74. reg = <0x50004000 0x4000>;
  75. interrupts = <1>;
  76. status = "disabled";
  77. };
  78. esdhc@50008000 { /* ESDHC2 */
  79. compatible = "fsl,imx53-esdhc";
  80. reg = <0x50008000 0x4000>;
  81. interrupts = <2>;
  82. status = "disabled";
  83. };
  84. uart3: serial@5000c000 {
  85. compatible = "fsl,imx53-uart", "fsl,imx21-uart";
  86. reg = <0x5000c000 0x4000>;
  87. interrupts = <33>;
  88. status = "disabled";
  89. };
  90. ecspi@50010000 { /* ECSPI1 */
  91. #address-cells = <1>;
  92. #size-cells = <0>;
  93. compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
  94. reg = <0x50010000 0x4000>;
  95. interrupts = <36>;
  96. status = "disabled";
  97. };
  98. ssi2: ssi@50014000 {
  99. compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
  100. reg = <0x50014000 0x4000>;
  101. interrupts = <30>;
  102. fsl,fifo-depth = <15>;
  103. fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
  104. status = "disabled";
  105. };
  106. esdhc@50020000 { /* ESDHC3 */
  107. compatible = "fsl,imx53-esdhc";
  108. reg = <0x50020000 0x4000>;
  109. interrupts = <3>;
  110. status = "disabled";
  111. };
  112. esdhc@50024000 { /* ESDHC4 */
  113. compatible = "fsl,imx53-esdhc";
  114. reg = <0x50024000 0x4000>;
  115. interrupts = <4>;
  116. status = "disabled";
  117. };
  118. };
  119. gpio1: gpio@53f84000 {
  120. compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
  121. reg = <0x53f84000 0x4000>;
  122. interrupts = <50 51>;
  123. gpio-controller;
  124. #gpio-cells = <2>;
  125. interrupt-controller;
  126. #interrupt-cells = <2>;
  127. };
  128. gpio2: gpio@53f88000 {
  129. compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
  130. reg = <0x53f88000 0x4000>;
  131. interrupts = <52 53>;
  132. gpio-controller;
  133. #gpio-cells = <2>;
  134. interrupt-controller;
  135. #interrupt-cells = <2>;
  136. };
  137. gpio3: gpio@53f8c000 {
  138. compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
  139. reg = <0x53f8c000 0x4000>;
  140. interrupts = <54 55>;
  141. gpio-controller;
  142. #gpio-cells = <2>;
  143. interrupt-controller;
  144. #interrupt-cells = <2>;
  145. };
  146. gpio4: gpio@53f90000 {
  147. compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
  148. reg = <0x53f90000 0x4000>;
  149. interrupts = <56 57>;
  150. gpio-controller;
  151. #gpio-cells = <2>;
  152. interrupt-controller;
  153. #interrupt-cells = <2>;
  154. };
  155. wdog@53f98000 { /* WDOG1 */
  156. compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
  157. reg = <0x53f98000 0x4000>;
  158. interrupts = <58>;
  159. };
  160. wdog@53f9c000 { /* WDOG2 */
  161. compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
  162. reg = <0x53f9c000 0x4000>;
  163. interrupts = <59>;
  164. status = "disabled";
  165. };
  166. uart1: serial@53fbc000 {
  167. compatible = "fsl,imx53-uart", "fsl,imx21-uart";
  168. reg = <0x53fbc000 0x4000>;
  169. interrupts = <31>;
  170. status = "disabled";
  171. };
  172. uart2: serial@53fc0000 {
  173. compatible = "fsl,imx53-uart", "fsl,imx21-uart";
  174. reg = <0x53fc0000 0x4000>;
  175. interrupts = <32>;
  176. status = "disabled";
  177. };
  178. can1: can@53fc8000 {
  179. compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
  180. reg = <0x53fc8000 0x4000>;
  181. interrupts = <82>;
  182. status = "disabled";
  183. };
  184. can2: can@53fcc000 {
  185. compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
  186. reg = <0x53fcc000 0x4000>;
  187. interrupts = <83>;
  188. status = "disabled";
  189. };
  190. gpio5: gpio@53fdc000 {
  191. compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
  192. reg = <0x53fdc000 0x4000>;
  193. interrupts = <103 104>;
  194. gpio-controller;
  195. #gpio-cells = <2>;
  196. interrupt-controller;
  197. #interrupt-cells = <2>;
  198. };
  199. gpio6: gpio@53fe0000 {
  200. compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
  201. reg = <0x53fe0000 0x4000>;
  202. interrupts = <105 106>;
  203. gpio-controller;
  204. #gpio-cells = <2>;
  205. interrupt-controller;
  206. #interrupt-cells = <2>;
  207. };
  208. gpio7: gpio@53fe4000 {
  209. compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
  210. reg = <0x53fe4000 0x4000>;
  211. interrupts = <107 108>;
  212. gpio-controller;
  213. #gpio-cells = <2>;
  214. interrupt-controller;
  215. #interrupt-cells = <2>;
  216. };
  217. i2c@53fec000 { /* I2C3 */
  218. #address-cells = <1>;
  219. #size-cells = <0>;
  220. compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
  221. reg = <0x53fec000 0x4000>;
  222. interrupts = <64>;
  223. status = "disabled";
  224. };
  225. uart4: serial@53ff0000 {
  226. compatible = "fsl,imx53-uart", "fsl,imx21-uart";
  227. reg = <0x53ff0000 0x4000>;
  228. interrupts = <13>;
  229. status = "disabled";
  230. };
  231. };
  232. aips@60000000 { /* AIPS2 */
  233. compatible = "fsl,aips-bus", "simple-bus";
  234. #address-cells = <1>;
  235. #size-cells = <1>;
  236. reg = <0x60000000 0x10000000>;
  237. ranges;
  238. uart5: serial@63f90000 {
  239. compatible = "fsl,imx53-uart", "fsl,imx21-uart";
  240. reg = <0x63f90000 0x4000>;
  241. interrupts = <86>;
  242. status = "disabled";
  243. };
  244. ecspi@63fac000 { /* ECSPI2 */
  245. #address-cells = <1>;
  246. #size-cells = <0>;
  247. compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
  248. reg = <0x63fac000 0x4000>;
  249. interrupts = <37>;
  250. status = "disabled";
  251. };
  252. sdma@63fb0000 {
  253. compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
  254. reg = <0x63fb0000 0x4000>;
  255. interrupts = <6>;
  256. fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
  257. };
  258. cspi@63fc0000 {
  259. #address-cells = <1>;
  260. #size-cells = <0>;
  261. compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
  262. reg = <0x63fc0000 0x4000>;
  263. interrupts = <38>;
  264. status = "disabled";
  265. };
  266. i2c@63fc4000 { /* I2C2 */
  267. #address-cells = <1>;
  268. #size-cells = <0>;
  269. compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
  270. reg = <0x63fc4000 0x4000>;
  271. interrupts = <63>;
  272. status = "disabled";
  273. };
  274. i2c@63fc8000 { /* I2C1 */
  275. #address-cells = <1>;
  276. #size-cells = <0>;
  277. compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
  278. reg = <0x63fc8000 0x4000>;
  279. interrupts = <62>;
  280. status = "disabled";
  281. };
  282. ssi1: ssi@63fcc000 {
  283. compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
  284. reg = <0x63fcc000 0x4000>;
  285. interrupts = <29>;
  286. fsl,fifo-depth = <15>;
  287. fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
  288. status = "disabled";
  289. };
  290. audmux@63fd0000 {
  291. compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
  292. reg = <0x63fd0000 0x4000>;
  293. status = "disabled";
  294. };
  295. ssi3: ssi@63fe8000 {
  296. compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
  297. reg = <0x63fe8000 0x4000>;
  298. interrupts = <96>;
  299. fsl,fifo-depth = <15>;
  300. fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
  301. status = "disabled";
  302. };
  303. ethernet@63fec000 {
  304. compatible = "fsl,imx53-fec", "fsl,imx25-fec";
  305. reg = <0x63fec000 0x4000>;
  306. interrupts = <87>;
  307. status = "disabled";
  308. };
  309. };
  310. };
  311. };