iwl-agn.c 108 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840
  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/sched.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/wireless.h>
  39. #include <linux/firmware.h>
  40. #include <linux/etherdevice.h>
  41. #include <linux/if_arp.h>
  42. #include <net/mac80211.h>
  43. #include <asm/div64.h>
  44. #define DRV_NAME "iwlagn"
  45. #include "iwl-eeprom.h"
  46. #include "iwl-dev.h"
  47. #include "iwl-core.h"
  48. #include "iwl-io.h"
  49. #include "iwl-helpers.h"
  50. #include "iwl-sta.h"
  51. #include "iwl-calib.h"
  52. #include "iwl-agn.h"
  53. /******************************************************************************
  54. *
  55. * module boiler plate
  56. *
  57. ******************************************************************************/
  58. /*
  59. * module name, copyright, version, etc.
  60. */
  61. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  62. #ifdef CONFIG_IWLWIFI_DEBUG
  63. #define VD "d"
  64. #else
  65. #define VD
  66. #endif
  67. #define DRV_VERSION IWLWIFI_VERSION VD
  68. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  69. MODULE_VERSION(DRV_VERSION);
  70. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  71. MODULE_LICENSE("GPL");
  72. MODULE_ALIAS("iwl4965");
  73. /*************** STATION TABLE MANAGEMENT ****
  74. * mac80211 should be examined to determine if sta_info is duplicating
  75. * the functionality provided here
  76. */
  77. /**************************************************************/
  78. /**
  79. * iwl_commit_rxon - commit staging_rxon to hardware
  80. *
  81. * The RXON command in staging_rxon is committed to the hardware and
  82. * the active_rxon structure is updated with the new data. This
  83. * function correctly transitions out of the RXON_ASSOC_MSK state if
  84. * a HW tune is required based on the RXON structure changes.
  85. */
  86. int iwl_commit_rxon(struct iwl_priv *priv)
  87. {
  88. /* cast away the const for active_rxon in this function */
  89. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  90. int ret;
  91. bool new_assoc =
  92. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  93. if (!iwl_is_alive(priv))
  94. return -EBUSY;
  95. /* always get timestamp with Rx frame */
  96. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  97. ret = iwl_check_rxon_cmd(priv);
  98. if (ret) {
  99. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  100. return -EINVAL;
  101. }
  102. /*
  103. * receive commit_rxon request
  104. * abort any previous channel switch if still in process
  105. */
  106. if (priv->switch_rxon.switch_in_progress &&
  107. (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
  108. IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
  109. le16_to_cpu(priv->switch_rxon.channel));
  110. priv->switch_rxon.switch_in_progress = false;
  111. }
  112. /* If we don't need to send a full RXON, we can use
  113. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  114. * and other flags for the current radio configuration. */
  115. if (!iwl_full_rxon_required(priv)) {
  116. ret = iwl_send_rxon_assoc(priv);
  117. if (ret) {
  118. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  119. return ret;
  120. }
  121. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  122. iwl_print_rx_config_cmd(priv);
  123. return 0;
  124. }
  125. /* station table will be cleared */
  126. priv->assoc_station_added = 0;
  127. /* If we are currently associated and the new config requires
  128. * an RXON_ASSOC and the new config wants the associated mask enabled,
  129. * we must clear the associated from the active configuration
  130. * before we apply the new config */
  131. if (iwl_is_associated(priv) && new_assoc) {
  132. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  133. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  134. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  135. sizeof(struct iwl_rxon_cmd),
  136. &priv->active_rxon);
  137. /* If the mask clearing failed then we set
  138. * active_rxon back to what it was previously */
  139. if (ret) {
  140. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  141. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  142. return ret;
  143. }
  144. iwl_clear_ucode_stations(priv, false);
  145. iwl_restore_stations(priv);
  146. }
  147. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  148. "* with%s RXON_FILTER_ASSOC_MSK\n"
  149. "* channel = %d\n"
  150. "* bssid = %pM\n",
  151. (new_assoc ? "" : "out"),
  152. le16_to_cpu(priv->staging_rxon.channel),
  153. priv->staging_rxon.bssid_addr);
  154. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  155. /* Apply the new configuration
  156. * RXON unassoc clears the station table in uCode so restoration of
  157. * stations is needed after it (the RXON command) completes
  158. */
  159. if (!new_assoc) {
  160. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  161. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  162. if (ret) {
  163. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  164. return ret;
  165. }
  166. IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON. \n");
  167. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  168. iwl_clear_ucode_stations(priv, false);
  169. iwl_restore_stations(priv);
  170. }
  171. priv->start_calib = 0;
  172. /* If we have set the ASSOC_MSK and we are in BSS mode then
  173. * add the IWL_AP_ID to the station rate table */
  174. if (new_assoc) {
  175. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  176. ret = iwl_rxon_add_station(priv,
  177. priv->active_rxon.bssid_addr, 1);
  178. if (ret == IWL_INVALID_STATION) {
  179. IWL_ERR(priv,
  180. "Error adding AP address for TX.\n");
  181. return -EIO;
  182. }
  183. priv->assoc_station_added = 1;
  184. if (priv->default_wep_key &&
  185. iwl_send_static_wepkey_cmd(priv, 0))
  186. IWL_ERR(priv,
  187. "Could not send WEP static key.\n");
  188. }
  189. /*
  190. * allow CTS-to-self if possible for new association.
  191. * this is relevant only for 5000 series and up,
  192. * but will not damage 4965
  193. */
  194. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  195. /* Apply the new configuration
  196. * RXON assoc doesn't clear the station table in uCode,
  197. */
  198. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  199. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  200. if (ret) {
  201. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  202. return ret;
  203. }
  204. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  205. }
  206. iwl_print_rx_config_cmd(priv);
  207. iwl_init_sensitivity(priv);
  208. /* If we issue a new RXON command which required a tune then we must
  209. * send a new TXPOWER command or we won't be able to Tx any frames */
  210. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  211. if (ret) {
  212. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  213. return ret;
  214. }
  215. return 0;
  216. }
  217. void iwl_update_chain_flags(struct iwl_priv *priv)
  218. {
  219. if (priv->cfg->ops->hcmd->set_rxon_chain)
  220. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  221. iwlcore_commit_rxon(priv);
  222. }
  223. static void iwl_clear_free_frames(struct iwl_priv *priv)
  224. {
  225. struct list_head *element;
  226. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  227. priv->frames_count);
  228. while (!list_empty(&priv->free_frames)) {
  229. element = priv->free_frames.next;
  230. list_del(element);
  231. kfree(list_entry(element, struct iwl_frame, list));
  232. priv->frames_count--;
  233. }
  234. if (priv->frames_count) {
  235. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  236. priv->frames_count);
  237. priv->frames_count = 0;
  238. }
  239. }
  240. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  241. {
  242. struct iwl_frame *frame;
  243. struct list_head *element;
  244. if (list_empty(&priv->free_frames)) {
  245. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  246. if (!frame) {
  247. IWL_ERR(priv, "Could not allocate frame!\n");
  248. return NULL;
  249. }
  250. priv->frames_count++;
  251. return frame;
  252. }
  253. element = priv->free_frames.next;
  254. list_del(element);
  255. return list_entry(element, struct iwl_frame, list);
  256. }
  257. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  258. {
  259. memset(frame, 0, sizeof(*frame));
  260. list_add(&frame->list, &priv->free_frames);
  261. }
  262. static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
  263. struct ieee80211_hdr *hdr,
  264. int left)
  265. {
  266. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  267. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  268. (priv->iw_mode != NL80211_IFTYPE_AP)))
  269. return 0;
  270. if (priv->ibss_beacon->len > left)
  271. return 0;
  272. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  273. return priv->ibss_beacon->len;
  274. }
  275. /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
  276. static void iwl_set_beacon_tim(struct iwl_priv *priv,
  277. struct iwl_tx_beacon_cmd *tx_beacon_cmd,
  278. u8 *beacon, u32 frame_size)
  279. {
  280. u16 tim_idx;
  281. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
  282. /*
  283. * The index is relative to frame start but we start looking at the
  284. * variable-length part of the beacon.
  285. */
  286. tim_idx = mgmt->u.beacon.variable - beacon;
  287. /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
  288. while ((tim_idx < (frame_size - 2)) &&
  289. (beacon[tim_idx] != WLAN_EID_TIM))
  290. tim_idx += beacon[tim_idx+1] + 2;
  291. /* If TIM field was found, set variables */
  292. if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
  293. tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
  294. tx_beacon_cmd->tim_size = beacon[tim_idx+1];
  295. } else
  296. IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
  297. }
  298. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  299. struct iwl_frame *frame)
  300. {
  301. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  302. u32 frame_size;
  303. u32 rate_flags;
  304. u32 rate;
  305. /*
  306. * We have to set up the TX command, the TX Beacon command, and the
  307. * beacon contents.
  308. */
  309. /* Initialize memory */
  310. tx_beacon_cmd = &frame->u.beacon;
  311. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  312. /* Set up TX beacon contents */
  313. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  314. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  315. if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
  316. return 0;
  317. /* Set up TX command fields */
  318. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  319. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  320. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  321. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  322. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
  323. /* Set up TX beacon command fields */
  324. iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
  325. frame_size);
  326. /* Set up packet rate and flags */
  327. rate = iwl_rate_get_lowest_plcp(priv);
  328. priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
  329. rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
  330. if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
  331. rate_flags |= RATE_MCS_CCK_MSK;
  332. tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
  333. rate_flags);
  334. return sizeof(*tx_beacon_cmd) + frame_size;
  335. }
  336. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  337. {
  338. struct iwl_frame *frame;
  339. unsigned int frame_size;
  340. int rc;
  341. frame = iwl_get_free_frame(priv);
  342. if (!frame) {
  343. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  344. "command.\n");
  345. return -ENOMEM;
  346. }
  347. frame_size = iwl_hw_get_beacon_cmd(priv, frame);
  348. if (!frame_size) {
  349. IWL_ERR(priv, "Error configuring the beacon command\n");
  350. iwl_free_frame(priv, frame);
  351. return -EINVAL;
  352. }
  353. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  354. &frame->u.cmd[0]);
  355. iwl_free_frame(priv, frame);
  356. return rc;
  357. }
  358. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  359. {
  360. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  361. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  362. if (sizeof(dma_addr_t) > sizeof(u32))
  363. addr |=
  364. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  365. return addr;
  366. }
  367. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  368. {
  369. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  370. return le16_to_cpu(tb->hi_n_len) >> 4;
  371. }
  372. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  373. dma_addr_t addr, u16 len)
  374. {
  375. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  376. u16 hi_n_len = len << 4;
  377. put_unaligned_le32(addr, &tb->lo);
  378. if (sizeof(dma_addr_t) > sizeof(u32))
  379. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  380. tb->hi_n_len = cpu_to_le16(hi_n_len);
  381. tfd->num_tbs = idx + 1;
  382. }
  383. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  384. {
  385. return tfd->num_tbs & 0x1f;
  386. }
  387. /**
  388. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  389. * @priv - driver private data
  390. * @txq - tx queue
  391. *
  392. * Does NOT advance any TFD circular buffer read/write indexes
  393. * Does NOT free the TFD itself (which is within circular buffer)
  394. */
  395. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  396. {
  397. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  398. struct iwl_tfd *tfd;
  399. struct pci_dev *dev = priv->pci_dev;
  400. int index = txq->q.read_ptr;
  401. int i;
  402. int num_tbs;
  403. tfd = &tfd_tmp[index];
  404. /* Sanity check on number of chunks */
  405. num_tbs = iwl_tfd_get_num_tbs(tfd);
  406. if (num_tbs >= IWL_NUM_OF_TBS) {
  407. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  408. /* @todo issue fatal error, it is quite serious situation */
  409. return;
  410. }
  411. /* Unmap tx_cmd */
  412. if (num_tbs)
  413. pci_unmap_single(dev,
  414. pci_unmap_addr(&txq->meta[index], mapping),
  415. pci_unmap_len(&txq->meta[index], len),
  416. PCI_DMA_BIDIRECTIONAL);
  417. /* Unmap chunks, if any. */
  418. for (i = 1; i < num_tbs; i++) {
  419. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  420. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  421. if (txq->txb) {
  422. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  423. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  424. }
  425. }
  426. }
  427. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  428. struct iwl_tx_queue *txq,
  429. dma_addr_t addr, u16 len,
  430. u8 reset, u8 pad)
  431. {
  432. struct iwl_queue *q;
  433. struct iwl_tfd *tfd, *tfd_tmp;
  434. u32 num_tbs;
  435. q = &txq->q;
  436. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  437. tfd = &tfd_tmp[q->write_ptr];
  438. if (reset)
  439. memset(tfd, 0, sizeof(*tfd));
  440. num_tbs = iwl_tfd_get_num_tbs(tfd);
  441. /* Each TFD can point to a maximum 20 Tx buffers */
  442. if (num_tbs >= IWL_NUM_OF_TBS) {
  443. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  444. IWL_NUM_OF_TBS);
  445. return -EINVAL;
  446. }
  447. BUG_ON(addr & ~DMA_BIT_MASK(36));
  448. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  449. IWL_ERR(priv, "Unaligned address = %llx\n",
  450. (unsigned long long)addr);
  451. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  452. return 0;
  453. }
  454. /*
  455. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  456. * given Tx queue, and enable the DMA channel used for that queue.
  457. *
  458. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  459. * channels supported in hardware.
  460. */
  461. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  462. struct iwl_tx_queue *txq)
  463. {
  464. int txq_id = txq->q.id;
  465. /* Circular buffer (TFD queue in DRAM) physical base address */
  466. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  467. txq->q.dma_addr >> 8);
  468. return 0;
  469. }
  470. /******************************************************************************
  471. *
  472. * Generic RX handler implementations
  473. *
  474. ******************************************************************************/
  475. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  476. struct iwl_rx_mem_buffer *rxb)
  477. {
  478. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  479. struct iwl_alive_resp *palive;
  480. struct delayed_work *pwork;
  481. palive = &pkt->u.alive_frame;
  482. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  483. "0x%01X 0x%01X\n",
  484. palive->is_valid, palive->ver_type,
  485. palive->ver_subtype);
  486. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  487. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  488. memcpy(&priv->card_alive_init,
  489. &pkt->u.alive_frame,
  490. sizeof(struct iwl_init_alive_resp));
  491. pwork = &priv->init_alive_start;
  492. } else {
  493. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  494. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  495. sizeof(struct iwl_alive_resp));
  496. pwork = &priv->alive_start;
  497. }
  498. /* We delay the ALIVE response by 5ms to
  499. * give the HW RF Kill time to activate... */
  500. if (palive->is_valid == UCODE_VALID_OK)
  501. queue_delayed_work(priv->workqueue, pwork,
  502. msecs_to_jiffies(5));
  503. else
  504. IWL_WARN(priv, "uCode did not respond OK.\n");
  505. }
  506. static void iwl_bg_beacon_update(struct work_struct *work)
  507. {
  508. struct iwl_priv *priv =
  509. container_of(work, struct iwl_priv, beacon_update);
  510. struct sk_buff *beacon;
  511. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  512. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  513. if (!beacon) {
  514. IWL_ERR(priv, "update beacon failed\n");
  515. return;
  516. }
  517. mutex_lock(&priv->mutex);
  518. /* new beacon skb is allocated every time; dispose previous.*/
  519. if (priv->ibss_beacon)
  520. dev_kfree_skb(priv->ibss_beacon);
  521. priv->ibss_beacon = beacon;
  522. mutex_unlock(&priv->mutex);
  523. iwl_send_beacon_cmd(priv);
  524. }
  525. /**
  526. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  527. *
  528. * This callback is provided in order to send a statistics request.
  529. *
  530. * This timer function is continually reset to execute within
  531. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  532. * was received. We need to ensure we receive the statistics in order
  533. * to update the temperature used for calibrating the TXPOWER.
  534. */
  535. static void iwl_bg_statistics_periodic(unsigned long data)
  536. {
  537. struct iwl_priv *priv = (struct iwl_priv *)data;
  538. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  539. return;
  540. /* dont send host command if rf-kill is on */
  541. if (!iwl_is_ready_rf(priv))
  542. return;
  543. iwl_send_statistics_request(priv, CMD_ASYNC, false);
  544. }
  545. static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
  546. u32 start_idx, u32 num_events,
  547. u32 mode)
  548. {
  549. u32 i;
  550. u32 ptr; /* SRAM byte address of log data */
  551. u32 ev, time, data; /* event log data */
  552. unsigned long reg_flags;
  553. if (mode == 0)
  554. ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
  555. else
  556. ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
  557. /* Make sure device is powered up for SRAM reads */
  558. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  559. if (iwl_grab_nic_access(priv)) {
  560. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  561. return;
  562. }
  563. /* Set starting address; reads will auto-increment */
  564. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  565. rmb();
  566. /*
  567. * "time" is actually "data" for mode 0 (no timestamp).
  568. * place event id # at far right for easier visual parsing.
  569. */
  570. for (i = 0; i < num_events; i++) {
  571. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  572. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  573. if (mode == 0) {
  574. trace_iwlwifi_dev_ucode_cont_event(priv,
  575. 0, time, ev);
  576. } else {
  577. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  578. trace_iwlwifi_dev_ucode_cont_event(priv,
  579. time, data, ev);
  580. }
  581. }
  582. /* Allow device to power down */
  583. iwl_release_nic_access(priv);
  584. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  585. }
  586. static void iwl_continuous_event_trace(struct iwl_priv *priv)
  587. {
  588. u32 capacity; /* event log capacity in # entries */
  589. u32 base; /* SRAM byte address of event log header */
  590. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  591. u32 num_wraps; /* # times uCode wrapped to top of log */
  592. u32 next_entry; /* index of next entry to be written by uCode */
  593. if (priv->ucode_type == UCODE_INIT)
  594. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  595. else
  596. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  597. if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  598. capacity = iwl_read_targ_mem(priv, base);
  599. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  600. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  601. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  602. } else
  603. return;
  604. if (num_wraps == priv->event_log.num_wraps) {
  605. iwl_print_cont_event_trace(priv,
  606. base, priv->event_log.next_entry,
  607. next_entry - priv->event_log.next_entry,
  608. mode);
  609. priv->event_log.non_wraps_count++;
  610. } else {
  611. if ((num_wraps - priv->event_log.num_wraps) > 1)
  612. priv->event_log.wraps_more_count++;
  613. else
  614. priv->event_log.wraps_once_count++;
  615. trace_iwlwifi_dev_ucode_wrap_event(priv,
  616. num_wraps - priv->event_log.num_wraps,
  617. next_entry, priv->event_log.next_entry);
  618. if (next_entry < priv->event_log.next_entry) {
  619. iwl_print_cont_event_trace(priv, base,
  620. priv->event_log.next_entry,
  621. capacity - priv->event_log.next_entry,
  622. mode);
  623. iwl_print_cont_event_trace(priv, base, 0,
  624. next_entry, mode);
  625. } else {
  626. iwl_print_cont_event_trace(priv, base,
  627. next_entry, capacity - next_entry,
  628. mode);
  629. iwl_print_cont_event_trace(priv, base, 0,
  630. next_entry, mode);
  631. }
  632. }
  633. priv->event_log.num_wraps = num_wraps;
  634. priv->event_log.next_entry = next_entry;
  635. }
  636. /**
  637. * iwl_bg_ucode_trace - Timer callback to log ucode event
  638. *
  639. * The timer is continually set to execute every
  640. * UCODE_TRACE_PERIOD milliseconds after the last timer expired
  641. * this function is to perform continuous uCode event logging operation
  642. * if enabled
  643. */
  644. static void iwl_bg_ucode_trace(unsigned long data)
  645. {
  646. struct iwl_priv *priv = (struct iwl_priv *)data;
  647. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  648. return;
  649. if (priv->event_log.ucode_trace) {
  650. iwl_continuous_event_trace(priv);
  651. /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
  652. mod_timer(&priv->ucode_trace,
  653. jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
  654. }
  655. }
  656. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  657. struct iwl_rx_mem_buffer *rxb)
  658. {
  659. #ifdef CONFIG_IWLWIFI_DEBUG
  660. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  661. struct iwl4965_beacon_notif *beacon =
  662. (struct iwl4965_beacon_notif *)pkt->u.raw;
  663. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  664. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  665. "tsf %d %d rate %d\n",
  666. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  667. beacon->beacon_notify_hdr.failure_frame,
  668. le32_to_cpu(beacon->ibss_mgr_status),
  669. le32_to_cpu(beacon->high_tsf),
  670. le32_to_cpu(beacon->low_tsf), rate);
  671. #endif
  672. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  673. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  674. queue_work(priv->workqueue, &priv->beacon_update);
  675. }
  676. /* Handle notification from uCode that card's power state is changing
  677. * due to software, hardware, or critical temperature RFKILL */
  678. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  679. struct iwl_rx_mem_buffer *rxb)
  680. {
  681. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  682. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  683. unsigned long status = priv->status;
  684. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
  685. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  686. (flags & SW_CARD_DISABLED) ? "Kill" : "On",
  687. (flags & CT_CARD_DISABLED) ?
  688. "Reached" : "Not reached");
  689. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  690. CT_CARD_DISABLED)) {
  691. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  692. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  693. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  694. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  695. if (!(flags & RXON_CARD_DISABLED)) {
  696. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  697. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  698. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  699. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  700. }
  701. if (flags & CT_CARD_DISABLED)
  702. iwl_tt_enter_ct_kill(priv);
  703. }
  704. if (!(flags & CT_CARD_DISABLED))
  705. iwl_tt_exit_ct_kill(priv);
  706. if (flags & HW_CARD_DISABLED)
  707. set_bit(STATUS_RF_KILL_HW, &priv->status);
  708. else
  709. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  710. if (!(flags & RXON_CARD_DISABLED))
  711. iwl_scan_cancel(priv);
  712. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  713. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  714. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  715. test_bit(STATUS_RF_KILL_HW, &priv->status));
  716. else
  717. wake_up_interruptible(&priv->wait_command_queue);
  718. }
  719. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  720. {
  721. if (src == IWL_PWR_SRC_VAUX) {
  722. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  723. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  724. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  725. ~APMG_PS_CTRL_MSK_PWR_SRC);
  726. } else {
  727. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  728. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  729. ~APMG_PS_CTRL_MSK_PWR_SRC);
  730. }
  731. return 0;
  732. }
  733. /**
  734. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  735. *
  736. * Setup the RX handlers for each of the reply types sent from the uCode
  737. * to the host.
  738. *
  739. * This function chains into the hardware specific files for them to setup
  740. * any hardware specific handlers as well.
  741. */
  742. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  743. {
  744. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  745. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  746. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  747. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  748. iwl_rx_spectrum_measure_notif;
  749. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  750. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  751. iwl_rx_pm_debug_statistics_notif;
  752. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  753. /*
  754. * The same handler is used for both the REPLY to a discrete
  755. * statistics request from the host as well as for the periodic
  756. * statistics notifications (after received beacons) from the uCode.
  757. */
  758. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
  759. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  760. iwl_setup_rx_scan_handlers(priv);
  761. /* status change handler */
  762. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  763. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  764. iwl_rx_missed_beacon_notif;
  765. /* Rx handlers */
  766. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
  767. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
  768. /* block ack */
  769. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
  770. /* Set up hardware specific Rx handlers */
  771. priv->cfg->ops->lib->rx_handler_setup(priv);
  772. }
  773. /**
  774. * iwl_rx_handle - Main entry function for receiving responses from uCode
  775. *
  776. * Uses the priv->rx_handlers callback function array to invoke
  777. * the appropriate handlers, including command responses,
  778. * frame-received notifications, and other notifications.
  779. */
  780. void iwl_rx_handle(struct iwl_priv *priv)
  781. {
  782. struct iwl_rx_mem_buffer *rxb;
  783. struct iwl_rx_packet *pkt;
  784. struct iwl_rx_queue *rxq = &priv->rxq;
  785. u32 r, i;
  786. int reclaim;
  787. unsigned long flags;
  788. u8 fill_rx = 0;
  789. u32 count = 8;
  790. int total_empty;
  791. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  792. * buffer that the driver may process (last buffer filled by ucode). */
  793. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  794. i = rxq->read;
  795. /* Rx interrupt, but nothing sent from uCode */
  796. if (i == r)
  797. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  798. /* calculate total frames need to be restock after handling RX */
  799. total_empty = r - rxq->write_actual;
  800. if (total_empty < 0)
  801. total_empty += RX_QUEUE_SIZE;
  802. if (total_empty > (RX_QUEUE_SIZE / 2))
  803. fill_rx = 1;
  804. while (i != r) {
  805. rxb = rxq->queue[i];
  806. /* If an RXB doesn't have a Rx queue slot associated with it,
  807. * then a bug has been introduced in the queue refilling
  808. * routines -- catch it here */
  809. BUG_ON(rxb == NULL);
  810. rxq->queue[i] = NULL;
  811. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  812. PAGE_SIZE << priv->hw_params.rx_page_order,
  813. PCI_DMA_FROMDEVICE);
  814. pkt = rxb_addr(rxb);
  815. trace_iwlwifi_dev_rx(priv, pkt,
  816. le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
  817. /* Reclaim a command buffer only if this packet is a response
  818. * to a (driver-originated) command.
  819. * If the packet (e.g. Rx frame) originated from uCode,
  820. * there is no command buffer to reclaim.
  821. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  822. * but apparently a few don't get set; catch them here. */
  823. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  824. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  825. (pkt->hdr.cmd != REPLY_RX) &&
  826. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  827. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  828. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  829. (pkt->hdr.cmd != REPLY_TX);
  830. /* Based on type of command response or notification,
  831. * handle those that need handling via function in
  832. * rx_handlers table. See iwl_setup_rx_handlers() */
  833. if (priv->rx_handlers[pkt->hdr.cmd]) {
  834. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  835. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  836. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  837. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  838. } else {
  839. /* No handling needed */
  840. IWL_DEBUG_RX(priv,
  841. "r %d i %d No handler needed for %s, 0x%02x\n",
  842. r, i, get_cmd_string(pkt->hdr.cmd),
  843. pkt->hdr.cmd);
  844. }
  845. /*
  846. * XXX: After here, we should always check rxb->page
  847. * against NULL before touching it or its virtual
  848. * memory (pkt). Because some rx_handler might have
  849. * already taken or freed the pages.
  850. */
  851. if (reclaim) {
  852. /* Invoke any callbacks, transfer the buffer to caller,
  853. * and fire off the (possibly) blocking iwl_send_cmd()
  854. * as we reclaim the driver command queue */
  855. if (rxb->page)
  856. iwl_tx_cmd_complete(priv, rxb);
  857. else
  858. IWL_WARN(priv, "Claim null rxb?\n");
  859. }
  860. /* Reuse the page if possible. For notification packets and
  861. * SKBs that fail to Rx correctly, add them back into the
  862. * rx_free list for reuse later. */
  863. spin_lock_irqsave(&rxq->lock, flags);
  864. if (rxb->page != NULL) {
  865. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  866. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  867. PCI_DMA_FROMDEVICE);
  868. list_add_tail(&rxb->list, &rxq->rx_free);
  869. rxq->free_count++;
  870. } else
  871. list_add_tail(&rxb->list, &rxq->rx_used);
  872. spin_unlock_irqrestore(&rxq->lock, flags);
  873. i = (i + 1) & RX_QUEUE_MASK;
  874. /* If there are a lot of unused frames,
  875. * restock the Rx queue so ucode wont assert. */
  876. if (fill_rx) {
  877. count++;
  878. if (count >= 8) {
  879. rxq->read = i;
  880. iwl_rx_replenish_now(priv);
  881. count = 0;
  882. }
  883. }
  884. }
  885. /* Backtrack one entry */
  886. rxq->read = i;
  887. if (fill_rx)
  888. iwl_rx_replenish_now(priv);
  889. else
  890. iwl_rx_queue_restock(priv);
  891. }
  892. /* call this function to flush any scheduled tasklet */
  893. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  894. {
  895. /* wait to make sure we flush pending tasklet*/
  896. synchronize_irq(priv->pci_dev->irq);
  897. tasklet_kill(&priv->irq_tasklet);
  898. }
  899. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  900. {
  901. u32 inta, handled = 0;
  902. u32 inta_fh;
  903. unsigned long flags;
  904. u32 i;
  905. #ifdef CONFIG_IWLWIFI_DEBUG
  906. u32 inta_mask;
  907. #endif
  908. spin_lock_irqsave(&priv->lock, flags);
  909. /* Ack/clear/reset pending uCode interrupts.
  910. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  911. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  912. inta = iwl_read32(priv, CSR_INT);
  913. iwl_write32(priv, CSR_INT, inta);
  914. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  915. * Any new interrupts that happen after this, either while we're
  916. * in this tasklet, or later, will show up in next ISR/tasklet. */
  917. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  918. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  919. #ifdef CONFIG_IWLWIFI_DEBUG
  920. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  921. /* just for debug */
  922. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  923. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  924. inta, inta_mask, inta_fh);
  925. }
  926. #endif
  927. spin_unlock_irqrestore(&priv->lock, flags);
  928. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  929. * atomic, make sure that inta covers all the interrupts that
  930. * we've discovered, even if FH interrupt came in just after
  931. * reading CSR_INT. */
  932. if (inta_fh & CSR49_FH_INT_RX_MASK)
  933. inta |= CSR_INT_BIT_FH_RX;
  934. if (inta_fh & CSR49_FH_INT_TX_MASK)
  935. inta |= CSR_INT_BIT_FH_TX;
  936. /* Now service all interrupt bits discovered above. */
  937. if (inta & CSR_INT_BIT_HW_ERR) {
  938. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  939. /* Tell the device to stop sending interrupts */
  940. iwl_disable_interrupts(priv);
  941. priv->isr_stats.hw++;
  942. iwl_irq_handle_error(priv);
  943. handled |= CSR_INT_BIT_HW_ERR;
  944. return;
  945. }
  946. #ifdef CONFIG_IWLWIFI_DEBUG
  947. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  948. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  949. if (inta & CSR_INT_BIT_SCD) {
  950. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  951. "the frame/frames.\n");
  952. priv->isr_stats.sch++;
  953. }
  954. /* Alive notification via Rx interrupt will do the real work */
  955. if (inta & CSR_INT_BIT_ALIVE) {
  956. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  957. priv->isr_stats.alive++;
  958. }
  959. }
  960. #endif
  961. /* Safely ignore these bits for debug checks below */
  962. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  963. /* HW RF KILL switch toggled */
  964. if (inta & CSR_INT_BIT_RF_KILL) {
  965. int hw_rf_kill = 0;
  966. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  967. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  968. hw_rf_kill = 1;
  969. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  970. hw_rf_kill ? "disable radio" : "enable radio");
  971. priv->isr_stats.rfkill++;
  972. /* driver only loads ucode once setting the interface up.
  973. * the driver allows loading the ucode even if the radio
  974. * is killed. Hence update the killswitch state here. The
  975. * rfkill handler will care about restarting if needed.
  976. */
  977. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  978. if (hw_rf_kill)
  979. set_bit(STATUS_RF_KILL_HW, &priv->status);
  980. else
  981. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  982. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  983. }
  984. handled |= CSR_INT_BIT_RF_KILL;
  985. }
  986. /* Chip got too hot and stopped itself */
  987. if (inta & CSR_INT_BIT_CT_KILL) {
  988. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  989. priv->isr_stats.ctkill++;
  990. handled |= CSR_INT_BIT_CT_KILL;
  991. }
  992. /* Error detected by uCode */
  993. if (inta & CSR_INT_BIT_SW_ERR) {
  994. IWL_ERR(priv, "Microcode SW error detected. "
  995. " Restarting 0x%X.\n", inta);
  996. priv->isr_stats.sw++;
  997. priv->isr_stats.sw_err = inta;
  998. iwl_irq_handle_error(priv);
  999. handled |= CSR_INT_BIT_SW_ERR;
  1000. }
  1001. /*
  1002. * uCode wakes up after power-down sleep.
  1003. * Tell device about any new tx or host commands enqueued,
  1004. * and about any Rx buffers made available while asleep.
  1005. */
  1006. if (inta & CSR_INT_BIT_WAKEUP) {
  1007. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1008. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1009. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  1010. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  1011. priv->isr_stats.wakeup++;
  1012. handled |= CSR_INT_BIT_WAKEUP;
  1013. }
  1014. /* All uCode command responses, including Tx command responses,
  1015. * Rx "responses" (frame-received notification), and other
  1016. * notifications from uCode come through here*/
  1017. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1018. iwl_rx_handle(priv);
  1019. priv->isr_stats.rx++;
  1020. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1021. }
  1022. /* This "Tx" DMA channel is used only for loading uCode */
  1023. if (inta & CSR_INT_BIT_FH_TX) {
  1024. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1025. priv->isr_stats.tx++;
  1026. handled |= CSR_INT_BIT_FH_TX;
  1027. /* Wake up uCode load routine, now that load is complete */
  1028. priv->ucode_write_complete = 1;
  1029. wake_up_interruptible(&priv->wait_command_queue);
  1030. }
  1031. if (inta & ~handled) {
  1032. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1033. priv->isr_stats.unhandled++;
  1034. }
  1035. if (inta & ~(priv->inta_mask)) {
  1036. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1037. inta & ~priv->inta_mask);
  1038. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  1039. }
  1040. /* Re-enable all interrupts */
  1041. /* only Re-enable if diabled by irq */
  1042. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1043. iwl_enable_interrupts(priv);
  1044. #ifdef CONFIG_IWLWIFI_DEBUG
  1045. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1046. inta = iwl_read32(priv, CSR_INT);
  1047. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1048. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1049. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  1050. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  1051. }
  1052. #endif
  1053. }
  1054. /* tasklet for iwlagn interrupt */
  1055. static void iwl_irq_tasklet(struct iwl_priv *priv)
  1056. {
  1057. u32 inta = 0;
  1058. u32 handled = 0;
  1059. unsigned long flags;
  1060. u32 i;
  1061. #ifdef CONFIG_IWLWIFI_DEBUG
  1062. u32 inta_mask;
  1063. #endif
  1064. spin_lock_irqsave(&priv->lock, flags);
  1065. /* Ack/clear/reset pending uCode interrupts.
  1066. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  1067. */
  1068. iwl_write32(priv, CSR_INT, priv->_agn.inta);
  1069. inta = priv->_agn.inta;
  1070. #ifdef CONFIG_IWLWIFI_DEBUG
  1071. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  1072. /* just for debug */
  1073. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1074. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  1075. inta, inta_mask);
  1076. }
  1077. #endif
  1078. spin_unlock_irqrestore(&priv->lock, flags);
  1079. /* saved interrupt in inta variable now we can reset priv->_agn.inta */
  1080. priv->_agn.inta = 0;
  1081. /* Now service all interrupt bits discovered above. */
  1082. if (inta & CSR_INT_BIT_HW_ERR) {
  1083. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  1084. /* Tell the device to stop sending interrupts */
  1085. iwl_disable_interrupts(priv);
  1086. priv->isr_stats.hw++;
  1087. iwl_irq_handle_error(priv);
  1088. handled |= CSR_INT_BIT_HW_ERR;
  1089. return;
  1090. }
  1091. #ifdef CONFIG_IWLWIFI_DEBUG
  1092. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1093. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  1094. if (inta & CSR_INT_BIT_SCD) {
  1095. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  1096. "the frame/frames.\n");
  1097. priv->isr_stats.sch++;
  1098. }
  1099. /* Alive notification via Rx interrupt will do the real work */
  1100. if (inta & CSR_INT_BIT_ALIVE) {
  1101. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  1102. priv->isr_stats.alive++;
  1103. }
  1104. }
  1105. #endif
  1106. /* Safely ignore these bits for debug checks below */
  1107. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  1108. /* HW RF KILL switch toggled */
  1109. if (inta & CSR_INT_BIT_RF_KILL) {
  1110. int hw_rf_kill = 0;
  1111. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  1112. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  1113. hw_rf_kill = 1;
  1114. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  1115. hw_rf_kill ? "disable radio" : "enable radio");
  1116. priv->isr_stats.rfkill++;
  1117. /* driver only loads ucode once setting the interface up.
  1118. * the driver allows loading the ucode even if the radio
  1119. * is killed. Hence update the killswitch state here. The
  1120. * rfkill handler will care about restarting if needed.
  1121. */
  1122. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  1123. if (hw_rf_kill)
  1124. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1125. else
  1126. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1127. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  1128. }
  1129. handled |= CSR_INT_BIT_RF_KILL;
  1130. }
  1131. /* Chip got too hot and stopped itself */
  1132. if (inta & CSR_INT_BIT_CT_KILL) {
  1133. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  1134. priv->isr_stats.ctkill++;
  1135. handled |= CSR_INT_BIT_CT_KILL;
  1136. }
  1137. /* Error detected by uCode */
  1138. if (inta & CSR_INT_BIT_SW_ERR) {
  1139. IWL_ERR(priv, "Microcode SW error detected. "
  1140. " Restarting 0x%X.\n", inta);
  1141. priv->isr_stats.sw++;
  1142. priv->isr_stats.sw_err = inta;
  1143. iwl_irq_handle_error(priv);
  1144. handled |= CSR_INT_BIT_SW_ERR;
  1145. }
  1146. /* uCode wakes up after power-down sleep */
  1147. if (inta & CSR_INT_BIT_WAKEUP) {
  1148. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1149. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1150. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  1151. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  1152. priv->isr_stats.wakeup++;
  1153. handled |= CSR_INT_BIT_WAKEUP;
  1154. }
  1155. /* All uCode command responses, including Tx command responses,
  1156. * Rx "responses" (frame-received notification), and other
  1157. * notifications from uCode come through here*/
  1158. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  1159. CSR_INT_BIT_RX_PERIODIC)) {
  1160. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  1161. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1162. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1163. iwl_write32(priv, CSR_FH_INT_STATUS,
  1164. CSR49_FH_INT_RX_MASK);
  1165. }
  1166. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  1167. handled |= CSR_INT_BIT_RX_PERIODIC;
  1168. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  1169. }
  1170. /* Sending RX interrupt require many steps to be done in the
  1171. * the device:
  1172. * 1- write interrupt to current index in ICT table.
  1173. * 2- dma RX frame.
  1174. * 3- update RX shared data to indicate last write index.
  1175. * 4- send interrupt.
  1176. * This could lead to RX race, driver could receive RX interrupt
  1177. * but the shared data changes does not reflect this;
  1178. * periodic interrupt will detect any dangling Rx activity.
  1179. */
  1180. /* Disable periodic interrupt; we use it as just a one-shot. */
  1181. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1182. CSR_INT_PERIODIC_DIS);
  1183. iwl_rx_handle(priv);
  1184. /*
  1185. * Enable periodic interrupt in 8 msec only if we received
  1186. * real RX interrupt (instead of just periodic int), to catch
  1187. * any dangling Rx interrupt. If it was just the periodic
  1188. * interrupt, there was no dangling Rx activity, and no need
  1189. * to extend the periodic interrupt; one-shot is enough.
  1190. */
  1191. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1192. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1193. CSR_INT_PERIODIC_ENA);
  1194. priv->isr_stats.rx++;
  1195. }
  1196. /* This "Tx" DMA channel is used only for loading uCode */
  1197. if (inta & CSR_INT_BIT_FH_TX) {
  1198. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1199. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1200. priv->isr_stats.tx++;
  1201. handled |= CSR_INT_BIT_FH_TX;
  1202. /* Wake up uCode load routine, now that load is complete */
  1203. priv->ucode_write_complete = 1;
  1204. wake_up_interruptible(&priv->wait_command_queue);
  1205. }
  1206. if (inta & ~handled) {
  1207. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1208. priv->isr_stats.unhandled++;
  1209. }
  1210. if (inta & ~(priv->inta_mask)) {
  1211. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1212. inta & ~priv->inta_mask);
  1213. }
  1214. /* Re-enable all interrupts */
  1215. /* only Re-enable if diabled by irq */
  1216. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1217. iwl_enable_interrupts(priv);
  1218. }
  1219. /******************************************************************************
  1220. *
  1221. * uCode download functions
  1222. *
  1223. ******************************************************************************/
  1224. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1225. {
  1226. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1227. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1228. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1229. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1230. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1231. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1232. }
  1233. static void iwl_nic_start(struct iwl_priv *priv)
  1234. {
  1235. /* Remove all resets to allow NIC to operate */
  1236. iwl_write32(priv, CSR_RESET, 0);
  1237. }
  1238. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
  1239. static int iwl_mac_setup_register(struct iwl_priv *priv);
  1240. static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
  1241. {
  1242. const char *name_pre = priv->cfg->fw_name_pre;
  1243. if (first)
  1244. priv->fw_index = priv->cfg->ucode_api_max;
  1245. else
  1246. priv->fw_index--;
  1247. if (priv->fw_index < priv->cfg->ucode_api_min) {
  1248. IWL_ERR(priv, "no suitable firmware found!\n");
  1249. return -ENOENT;
  1250. }
  1251. sprintf(priv->firmware_name, "%s%d%s",
  1252. name_pre, priv->fw_index, ".ucode");
  1253. IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n",
  1254. priv->firmware_name);
  1255. return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
  1256. &priv->pci_dev->dev, GFP_KERNEL, priv,
  1257. iwl_ucode_callback);
  1258. }
  1259. /**
  1260. * iwl_ucode_callback - callback when firmware was loaded
  1261. *
  1262. * If loaded successfully, copies the firmware into buffers
  1263. * for the card to fetch (via DMA).
  1264. */
  1265. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
  1266. {
  1267. struct iwl_priv *priv = context;
  1268. struct iwl_ucode_header *ucode;
  1269. const unsigned int api_max = priv->cfg->ucode_api_max;
  1270. const unsigned int api_min = priv->cfg->ucode_api_min;
  1271. u8 *src;
  1272. size_t len;
  1273. u32 api_ver, build;
  1274. u32 inst_size, data_size, init_size, init_data_size, boot_size;
  1275. int err;
  1276. u16 eeprom_ver;
  1277. if (!ucode_raw) {
  1278. IWL_ERR(priv, "request for firmware file '%s' failed.\n",
  1279. priv->firmware_name);
  1280. goto try_again;
  1281. }
  1282. IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
  1283. priv->firmware_name, ucode_raw->size);
  1284. /* Make sure that we got at least the v1 header! */
  1285. if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
  1286. IWL_ERR(priv, "File size way too small!\n");
  1287. goto try_again;
  1288. }
  1289. /* Data from ucode file: header followed by uCode images */
  1290. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1291. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1292. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1293. build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
  1294. inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
  1295. data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
  1296. init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
  1297. init_data_size =
  1298. priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
  1299. boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
  1300. src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
  1301. /* api_ver should match the api version forming part of the
  1302. * firmware filename ... but we don't check for that and only rely
  1303. * on the API version read from firmware header from here on forward */
  1304. if (api_ver < api_min || api_ver > api_max) {
  1305. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1306. "Driver supports v%u, firmware is v%u.\n",
  1307. api_max, api_ver);
  1308. goto try_again;
  1309. }
  1310. if (api_ver != api_max)
  1311. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1312. "got v%u. New firmware can be obtained "
  1313. "from http://www.intellinuxwireless.org.\n",
  1314. api_max, api_ver);
  1315. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1316. IWL_UCODE_MAJOR(priv->ucode_ver),
  1317. IWL_UCODE_MINOR(priv->ucode_ver),
  1318. IWL_UCODE_API(priv->ucode_ver),
  1319. IWL_UCODE_SERIAL(priv->ucode_ver));
  1320. snprintf(priv->hw->wiphy->fw_version,
  1321. sizeof(priv->hw->wiphy->fw_version),
  1322. "%u.%u.%u.%u",
  1323. IWL_UCODE_MAJOR(priv->ucode_ver),
  1324. IWL_UCODE_MINOR(priv->ucode_ver),
  1325. IWL_UCODE_API(priv->ucode_ver),
  1326. IWL_UCODE_SERIAL(priv->ucode_ver));
  1327. if (build)
  1328. IWL_DEBUG_INFO(priv, "Build %u\n", build);
  1329. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  1330. IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
  1331. (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
  1332. ? "OTP" : "EEPROM", eeprom_ver);
  1333. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1334. priv->ucode_ver);
  1335. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1336. inst_size);
  1337. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1338. data_size);
  1339. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1340. init_size);
  1341. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1342. init_data_size);
  1343. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1344. boot_size);
  1345. /*
  1346. * For any of the failures below (before allocating pci memory)
  1347. * we will try to load a version with a smaller API -- maybe the
  1348. * user just got a corrupted version of the latest API.
  1349. */
  1350. /* Verify size of file vs. image size info in file's header */
  1351. if (ucode_raw->size !=
  1352. priv->cfg->ops->ucode->get_header_size(api_ver) +
  1353. inst_size + data_size + init_size +
  1354. init_data_size + boot_size) {
  1355. IWL_DEBUG_INFO(priv,
  1356. "uCode file size %d does not match expected size\n",
  1357. (int)ucode_raw->size);
  1358. goto try_again;
  1359. }
  1360. /* Verify that uCode images will fit in card's SRAM */
  1361. if (inst_size > priv->hw_params.max_inst_size) {
  1362. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1363. inst_size);
  1364. goto try_again;
  1365. }
  1366. if (data_size > priv->hw_params.max_data_size) {
  1367. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1368. data_size);
  1369. goto try_again;
  1370. }
  1371. if (init_size > priv->hw_params.max_inst_size) {
  1372. IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
  1373. init_size);
  1374. goto try_again;
  1375. }
  1376. if (init_data_size > priv->hw_params.max_data_size) {
  1377. IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
  1378. init_data_size);
  1379. goto try_again;
  1380. }
  1381. if (boot_size > priv->hw_params.max_bsm_size) {
  1382. IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
  1383. boot_size);
  1384. goto try_again;
  1385. }
  1386. /* Allocate ucode buffers for card's bus-master loading ... */
  1387. /* Runtime instructions and 2 copies of data:
  1388. * 1) unmodified from disk
  1389. * 2) backup cache for save/restore during power-downs */
  1390. priv->ucode_code.len = inst_size;
  1391. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1392. priv->ucode_data.len = data_size;
  1393. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1394. priv->ucode_data_backup.len = data_size;
  1395. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1396. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1397. !priv->ucode_data_backup.v_addr)
  1398. goto err_pci_alloc;
  1399. /* Initialization instructions and data */
  1400. if (init_size && init_data_size) {
  1401. priv->ucode_init.len = init_size;
  1402. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1403. priv->ucode_init_data.len = init_data_size;
  1404. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1405. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1406. goto err_pci_alloc;
  1407. }
  1408. /* Bootstrap (instructions only, no data) */
  1409. if (boot_size) {
  1410. priv->ucode_boot.len = boot_size;
  1411. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1412. if (!priv->ucode_boot.v_addr)
  1413. goto err_pci_alloc;
  1414. }
  1415. /* Copy images into buffers for card's bus-master reads ... */
  1416. /* Runtime instructions (first block of data in file) */
  1417. len = inst_size;
  1418. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
  1419. memcpy(priv->ucode_code.v_addr, src, len);
  1420. src += len;
  1421. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1422. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1423. /* Runtime data (2nd block)
  1424. * NOTE: Copy into backup buffer will be done in iwl_up() */
  1425. len = data_size;
  1426. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
  1427. memcpy(priv->ucode_data.v_addr, src, len);
  1428. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1429. src += len;
  1430. /* Initialization instructions (3rd block) */
  1431. if (init_size) {
  1432. len = init_size;
  1433. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1434. len);
  1435. memcpy(priv->ucode_init.v_addr, src, len);
  1436. src += len;
  1437. }
  1438. /* Initialization data (4th block) */
  1439. if (init_data_size) {
  1440. len = init_data_size;
  1441. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1442. len);
  1443. memcpy(priv->ucode_init_data.v_addr, src, len);
  1444. src += len;
  1445. }
  1446. /* Bootstrap instructions (5th block) */
  1447. len = boot_size;
  1448. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
  1449. memcpy(priv->ucode_boot.v_addr, src, len);
  1450. /**************************************************
  1451. * This is still part of probe() in a sense...
  1452. *
  1453. * 9. Setup and register with mac80211 and debugfs
  1454. **************************************************/
  1455. err = iwl_mac_setup_register(priv);
  1456. if (err)
  1457. goto out_unbind;
  1458. err = iwl_dbgfs_register(priv, DRV_NAME);
  1459. if (err)
  1460. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  1461. /* We have our copies now, allow OS release its copies */
  1462. release_firmware(ucode_raw);
  1463. return;
  1464. try_again:
  1465. /* try next, if any */
  1466. if (iwl_request_firmware(priv, false))
  1467. goto out_unbind;
  1468. release_firmware(ucode_raw);
  1469. return;
  1470. err_pci_alloc:
  1471. IWL_ERR(priv, "failed to allocate pci memory\n");
  1472. iwl_dealloc_ucode_pci(priv);
  1473. out_unbind:
  1474. device_release_driver(&priv->pci_dev->dev);
  1475. release_firmware(ucode_raw);
  1476. }
  1477. static const char *desc_lookup_text[] = {
  1478. "OK",
  1479. "FAIL",
  1480. "BAD_PARAM",
  1481. "BAD_CHECKSUM",
  1482. "NMI_INTERRUPT_WDG",
  1483. "SYSASSERT",
  1484. "FATAL_ERROR",
  1485. "BAD_COMMAND",
  1486. "HW_ERROR_TUNE_LOCK",
  1487. "HW_ERROR_TEMPERATURE",
  1488. "ILLEGAL_CHAN_FREQ",
  1489. "VCC_NOT_STABLE",
  1490. "FH_ERROR",
  1491. "NMI_INTERRUPT_HOST",
  1492. "NMI_INTERRUPT_ACTION_PT",
  1493. "NMI_INTERRUPT_UNKNOWN",
  1494. "UCODE_VERSION_MISMATCH",
  1495. "HW_ERROR_ABS_LOCK",
  1496. "HW_ERROR_CAL_LOCK_FAIL",
  1497. "NMI_INTERRUPT_INST_ACTION_PT",
  1498. "NMI_INTERRUPT_DATA_ACTION_PT",
  1499. "NMI_TRM_HW_ER",
  1500. "NMI_INTERRUPT_TRM",
  1501. "NMI_INTERRUPT_BREAK_POINT"
  1502. "DEBUG_0",
  1503. "DEBUG_1",
  1504. "DEBUG_2",
  1505. "DEBUG_3",
  1506. "ADVANCED SYSASSERT"
  1507. };
  1508. static const char *desc_lookup(int i)
  1509. {
  1510. int max = ARRAY_SIZE(desc_lookup_text) - 1;
  1511. if (i < 0 || i > max)
  1512. i = max;
  1513. return desc_lookup_text[i];
  1514. }
  1515. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1516. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1517. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1518. {
  1519. u32 data2, line;
  1520. u32 desc, time, count, base, data1;
  1521. u32 blink1, blink2, ilink1, ilink2;
  1522. if (priv->ucode_type == UCODE_INIT)
  1523. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1524. else
  1525. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1526. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1527. IWL_ERR(priv,
  1528. "Not valid error log pointer 0x%08X for %s uCode\n",
  1529. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1530. return;
  1531. }
  1532. count = iwl_read_targ_mem(priv, base);
  1533. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1534. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1535. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1536. priv->status, count);
  1537. }
  1538. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1539. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  1540. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  1541. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  1542. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  1543. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  1544. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  1545. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  1546. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  1547. trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
  1548. blink1, blink2, ilink1, ilink2);
  1549. IWL_ERR(priv, "Desc Time "
  1550. "data1 data2 line\n");
  1551. IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
  1552. desc_lookup(desc), desc, time, data1, data2, line);
  1553. IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
  1554. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
  1555. ilink1, ilink2);
  1556. }
  1557. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1558. /**
  1559. * iwl_print_event_log - Dump error event log to syslog
  1560. *
  1561. */
  1562. static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1563. u32 num_events, u32 mode,
  1564. int pos, char **buf, size_t bufsz)
  1565. {
  1566. u32 i;
  1567. u32 base; /* SRAM byte address of event log header */
  1568. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1569. u32 ptr; /* SRAM byte address of log data */
  1570. u32 ev, time, data; /* event log data */
  1571. unsigned long reg_flags;
  1572. if (num_events == 0)
  1573. return pos;
  1574. if (priv->ucode_type == UCODE_INIT)
  1575. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1576. else
  1577. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1578. if (mode == 0)
  1579. event_size = 2 * sizeof(u32);
  1580. else
  1581. event_size = 3 * sizeof(u32);
  1582. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1583. /* Make sure device is powered up for SRAM reads */
  1584. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  1585. iwl_grab_nic_access(priv);
  1586. /* Set starting address; reads will auto-increment */
  1587. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  1588. rmb();
  1589. /* "time" is actually "data" for mode 0 (no timestamp).
  1590. * place event id # at far right for easier visual parsing. */
  1591. for (i = 0; i < num_events; i++) {
  1592. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1593. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1594. if (mode == 0) {
  1595. /* data, ev */
  1596. if (bufsz) {
  1597. pos += scnprintf(*buf + pos, bufsz - pos,
  1598. "EVT_LOG:0x%08x:%04u\n",
  1599. time, ev);
  1600. } else {
  1601. trace_iwlwifi_dev_ucode_event(priv, 0,
  1602. time, ev);
  1603. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
  1604. time, ev);
  1605. }
  1606. } else {
  1607. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1608. if (bufsz) {
  1609. pos += scnprintf(*buf + pos, bufsz - pos,
  1610. "EVT_LOGT:%010u:0x%08x:%04u\n",
  1611. time, data, ev);
  1612. } else {
  1613. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1614. time, data, ev);
  1615. trace_iwlwifi_dev_ucode_event(priv, time,
  1616. data, ev);
  1617. }
  1618. }
  1619. }
  1620. /* Allow device to power down */
  1621. iwl_release_nic_access(priv);
  1622. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  1623. return pos;
  1624. }
  1625. /**
  1626. * iwl_print_last_event_logs - Dump the newest # of event log to syslog
  1627. */
  1628. static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
  1629. u32 num_wraps, u32 next_entry,
  1630. u32 size, u32 mode,
  1631. int pos, char **buf, size_t bufsz)
  1632. {
  1633. /*
  1634. * display the newest DEFAULT_LOG_ENTRIES entries
  1635. * i.e the entries just before the next ont that uCode would fill.
  1636. */
  1637. if (num_wraps) {
  1638. if (next_entry < size) {
  1639. pos = iwl_print_event_log(priv,
  1640. capacity - (size - next_entry),
  1641. size - next_entry, mode,
  1642. pos, buf, bufsz);
  1643. pos = iwl_print_event_log(priv, 0,
  1644. next_entry, mode,
  1645. pos, buf, bufsz);
  1646. } else
  1647. pos = iwl_print_event_log(priv, next_entry - size,
  1648. size, mode, pos, buf, bufsz);
  1649. } else {
  1650. if (next_entry < size) {
  1651. pos = iwl_print_event_log(priv, 0, next_entry,
  1652. mode, pos, buf, bufsz);
  1653. } else {
  1654. pos = iwl_print_event_log(priv, next_entry - size,
  1655. size, mode, pos, buf, bufsz);
  1656. }
  1657. }
  1658. return pos;
  1659. }
  1660. /* For sanity check only. Actual size is determined by uCode, typ. 512 */
  1661. #define MAX_EVENT_LOG_SIZE (512)
  1662. #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
  1663. int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
  1664. char **buf, bool display)
  1665. {
  1666. u32 base; /* SRAM byte address of event log header */
  1667. u32 capacity; /* event log capacity in # entries */
  1668. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1669. u32 num_wraps; /* # times uCode wrapped to top of log */
  1670. u32 next_entry; /* index of next entry to be written by uCode */
  1671. u32 size; /* # entries that we'll print */
  1672. int pos = 0;
  1673. size_t bufsz = 0;
  1674. if (priv->ucode_type == UCODE_INIT)
  1675. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1676. else
  1677. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1678. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1679. IWL_ERR(priv,
  1680. "Invalid event log pointer 0x%08X for %s uCode\n",
  1681. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1682. return -EINVAL;
  1683. }
  1684. /* event log header */
  1685. capacity = iwl_read_targ_mem(priv, base);
  1686. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1687. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1688. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1689. if (capacity > MAX_EVENT_LOG_SIZE) {
  1690. IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
  1691. capacity, MAX_EVENT_LOG_SIZE);
  1692. capacity = MAX_EVENT_LOG_SIZE;
  1693. }
  1694. if (next_entry > MAX_EVENT_LOG_SIZE) {
  1695. IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
  1696. next_entry, MAX_EVENT_LOG_SIZE);
  1697. next_entry = MAX_EVENT_LOG_SIZE;
  1698. }
  1699. size = num_wraps ? capacity : next_entry;
  1700. /* bail out if nothing in log */
  1701. if (size == 0) {
  1702. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1703. return pos;
  1704. }
  1705. #ifdef CONFIG_IWLWIFI_DEBUG
  1706. if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
  1707. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1708. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1709. #else
  1710. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1711. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1712. #endif
  1713. IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
  1714. size);
  1715. #ifdef CONFIG_IWLWIFI_DEBUG
  1716. if (display) {
  1717. if (full_log)
  1718. bufsz = capacity * 48;
  1719. else
  1720. bufsz = size * 48;
  1721. *buf = kmalloc(bufsz, GFP_KERNEL);
  1722. if (!*buf)
  1723. return -ENOMEM;
  1724. }
  1725. if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
  1726. /*
  1727. * if uCode has wrapped back to top of log,
  1728. * start at the oldest entry,
  1729. * i.e the next one that uCode would fill.
  1730. */
  1731. if (num_wraps)
  1732. pos = iwl_print_event_log(priv, next_entry,
  1733. capacity - next_entry, mode,
  1734. pos, buf, bufsz);
  1735. /* (then/else) start at top of log */
  1736. pos = iwl_print_event_log(priv, 0,
  1737. next_entry, mode, pos, buf, bufsz);
  1738. } else
  1739. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  1740. next_entry, size, mode,
  1741. pos, buf, bufsz);
  1742. #else
  1743. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  1744. next_entry, size, mode,
  1745. pos, buf, bufsz);
  1746. #endif
  1747. return pos;
  1748. }
  1749. /**
  1750. * iwl_alive_start - called after REPLY_ALIVE notification received
  1751. * from protocol/runtime uCode (initialization uCode's
  1752. * Alive gets handled by iwl_init_alive_start()).
  1753. */
  1754. static void iwl_alive_start(struct iwl_priv *priv)
  1755. {
  1756. int ret = 0;
  1757. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1758. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1759. /* We had an error bringing up the hardware, so take it
  1760. * all the way back down so we can try again */
  1761. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1762. goto restart;
  1763. }
  1764. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1765. * This is a paranoid check, because we would not have gotten the
  1766. * "runtime" alive if code weren't properly loaded. */
  1767. if (iwl_verify_ucode(priv)) {
  1768. /* Runtime instruction load was bad;
  1769. * take it all the way back down so we can try again */
  1770. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1771. goto restart;
  1772. }
  1773. ret = priv->cfg->ops->lib->alive_notify(priv);
  1774. if (ret) {
  1775. IWL_WARN(priv,
  1776. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1777. goto restart;
  1778. }
  1779. /* After the ALIVE response, we can send host commands to the uCode */
  1780. set_bit(STATUS_ALIVE, &priv->status);
  1781. if (iwl_is_rfkill(priv))
  1782. return;
  1783. ieee80211_wake_queues(priv->hw);
  1784. priv->active_rate = IWL_RATES_MASK;
  1785. /* Configure Tx antenna selection based on H/W config */
  1786. if (priv->cfg->ops->hcmd->set_tx_ant)
  1787. priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
  1788. if (iwl_is_associated(priv)) {
  1789. struct iwl_rxon_cmd *active_rxon =
  1790. (struct iwl_rxon_cmd *)&priv->active_rxon;
  1791. /* apply any changes in staging */
  1792. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1793. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1794. } else {
  1795. /* Initialize our rx_config data */
  1796. iwl_connection_init_rx_config(priv, priv->iw_mode);
  1797. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1798. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1799. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1800. }
  1801. /* Configure Bluetooth device coexistence support */
  1802. iwl_send_bt_config(priv);
  1803. iwl_reset_run_time_calib(priv);
  1804. /* Configure the adapter for unassociated operation */
  1805. iwlcore_commit_rxon(priv);
  1806. /* At this point, the NIC is initialized and operational */
  1807. iwl_rf_kill_ct_config(priv);
  1808. iwl_leds_init(priv);
  1809. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1810. set_bit(STATUS_READY, &priv->status);
  1811. wake_up_interruptible(&priv->wait_command_queue);
  1812. iwl_power_update_mode(priv, true);
  1813. IWL_DEBUG_INFO(priv, "Updated power mode\n");
  1814. return;
  1815. restart:
  1816. queue_work(priv->workqueue, &priv->restart);
  1817. }
  1818. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1819. static void __iwl_down(struct iwl_priv *priv)
  1820. {
  1821. unsigned long flags;
  1822. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  1823. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1824. if (!exit_pending)
  1825. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1826. iwl_clear_ucode_stations(priv, true);
  1827. /* Unblock any waiting calls */
  1828. wake_up_interruptible_all(&priv->wait_command_queue);
  1829. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1830. * exiting the module */
  1831. if (!exit_pending)
  1832. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1833. /* stop and reset the on-board processor */
  1834. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1835. /* tell the device to stop sending interrupts */
  1836. spin_lock_irqsave(&priv->lock, flags);
  1837. iwl_disable_interrupts(priv);
  1838. spin_unlock_irqrestore(&priv->lock, flags);
  1839. iwl_synchronize_irq(priv);
  1840. if (priv->mac80211_registered)
  1841. ieee80211_stop_queues(priv->hw);
  1842. /* If we have not previously called iwl_init() then
  1843. * clear all bits but the RF Kill bit and return */
  1844. if (!iwl_is_init(priv)) {
  1845. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1846. STATUS_RF_KILL_HW |
  1847. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1848. STATUS_GEO_CONFIGURED |
  1849. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1850. STATUS_EXIT_PENDING;
  1851. goto exit;
  1852. }
  1853. /* ...otherwise clear out all the status bits but the RF Kill
  1854. * bit and continue taking the NIC down. */
  1855. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1856. STATUS_RF_KILL_HW |
  1857. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1858. STATUS_GEO_CONFIGURED |
  1859. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1860. STATUS_FW_ERROR |
  1861. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1862. STATUS_EXIT_PENDING;
  1863. /* device going down, Stop using ICT table */
  1864. iwl_disable_ict(priv);
  1865. iwl_txq_ctx_stop(priv);
  1866. iwl_rxq_stop(priv);
  1867. /* Power-down device's busmaster DMA clocks */
  1868. iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  1869. udelay(5);
  1870. /* Make sure (redundant) we've released our request to stay awake */
  1871. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1872. /* Stop the device, and put it in low power state */
  1873. priv->cfg->ops->lib->apm_ops.stop(priv);
  1874. exit:
  1875. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1876. if (priv->ibss_beacon)
  1877. dev_kfree_skb(priv->ibss_beacon);
  1878. priv->ibss_beacon = NULL;
  1879. /* clear out any free frames */
  1880. iwl_clear_free_frames(priv);
  1881. }
  1882. static void iwl_down(struct iwl_priv *priv)
  1883. {
  1884. mutex_lock(&priv->mutex);
  1885. __iwl_down(priv);
  1886. mutex_unlock(&priv->mutex);
  1887. iwl_cancel_deferred_work(priv);
  1888. }
  1889. #define HW_READY_TIMEOUT (50)
  1890. static int iwl_set_hw_ready(struct iwl_priv *priv)
  1891. {
  1892. int ret = 0;
  1893. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1894. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  1895. /* See if we got it */
  1896. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1897. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1898. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1899. HW_READY_TIMEOUT);
  1900. if (ret != -ETIMEDOUT)
  1901. priv->hw_ready = true;
  1902. else
  1903. priv->hw_ready = false;
  1904. IWL_DEBUG_INFO(priv, "hardware %s\n",
  1905. (priv->hw_ready == 1) ? "ready" : "not ready");
  1906. return ret;
  1907. }
  1908. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  1909. {
  1910. int ret = 0;
  1911. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
  1912. ret = iwl_set_hw_ready(priv);
  1913. if (priv->hw_ready)
  1914. return ret;
  1915. /* If HW is not ready, prepare the conditions to check again */
  1916. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1917. CSR_HW_IF_CONFIG_REG_PREPARE);
  1918. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1919. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  1920. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  1921. /* HW should be ready by now, check again. */
  1922. if (ret != -ETIMEDOUT)
  1923. iwl_set_hw_ready(priv);
  1924. return ret;
  1925. }
  1926. #define MAX_HW_RESTARTS 5
  1927. static int __iwl_up(struct iwl_priv *priv)
  1928. {
  1929. int i;
  1930. int ret;
  1931. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1932. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1933. return -EIO;
  1934. }
  1935. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1936. IWL_ERR(priv, "ucode not available for device bringup\n");
  1937. return -EIO;
  1938. }
  1939. iwl_prepare_card_hw(priv);
  1940. if (!priv->hw_ready) {
  1941. IWL_WARN(priv, "Exit HW not ready\n");
  1942. return -EIO;
  1943. }
  1944. /* If platform's RF_KILL switch is NOT set to KILL */
  1945. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1946. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1947. else
  1948. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1949. if (iwl_is_rfkill(priv)) {
  1950. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  1951. iwl_enable_interrupts(priv);
  1952. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  1953. return 0;
  1954. }
  1955. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1956. ret = iwl_hw_nic_init(priv);
  1957. if (ret) {
  1958. IWL_ERR(priv, "Unable to init nic\n");
  1959. return ret;
  1960. }
  1961. /* make sure rfkill handshake bits are cleared */
  1962. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1963. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1964. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  1965. /* clear (again), then enable host interrupts */
  1966. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1967. iwl_enable_interrupts(priv);
  1968. /* really make sure rfkill handshake bits are cleared */
  1969. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1970. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1971. /* Copy original ucode data image from disk into backup cache.
  1972. * This will be used to initialize the on-board processor's
  1973. * data SRAM for a clean start when the runtime program first loads. */
  1974. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  1975. priv->ucode_data.len);
  1976. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  1977. /* load bootstrap state machine,
  1978. * load bootstrap program into processor's memory,
  1979. * prepare to load the "initialize" uCode */
  1980. ret = priv->cfg->ops->lib->load_ucode(priv);
  1981. if (ret) {
  1982. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  1983. ret);
  1984. continue;
  1985. }
  1986. /* start card; "initialize" will load runtime ucode */
  1987. iwl_nic_start(priv);
  1988. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  1989. return 0;
  1990. }
  1991. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1992. __iwl_down(priv);
  1993. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1994. /* tried to restart and config the device for as long as our
  1995. * patience could withstand */
  1996. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  1997. return -EIO;
  1998. }
  1999. /*****************************************************************************
  2000. *
  2001. * Workqueue callbacks
  2002. *
  2003. *****************************************************************************/
  2004. static void iwl_bg_init_alive_start(struct work_struct *data)
  2005. {
  2006. struct iwl_priv *priv =
  2007. container_of(data, struct iwl_priv, init_alive_start.work);
  2008. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2009. return;
  2010. mutex_lock(&priv->mutex);
  2011. priv->cfg->ops->lib->init_alive_start(priv);
  2012. mutex_unlock(&priv->mutex);
  2013. }
  2014. static void iwl_bg_alive_start(struct work_struct *data)
  2015. {
  2016. struct iwl_priv *priv =
  2017. container_of(data, struct iwl_priv, alive_start.work);
  2018. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2019. return;
  2020. /* enable dram interrupt */
  2021. iwl_reset_ict(priv);
  2022. mutex_lock(&priv->mutex);
  2023. iwl_alive_start(priv);
  2024. mutex_unlock(&priv->mutex);
  2025. }
  2026. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  2027. {
  2028. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  2029. run_time_calib_work);
  2030. mutex_lock(&priv->mutex);
  2031. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  2032. test_bit(STATUS_SCANNING, &priv->status)) {
  2033. mutex_unlock(&priv->mutex);
  2034. return;
  2035. }
  2036. if (priv->start_calib) {
  2037. iwl_chain_noise_calibration(priv, &priv->statistics);
  2038. iwl_sensitivity_calibration(priv, &priv->statistics);
  2039. }
  2040. mutex_unlock(&priv->mutex);
  2041. return;
  2042. }
  2043. static void iwl_bg_restart(struct work_struct *data)
  2044. {
  2045. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  2046. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2047. return;
  2048. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  2049. mutex_lock(&priv->mutex);
  2050. priv->vif = NULL;
  2051. priv->is_open = 0;
  2052. mutex_unlock(&priv->mutex);
  2053. iwl_down(priv);
  2054. ieee80211_restart_hw(priv->hw);
  2055. } else {
  2056. iwl_down(priv);
  2057. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2058. return;
  2059. mutex_lock(&priv->mutex);
  2060. __iwl_up(priv);
  2061. mutex_unlock(&priv->mutex);
  2062. }
  2063. }
  2064. static void iwl_bg_rx_replenish(struct work_struct *data)
  2065. {
  2066. struct iwl_priv *priv =
  2067. container_of(data, struct iwl_priv, rx_replenish);
  2068. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2069. return;
  2070. mutex_lock(&priv->mutex);
  2071. iwl_rx_replenish(priv);
  2072. mutex_unlock(&priv->mutex);
  2073. }
  2074. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  2075. void iwl_post_associate(struct iwl_priv *priv)
  2076. {
  2077. struct ieee80211_conf *conf = NULL;
  2078. int ret = 0;
  2079. unsigned long flags;
  2080. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  2081. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  2082. return;
  2083. }
  2084. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  2085. priv->assoc_id, priv->active_rxon.bssid_addr);
  2086. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2087. return;
  2088. if (!priv->vif || !priv->is_open)
  2089. return;
  2090. iwl_scan_cancel_timeout(priv, 200);
  2091. conf = ieee80211_get_hw_conf(priv->hw);
  2092. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2093. iwlcore_commit_rxon(priv);
  2094. iwl_setup_rxon_timing(priv);
  2095. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2096. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2097. if (ret)
  2098. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2099. "Attempting to continue.\n");
  2100. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2101. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2102. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2103. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2104. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  2105. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  2106. priv->assoc_id, priv->beacon_int);
  2107. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  2108. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2109. else
  2110. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2111. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2112. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2113. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2114. else
  2115. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2116. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2117. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2118. }
  2119. iwlcore_commit_rxon(priv);
  2120. switch (priv->iw_mode) {
  2121. case NL80211_IFTYPE_STATION:
  2122. break;
  2123. case NL80211_IFTYPE_ADHOC:
  2124. /* assume default assoc id */
  2125. priv->assoc_id = 1;
  2126. iwl_rxon_add_station(priv, priv->bssid, 0);
  2127. iwl_send_beacon_cmd(priv);
  2128. break;
  2129. default:
  2130. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  2131. __func__, priv->iw_mode);
  2132. break;
  2133. }
  2134. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2135. priv->assoc_station_added = 1;
  2136. spin_lock_irqsave(&priv->lock, flags);
  2137. iwl_activate_qos(priv, 0);
  2138. spin_unlock_irqrestore(&priv->lock, flags);
  2139. /* the chain noise calibration will enabled PM upon completion
  2140. * If chain noise has already been run, then we need to enable
  2141. * power management here */
  2142. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  2143. iwl_power_update_mode(priv, false);
  2144. /* Enable Rx differential gain and sensitivity calibrations */
  2145. iwl_chain_noise_reset(priv);
  2146. priv->start_calib = 1;
  2147. }
  2148. /*****************************************************************************
  2149. *
  2150. * mac80211 entry point functions
  2151. *
  2152. *****************************************************************************/
  2153. #define UCODE_READY_TIMEOUT (4 * HZ)
  2154. /*
  2155. * Not a mac80211 entry point function, but it fits in with all the
  2156. * other mac80211 functions grouped here.
  2157. */
  2158. static int iwl_mac_setup_register(struct iwl_priv *priv)
  2159. {
  2160. int ret;
  2161. struct ieee80211_hw *hw = priv->hw;
  2162. hw->rate_control_algorithm = "iwl-agn-rs";
  2163. /* Tell mac80211 our characteristics */
  2164. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  2165. IEEE80211_HW_NOISE_DBM |
  2166. IEEE80211_HW_AMPDU_AGGREGATION |
  2167. IEEE80211_HW_SPECTRUM_MGMT;
  2168. if (!priv->cfg->broken_powersave)
  2169. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  2170. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  2171. if (priv->cfg->sku & IWL_SKU_N)
  2172. hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
  2173. IEEE80211_HW_SUPPORTS_STATIC_SMPS;
  2174. hw->sta_data_size = sizeof(struct iwl_station_priv);
  2175. hw->wiphy->interface_modes =
  2176. BIT(NL80211_IFTYPE_STATION) |
  2177. BIT(NL80211_IFTYPE_ADHOC);
  2178. hw->wiphy->flags |= WIPHY_FLAG_STRICT_REGULATORY |
  2179. WIPHY_FLAG_DISABLE_BEACON_HINTS;
  2180. /*
  2181. * For now, disable PS by default because it affects
  2182. * RX performance significantly.
  2183. */
  2184. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  2185. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX + 1;
  2186. /* we create the 802.11 header and a zero-length SSID element */
  2187. hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
  2188. /* Default value; 4 EDCA QOS priorities */
  2189. hw->queues = 4;
  2190. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  2191. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  2192. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  2193. &priv->bands[IEEE80211_BAND_2GHZ];
  2194. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  2195. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  2196. &priv->bands[IEEE80211_BAND_5GHZ];
  2197. ret = ieee80211_register_hw(priv->hw);
  2198. if (ret) {
  2199. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  2200. return ret;
  2201. }
  2202. priv->mac80211_registered = 1;
  2203. return 0;
  2204. }
  2205. static int iwl_mac_start(struct ieee80211_hw *hw)
  2206. {
  2207. struct iwl_priv *priv = hw->priv;
  2208. int ret;
  2209. IWL_DEBUG_MAC80211(priv, "enter\n");
  2210. /* we should be verifying the device is ready to be opened */
  2211. mutex_lock(&priv->mutex);
  2212. ret = __iwl_up(priv);
  2213. mutex_unlock(&priv->mutex);
  2214. if (ret)
  2215. return ret;
  2216. if (iwl_is_rfkill(priv))
  2217. goto out;
  2218. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  2219. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  2220. * mac80211 will not be run successfully. */
  2221. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  2222. test_bit(STATUS_READY, &priv->status),
  2223. UCODE_READY_TIMEOUT);
  2224. if (!ret) {
  2225. if (!test_bit(STATUS_READY, &priv->status)) {
  2226. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  2227. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  2228. return -ETIMEDOUT;
  2229. }
  2230. }
  2231. iwl_led_start(priv);
  2232. out:
  2233. priv->is_open = 1;
  2234. IWL_DEBUG_MAC80211(priv, "leave\n");
  2235. return 0;
  2236. }
  2237. static void iwl_mac_stop(struct ieee80211_hw *hw)
  2238. {
  2239. struct iwl_priv *priv = hw->priv;
  2240. IWL_DEBUG_MAC80211(priv, "enter\n");
  2241. if (!priv->is_open)
  2242. return;
  2243. priv->is_open = 0;
  2244. if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
  2245. /* stop mac, cancel any scan request and clear
  2246. * RXON_FILTER_ASSOC_MSK BIT
  2247. */
  2248. mutex_lock(&priv->mutex);
  2249. iwl_scan_cancel_timeout(priv, 100);
  2250. mutex_unlock(&priv->mutex);
  2251. }
  2252. iwl_down(priv);
  2253. flush_workqueue(priv->workqueue);
  2254. /* enable interrupts again in order to receive rfkill changes */
  2255. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2256. iwl_enable_interrupts(priv);
  2257. IWL_DEBUG_MAC80211(priv, "leave\n");
  2258. }
  2259. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2260. {
  2261. struct iwl_priv *priv = hw->priv;
  2262. IWL_DEBUG_MACDUMP(priv, "enter\n");
  2263. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2264. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2265. if (iwl_tx_skb(priv, skb))
  2266. dev_kfree_skb_any(skb);
  2267. IWL_DEBUG_MACDUMP(priv, "leave\n");
  2268. return NETDEV_TX_OK;
  2269. }
  2270. void iwl_config_ap(struct iwl_priv *priv)
  2271. {
  2272. int ret = 0;
  2273. unsigned long flags;
  2274. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2275. return;
  2276. /* The following should be done only at AP bring up */
  2277. if (!iwl_is_associated(priv)) {
  2278. /* RXON - unassoc (to set timing command) */
  2279. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2280. iwlcore_commit_rxon(priv);
  2281. /* RXON Timing */
  2282. iwl_setup_rxon_timing(priv);
  2283. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2284. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2285. if (ret)
  2286. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2287. "Attempting to continue.\n");
  2288. /* AP has all antennas */
  2289. priv->chain_noise_data.active_chains =
  2290. priv->hw_params.valid_rx_ant;
  2291. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2292. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2293. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2294. /* FIXME: what should be the assoc_id for AP? */
  2295. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  2296. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  2297. priv->staging_rxon.flags |=
  2298. RXON_FLG_SHORT_PREAMBLE_MSK;
  2299. else
  2300. priv->staging_rxon.flags &=
  2301. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2302. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2303. if (priv->assoc_capability &
  2304. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2305. priv->staging_rxon.flags |=
  2306. RXON_FLG_SHORT_SLOT_MSK;
  2307. else
  2308. priv->staging_rxon.flags &=
  2309. ~RXON_FLG_SHORT_SLOT_MSK;
  2310. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2311. priv->staging_rxon.flags &=
  2312. ~RXON_FLG_SHORT_SLOT_MSK;
  2313. }
  2314. /* restore RXON assoc */
  2315. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2316. iwlcore_commit_rxon(priv);
  2317. iwl_reset_qos(priv);
  2318. spin_lock_irqsave(&priv->lock, flags);
  2319. iwl_activate_qos(priv, 1);
  2320. spin_unlock_irqrestore(&priv->lock, flags);
  2321. iwl_add_bcast_station(priv);
  2322. }
  2323. iwl_send_beacon_cmd(priv);
  2324. /* FIXME - we need to add code here to detect a totally new
  2325. * configuration, reset the AP, unassoc, rxon timing, assoc,
  2326. * clear sta table, add BCAST sta... */
  2327. }
  2328. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  2329. struct ieee80211_vif *vif,
  2330. struct ieee80211_key_conf *keyconf,
  2331. struct ieee80211_sta *sta,
  2332. u32 iv32, u16 *phase1key)
  2333. {
  2334. struct iwl_priv *priv = hw->priv;
  2335. IWL_DEBUG_MAC80211(priv, "enter\n");
  2336. iwl_update_tkip_key(priv, keyconf,
  2337. sta ? sta->addr : iwl_bcast_addr,
  2338. iv32, phase1key);
  2339. IWL_DEBUG_MAC80211(priv, "leave\n");
  2340. }
  2341. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2342. struct ieee80211_vif *vif,
  2343. struct ieee80211_sta *sta,
  2344. struct ieee80211_key_conf *key)
  2345. {
  2346. struct iwl_priv *priv = hw->priv;
  2347. const u8 *addr;
  2348. int ret;
  2349. u8 sta_id;
  2350. bool is_default_wep_key = false;
  2351. IWL_DEBUG_MAC80211(priv, "enter\n");
  2352. if (priv->cfg->mod_params->sw_crypto) {
  2353. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2354. return -EOPNOTSUPP;
  2355. }
  2356. addr = sta ? sta->addr : iwl_bcast_addr;
  2357. sta_id = iwl_find_station(priv, addr);
  2358. if (sta_id == IWL_INVALID_STATION) {
  2359. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  2360. addr);
  2361. return -EINVAL;
  2362. }
  2363. mutex_lock(&priv->mutex);
  2364. iwl_scan_cancel_timeout(priv, 100);
  2365. /* If we are getting WEP group key and we didn't receive any key mapping
  2366. * so far, we are in legacy wep mode (group key only), otherwise we are
  2367. * in 1X mode.
  2368. * In legacy wep mode, we use another host command to the uCode */
  2369. if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
  2370. priv->iw_mode != NL80211_IFTYPE_AP) {
  2371. if (cmd == SET_KEY)
  2372. is_default_wep_key = !priv->key_mapping_key;
  2373. else
  2374. is_default_wep_key =
  2375. (key->hw_key_idx == HW_KEY_DEFAULT);
  2376. }
  2377. switch (cmd) {
  2378. case SET_KEY:
  2379. if (is_default_wep_key)
  2380. ret = iwl_set_default_wep_key(priv, key);
  2381. else
  2382. ret = iwl_set_dynamic_key(priv, key, sta_id);
  2383. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2384. break;
  2385. case DISABLE_KEY:
  2386. if (is_default_wep_key)
  2387. ret = iwl_remove_default_wep_key(priv, key);
  2388. else
  2389. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  2390. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2391. break;
  2392. default:
  2393. ret = -EINVAL;
  2394. }
  2395. mutex_unlock(&priv->mutex);
  2396. IWL_DEBUG_MAC80211(priv, "leave\n");
  2397. return ret;
  2398. }
  2399. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  2400. struct ieee80211_vif *vif,
  2401. enum ieee80211_ampdu_mlme_action action,
  2402. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2403. {
  2404. struct iwl_priv *priv = hw->priv;
  2405. int ret;
  2406. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2407. sta->addr, tid);
  2408. if (!(priv->cfg->sku & IWL_SKU_N))
  2409. return -EACCES;
  2410. switch (action) {
  2411. case IEEE80211_AMPDU_RX_START:
  2412. IWL_DEBUG_HT(priv, "start Rx\n");
  2413. return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
  2414. case IEEE80211_AMPDU_RX_STOP:
  2415. IWL_DEBUG_HT(priv, "stop Rx\n");
  2416. ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
  2417. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2418. return 0;
  2419. else
  2420. return ret;
  2421. case IEEE80211_AMPDU_TX_START:
  2422. IWL_DEBUG_HT(priv, "start Tx\n");
  2423. return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
  2424. case IEEE80211_AMPDU_TX_STOP:
  2425. IWL_DEBUG_HT(priv, "stop Tx\n");
  2426. ret = iwl_tx_agg_stop(priv, sta->addr, tid);
  2427. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2428. return 0;
  2429. else
  2430. return ret;
  2431. case IEEE80211_AMPDU_TX_OPERATIONAL:
  2432. /* do nothing */
  2433. return -EOPNOTSUPP;
  2434. default:
  2435. IWL_DEBUG_HT(priv, "unknown\n");
  2436. return -EINVAL;
  2437. break;
  2438. }
  2439. return 0;
  2440. }
  2441. static int iwl_mac_get_stats(struct ieee80211_hw *hw,
  2442. struct ieee80211_low_level_stats *stats)
  2443. {
  2444. struct iwl_priv *priv = hw->priv;
  2445. priv = hw->priv;
  2446. IWL_DEBUG_MAC80211(priv, "enter\n");
  2447. IWL_DEBUG_MAC80211(priv, "leave\n");
  2448. return 0;
  2449. }
  2450. static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
  2451. struct ieee80211_vif *vif,
  2452. enum sta_notify_cmd cmd,
  2453. struct ieee80211_sta *sta)
  2454. {
  2455. struct iwl_priv *priv = hw->priv;
  2456. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2457. int sta_id;
  2458. /*
  2459. * TODO: We really should use this callback to
  2460. * actually maintain the station table in
  2461. * the device.
  2462. */
  2463. switch (cmd) {
  2464. case STA_NOTIFY_ADD:
  2465. atomic_set(&sta_priv->pending_frames, 0);
  2466. if (vif->type == NL80211_IFTYPE_AP)
  2467. sta_priv->client = true;
  2468. break;
  2469. case STA_NOTIFY_SLEEP:
  2470. WARN_ON(!sta_priv->client);
  2471. sta_priv->asleep = true;
  2472. if (atomic_read(&sta_priv->pending_frames) > 0)
  2473. ieee80211_sta_block_awake(hw, sta, true);
  2474. break;
  2475. case STA_NOTIFY_AWAKE:
  2476. WARN_ON(!sta_priv->client);
  2477. if (!sta_priv->asleep)
  2478. break;
  2479. sta_priv->asleep = false;
  2480. sta_id = iwl_find_station(priv, sta->addr);
  2481. if (sta_id != IWL_INVALID_STATION)
  2482. iwl_sta_modify_ps_wake(priv, sta_id);
  2483. break;
  2484. default:
  2485. break;
  2486. }
  2487. }
  2488. /*****************************************************************************
  2489. *
  2490. * sysfs attributes
  2491. *
  2492. *****************************************************************************/
  2493. #ifdef CONFIG_IWLWIFI_DEBUG
  2494. /*
  2495. * The following adds a new attribute to the sysfs representation
  2496. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  2497. * used for controlling the debug level.
  2498. *
  2499. * See the level definitions in iwl for details.
  2500. *
  2501. * The debug_level being managed using sysfs below is a per device debug
  2502. * level that is used instead of the global debug level if it (the per
  2503. * device debug level) is set.
  2504. */
  2505. static ssize_t show_debug_level(struct device *d,
  2506. struct device_attribute *attr, char *buf)
  2507. {
  2508. struct iwl_priv *priv = dev_get_drvdata(d);
  2509. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  2510. }
  2511. static ssize_t store_debug_level(struct device *d,
  2512. struct device_attribute *attr,
  2513. const char *buf, size_t count)
  2514. {
  2515. struct iwl_priv *priv = dev_get_drvdata(d);
  2516. unsigned long val;
  2517. int ret;
  2518. ret = strict_strtoul(buf, 0, &val);
  2519. if (ret)
  2520. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  2521. else {
  2522. priv->debug_level = val;
  2523. if (iwl_alloc_traffic_mem(priv))
  2524. IWL_ERR(priv,
  2525. "Not enough memory to generate traffic log\n");
  2526. }
  2527. return strnlen(buf, count);
  2528. }
  2529. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2530. show_debug_level, store_debug_level);
  2531. #endif /* CONFIG_IWLWIFI_DEBUG */
  2532. static ssize_t show_temperature(struct device *d,
  2533. struct device_attribute *attr, char *buf)
  2534. {
  2535. struct iwl_priv *priv = dev_get_drvdata(d);
  2536. if (!iwl_is_alive(priv))
  2537. return -EAGAIN;
  2538. return sprintf(buf, "%d\n", priv->temperature);
  2539. }
  2540. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2541. static ssize_t show_tx_power(struct device *d,
  2542. struct device_attribute *attr, char *buf)
  2543. {
  2544. struct iwl_priv *priv = dev_get_drvdata(d);
  2545. if (!iwl_is_ready_rf(priv))
  2546. return sprintf(buf, "off\n");
  2547. else
  2548. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2549. }
  2550. static ssize_t store_tx_power(struct device *d,
  2551. struct device_attribute *attr,
  2552. const char *buf, size_t count)
  2553. {
  2554. struct iwl_priv *priv = dev_get_drvdata(d);
  2555. unsigned long val;
  2556. int ret;
  2557. ret = strict_strtoul(buf, 10, &val);
  2558. if (ret)
  2559. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  2560. else {
  2561. ret = iwl_set_tx_power(priv, val, false);
  2562. if (ret)
  2563. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  2564. ret);
  2565. else
  2566. ret = count;
  2567. }
  2568. return ret;
  2569. }
  2570. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2571. static ssize_t show_statistics(struct device *d,
  2572. struct device_attribute *attr, char *buf)
  2573. {
  2574. struct iwl_priv *priv = dev_get_drvdata(d);
  2575. u32 size = sizeof(struct iwl_notif_statistics);
  2576. u32 len = 0, ofs = 0;
  2577. u8 *data = (u8 *)&priv->statistics;
  2578. int rc = 0;
  2579. if (!iwl_is_alive(priv))
  2580. return -EAGAIN;
  2581. mutex_lock(&priv->mutex);
  2582. rc = iwl_send_statistics_request(priv, CMD_SYNC, false);
  2583. mutex_unlock(&priv->mutex);
  2584. if (rc) {
  2585. len = sprintf(buf,
  2586. "Error sending statistics request: 0x%08X\n", rc);
  2587. return len;
  2588. }
  2589. while (size && (PAGE_SIZE - len)) {
  2590. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2591. PAGE_SIZE - len, 1);
  2592. len = strlen(buf);
  2593. if (PAGE_SIZE - len)
  2594. buf[len++] = '\n';
  2595. ofs += 16;
  2596. size -= min(size, 16U);
  2597. }
  2598. return len;
  2599. }
  2600. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  2601. static ssize_t show_rts_ht_protection(struct device *d,
  2602. struct device_attribute *attr, char *buf)
  2603. {
  2604. struct iwl_priv *priv = dev_get_drvdata(d);
  2605. return sprintf(buf, "%s\n",
  2606. priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
  2607. }
  2608. static ssize_t store_rts_ht_protection(struct device *d,
  2609. struct device_attribute *attr,
  2610. const char *buf, size_t count)
  2611. {
  2612. struct iwl_priv *priv = dev_get_drvdata(d);
  2613. unsigned long val;
  2614. int ret;
  2615. ret = strict_strtoul(buf, 10, &val);
  2616. if (ret)
  2617. IWL_INFO(priv, "Input is not in decimal form.\n");
  2618. else {
  2619. if (!iwl_is_associated(priv))
  2620. priv->cfg->use_rts_for_ht = val ? true : false;
  2621. else
  2622. IWL_ERR(priv, "Sta associated with AP - "
  2623. "Change protection mechanism is not allowed\n");
  2624. ret = count;
  2625. }
  2626. return ret;
  2627. }
  2628. static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
  2629. show_rts_ht_protection, store_rts_ht_protection);
  2630. /*****************************************************************************
  2631. *
  2632. * driver setup and teardown
  2633. *
  2634. *****************************************************************************/
  2635. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2636. {
  2637. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2638. init_waitqueue_head(&priv->wait_command_queue);
  2639. INIT_WORK(&priv->restart, iwl_bg_restart);
  2640. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2641. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2642. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2643. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2644. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2645. iwl_setup_scan_deferred_work(priv);
  2646. if (priv->cfg->ops->lib->setup_deferred_work)
  2647. priv->cfg->ops->lib->setup_deferred_work(priv);
  2648. init_timer(&priv->statistics_periodic);
  2649. priv->statistics_periodic.data = (unsigned long)priv;
  2650. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2651. init_timer(&priv->ucode_trace);
  2652. priv->ucode_trace.data = (unsigned long)priv;
  2653. priv->ucode_trace.function = iwl_bg_ucode_trace;
  2654. if (!priv->cfg->use_isr_legacy)
  2655. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2656. iwl_irq_tasklet, (unsigned long)priv);
  2657. else
  2658. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2659. iwl_irq_tasklet_legacy, (unsigned long)priv);
  2660. }
  2661. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2662. {
  2663. if (priv->cfg->ops->lib->cancel_deferred_work)
  2664. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2665. cancel_delayed_work_sync(&priv->init_alive_start);
  2666. cancel_delayed_work(&priv->scan_check);
  2667. cancel_delayed_work(&priv->alive_start);
  2668. cancel_work_sync(&priv->beacon_update);
  2669. del_timer_sync(&priv->statistics_periodic);
  2670. del_timer_sync(&priv->ucode_trace);
  2671. }
  2672. static void iwl_init_hw_rates(struct iwl_priv *priv,
  2673. struct ieee80211_rate *rates)
  2674. {
  2675. int i;
  2676. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  2677. rates[i].bitrate = iwl_rates[i].ieee * 5;
  2678. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  2679. rates[i].hw_value_short = i;
  2680. rates[i].flags = 0;
  2681. if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
  2682. /*
  2683. * If CCK != 1M then set short preamble rate flag.
  2684. */
  2685. rates[i].flags |=
  2686. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  2687. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  2688. }
  2689. }
  2690. }
  2691. static int iwl_init_drv(struct iwl_priv *priv)
  2692. {
  2693. int ret;
  2694. priv->ibss_beacon = NULL;
  2695. spin_lock_init(&priv->sta_lock);
  2696. spin_lock_init(&priv->hcmd_lock);
  2697. INIT_LIST_HEAD(&priv->free_frames);
  2698. mutex_init(&priv->mutex);
  2699. mutex_init(&priv->sync_cmd_mutex);
  2700. priv->ieee_channels = NULL;
  2701. priv->ieee_rates = NULL;
  2702. priv->band = IEEE80211_BAND_2GHZ;
  2703. priv->iw_mode = NL80211_IFTYPE_STATION;
  2704. priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
  2705. priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
  2706. /* initialize force reset */
  2707. priv->force_reset[IWL_RF_RESET].reset_duration =
  2708. IWL_DELAY_NEXT_FORCE_RF_RESET;
  2709. priv->force_reset[IWL_FW_RESET].reset_duration =
  2710. IWL_DELAY_NEXT_FORCE_FW_RELOAD;
  2711. /* Choose which receivers/antennas to use */
  2712. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2713. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2714. iwl_init_scan_params(priv);
  2715. iwl_reset_qos(priv);
  2716. priv->qos_data.qos_active = 0;
  2717. priv->qos_data.qos_cap.val = 0;
  2718. /* Set the tx_power_user_lmt to the lowest power level
  2719. * this value will get overwritten by channel max power avg
  2720. * from eeprom */
  2721. priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
  2722. ret = iwl_init_channel_map(priv);
  2723. if (ret) {
  2724. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  2725. goto err;
  2726. }
  2727. ret = iwlcore_init_geos(priv);
  2728. if (ret) {
  2729. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  2730. goto err_free_channel_map;
  2731. }
  2732. iwl_init_hw_rates(priv, priv->ieee_rates);
  2733. return 0;
  2734. err_free_channel_map:
  2735. iwl_free_channel_map(priv);
  2736. err:
  2737. return ret;
  2738. }
  2739. static void iwl_uninit_drv(struct iwl_priv *priv)
  2740. {
  2741. iwl_calib_free_results(priv);
  2742. iwlcore_free_geos(priv);
  2743. iwl_free_channel_map(priv);
  2744. kfree(priv->scan);
  2745. }
  2746. static struct attribute *iwl_sysfs_entries[] = {
  2747. &dev_attr_statistics.attr,
  2748. &dev_attr_temperature.attr,
  2749. &dev_attr_tx_power.attr,
  2750. &dev_attr_rts_ht_protection.attr,
  2751. #ifdef CONFIG_IWLWIFI_DEBUG
  2752. &dev_attr_debug_level.attr,
  2753. #endif
  2754. NULL
  2755. };
  2756. static struct attribute_group iwl_attribute_group = {
  2757. .name = NULL, /* put in device directory */
  2758. .attrs = iwl_sysfs_entries,
  2759. };
  2760. static struct ieee80211_ops iwl_hw_ops = {
  2761. .tx = iwl_mac_tx,
  2762. .start = iwl_mac_start,
  2763. .stop = iwl_mac_stop,
  2764. .add_interface = iwl_mac_add_interface,
  2765. .remove_interface = iwl_mac_remove_interface,
  2766. .config = iwl_mac_config,
  2767. .configure_filter = iwl_configure_filter,
  2768. .set_key = iwl_mac_set_key,
  2769. .update_tkip_key = iwl_mac_update_tkip_key,
  2770. .get_stats = iwl_mac_get_stats,
  2771. .conf_tx = iwl_mac_conf_tx,
  2772. .reset_tsf = iwl_mac_reset_tsf,
  2773. .bss_info_changed = iwl_bss_info_changed,
  2774. .ampdu_action = iwl_mac_ampdu_action,
  2775. .hw_scan = iwl_mac_hw_scan,
  2776. .sta_notify = iwl_mac_sta_notify,
  2777. };
  2778. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2779. {
  2780. int err = 0;
  2781. struct iwl_priv *priv;
  2782. struct ieee80211_hw *hw;
  2783. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2784. unsigned long flags;
  2785. u16 pci_cmd;
  2786. /************************
  2787. * 1. Allocating HW data
  2788. ************************/
  2789. /* Disabling hardware scan means that mac80211 will perform scans
  2790. * "the hard way", rather than using device's scan. */
  2791. if (cfg->mod_params->disable_hw_scan) {
  2792. if (iwl_debug_level & IWL_DL_INFO)
  2793. dev_printk(KERN_DEBUG, &(pdev->dev),
  2794. "Disabling hw_scan\n");
  2795. iwl_hw_ops.hw_scan = NULL;
  2796. }
  2797. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  2798. if (!hw) {
  2799. err = -ENOMEM;
  2800. goto out;
  2801. }
  2802. priv = hw->priv;
  2803. /* At this point both hw and priv are allocated. */
  2804. SET_IEEE80211_DEV(hw, &pdev->dev);
  2805. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2806. priv->cfg = cfg;
  2807. priv->pci_dev = pdev;
  2808. priv->inta_mask = CSR_INI_SET_MASK;
  2809. #ifdef CONFIG_IWLWIFI_DEBUG
  2810. atomic_set(&priv->restrict_refcnt, 0);
  2811. #endif
  2812. if (iwl_alloc_traffic_mem(priv))
  2813. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  2814. /**************************
  2815. * 2. Initializing PCI bus
  2816. **************************/
  2817. if (pci_enable_device(pdev)) {
  2818. err = -ENODEV;
  2819. goto out_ieee80211_free_hw;
  2820. }
  2821. pci_set_master(pdev);
  2822. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2823. if (!err)
  2824. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2825. if (err) {
  2826. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2827. if (!err)
  2828. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2829. /* both attempts failed: */
  2830. if (err) {
  2831. IWL_WARN(priv, "No suitable DMA available.\n");
  2832. goto out_pci_disable_device;
  2833. }
  2834. }
  2835. err = pci_request_regions(pdev, DRV_NAME);
  2836. if (err)
  2837. goto out_pci_disable_device;
  2838. pci_set_drvdata(pdev, priv);
  2839. /***********************
  2840. * 3. Read REV register
  2841. ***********************/
  2842. priv->hw_base = pci_iomap(pdev, 0, 0);
  2843. if (!priv->hw_base) {
  2844. err = -ENODEV;
  2845. goto out_pci_release_regions;
  2846. }
  2847. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2848. (unsigned long long) pci_resource_len(pdev, 0));
  2849. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2850. /* these spin locks will be used in apm_ops.init and EEPROM access
  2851. * we should init now
  2852. */
  2853. spin_lock_init(&priv->reg_lock);
  2854. spin_lock_init(&priv->lock);
  2855. /*
  2856. * stop and reset the on-board processor just in case it is in a
  2857. * strange state ... like being left stranded by a primary kernel
  2858. * and this is now the kdump kernel trying to start up
  2859. */
  2860. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  2861. iwl_hw_detect(priv);
  2862. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
  2863. priv->cfg->name, priv->hw_rev);
  2864. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2865. * PCI Tx retries from interfering with C3 CPU state */
  2866. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2867. iwl_prepare_card_hw(priv);
  2868. if (!priv->hw_ready) {
  2869. IWL_WARN(priv, "Failed, HW not ready\n");
  2870. goto out_iounmap;
  2871. }
  2872. /*****************
  2873. * 4. Read EEPROM
  2874. *****************/
  2875. /* Read the EEPROM */
  2876. err = iwl_eeprom_init(priv);
  2877. if (err) {
  2878. IWL_ERR(priv, "Unable to init EEPROM\n");
  2879. goto out_iounmap;
  2880. }
  2881. err = iwl_eeprom_check_version(priv);
  2882. if (err)
  2883. goto out_free_eeprom;
  2884. /* extract MAC Address */
  2885. iwl_eeprom_get_mac(priv, priv->mac_addr);
  2886. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  2887. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  2888. /************************
  2889. * 5. Setup HW constants
  2890. ************************/
  2891. if (iwl_set_hw_params(priv)) {
  2892. IWL_ERR(priv, "failed to set hw parameters\n");
  2893. goto out_free_eeprom;
  2894. }
  2895. /*******************
  2896. * 6. Setup priv
  2897. *******************/
  2898. err = iwl_init_drv(priv);
  2899. if (err)
  2900. goto out_free_eeprom;
  2901. /* At this point both hw and priv are initialized. */
  2902. /********************
  2903. * 7. Setup services
  2904. ********************/
  2905. spin_lock_irqsave(&priv->lock, flags);
  2906. iwl_disable_interrupts(priv);
  2907. spin_unlock_irqrestore(&priv->lock, flags);
  2908. pci_enable_msi(priv->pci_dev);
  2909. iwl_alloc_isr_ict(priv);
  2910. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  2911. IRQF_SHARED, DRV_NAME, priv);
  2912. if (err) {
  2913. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  2914. goto out_disable_msi;
  2915. }
  2916. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  2917. if (err) {
  2918. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  2919. goto out_free_irq;
  2920. }
  2921. iwl_setup_deferred_work(priv);
  2922. iwl_setup_rx_handlers(priv);
  2923. /*********************************************
  2924. * 8. Enable interrupts and read RFKILL state
  2925. *********************************************/
  2926. /* enable interrupts if needed: hw bug w/a */
  2927. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  2928. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  2929. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  2930. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  2931. }
  2932. iwl_enable_interrupts(priv);
  2933. /* If platform's RF_KILL switch is NOT set to KILL */
  2934. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2935. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2936. else
  2937. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2938. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  2939. test_bit(STATUS_RF_KILL_HW, &priv->status));
  2940. iwl_power_initialize(priv);
  2941. iwl_tt_initialize(priv);
  2942. err = iwl_request_firmware(priv, true);
  2943. if (err)
  2944. goto out_remove_sysfs;
  2945. return 0;
  2946. out_remove_sysfs:
  2947. destroy_workqueue(priv->workqueue);
  2948. priv->workqueue = NULL;
  2949. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2950. out_free_irq:
  2951. free_irq(priv->pci_dev->irq, priv);
  2952. iwl_free_isr_ict(priv);
  2953. out_disable_msi:
  2954. pci_disable_msi(priv->pci_dev);
  2955. iwl_uninit_drv(priv);
  2956. out_free_eeprom:
  2957. iwl_eeprom_free(priv);
  2958. out_iounmap:
  2959. pci_iounmap(pdev, priv->hw_base);
  2960. out_pci_release_regions:
  2961. pci_set_drvdata(pdev, NULL);
  2962. pci_release_regions(pdev);
  2963. out_pci_disable_device:
  2964. pci_disable_device(pdev);
  2965. out_ieee80211_free_hw:
  2966. iwl_free_traffic_mem(priv);
  2967. ieee80211_free_hw(priv->hw);
  2968. out:
  2969. return err;
  2970. }
  2971. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  2972. {
  2973. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2974. unsigned long flags;
  2975. if (!priv)
  2976. return;
  2977. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  2978. iwl_dbgfs_unregister(priv);
  2979. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2980. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  2981. * to be called and iwl_down since we are removing the device
  2982. * we need to set STATUS_EXIT_PENDING bit.
  2983. */
  2984. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2985. if (priv->mac80211_registered) {
  2986. ieee80211_unregister_hw(priv->hw);
  2987. priv->mac80211_registered = 0;
  2988. } else {
  2989. iwl_down(priv);
  2990. }
  2991. /*
  2992. * Make sure device is reset to low power before unloading driver.
  2993. * This may be redundant with iwl_down(), but there are paths to
  2994. * run iwl_down() without calling apm_ops.stop(), and there are
  2995. * paths to avoid running iwl_down() at all before leaving driver.
  2996. * This (inexpensive) call *makes sure* device is reset.
  2997. */
  2998. priv->cfg->ops->lib->apm_ops.stop(priv);
  2999. iwl_tt_exit(priv);
  3000. /* make sure we flush any pending irq or
  3001. * tasklet for the driver
  3002. */
  3003. spin_lock_irqsave(&priv->lock, flags);
  3004. iwl_disable_interrupts(priv);
  3005. spin_unlock_irqrestore(&priv->lock, flags);
  3006. iwl_synchronize_irq(priv);
  3007. iwl_dealloc_ucode_pci(priv);
  3008. if (priv->rxq.bd)
  3009. iwl_rx_queue_free(priv, &priv->rxq);
  3010. iwl_hw_txq_ctx_free(priv);
  3011. iwl_eeprom_free(priv);
  3012. /*netif_stop_queue(dev); */
  3013. flush_workqueue(priv->workqueue);
  3014. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  3015. * priv->workqueue... so we can't take down the workqueue
  3016. * until now... */
  3017. destroy_workqueue(priv->workqueue);
  3018. priv->workqueue = NULL;
  3019. iwl_free_traffic_mem(priv);
  3020. free_irq(priv->pci_dev->irq, priv);
  3021. pci_disable_msi(priv->pci_dev);
  3022. pci_iounmap(pdev, priv->hw_base);
  3023. pci_release_regions(pdev);
  3024. pci_disable_device(pdev);
  3025. pci_set_drvdata(pdev, NULL);
  3026. iwl_uninit_drv(priv);
  3027. iwl_free_isr_ict(priv);
  3028. if (priv->ibss_beacon)
  3029. dev_kfree_skb(priv->ibss_beacon);
  3030. ieee80211_free_hw(priv->hw);
  3031. }
  3032. /*****************************************************************************
  3033. *
  3034. * driver and module entry point
  3035. *
  3036. *****************************************************************************/
  3037. /* Hardware specific file defines the PCI IDs table for that hardware module */
  3038. static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
  3039. #ifdef CONFIG_IWL4965
  3040. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  3041. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  3042. #endif /* CONFIG_IWL4965 */
  3043. #ifdef CONFIG_IWL5000
  3044. /* 5100 Series WiFi */
  3045. {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
  3046. {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
  3047. {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
  3048. {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
  3049. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
  3050. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3051. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
  3052. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
  3053. {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
  3054. {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
  3055. {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
  3056. {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
  3057. {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
  3058. {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3059. {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
  3060. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
  3061. {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
  3062. {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
  3063. {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
  3064. {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
  3065. {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
  3066. {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3067. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
  3068. {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
  3069. /* 5300 Series WiFi */
  3070. {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
  3071. {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
  3072. {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
  3073. {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
  3074. {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
  3075. {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
  3076. {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
  3077. {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
  3078. {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
  3079. {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
  3080. {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
  3081. {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
  3082. /* 5350 Series WiFi/WiMax */
  3083. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
  3084. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
  3085. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
  3086. /* 5150 Series Wifi/WiMax */
  3087. {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
  3088. {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
  3089. {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
  3090. {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
  3091. {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
  3092. {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
  3093. {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
  3094. {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
  3095. {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
  3096. {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
  3097. /* 6x00 Series */
  3098. {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
  3099. {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
  3100. {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
  3101. {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
  3102. {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
  3103. {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
  3104. {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
  3105. {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
  3106. {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
  3107. {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
  3108. /* 6x50 WiFi/WiMax Series */
  3109. {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
  3110. {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
  3111. {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
  3112. {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
  3113. {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
  3114. {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
  3115. /* 1000 Series WiFi */
  3116. {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
  3117. {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
  3118. {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
  3119. {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
  3120. {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
  3121. {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
  3122. {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
  3123. {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
  3124. {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
  3125. {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
  3126. {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
  3127. {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
  3128. #endif /* CONFIG_IWL5000 */
  3129. {0}
  3130. };
  3131. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  3132. static struct pci_driver iwl_driver = {
  3133. .name = DRV_NAME,
  3134. .id_table = iwl_hw_card_ids,
  3135. .probe = iwl_pci_probe,
  3136. .remove = __devexit_p(iwl_pci_remove),
  3137. #ifdef CONFIG_PM
  3138. .suspend = iwl_pci_suspend,
  3139. .resume = iwl_pci_resume,
  3140. #endif
  3141. };
  3142. static int __init iwl_init(void)
  3143. {
  3144. int ret;
  3145. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3146. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  3147. ret = iwlagn_rate_control_register();
  3148. if (ret) {
  3149. printk(KERN_ERR DRV_NAME
  3150. "Unable to register rate control algorithm: %d\n", ret);
  3151. return ret;
  3152. }
  3153. ret = pci_register_driver(&iwl_driver);
  3154. if (ret) {
  3155. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  3156. goto error_register;
  3157. }
  3158. return ret;
  3159. error_register:
  3160. iwlagn_rate_control_unregister();
  3161. return ret;
  3162. }
  3163. static void __exit iwl_exit(void)
  3164. {
  3165. pci_unregister_driver(&iwl_driver);
  3166. iwlagn_rate_control_unregister();
  3167. }
  3168. module_exit(iwl_exit);
  3169. module_init(iwl_init);
  3170. #ifdef CONFIG_IWLWIFI_DEBUG
  3171. module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
  3172. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  3173. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  3174. MODULE_PARM_DESC(debug, "debug output mask");
  3175. #endif