pasemi_mac.c 35 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431
  1. /*
  2. * Copyright (C) 2006-2007 PA Semi, Inc
  3. *
  4. * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/init.h>
  20. #include <linux/module.h>
  21. #include <linux/pci.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/dmaengine.h>
  24. #include <linux/delay.h>
  25. #include <linux/netdevice.h>
  26. #include <linux/etherdevice.h>
  27. #include <asm/dma-mapping.h>
  28. #include <linux/in.h>
  29. #include <linux/skbuff.h>
  30. #include <linux/ip.h>
  31. #include <linux/tcp.h>
  32. #include <net/checksum.h>
  33. #include <asm/irq.h>
  34. #include "pasemi_mac.h"
  35. /* We have our own align, since ppc64 in general has it at 0 because
  36. * of design flaws in some of the server bridge chips. However, for
  37. * PWRficient doing the unaligned copies is more expensive than doing
  38. * unaligned DMA, so make sure the data is aligned instead.
  39. */
  40. #define LOCAL_SKB_ALIGN 2
  41. /* TODO list
  42. *
  43. * - Multicast support
  44. * - Large MTU support
  45. * - SW LRO
  46. * - Multiqueue RX/TX
  47. */
  48. /* Must be a power of two */
  49. #define RX_RING_SIZE 4096
  50. #define TX_RING_SIZE 4096
  51. #define DEFAULT_MSG_ENABLE \
  52. (NETIF_MSG_DRV | \
  53. NETIF_MSG_PROBE | \
  54. NETIF_MSG_LINK | \
  55. NETIF_MSG_TIMER | \
  56. NETIF_MSG_IFDOWN | \
  57. NETIF_MSG_IFUP | \
  58. NETIF_MSG_RX_ERR | \
  59. NETIF_MSG_TX_ERR)
  60. #define TX_RING(mac, num) ((mac)->tx->ring[(num) & (TX_RING_SIZE-1)])
  61. #define TX_RING_INFO(mac, num) ((mac)->tx->ring_info[(num) & (TX_RING_SIZE-1)])
  62. #define RX_RING(mac, num) ((mac)->rx->ring[(num) & (RX_RING_SIZE-1)])
  63. #define RX_RING_INFO(mac, num) ((mac)->rx->ring_info[(num) & (RX_RING_SIZE-1)])
  64. #define RX_BUFF(mac, num) ((mac)->rx->buffers[(num) & (RX_RING_SIZE-1)])
  65. #define RING_USED(ring) (((ring)->next_to_fill - (ring)->next_to_clean) \
  66. & ((ring)->size - 1))
  67. #define RING_AVAIL(ring) ((ring->size) - RING_USED(ring))
  68. #define BUF_SIZE 1646 /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
  69. MODULE_LICENSE("GPL");
  70. MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
  71. MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver");
  72. static int debug = -1; /* -1 == use DEFAULT_MSG_ENABLE as value */
  73. module_param(debug, int, 0);
  74. MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value");
  75. static struct pasdma_status *dma_status;
  76. static void write_iob_reg(struct pasemi_mac *mac, unsigned int reg,
  77. unsigned int val)
  78. {
  79. out_le32(mac->iob_regs+reg, val);
  80. }
  81. static unsigned int read_mac_reg(struct pasemi_mac *mac, unsigned int reg)
  82. {
  83. return in_le32(mac->regs+reg);
  84. }
  85. static void write_mac_reg(struct pasemi_mac *mac, unsigned int reg,
  86. unsigned int val)
  87. {
  88. out_le32(mac->regs+reg, val);
  89. }
  90. static unsigned int read_dma_reg(struct pasemi_mac *mac, unsigned int reg)
  91. {
  92. return in_le32(mac->dma_regs+reg);
  93. }
  94. static void write_dma_reg(struct pasemi_mac *mac, unsigned int reg,
  95. unsigned int val)
  96. {
  97. out_le32(mac->dma_regs+reg, val);
  98. }
  99. static int pasemi_get_mac_addr(struct pasemi_mac *mac)
  100. {
  101. struct pci_dev *pdev = mac->pdev;
  102. struct device_node *dn = pci_device_to_OF_node(pdev);
  103. int len;
  104. const u8 *maddr;
  105. u8 addr[6];
  106. if (!dn) {
  107. dev_dbg(&pdev->dev,
  108. "No device node for mac, not configuring\n");
  109. return -ENOENT;
  110. }
  111. maddr = of_get_property(dn, "local-mac-address", &len);
  112. if (maddr && len == 6) {
  113. memcpy(mac->mac_addr, maddr, 6);
  114. return 0;
  115. }
  116. /* Some old versions of firmware mistakenly uses mac-address
  117. * (and as a string) instead of a byte array in local-mac-address.
  118. */
  119. if (maddr == NULL)
  120. maddr = of_get_property(dn, "mac-address", NULL);
  121. if (maddr == NULL) {
  122. dev_warn(&pdev->dev,
  123. "no mac address in device tree, not configuring\n");
  124. return -ENOENT;
  125. }
  126. if (sscanf(maddr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &addr[0],
  127. &addr[1], &addr[2], &addr[3], &addr[4], &addr[5]) != 6) {
  128. dev_warn(&pdev->dev,
  129. "can't parse mac address, not configuring\n");
  130. return -EINVAL;
  131. }
  132. memcpy(mac->mac_addr, addr, 6);
  133. return 0;
  134. }
  135. static int pasemi_mac_unmap_tx_skb(struct pasemi_mac *mac,
  136. struct sk_buff *skb,
  137. dma_addr_t *dmas)
  138. {
  139. int f;
  140. int nfrags = skb_shinfo(skb)->nr_frags;
  141. pci_unmap_single(mac->dma_pdev, dmas[0], skb_headlen(skb),
  142. PCI_DMA_TODEVICE);
  143. for (f = 0; f < nfrags; f++) {
  144. skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
  145. pci_unmap_page(mac->dma_pdev, dmas[f+1], frag->size,
  146. PCI_DMA_TODEVICE);
  147. }
  148. dev_kfree_skb_irq(skb);
  149. /* Freed descriptor slot + main SKB ptr + nfrags additional ptrs,
  150. * aligned up to a power of 2
  151. */
  152. return (nfrags + 3) & ~1;
  153. }
  154. static int pasemi_mac_setup_rx_resources(struct net_device *dev)
  155. {
  156. struct pasemi_mac_rxring *ring;
  157. struct pasemi_mac *mac = netdev_priv(dev);
  158. int chan_id = mac->dma_rxch;
  159. ring = kzalloc(sizeof(*ring), GFP_KERNEL);
  160. if (!ring)
  161. goto out_ring;
  162. spin_lock_init(&ring->lock);
  163. ring->size = RX_RING_SIZE;
  164. ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
  165. RX_RING_SIZE, GFP_KERNEL);
  166. if (!ring->ring_info)
  167. goto out_ring_info;
  168. /* Allocate descriptors */
  169. ring->ring = dma_alloc_coherent(&mac->dma_pdev->dev,
  170. RX_RING_SIZE * sizeof(u64),
  171. &ring->dma, GFP_KERNEL);
  172. if (!ring->ring)
  173. goto out_ring_desc;
  174. memset(ring->ring, 0, RX_RING_SIZE * sizeof(u64));
  175. ring->buffers = dma_alloc_coherent(&mac->dma_pdev->dev,
  176. RX_RING_SIZE * sizeof(u64),
  177. &ring->buf_dma, GFP_KERNEL);
  178. if (!ring->buffers)
  179. goto out_buffers;
  180. memset(ring->buffers, 0, RX_RING_SIZE * sizeof(u64));
  181. write_dma_reg(mac, PAS_DMA_RXCHAN_BASEL(chan_id), PAS_DMA_RXCHAN_BASEL_BRBL(ring->dma));
  182. write_dma_reg(mac, PAS_DMA_RXCHAN_BASEU(chan_id),
  183. PAS_DMA_RXCHAN_BASEU_BRBH(ring->dma >> 32) |
  184. PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 3));
  185. write_dma_reg(mac, PAS_DMA_RXCHAN_CFG(chan_id),
  186. PAS_DMA_RXCHAN_CFG_HBU(2));
  187. write_dma_reg(mac, PAS_DMA_RXINT_BASEL(mac->dma_if),
  188. PAS_DMA_RXINT_BASEL_BRBL(__pa(ring->buffers)));
  189. write_dma_reg(mac, PAS_DMA_RXINT_BASEU(mac->dma_if),
  190. PAS_DMA_RXINT_BASEU_BRBH(__pa(ring->buffers) >> 32) |
  191. PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3));
  192. write_dma_reg(mac, PAS_DMA_RXINT_CFG(mac->dma_if),
  193. PAS_DMA_RXINT_CFG_DHL(3) |
  194. PAS_DMA_RXINT_CFG_L2 |
  195. PAS_DMA_RXINT_CFG_LW);
  196. ring->next_to_fill = 0;
  197. ring->next_to_clean = 0;
  198. snprintf(ring->irq_name, sizeof(ring->irq_name),
  199. "%s rx", dev->name);
  200. mac->rx = ring;
  201. return 0;
  202. out_buffers:
  203. dma_free_coherent(&mac->dma_pdev->dev,
  204. RX_RING_SIZE * sizeof(u64),
  205. mac->rx->ring, mac->rx->dma);
  206. out_ring_desc:
  207. kfree(ring->ring_info);
  208. out_ring_info:
  209. kfree(ring);
  210. out_ring:
  211. return -ENOMEM;
  212. }
  213. static int pasemi_mac_setup_tx_resources(struct net_device *dev)
  214. {
  215. struct pasemi_mac *mac = netdev_priv(dev);
  216. u32 val;
  217. int chan_id = mac->dma_txch;
  218. struct pasemi_mac_txring *ring;
  219. ring = kzalloc(sizeof(*ring), GFP_KERNEL);
  220. if (!ring)
  221. goto out_ring;
  222. spin_lock_init(&ring->lock);
  223. ring->size = TX_RING_SIZE;
  224. ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
  225. TX_RING_SIZE, GFP_KERNEL);
  226. if (!ring->ring_info)
  227. goto out_ring_info;
  228. /* Allocate descriptors */
  229. ring->ring = dma_alloc_coherent(&mac->dma_pdev->dev,
  230. TX_RING_SIZE * sizeof(u64),
  231. &ring->dma, GFP_KERNEL);
  232. if (!ring->ring)
  233. goto out_ring_desc;
  234. memset(ring->ring, 0, TX_RING_SIZE * sizeof(u64));
  235. write_dma_reg(mac, PAS_DMA_TXCHAN_BASEL(chan_id),
  236. PAS_DMA_TXCHAN_BASEL_BRBL(ring->dma));
  237. val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->dma >> 32);
  238. val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 3);
  239. write_dma_reg(mac, PAS_DMA_TXCHAN_BASEU(chan_id), val);
  240. write_dma_reg(mac, PAS_DMA_TXCHAN_CFG(chan_id),
  241. PAS_DMA_TXCHAN_CFG_TY_IFACE |
  242. PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) |
  243. PAS_DMA_TXCHAN_CFG_UP |
  244. PAS_DMA_TXCHAN_CFG_WT(2));
  245. ring->next_to_fill = 0;
  246. ring->next_to_clean = 0;
  247. snprintf(ring->irq_name, sizeof(ring->irq_name),
  248. "%s tx", dev->name);
  249. mac->tx = ring;
  250. return 0;
  251. out_ring_desc:
  252. kfree(ring->ring_info);
  253. out_ring_info:
  254. kfree(ring);
  255. out_ring:
  256. return -ENOMEM;
  257. }
  258. static void pasemi_mac_free_tx_resources(struct net_device *dev)
  259. {
  260. struct pasemi_mac *mac = netdev_priv(dev);
  261. unsigned int i, j;
  262. struct pasemi_mac_buffer *info;
  263. dma_addr_t dmas[MAX_SKB_FRAGS+1];
  264. int freed;
  265. int start, limit;
  266. start = mac->tx->next_to_clean;
  267. limit = mac->tx->next_to_fill;
  268. /* Compensate for when fill has wrapped and clean has not */
  269. if (start > limit)
  270. limit += TX_RING_SIZE;
  271. for (i = start; i < limit; i += freed) {
  272. info = &TX_RING_INFO(mac, i+1);
  273. if (info->dma && info->skb) {
  274. for (j = 0; j <= skb_shinfo(info->skb)->nr_frags; j++)
  275. dmas[j] = TX_RING_INFO(mac, i+1+j).dma;
  276. freed = pasemi_mac_unmap_tx_skb(mac, info->skb, dmas);
  277. } else
  278. freed = 2;
  279. }
  280. for (i = 0; i < TX_RING_SIZE; i++)
  281. TX_RING(mac, i) = 0;
  282. dma_free_coherent(&mac->dma_pdev->dev,
  283. TX_RING_SIZE * sizeof(u64),
  284. mac->tx->ring, mac->tx->dma);
  285. kfree(mac->tx->ring_info);
  286. kfree(mac->tx);
  287. mac->tx = NULL;
  288. }
  289. static void pasemi_mac_free_rx_resources(struct net_device *dev)
  290. {
  291. struct pasemi_mac *mac = netdev_priv(dev);
  292. unsigned int i;
  293. struct pasemi_mac_buffer *info;
  294. for (i = 0; i < RX_RING_SIZE; i++) {
  295. info = &RX_RING_INFO(mac, i);
  296. if (info->skb && info->dma) {
  297. pci_unmap_single(mac->dma_pdev,
  298. info->dma,
  299. info->skb->len,
  300. PCI_DMA_FROMDEVICE);
  301. dev_kfree_skb_any(info->skb);
  302. }
  303. info->dma = 0;
  304. info->skb = NULL;
  305. }
  306. for (i = 0; i < RX_RING_SIZE; i++)
  307. RX_RING(mac, i) = 0;
  308. dma_free_coherent(&mac->dma_pdev->dev,
  309. RX_RING_SIZE * sizeof(u64),
  310. mac->rx->ring, mac->rx->dma);
  311. dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64),
  312. mac->rx->buffers, mac->rx->buf_dma);
  313. kfree(mac->rx->ring_info);
  314. kfree(mac->rx);
  315. mac->rx = NULL;
  316. }
  317. static void pasemi_mac_replenish_rx_ring(struct net_device *dev, int limit)
  318. {
  319. struct pasemi_mac *mac = netdev_priv(dev);
  320. int start = mac->rx->next_to_fill;
  321. unsigned int fill, count;
  322. if (limit <= 0)
  323. return;
  324. fill = start;
  325. for (count = 0; count < limit; count++) {
  326. struct pasemi_mac_buffer *info = &RX_RING_INFO(mac, fill);
  327. u64 *buff = &RX_BUFF(mac, fill);
  328. struct sk_buff *skb;
  329. dma_addr_t dma;
  330. /* Entry in use? */
  331. WARN_ON(*buff);
  332. /* skb might still be in there for recycle on short receives */
  333. if (info->skb)
  334. skb = info->skb;
  335. else {
  336. skb = dev_alloc_skb(BUF_SIZE);
  337. skb_reserve(skb, LOCAL_SKB_ALIGN);
  338. }
  339. if (unlikely(!skb))
  340. break;
  341. dma = pci_map_single(mac->dma_pdev, skb->data,
  342. BUF_SIZE - LOCAL_SKB_ALIGN,
  343. PCI_DMA_FROMDEVICE);
  344. if (unlikely(dma_mapping_error(dma))) {
  345. dev_kfree_skb_irq(info->skb);
  346. break;
  347. }
  348. info->skb = skb;
  349. info->dma = dma;
  350. *buff = XCT_RXB_LEN(BUF_SIZE) | XCT_RXB_ADDR(dma);
  351. fill++;
  352. }
  353. wmb();
  354. write_dma_reg(mac, PAS_DMA_RXCHAN_INCR(mac->dma_rxch), count);
  355. write_dma_reg(mac, PAS_DMA_RXINT_INCR(mac->dma_if), count);
  356. mac->rx->next_to_fill += count;
  357. }
  358. static void pasemi_mac_restart_rx_intr(struct pasemi_mac *mac)
  359. {
  360. unsigned int reg, pcnt;
  361. /* Re-enable packet count interrupts: finally
  362. * ack the packet count interrupt we got in rx_intr.
  363. */
  364. pcnt = *mac->rx_status & PAS_STATUS_PCNT_M;
  365. reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC;
  366. write_iob_reg(mac, PAS_IOB_DMA_RXCH_RESET(mac->dma_rxch), reg);
  367. }
  368. static void pasemi_mac_restart_tx_intr(struct pasemi_mac *mac)
  369. {
  370. unsigned int reg, pcnt;
  371. /* Re-enable packet count interrupts */
  372. pcnt = *mac->tx_status & PAS_STATUS_PCNT_M;
  373. reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC;
  374. write_iob_reg(mac, PAS_IOB_DMA_TXCH_RESET(mac->dma_txch), reg);
  375. }
  376. static inline void pasemi_mac_rx_error(struct pasemi_mac *mac, u64 macrx)
  377. {
  378. unsigned int rcmdsta, ccmdsta;
  379. if (!netif_msg_rx_err(mac))
  380. return;
  381. rcmdsta = read_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
  382. ccmdsta = read_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch));
  383. printk(KERN_ERR "pasemi_mac: rx error. macrx %016lx, rx status %lx\n",
  384. macrx, *mac->rx_status);
  385. printk(KERN_ERR "pasemi_mac: rcmdsta %08x ccmdsta %08x\n",
  386. rcmdsta, ccmdsta);
  387. }
  388. static inline void pasemi_mac_tx_error(struct pasemi_mac *mac, u64 mactx)
  389. {
  390. unsigned int cmdsta;
  391. if (!netif_msg_tx_err(mac))
  392. return;
  393. cmdsta = read_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch));
  394. printk(KERN_ERR "pasemi_mac: tx error. mactx 0x%016lx, "\
  395. "tx status 0x%016lx\n", mactx, *mac->tx_status);
  396. printk(KERN_ERR "pasemi_mac: tcmdsta 0x%08x\n", cmdsta);
  397. }
  398. static int pasemi_mac_clean_rx(struct pasemi_mac *mac, int limit)
  399. {
  400. unsigned int n;
  401. int count;
  402. struct pasemi_mac_buffer *info;
  403. struct sk_buff *skb;
  404. unsigned int i, len;
  405. u64 macrx;
  406. dma_addr_t dma;
  407. spin_lock(&mac->rx->lock);
  408. n = mac->rx->next_to_clean;
  409. for (count = limit; count; count--) {
  410. macrx = RX_RING(mac, n);
  411. if ((macrx & XCT_MACRX_E) ||
  412. (*mac->rx_status & PAS_STATUS_ERROR))
  413. pasemi_mac_rx_error(mac, macrx);
  414. if (!(macrx & XCT_MACRX_O))
  415. break;
  416. info = NULL;
  417. /* We have to scan for our skb since there's no way
  418. * to back-map them from the descriptor, and if we
  419. * have several receive channels then they might not
  420. * show up in the same order as they were put on the
  421. * interface ring.
  422. */
  423. dma = (RX_RING(mac, n+1) & XCT_PTR_ADDR_M);
  424. for (i = mac->rx->next_to_fill;
  425. i < (mac->rx->next_to_fill + RX_RING_SIZE);
  426. i++) {
  427. info = &RX_RING_INFO(mac, i);
  428. if (info->dma == dma)
  429. break;
  430. }
  431. skb = info->skb;
  432. prefetch(skb);
  433. prefetch(&skb->data_len);
  434. len = (macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S;
  435. if (len < 256) {
  436. struct sk_buff *new_skb;
  437. new_skb = netdev_alloc_skb(mac->netdev,
  438. len + LOCAL_SKB_ALIGN);
  439. if (new_skb) {
  440. skb_reserve(new_skb, LOCAL_SKB_ALIGN);
  441. memcpy(new_skb->data, skb->data, len);
  442. /* save the skb in buffer_info as good */
  443. skb = new_skb;
  444. }
  445. /* else just continue with the old one */
  446. } else
  447. info->skb = NULL;
  448. pci_unmap_single(mac->dma_pdev, dma, len, PCI_DMA_FROMDEVICE);
  449. info->dma = 0;
  450. skb_put(skb, len);
  451. if (likely((macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK)) {
  452. skb->ip_summed = CHECKSUM_UNNECESSARY;
  453. skb->csum = (macrx & XCT_MACRX_CSUM_M) >>
  454. XCT_MACRX_CSUM_S;
  455. } else
  456. skb->ip_summed = CHECKSUM_NONE;
  457. mac->netdev->stats.rx_bytes += len;
  458. mac->netdev->stats.rx_packets++;
  459. skb->protocol = eth_type_trans(skb, mac->netdev);
  460. netif_receive_skb(skb);
  461. RX_RING(mac, n) = 0;
  462. RX_RING(mac, n+1) = 0;
  463. /* Need to zero it out since hardware doesn't, since the
  464. * replenish loop uses it to tell when it's done.
  465. */
  466. RX_BUFF(mac, i) = 0;
  467. n += 2;
  468. }
  469. if (n > RX_RING_SIZE) {
  470. /* Errata 5971 workaround: L2 target of headers */
  471. write_iob_reg(mac, PAS_IOB_COM_PKTHDRCNT, 0);
  472. n &= (RX_RING_SIZE-1);
  473. }
  474. mac->rx->next_to_clean = n;
  475. pasemi_mac_replenish_rx_ring(mac->netdev, limit-count);
  476. spin_unlock(&mac->rx->lock);
  477. return count;
  478. }
  479. /* Can't make this too large or we blow the kernel stack limits */
  480. #define TX_CLEAN_BATCHSIZE (128/MAX_SKB_FRAGS)
  481. static int pasemi_mac_clean_tx(struct pasemi_mac *mac)
  482. {
  483. int i, j;
  484. unsigned int start, descr_count, buf_count, batch_limit;
  485. unsigned int ring_limit;
  486. unsigned int total_count;
  487. unsigned long flags;
  488. struct sk_buff *skbs[TX_CLEAN_BATCHSIZE];
  489. dma_addr_t dmas[TX_CLEAN_BATCHSIZE][MAX_SKB_FRAGS+1];
  490. total_count = 0;
  491. batch_limit = TX_CLEAN_BATCHSIZE;
  492. restart:
  493. spin_lock_irqsave(&mac->tx->lock, flags);
  494. start = mac->tx->next_to_clean;
  495. ring_limit = mac->tx->next_to_fill;
  496. /* Compensate for when fill has wrapped but clean has not */
  497. if (start > ring_limit)
  498. ring_limit += TX_RING_SIZE;
  499. buf_count = 0;
  500. descr_count = 0;
  501. for (i = start;
  502. descr_count < batch_limit && i < ring_limit;
  503. i += buf_count) {
  504. u64 mactx = TX_RING(mac, i);
  505. struct sk_buff *skb;
  506. if ((mactx & XCT_MACTX_E) ||
  507. (*mac->tx_status & PAS_STATUS_ERROR))
  508. pasemi_mac_tx_error(mac, mactx);
  509. if (unlikely(mactx & XCT_MACTX_O))
  510. /* Not yet transmitted */
  511. break;
  512. skb = TX_RING_INFO(mac, i+1).skb;
  513. skbs[descr_count] = skb;
  514. buf_count = 2 + skb_shinfo(skb)->nr_frags;
  515. for (j = 0; j <= skb_shinfo(skb)->nr_frags; j++)
  516. dmas[descr_count][j] = TX_RING_INFO(mac, i+1+j).dma;
  517. TX_RING(mac, i) = 0;
  518. TX_RING(mac, i+1) = 0;
  519. /* Since we always fill with an even number of entries, make
  520. * sure we skip any unused one at the end as well.
  521. */
  522. if (buf_count & 1)
  523. buf_count++;
  524. descr_count++;
  525. }
  526. mac->tx->next_to_clean = i & (TX_RING_SIZE-1);
  527. spin_unlock_irqrestore(&mac->tx->lock, flags);
  528. netif_wake_queue(mac->netdev);
  529. for (i = 0; i < descr_count; i++)
  530. pasemi_mac_unmap_tx_skb(mac, skbs[i], dmas[i]);
  531. total_count += descr_count;
  532. /* If the batch was full, try to clean more */
  533. if (descr_count == batch_limit)
  534. goto restart;
  535. return total_count;
  536. }
  537. static irqreturn_t pasemi_mac_rx_intr(int irq, void *data)
  538. {
  539. struct net_device *dev = data;
  540. struct pasemi_mac *mac = netdev_priv(dev);
  541. unsigned int reg;
  542. if (!(*mac->rx_status & PAS_STATUS_CAUSE_M))
  543. return IRQ_NONE;
  544. /* Don't reset packet count so it won't fire again but clear
  545. * all others.
  546. */
  547. reg = 0;
  548. if (*mac->rx_status & PAS_STATUS_SOFT)
  549. reg |= PAS_IOB_DMA_RXCH_RESET_SINTC;
  550. if (*mac->rx_status & PAS_STATUS_ERROR)
  551. reg |= PAS_IOB_DMA_RXCH_RESET_DINTC;
  552. if (*mac->rx_status & PAS_STATUS_TIMER)
  553. reg |= PAS_IOB_DMA_RXCH_RESET_TINTC;
  554. netif_rx_schedule(dev, &mac->napi);
  555. write_iob_reg(mac, PAS_IOB_DMA_RXCH_RESET(mac->dma_rxch), reg);
  556. return IRQ_HANDLED;
  557. }
  558. static irqreturn_t pasemi_mac_tx_intr(int irq, void *data)
  559. {
  560. struct net_device *dev = data;
  561. struct pasemi_mac *mac = netdev_priv(dev);
  562. unsigned int reg, pcnt;
  563. if (!(*mac->tx_status & PAS_STATUS_CAUSE_M))
  564. return IRQ_NONE;
  565. pasemi_mac_clean_tx(mac);
  566. pcnt = *mac->tx_status & PAS_STATUS_PCNT_M;
  567. reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC;
  568. if (*mac->tx_status & PAS_STATUS_SOFT)
  569. reg |= PAS_IOB_DMA_TXCH_RESET_SINTC;
  570. if (*mac->tx_status & PAS_STATUS_ERROR)
  571. reg |= PAS_IOB_DMA_TXCH_RESET_DINTC;
  572. write_iob_reg(mac, PAS_IOB_DMA_TXCH_RESET(mac->dma_txch), reg);
  573. return IRQ_HANDLED;
  574. }
  575. static void pasemi_adjust_link(struct net_device *dev)
  576. {
  577. struct pasemi_mac *mac = netdev_priv(dev);
  578. int msg;
  579. unsigned int flags;
  580. unsigned int new_flags;
  581. if (!mac->phydev->link) {
  582. /* If no link, MAC speed settings don't matter. Just report
  583. * link down and return.
  584. */
  585. if (mac->link && netif_msg_link(mac))
  586. printk(KERN_INFO "%s: Link is down.\n", dev->name);
  587. netif_carrier_off(dev);
  588. mac->link = 0;
  589. return;
  590. } else
  591. netif_carrier_on(dev);
  592. flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
  593. new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M |
  594. PAS_MAC_CFG_PCFG_TSR_M);
  595. if (!mac->phydev->duplex)
  596. new_flags |= PAS_MAC_CFG_PCFG_HD;
  597. switch (mac->phydev->speed) {
  598. case 1000:
  599. new_flags |= PAS_MAC_CFG_PCFG_SPD_1G |
  600. PAS_MAC_CFG_PCFG_TSR_1G;
  601. break;
  602. case 100:
  603. new_flags |= PAS_MAC_CFG_PCFG_SPD_100M |
  604. PAS_MAC_CFG_PCFG_TSR_100M;
  605. break;
  606. case 10:
  607. new_flags |= PAS_MAC_CFG_PCFG_SPD_10M |
  608. PAS_MAC_CFG_PCFG_TSR_10M;
  609. break;
  610. default:
  611. printk("Unsupported speed %d\n", mac->phydev->speed);
  612. }
  613. /* Print on link or speed/duplex change */
  614. msg = mac->link != mac->phydev->link || flags != new_flags;
  615. mac->duplex = mac->phydev->duplex;
  616. mac->speed = mac->phydev->speed;
  617. mac->link = mac->phydev->link;
  618. if (new_flags != flags)
  619. write_mac_reg(mac, PAS_MAC_CFG_PCFG, new_flags);
  620. if (msg && netif_msg_link(mac))
  621. printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n",
  622. dev->name, mac->speed, mac->duplex ? "full" : "half");
  623. }
  624. static int pasemi_mac_phy_init(struct net_device *dev)
  625. {
  626. struct pasemi_mac *mac = netdev_priv(dev);
  627. struct device_node *dn, *phy_dn;
  628. struct phy_device *phydev;
  629. unsigned int phy_id;
  630. const phandle *ph;
  631. const unsigned int *prop;
  632. struct resource r;
  633. int ret;
  634. dn = pci_device_to_OF_node(mac->pdev);
  635. ph = of_get_property(dn, "phy-handle", NULL);
  636. if (!ph)
  637. return -ENODEV;
  638. phy_dn = of_find_node_by_phandle(*ph);
  639. prop = of_get_property(phy_dn, "reg", NULL);
  640. ret = of_address_to_resource(phy_dn->parent, 0, &r);
  641. if (ret)
  642. goto err;
  643. phy_id = *prop;
  644. snprintf(mac->phy_id, BUS_ID_SIZE, PHY_ID_FMT, (int)r.start, phy_id);
  645. of_node_put(phy_dn);
  646. mac->link = 0;
  647. mac->speed = 0;
  648. mac->duplex = -1;
  649. phydev = phy_connect(dev, mac->phy_id, &pasemi_adjust_link, 0, PHY_INTERFACE_MODE_SGMII);
  650. if (IS_ERR(phydev)) {
  651. printk(KERN_ERR "%s: Could not attach to phy\n", dev->name);
  652. return PTR_ERR(phydev);
  653. }
  654. mac->phydev = phydev;
  655. return 0;
  656. err:
  657. of_node_put(phy_dn);
  658. return -ENODEV;
  659. }
  660. static int pasemi_mac_open(struct net_device *dev)
  661. {
  662. struct pasemi_mac *mac = netdev_priv(dev);
  663. int base_irq;
  664. unsigned int flags;
  665. int ret;
  666. /* enable rx section */
  667. write_dma_reg(mac, PAS_DMA_COM_RXCMD, PAS_DMA_COM_RXCMD_EN);
  668. /* enable tx section */
  669. write_dma_reg(mac, PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN);
  670. flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) |
  671. PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) |
  672. PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12);
  673. write_mac_reg(mac, PAS_MAC_CFG_TXP, flags);
  674. write_iob_reg(mac, PAS_IOB_DMA_RXCH_CFG(mac->dma_rxch),
  675. PAS_IOB_DMA_RXCH_CFG_CNTTH(0));
  676. write_iob_reg(mac, PAS_IOB_DMA_TXCH_CFG(mac->dma_txch),
  677. PAS_IOB_DMA_TXCH_CFG_CNTTH(128));
  678. /* Clear out any residual packet count state from firmware */
  679. pasemi_mac_restart_rx_intr(mac);
  680. pasemi_mac_restart_tx_intr(mac);
  681. /* 0xffffff is max value, about 16ms */
  682. write_iob_reg(mac, PAS_IOB_DMA_COM_TIMEOUTCFG,
  683. PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0xffffff));
  684. ret = pasemi_mac_setup_rx_resources(dev);
  685. if (ret)
  686. goto out_rx_resources;
  687. ret = pasemi_mac_setup_tx_resources(dev);
  688. if (ret)
  689. goto out_tx_resources;
  690. write_mac_reg(mac, PAS_MAC_IPC_CHNL,
  691. PAS_MAC_IPC_CHNL_DCHNO(mac->dma_rxch) |
  692. PAS_MAC_IPC_CHNL_BCH(mac->dma_rxch));
  693. /* enable rx if */
  694. write_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
  695. PAS_DMA_RXINT_RCMDSTA_EN);
  696. /* enable rx channel */
  697. write_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch),
  698. PAS_DMA_RXCHAN_CCMDSTA_EN |
  699. PAS_DMA_RXCHAN_CCMDSTA_DU);
  700. /* enable tx channel */
  701. write_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch),
  702. PAS_DMA_TXCHAN_TCMDSTA_EN);
  703. pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE);
  704. flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PE |
  705. PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE;
  706. if (mac->type == MAC_TYPE_GMAC)
  707. flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G;
  708. else
  709. flags |= PAS_MAC_CFG_PCFG_TSR_10G | PAS_MAC_CFG_PCFG_SPD_10G;
  710. /* Enable interface in MAC */
  711. write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
  712. ret = pasemi_mac_phy_init(dev);
  713. /* Some configs don't have PHYs (XAUI etc), so don't complain about
  714. * failed init due to -ENODEV.
  715. */
  716. if (ret && ret != -ENODEV)
  717. dev_warn(&mac->pdev->dev, "phy init failed: %d\n", ret);
  718. netif_start_queue(dev);
  719. napi_enable(&mac->napi);
  720. /* Interrupts are a bit different for our DMA controller: While
  721. * it's got one a regular PCI device header, the interrupt there
  722. * is really the base of the range it's using. Each tx and rx
  723. * channel has it's own interrupt source.
  724. */
  725. base_irq = virq_to_hw(mac->dma_pdev->irq);
  726. mac->tx_irq = irq_create_mapping(NULL, base_irq + mac->dma_txch);
  727. mac->rx_irq = irq_create_mapping(NULL, base_irq + 20 + mac->dma_txch);
  728. ret = request_irq(mac->tx_irq, &pasemi_mac_tx_intr, IRQF_DISABLED,
  729. mac->tx->irq_name, dev);
  730. if (ret) {
  731. dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
  732. base_irq + mac->dma_txch, ret);
  733. goto out_tx_int;
  734. }
  735. ret = request_irq(mac->rx_irq, &pasemi_mac_rx_intr, IRQF_DISABLED,
  736. mac->rx->irq_name, dev);
  737. if (ret) {
  738. dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
  739. base_irq + 20 + mac->dma_rxch, ret);
  740. goto out_rx_int;
  741. }
  742. if (mac->phydev)
  743. phy_start(mac->phydev);
  744. return 0;
  745. out_rx_int:
  746. free_irq(mac->tx_irq, dev);
  747. out_tx_int:
  748. napi_disable(&mac->napi);
  749. netif_stop_queue(dev);
  750. pasemi_mac_free_tx_resources(dev);
  751. out_tx_resources:
  752. pasemi_mac_free_rx_resources(dev);
  753. out_rx_resources:
  754. return ret;
  755. }
  756. #define MAX_RETRIES 5000
  757. static int pasemi_mac_close(struct net_device *dev)
  758. {
  759. struct pasemi_mac *mac = netdev_priv(dev);
  760. unsigned int stat;
  761. int retries;
  762. if (mac->phydev) {
  763. phy_stop(mac->phydev);
  764. phy_disconnect(mac->phydev);
  765. }
  766. netif_stop_queue(dev);
  767. napi_disable(&mac->napi);
  768. /* Clean out any pending buffers */
  769. pasemi_mac_clean_tx(mac);
  770. pasemi_mac_clean_rx(mac, RX_RING_SIZE);
  771. /* Disable interface */
  772. write_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), PAS_DMA_TXCHAN_TCMDSTA_ST);
  773. write_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if), PAS_DMA_RXINT_RCMDSTA_ST);
  774. write_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), PAS_DMA_RXCHAN_CCMDSTA_ST);
  775. for (retries = 0; retries < MAX_RETRIES; retries++) {
  776. stat = read_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch));
  777. if (!(stat & PAS_DMA_TXCHAN_TCMDSTA_ACT))
  778. break;
  779. cond_resched();
  780. }
  781. if (stat & PAS_DMA_TXCHAN_TCMDSTA_ACT)
  782. dev_err(&mac->dma_pdev->dev, "Failed to stop tx channel\n");
  783. for (retries = 0; retries < MAX_RETRIES; retries++) {
  784. stat = read_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch));
  785. if (!(stat & PAS_DMA_RXCHAN_CCMDSTA_ACT))
  786. break;
  787. cond_resched();
  788. }
  789. if (stat & PAS_DMA_RXCHAN_CCMDSTA_ACT)
  790. dev_err(&mac->dma_pdev->dev, "Failed to stop rx channel\n");
  791. for (retries = 0; retries < MAX_RETRIES; retries++) {
  792. stat = read_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
  793. if (!(stat & PAS_DMA_RXINT_RCMDSTA_ACT))
  794. break;
  795. cond_resched();
  796. }
  797. if (stat & PAS_DMA_RXINT_RCMDSTA_ACT)
  798. dev_err(&mac->dma_pdev->dev, "Failed to stop rx interface\n");
  799. /* Then, disable the channel. This must be done separately from
  800. * stopping, since you can't disable when active.
  801. */
  802. write_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), 0);
  803. write_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), 0);
  804. write_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0);
  805. free_irq(mac->tx_irq, dev);
  806. free_irq(mac->rx_irq, dev);
  807. /* Free resources */
  808. pasemi_mac_free_rx_resources(dev);
  809. pasemi_mac_free_tx_resources(dev);
  810. return 0;
  811. }
  812. static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev)
  813. {
  814. struct pasemi_mac *mac = netdev_priv(dev);
  815. struct pasemi_mac_txring *txring;
  816. u64 dflags, mactx;
  817. dma_addr_t map[MAX_SKB_FRAGS+1];
  818. unsigned int map_size[MAX_SKB_FRAGS+1];
  819. unsigned long flags;
  820. int i, nfrags;
  821. dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_SS | XCT_MACTX_CRC_PAD;
  822. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  823. const unsigned char *nh = skb_network_header(skb);
  824. switch (ip_hdr(skb)->protocol) {
  825. case IPPROTO_TCP:
  826. dflags |= XCT_MACTX_CSUM_TCP;
  827. dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
  828. dflags |= XCT_MACTX_IPO(nh - skb->data);
  829. break;
  830. case IPPROTO_UDP:
  831. dflags |= XCT_MACTX_CSUM_UDP;
  832. dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
  833. dflags |= XCT_MACTX_IPO(nh - skb->data);
  834. break;
  835. }
  836. }
  837. nfrags = skb_shinfo(skb)->nr_frags;
  838. map[0] = pci_map_single(mac->dma_pdev, skb->data, skb_headlen(skb),
  839. PCI_DMA_TODEVICE);
  840. map_size[0] = skb_headlen(skb);
  841. if (dma_mapping_error(map[0]))
  842. goto out_err_nolock;
  843. for (i = 0; i < nfrags; i++) {
  844. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  845. map[i+1] = pci_map_page(mac->dma_pdev, frag->page,
  846. frag->page_offset, frag->size,
  847. PCI_DMA_TODEVICE);
  848. map_size[i+1] = frag->size;
  849. if (dma_mapping_error(map[i+1])) {
  850. nfrags = i;
  851. goto out_err_nolock;
  852. }
  853. }
  854. mactx = dflags | XCT_MACTX_LLEN(skb->len);
  855. txring = mac->tx;
  856. spin_lock_irqsave(&txring->lock, flags);
  857. /* Avoid stepping on the same cache line that the DMA controller
  858. * is currently about to send, so leave at least 8 words available.
  859. * Total free space needed is mactx + fragments + 8
  860. */
  861. if (RING_AVAIL(txring) < nfrags + 10) {
  862. /* no room -- stop the queue and wait for tx intr */
  863. netif_stop_queue(dev);
  864. goto out_err;
  865. }
  866. TX_RING(mac, txring->next_to_fill) = mactx;
  867. txring->next_to_fill++;
  868. TX_RING_INFO(mac, txring->next_to_fill).skb = skb;
  869. for (i = 0; i <= nfrags; i++) {
  870. TX_RING(mac, txring->next_to_fill+i) =
  871. XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]);
  872. TX_RING_INFO(mac, txring->next_to_fill+i).dma = map[i];
  873. }
  874. /* We have to add an even number of 8-byte entries to the ring
  875. * even if the last one is unused. That means always an odd number
  876. * of pointers + one mactx descriptor.
  877. */
  878. if (nfrags & 1)
  879. nfrags++;
  880. txring->next_to_fill = (txring->next_to_fill + nfrags + 1) &
  881. (TX_RING_SIZE-1);
  882. dev->stats.tx_packets++;
  883. dev->stats.tx_bytes += skb->len;
  884. spin_unlock_irqrestore(&txring->lock, flags);
  885. write_dma_reg(mac, PAS_DMA_TXCHAN_INCR(mac->dma_txch), (nfrags+2) >> 1);
  886. return NETDEV_TX_OK;
  887. out_err:
  888. spin_unlock_irqrestore(&txring->lock, flags);
  889. out_err_nolock:
  890. while (nfrags--)
  891. pci_unmap_single(mac->dma_pdev, map[nfrags], map_size[nfrags],
  892. PCI_DMA_TODEVICE);
  893. return NETDEV_TX_BUSY;
  894. }
  895. static void pasemi_mac_set_rx_mode(struct net_device *dev)
  896. {
  897. struct pasemi_mac *mac = netdev_priv(dev);
  898. unsigned int flags;
  899. flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
  900. /* Set promiscuous */
  901. if (dev->flags & IFF_PROMISC)
  902. flags |= PAS_MAC_CFG_PCFG_PR;
  903. else
  904. flags &= ~PAS_MAC_CFG_PCFG_PR;
  905. write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
  906. }
  907. static int pasemi_mac_poll(struct napi_struct *napi, int budget)
  908. {
  909. struct pasemi_mac *mac = container_of(napi, struct pasemi_mac, napi);
  910. struct net_device *dev = mac->netdev;
  911. int pkts;
  912. pasemi_mac_clean_tx(mac);
  913. pkts = pasemi_mac_clean_rx(mac, budget);
  914. if (pkts < budget) {
  915. /* all done, no more packets present */
  916. netif_rx_complete(dev, napi);
  917. pasemi_mac_restart_rx_intr(mac);
  918. }
  919. return pkts;
  920. }
  921. static void __iomem * __devinit map_onedev(struct pci_dev *p, int index)
  922. {
  923. struct device_node *dn;
  924. void __iomem *ret;
  925. dn = pci_device_to_OF_node(p);
  926. if (!dn)
  927. goto fallback;
  928. ret = of_iomap(dn, index);
  929. if (!ret)
  930. goto fallback;
  931. return ret;
  932. fallback:
  933. /* This is hardcoded and ugly, but we have some firmware versions
  934. * that don't provide the register space in the device tree. Luckily
  935. * they are at well-known locations so we can just do the math here.
  936. */
  937. return ioremap(0xe0000000 + (p->devfn << 12), 0x2000);
  938. }
  939. static int __devinit pasemi_mac_map_regs(struct pasemi_mac *mac)
  940. {
  941. struct resource res;
  942. struct device_node *dn;
  943. int err;
  944. mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL);
  945. if (!mac->dma_pdev) {
  946. dev_err(&mac->pdev->dev, "Can't find DMA Controller\n");
  947. return -ENODEV;
  948. }
  949. mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
  950. if (!mac->iob_pdev) {
  951. dev_err(&mac->pdev->dev, "Can't find I/O Bridge\n");
  952. return -ENODEV;
  953. }
  954. mac->regs = map_onedev(mac->pdev, 0);
  955. mac->dma_regs = map_onedev(mac->dma_pdev, 0);
  956. mac->iob_regs = map_onedev(mac->iob_pdev, 0);
  957. if (!mac->regs || !mac->dma_regs || !mac->iob_regs) {
  958. dev_err(&mac->pdev->dev, "Can't map registers\n");
  959. return -ENODEV;
  960. }
  961. /* The dma status structure is located in the I/O bridge, and
  962. * is cache coherent.
  963. */
  964. if (!dma_status) {
  965. dn = pci_device_to_OF_node(mac->iob_pdev);
  966. if (dn)
  967. err = of_address_to_resource(dn, 1, &res);
  968. if (!dn || err) {
  969. /* Fallback for old firmware */
  970. res.start = 0xfd800000;
  971. res.end = res.start + 0x1000;
  972. }
  973. dma_status = __ioremap(res.start, res.end-res.start, 0);
  974. }
  975. return 0;
  976. }
  977. static int __devinit
  978. pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  979. {
  980. static int index = 0;
  981. struct net_device *dev;
  982. struct pasemi_mac *mac;
  983. int err;
  984. DECLARE_MAC_BUF(mac_buf);
  985. err = pci_enable_device(pdev);
  986. if (err)
  987. return err;
  988. dev = alloc_etherdev(sizeof(struct pasemi_mac));
  989. if (dev == NULL) {
  990. dev_err(&pdev->dev,
  991. "pasemi_mac: Could not allocate ethernet device.\n");
  992. err = -ENOMEM;
  993. goto out_disable_device;
  994. }
  995. pci_set_drvdata(pdev, dev);
  996. SET_NETDEV_DEV(dev, &pdev->dev);
  997. mac = netdev_priv(dev);
  998. mac->pdev = pdev;
  999. mac->netdev = dev;
  1000. netif_napi_add(dev, &mac->napi, pasemi_mac_poll, 64);
  1001. dev->features = NETIF_F_HW_CSUM | NETIF_F_LLTX | NETIF_F_SG;
  1002. /* These should come out of the device tree eventually */
  1003. mac->dma_txch = index;
  1004. mac->dma_rxch = index;
  1005. /* We probe GMAC before XAUI, but the DMA interfaces are
  1006. * in XAUI, GMAC order.
  1007. */
  1008. if (index < 4)
  1009. mac->dma_if = index + 2;
  1010. else
  1011. mac->dma_if = index - 4;
  1012. index++;
  1013. switch (pdev->device) {
  1014. case 0xa005:
  1015. mac->type = MAC_TYPE_GMAC;
  1016. break;
  1017. case 0xa006:
  1018. mac->type = MAC_TYPE_XAUI;
  1019. break;
  1020. default:
  1021. err = -ENODEV;
  1022. goto out;
  1023. }
  1024. /* get mac addr from device tree */
  1025. if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) {
  1026. err = -ENODEV;
  1027. goto out;
  1028. }
  1029. memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr));
  1030. dev->open = pasemi_mac_open;
  1031. dev->stop = pasemi_mac_close;
  1032. dev->hard_start_xmit = pasemi_mac_start_tx;
  1033. dev->set_multicast_list = pasemi_mac_set_rx_mode;
  1034. err = pasemi_mac_map_regs(mac);
  1035. if (err)
  1036. goto out;
  1037. mac->rx_status = &dma_status->rx_sta[mac->dma_rxch];
  1038. mac->tx_status = &dma_status->tx_sta[mac->dma_txch];
  1039. mac->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
  1040. /* Enable most messages by default */
  1041. mac->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
  1042. err = register_netdev(dev);
  1043. if (err) {
  1044. dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n",
  1045. err);
  1046. goto out;
  1047. } else if netif_msg_probe(mac)
  1048. printk(KERN_INFO "%s: PA Semi %s: intf %d, txch %d, rxch %d, "
  1049. "hw addr %s\n",
  1050. dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI",
  1051. mac->dma_if, mac->dma_txch, mac->dma_rxch,
  1052. print_mac(mac_buf, dev->dev_addr));
  1053. return err;
  1054. out:
  1055. if (mac->iob_pdev)
  1056. pci_dev_put(mac->iob_pdev);
  1057. if (mac->dma_pdev)
  1058. pci_dev_put(mac->dma_pdev);
  1059. if (mac->dma_regs)
  1060. iounmap(mac->dma_regs);
  1061. if (mac->iob_regs)
  1062. iounmap(mac->iob_regs);
  1063. if (mac->regs)
  1064. iounmap(mac->regs);
  1065. free_netdev(dev);
  1066. out_disable_device:
  1067. pci_disable_device(pdev);
  1068. return err;
  1069. }
  1070. static void __devexit pasemi_mac_remove(struct pci_dev *pdev)
  1071. {
  1072. struct net_device *netdev = pci_get_drvdata(pdev);
  1073. struct pasemi_mac *mac;
  1074. if (!netdev)
  1075. return;
  1076. mac = netdev_priv(netdev);
  1077. unregister_netdev(netdev);
  1078. pci_disable_device(pdev);
  1079. pci_dev_put(mac->dma_pdev);
  1080. pci_dev_put(mac->iob_pdev);
  1081. iounmap(mac->regs);
  1082. iounmap(mac->dma_regs);
  1083. iounmap(mac->iob_regs);
  1084. pci_set_drvdata(pdev, NULL);
  1085. free_netdev(netdev);
  1086. }
  1087. static struct pci_device_id pasemi_mac_pci_tbl[] = {
  1088. { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) },
  1089. { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) },
  1090. { },
  1091. };
  1092. MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl);
  1093. static struct pci_driver pasemi_mac_driver = {
  1094. .name = "pasemi_mac",
  1095. .id_table = pasemi_mac_pci_tbl,
  1096. .probe = pasemi_mac_probe,
  1097. .remove = __devexit_p(pasemi_mac_remove),
  1098. };
  1099. static void __exit pasemi_mac_cleanup_module(void)
  1100. {
  1101. pci_unregister_driver(&pasemi_mac_driver);
  1102. __iounmap(dma_status);
  1103. dma_status = NULL;
  1104. }
  1105. int pasemi_mac_init_module(void)
  1106. {
  1107. return pci_register_driver(&pasemi_mac_driver);
  1108. }
  1109. module_init(pasemi_mac_init_module);
  1110. module_exit(pasemi_mac_cleanup_module);