core.c 45 KB

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  1. /*
  2. * Copyright (c) 2008, Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. /* Implementation of the main "ATH" layer. */
  17. #include "core.h"
  18. #include "regd.h"
  19. static int ath_outdoor; /* enable outdoor use */
  20. static u32 ath_chainmask_sel_up_rssi_thres =
  21. ATH_CHAINMASK_SEL_UP_RSSI_THRES;
  22. static u32 ath_chainmask_sel_down_rssi_thres =
  23. ATH_CHAINMASK_SEL_DOWN_RSSI_THRES;
  24. static u32 ath_chainmask_sel_period =
  25. ATH_CHAINMASK_SEL_TIMEOUT;
  26. /* return bus cachesize in 4B word units */
  27. static void bus_read_cachesize(struct ath_softc *sc, int *csz)
  28. {
  29. u8 u8tmp;
  30. pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
  31. *csz = (int)u8tmp;
  32. /*
  33. * This check was put in to avoid "unplesant" consequences if
  34. * the bootrom has not fully initialized all PCI devices.
  35. * Sometimes the cache line size register is not set
  36. */
  37. if (*csz == 0)
  38. *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
  39. }
  40. /*
  41. * Set current operating mode
  42. *
  43. * This function initializes and fills the rate table in the ATH object based
  44. * on the operating mode. The blink rates are also set up here, although
  45. * they have been superceeded by the ath_led module.
  46. */
  47. static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
  48. {
  49. const struct ath9k_rate_table *rt;
  50. int i;
  51. memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
  52. rt = ath9k_hw_getratetable(sc->sc_ah, mode);
  53. BUG_ON(!rt);
  54. for (i = 0; i < rt->rateCount; i++)
  55. sc->sc_rixmap[rt->info[i].rateCode] = (u8) i;
  56. memzero(sc->sc_hwmap, sizeof(sc->sc_hwmap));
  57. for (i = 0; i < 256; i++) {
  58. u8 ix = rt->rateCodeToIndex[i];
  59. if (ix == 0xff)
  60. continue;
  61. sc->sc_hwmap[i].ieeerate =
  62. rt->info[ix].dot11Rate & IEEE80211_RATE_VAL;
  63. sc->sc_hwmap[i].rateKbps = rt->info[ix].rateKbps;
  64. if (rt->info[ix].shortPreamble ||
  65. rt->info[ix].phy == PHY_OFDM) {
  66. /* XXX: Handle this */
  67. }
  68. /* NB: this uses the last entry if the rate isn't found */
  69. /* XXX beware of overlow */
  70. }
  71. sc->sc_currates = rt;
  72. sc->sc_curmode = mode;
  73. /*
  74. * All protection frames are transmited at 2Mb/s for
  75. * 11g, otherwise at 1Mb/s.
  76. * XXX select protection rate index from rate table.
  77. */
  78. sc->sc_protrix = (mode == ATH9K_MODE_11G ? 1 : 0);
  79. }
  80. /*
  81. * Set up rate table (legacy rates)
  82. */
  83. static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
  84. {
  85. struct ath_hal *ah = sc->sc_ah;
  86. const struct ath9k_rate_table *rt = NULL;
  87. struct ieee80211_supported_band *sband;
  88. struct ieee80211_rate *rate;
  89. int i, maxrates;
  90. switch (band) {
  91. case IEEE80211_BAND_2GHZ:
  92. rt = ath9k_hw_getratetable(ah, ATH9K_MODE_11G);
  93. break;
  94. case IEEE80211_BAND_5GHZ:
  95. rt = ath9k_hw_getratetable(ah, ATH9K_MODE_11A);
  96. break;
  97. default:
  98. break;
  99. }
  100. if (rt == NULL)
  101. return;
  102. sband = &sc->sbands[band];
  103. rate = sc->rates[band];
  104. if (rt->rateCount > ATH_RATE_MAX)
  105. maxrates = ATH_RATE_MAX;
  106. else
  107. maxrates = rt->rateCount;
  108. for (i = 0; i < maxrates; i++) {
  109. rate[i].bitrate = rt->info[i].rateKbps / 100;
  110. rate[i].hw_value = rt->info[i].rateCode;
  111. sband->n_bitrates++;
  112. DPRINTF(sc, ATH_DBG_CONFIG,
  113. "%s: Rate: %2dMbps, ratecode: %2d\n",
  114. __func__,
  115. rate[i].bitrate / 10,
  116. rate[i].hw_value);
  117. }
  118. }
  119. /*
  120. * Set up channel list
  121. */
  122. static int ath_setup_channels(struct ath_softc *sc)
  123. {
  124. struct ath_hal *ah = sc->sc_ah;
  125. int nchan, i, a = 0, b = 0;
  126. u8 regclassids[ATH_REGCLASSIDS_MAX];
  127. u32 nregclass = 0;
  128. struct ieee80211_supported_band *band_2ghz;
  129. struct ieee80211_supported_band *band_5ghz;
  130. struct ieee80211_channel *chan_2ghz;
  131. struct ieee80211_channel *chan_5ghz;
  132. struct ath9k_channel *c;
  133. /* Fill in ah->ah_channels */
  134. if (!ath9k_regd_init_channels(ah,
  135. ATH_CHAN_MAX,
  136. (u32 *)&nchan,
  137. regclassids,
  138. ATH_REGCLASSIDS_MAX,
  139. &nregclass,
  140. CTRY_DEFAULT,
  141. false,
  142. 1)) {
  143. u32 rd = ah->ah_currentRD;
  144. DPRINTF(sc, ATH_DBG_FATAL,
  145. "%s: unable to collect channel list; "
  146. "regdomain likely %u country code %u\n",
  147. __func__, rd, CTRY_DEFAULT);
  148. return -EINVAL;
  149. }
  150. band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
  151. band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
  152. chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
  153. chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
  154. for (i = 0; i < nchan; i++) {
  155. c = &ah->ah_channels[i];
  156. if (IS_CHAN_2GHZ(c)) {
  157. chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
  158. chan_2ghz[a].center_freq = c->channel;
  159. chan_2ghz[a].max_power = c->maxTxPower;
  160. if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
  161. chan_2ghz[a].flags |=
  162. IEEE80211_CHAN_NO_IBSS;
  163. if (c->channelFlags & CHANNEL_PASSIVE)
  164. chan_2ghz[a].flags |=
  165. IEEE80211_CHAN_PASSIVE_SCAN;
  166. band_2ghz->n_channels = ++a;
  167. DPRINTF(sc, ATH_DBG_CONFIG,
  168. "%s: 2MHz channel: %d, "
  169. "channelFlags: 0x%x\n",
  170. __func__,
  171. c->channel,
  172. c->channelFlags);
  173. } else if (IS_CHAN_5GHZ(c)) {
  174. chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
  175. chan_5ghz[b].center_freq = c->channel;
  176. chan_5ghz[b].max_power = c->maxTxPower;
  177. if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
  178. chan_5ghz[b].flags |=
  179. IEEE80211_CHAN_NO_IBSS;
  180. if (c->channelFlags & CHANNEL_PASSIVE)
  181. chan_5ghz[b].flags |=
  182. IEEE80211_CHAN_PASSIVE_SCAN;
  183. band_5ghz->n_channels = ++b;
  184. DPRINTF(sc, ATH_DBG_CONFIG,
  185. "%s: 5MHz channel: %d, "
  186. "channelFlags: 0x%x\n",
  187. __func__,
  188. c->channel,
  189. c->channelFlags);
  190. }
  191. }
  192. return 0;
  193. }
  194. /*
  195. * Determine mode from channel flags
  196. *
  197. * This routine will provide the enumerated WIRELESSS_MODE value based
  198. * on the settings of the channel flags. If ho valid set of flags
  199. * exist, the lowest mode (11b) is selected.
  200. */
  201. static enum wireless_mode ath_chan2mode(struct ath9k_channel *chan)
  202. {
  203. if (chan->chanmode == CHANNEL_A)
  204. return ATH9K_MODE_11A;
  205. else if (chan->chanmode == CHANNEL_G)
  206. return ATH9K_MODE_11G;
  207. else if (chan->chanmode == CHANNEL_B)
  208. return ATH9K_MODE_11B;
  209. else if (chan->chanmode == CHANNEL_A_HT20)
  210. return ATH9K_MODE_11NA_HT20;
  211. else if (chan->chanmode == CHANNEL_G_HT20)
  212. return ATH9K_MODE_11NG_HT20;
  213. else if (chan->chanmode == CHANNEL_A_HT40PLUS)
  214. return ATH9K_MODE_11NA_HT40PLUS;
  215. else if (chan->chanmode == CHANNEL_A_HT40MINUS)
  216. return ATH9K_MODE_11NA_HT40MINUS;
  217. else if (chan->chanmode == CHANNEL_G_HT40PLUS)
  218. return ATH9K_MODE_11NG_HT40PLUS;
  219. else if (chan->chanmode == CHANNEL_G_HT40MINUS)
  220. return ATH9K_MODE_11NG_HT40MINUS;
  221. /* NB: should not get here */
  222. return ATH9K_MODE_11B;
  223. }
  224. /*
  225. * Stop the device, grabbing the top-level lock to protect
  226. * against concurrent entry through ath_init (which can happen
  227. * if another thread does a system call and the thread doing the
  228. * stop is preempted).
  229. */
  230. static int ath_stop(struct ath_softc *sc)
  231. {
  232. struct ath_hal *ah = sc->sc_ah;
  233. DPRINTF(sc, ATH_DBG_CONFIG, "%s: invalid %u\n",
  234. __func__, sc->sc_invalid);
  235. /*
  236. * Shutdown the hardware and driver:
  237. * stop output from above
  238. * reset 802.11 state machine
  239. * (sends station deassoc/deauth frames)
  240. * turn off timers
  241. * disable interrupts
  242. * clear transmit machinery
  243. * clear receive machinery
  244. * turn off the radio
  245. * reclaim beacon resources
  246. *
  247. * Note that some of this work is not possible if the
  248. * hardware is gone (invalid).
  249. */
  250. if (!sc->sc_invalid)
  251. ath9k_hw_set_interrupts(ah, 0);
  252. ath_draintxq(sc, false);
  253. if (!sc->sc_invalid) {
  254. ath_stoprecv(sc);
  255. ath9k_hw_phy_disable(ah);
  256. } else
  257. sc->sc_rxlink = NULL;
  258. return 0;
  259. }
  260. /*
  261. * Set the current channel
  262. *
  263. * Set/change channels. If the channel is really being changed, it's done
  264. * by reseting the chip. To accomplish this we must first cleanup any pending
  265. * DMA, then restart stuff after a la ath_init.
  266. */
  267. int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
  268. {
  269. struct ath_hal *ah = sc->sc_ah;
  270. bool fastcc = true, stopped;
  271. enum ath9k_ht_macmode ht_macmode;
  272. if (sc->sc_invalid) /* if the device is invalid or removed */
  273. return -EIO;
  274. DPRINTF(sc, ATH_DBG_CONFIG,
  275. "%s: %u (%u MHz) -> %u (%u MHz), cflags:%x\n",
  276. __func__,
  277. ath9k_hw_mhz2ieee(ah, sc->sc_curchan.channel,
  278. sc->sc_curchan.channelFlags),
  279. sc->sc_curchan.channel,
  280. ath9k_hw_mhz2ieee(ah, hchan->channel, hchan->channelFlags),
  281. hchan->channel, hchan->channelFlags);
  282. ht_macmode = ath_cwm_macmode(sc);
  283. if (hchan->channel != sc->sc_curchan.channel ||
  284. hchan->channelFlags != sc->sc_curchan.channelFlags ||
  285. sc->sc_update_chainmask || sc->sc_full_reset) {
  286. int status;
  287. /*
  288. * This is only performed if the channel settings have
  289. * actually changed.
  290. *
  291. * To switch channels clear any pending DMA operations;
  292. * wait long enough for the RX fifo to drain, reset the
  293. * hardware at the new frequency, and then re-enable
  294. * the relevant bits of the h/w.
  295. */
  296. ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */
  297. ath_draintxq(sc, false); /* clear pending tx frames */
  298. stopped = ath_stoprecv(sc); /* turn off frame recv */
  299. /* XXX: do not flush receive queue here. We don't want
  300. * to flush data frames already in queue because of
  301. * changing channel. */
  302. if (!stopped || sc->sc_full_reset)
  303. fastcc = false;
  304. spin_lock_bh(&sc->sc_resetlock);
  305. if (!ath9k_hw_reset(ah, sc->sc_opmode, hchan,
  306. ht_macmode, sc->sc_tx_chainmask,
  307. sc->sc_rx_chainmask,
  308. sc->sc_ht_extprotspacing,
  309. fastcc, &status)) {
  310. DPRINTF(sc, ATH_DBG_FATAL,
  311. "%s: unable to reset channel %u (%uMhz) "
  312. "flags 0x%x hal status %u\n", __func__,
  313. ath9k_hw_mhz2ieee(ah, hchan->channel,
  314. hchan->channelFlags),
  315. hchan->channel, hchan->channelFlags, status);
  316. spin_unlock_bh(&sc->sc_resetlock);
  317. return -EIO;
  318. }
  319. spin_unlock_bh(&sc->sc_resetlock);
  320. sc->sc_curchan = *hchan;
  321. sc->sc_update_chainmask = 0;
  322. sc->sc_full_reset = 0;
  323. /* Re-enable rx framework */
  324. if (ath_startrecv(sc) != 0) {
  325. DPRINTF(sc, ATH_DBG_FATAL,
  326. "%s: unable to restart recv logic\n", __func__);
  327. return -EIO;
  328. }
  329. /*
  330. * Change channels and update the h/w rate map
  331. * if we're switching; e.g. 11a to 11b/g.
  332. */
  333. ath_setcurmode(sc, ath_chan2mode(hchan));
  334. ath_update_txpow(sc); /* update tx power state */
  335. /*
  336. * Re-enable interrupts.
  337. */
  338. ath9k_hw_set_interrupts(ah, sc->sc_imask);
  339. }
  340. return 0;
  341. }
  342. /**********************/
  343. /* Chainmask Handling */
  344. /**********************/
  345. static void ath_chainmask_sel_timertimeout(unsigned long data)
  346. {
  347. struct ath_chainmask_sel *cm = (struct ath_chainmask_sel *)data;
  348. cm->switch_allowed = 1;
  349. }
  350. /* Start chainmask select timer */
  351. static void ath_chainmask_sel_timerstart(struct ath_chainmask_sel *cm)
  352. {
  353. cm->switch_allowed = 0;
  354. mod_timer(&cm->timer, ath_chainmask_sel_period);
  355. }
  356. /* Stop chainmask select timer */
  357. static void ath_chainmask_sel_timerstop(struct ath_chainmask_sel *cm)
  358. {
  359. cm->switch_allowed = 0;
  360. del_timer_sync(&cm->timer);
  361. }
  362. static void ath_chainmask_sel_init(struct ath_softc *sc, struct ath_node *an)
  363. {
  364. struct ath_chainmask_sel *cm = &an->an_chainmask_sel;
  365. memzero(cm, sizeof(struct ath_chainmask_sel));
  366. cm->cur_tx_mask = sc->sc_tx_chainmask;
  367. cm->cur_rx_mask = sc->sc_rx_chainmask;
  368. cm->tx_avgrssi = ATH_RSSI_DUMMY_MARKER;
  369. setup_timer(&cm->timer,
  370. ath_chainmask_sel_timertimeout, (unsigned long) cm);
  371. }
  372. int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an)
  373. {
  374. struct ath_chainmask_sel *cm = &an->an_chainmask_sel;
  375. /*
  376. * Disable auto-swtiching in one of the following if conditions.
  377. * sc_chainmask_auto_sel is used for internal global auto-switching
  378. * enabled/disabled setting
  379. */
  380. if (sc->sc_ah->ah_caps.tx_chainmask != ATH_CHAINMASK_SEL_3X3) {
  381. cm->cur_tx_mask = sc->sc_tx_chainmask;
  382. return cm->cur_tx_mask;
  383. }
  384. if (cm->tx_avgrssi == ATH_RSSI_DUMMY_MARKER)
  385. return cm->cur_tx_mask;
  386. if (cm->switch_allowed) {
  387. /* Switch down from tx 3 to tx 2. */
  388. if (cm->cur_tx_mask == ATH_CHAINMASK_SEL_3X3 &&
  389. ATH_RSSI_OUT(cm->tx_avgrssi) >=
  390. ath_chainmask_sel_down_rssi_thres) {
  391. cm->cur_tx_mask = sc->sc_tx_chainmask;
  392. /* Don't let another switch happen until
  393. * this timer expires */
  394. ath_chainmask_sel_timerstart(cm);
  395. }
  396. /* Switch up from tx 2 to 3. */
  397. else if (cm->cur_tx_mask == sc->sc_tx_chainmask &&
  398. ATH_RSSI_OUT(cm->tx_avgrssi) <=
  399. ath_chainmask_sel_up_rssi_thres) {
  400. cm->cur_tx_mask = ATH_CHAINMASK_SEL_3X3;
  401. /* Don't let another switch happen
  402. * until this timer expires */
  403. ath_chainmask_sel_timerstart(cm);
  404. }
  405. }
  406. return cm->cur_tx_mask;
  407. }
  408. /*
  409. * Update tx/rx chainmask. For legacy association,
  410. * hard code chainmask to 1x1, for 11n association, use
  411. * the chainmask configuration.
  412. */
  413. void ath_update_chainmask(struct ath_softc *sc, int is_ht)
  414. {
  415. sc->sc_update_chainmask = 1;
  416. if (is_ht) {
  417. sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
  418. sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
  419. } else {
  420. sc->sc_tx_chainmask = 1;
  421. sc->sc_rx_chainmask = 1;
  422. }
  423. DPRINTF(sc, ATH_DBG_CONFIG, "%s: tx chmask: %d, rx chmask: %d\n",
  424. __func__, sc->sc_tx_chainmask, sc->sc_rx_chainmask);
  425. }
  426. /******************/
  427. /* VAP management */
  428. /******************/
  429. /*
  430. * VAP in Listen mode
  431. *
  432. * This routine brings the VAP out of the down state into a "listen" state
  433. * where it waits for association requests. This is used in AP and AdHoc
  434. * modes.
  435. */
  436. int ath_vap_listen(struct ath_softc *sc, int if_id)
  437. {
  438. struct ath_hal *ah = sc->sc_ah;
  439. struct ath_vap *avp;
  440. u32 rfilt = 0;
  441. DECLARE_MAC_BUF(mac);
  442. avp = sc->sc_vaps[if_id];
  443. if (avp == NULL) {
  444. DPRINTF(sc, ATH_DBG_FATAL, "%s: invalid interface id %u\n",
  445. __func__, if_id);
  446. return -EINVAL;
  447. }
  448. #ifdef CONFIG_SLOW_ANT_DIV
  449. ath_slow_ant_div_stop(&sc->sc_antdiv);
  450. #endif
  451. /* update ratectrl about the new state */
  452. ath_rate_newstate(sc, avp);
  453. rfilt = ath_calcrxfilter(sc);
  454. ath9k_hw_setrxfilter(ah, rfilt);
  455. if (sc->sc_opmode == ATH9K_M_STA || sc->sc_opmode == ATH9K_M_IBSS) {
  456. memcpy(sc->sc_curbssid, ath_bcast_mac, ETH_ALEN);
  457. ath9k_hw_write_associd(ah, sc->sc_curbssid, sc->sc_curaid);
  458. } else
  459. sc->sc_curaid = 0;
  460. DPRINTF(sc, ATH_DBG_CONFIG,
  461. "%s: RX filter 0x%x bssid %s aid 0x%x\n",
  462. __func__, rfilt, print_mac(mac,
  463. sc->sc_curbssid), sc->sc_curaid);
  464. /*
  465. * XXXX
  466. * Disable BMISS interrupt when we're not associated
  467. */
  468. ath9k_hw_set_interrupts(ah,
  469. sc->sc_imask & ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS));
  470. sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  471. /* need to reconfigure the beacons when it moves to RUN */
  472. sc->sc_beacons = 0;
  473. return 0;
  474. }
  475. int ath_vap_attach(struct ath_softc *sc,
  476. int if_id,
  477. struct ieee80211_vif *if_data,
  478. enum ath9k_opmode opmode)
  479. {
  480. struct ath_vap *avp;
  481. if (if_id >= ATH_BCBUF || sc->sc_vaps[if_id] != NULL) {
  482. DPRINTF(sc, ATH_DBG_FATAL,
  483. "%s: Invalid interface id = %u\n", __func__, if_id);
  484. return -EINVAL;
  485. }
  486. switch (opmode) {
  487. case ATH9K_M_STA:
  488. case ATH9K_M_IBSS:
  489. case ATH9K_M_MONITOR:
  490. break;
  491. case ATH9K_M_HOSTAP:
  492. /* XXX not right, beacon buffer is allocated on RUN trans */
  493. if (list_empty(&sc->sc_bbuf))
  494. return -ENOMEM;
  495. break;
  496. default:
  497. return -EINVAL;
  498. }
  499. /* create ath_vap */
  500. avp = kmalloc(sizeof(struct ath_vap), GFP_KERNEL);
  501. if (avp == NULL)
  502. return -ENOMEM;
  503. memzero(avp, sizeof(struct ath_vap));
  504. avp->av_if_data = if_data;
  505. /* Set the VAP opmode */
  506. avp->av_opmode = opmode;
  507. avp->av_bslot = -1;
  508. INIT_LIST_HEAD(&avp->av_mcastq.axq_q);
  509. INIT_LIST_HEAD(&avp->av_mcastq.axq_acq);
  510. spin_lock_init(&avp->av_mcastq.axq_lock);
  511. ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
  512. sc->sc_vaps[if_id] = avp;
  513. sc->sc_nvaps++;
  514. /* Set the device opmode */
  515. sc->sc_opmode = opmode;
  516. /* default VAP configuration */
  517. avp->av_config.av_fixed_rateset = IEEE80211_FIXED_RATE_NONE;
  518. avp->av_config.av_fixed_retryset = 0x03030303;
  519. return 0;
  520. }
  521. int ath_vap_detach(struct ath_softc *sc, int if_id)
  522. {
  523. struct ath_hal *ah = sc->sc_ah;
  524. struct ath_vap *avp;
  525. avp = sc->sc_vaps[if_id];
  526. if (avp == NULL) {
  527. DPRINTF(sc, ATH_DBG_FATAL, "%s: invalid interface id %u\n",
  528. __func__, if_id);
  529. return -EINVAL;
  530. }
  531. /*
  532. * Quiesce the hardware while we remove the vap. In
  533. * particular we need to reclaim all references to the
  534. * vap state by any frames pending on the tx queues.
  535. *
  536. * XXX can we do this w/o affecting other vap's?
  537. */
  538. ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */
  539. ath_draintxq(sc, false); /* stop xmit side */
  540. ath_stoprecv(sc); /* stop recv side */
  541. ath_flushrecv(sc); /* flush recv queue */
  542. /* Reclaim any pending mcast bufs on the vap. */
  543. ath_tx_draintxq(sc, &avp->av_mcastq, false);
  544. kfree(avp);
  545. sc->sc_vaps[if_id] = NULL;
  546. sc->sc_nvaps--;
  547. return 0;
  548. }
  549. int ath_vap_config(struct ath_softc *sc,
  550. int if_id, struct ath_vap_config *if_config)
  551. {
  552. struct ath_vap *avp;
  553. if (if_id >= ATH_BCBUF) {
  554. DPRINTF(sc, ATH_DBG_FATAL,
  555. "%s: Invalid interface id = %u\n", __func__, if_id);
  556. return -EINVAL;
  557. }
  558. avp = sc->sc_vaps[if_id];
  559. ASSERT(avp != NULL);
  560. if (avp)
  561. memcpy(&avp->av_config, if_config, sizeof(avp->av_config));
  562. return 0;
  563. }
  564. /********/
  565. /* Core */
  566. /********/
  567. int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan)
  568. {
  569. struct ath_hal *ah = sc->sc_ah;
  570. int status;
  571. int error = 0;
  572. enum ath9k_ht_macmode ht_macmode = ath_cwm_macmode(sc);
  573. DPRINTF(sc, ATH_DBG_CONFIG, "%s: mode %d\n", __func__, sc->sc_opmode);
  574. /*
  575. * Stop anything previously setup. This is safe
  576. * whether this is the first time through or not.
  577. */
  578. ath_stop(sc);
  579. /* Initialize chanmask selection */
  580. sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
  581. sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
  582. /* Reset SERDES registers */
  583. ath9k_hw_configpcipowersave(ah, 0);
  584. /*
  585. * The basic interface to setting the hardware in a good
  586. * state is ``reset''. On return the hardware is known to
  587. * be powered up and with interrupts disabled. This must
  588. * be followed by initialization of the appropriate bits
  589. * and then setup of the interrupt mask.
  590. */
  591. sc->sc_curchan = *initial_chan;
  592. spin_lock_bh(&sc->sc_resetlock);
  593. if (!ath9k_hw_reset(ah, sc->sc_opmode, &sc->sc_curchan, ht_macmode,
  594. sc->sc_tx_chainmask, sc->sc_rx_chainmask,
  595. sc->sc_ht_extprotspacing, false, &status)) {
  596. DPRINTF(sc, ATH_DBG_FATAL,
  597. "%s: unable to reset hardware; hal status %u "
  598. "(freq %u flags 0x%x)\n", __func__, status,
  599. sc->sc_curchan.channel, sc->sc_curchan.channelFlags);
  600. error = -EIO;
  601. spin_unlock_bh(&sc->sc_resetlock);
  602. goto done;
  603. }
  604. spin_unlock_bh(&sc->sc_resetlock);
  605. /*
  606. * This is needed only to setup initial state
  607. * but it's best done after a reset.
  608. */
  609. ath_update_txpow(sc);
  610. /*
  611. * Setup the hardware after reset:
  612. * The receive engine is set going.
  613. * Frame transmit is handled entirely
  614. * in the frame output path; there's nothing to do
  615. * here except setup the interrupt mask.
  616. */
  617. if (ath_startrecv(sc) != 0) {
  618. DPRINTF(sc, ATH_DBG_FATAL,
  619. "%s: unable to start recv logic\n", __func__);
  620. error = -EIO;
  621. goto done;
  622. }
  623. /* Setup our intr mask. */
  624. sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
  625. | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
  626. | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
  627. if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
  628. sc->sc_imask |= ATH9K_INT_GTT;
  629. if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
  630. sc->sc_imask |= ATH9K_INT_CST;
  631. /*
  632. * Enable MIB interrupts when there are hardware phy counters.
  633. * Note we only do this (at the moment) for station mode.
  634. */
  635. if (ath9k_hw_phycounters(ah) &&
  636. ((sc->sc_opmode == ATH9K_M_STA) || (sc->sc_opmode == ATH9K_M_IBSS)))
  637. sc->sc_imask |= ATH9K_INT_MIB;
  638. /*
  639. * Some hardware processes the TIM IE and fires an
  640. * interrupt when the TIM bit is set. For hardware
  641. * that does, if not overridden by configuration,
  642. * enable the TIM interrupt when operating as station.
  643. */
  644. if ((ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
  645. (sc->sc_opmode == ATH9K_M_STA) &&
  646. !sc->sc_config.swBeaconProcess)
  647. sc->sc_imask |= ATH9K_INT_TIM;
  648. /*
  649. * Don't enable interrupts here as we've not yet built our
  650. * vap and node data structures, which will be needed as soon
  651. * as we start receiving.
  652. */
  653. ath_setcurmode(sc, ath_chan2mode(initial_chan));
  654. /* XXX: we must make sure h/w is ready and clear invalid flag
  655. * before turning on interrupt. */
  656. sc->sc_invalid = 0;
  657. done:
  658. return error;
  659. }
  660. int ath_reset(struct ath_softc *sc, bool retry_tx)
  661. {
  662. struct ath_hal *ah = sc->sc_ah;
  663. int status;
  664. int error = 0;
  665. enum ath9k_ht_macmode ht_macmode = ath_cwm_macmode(sc);
  666. ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */
  667. ath_draintxq(sc, retry_tx); /* stop xmit */
  668. ath_stoprecv(sc); /* stop recv */
  669. ath_flushrecv(sc); /* flush recv queue */
  670. /* Reset chip */
  671. spin_lock_bh(&sc->sc_resetlock);
  672. if (!ath9k_hw_reset(ah, sc->sc_opmode, &sc->sc_curchan,
  673. ht_macmode,
  674. sc->sc_tx_chainmask, sc->sc_rx_chainmask,
  675. sc->sc_ht_extprotspacing, false, &status)) {
  676. DPRINTF(sc, ATH_DBG_FATAL,
  677. "%s: unable to reset hardware; hal status %u\n",
  678. __func__, status);
  679. error = -EIO;
  680. }
  681. spin_unlock_bh(&sc->sc_resetlock);
  682. if (ath_startrecv(sc) != 0) /* restart recv */
  683. DPRINTF(sc, ATH_DBG_FATAL,
  684. "%s: unable to start recv logic\n", __func__);
  685. /*
  686. * We may be doing a reset in response to a request
  687. * that changes the channel so update any state that
  688. * might change as a result.
  689. */
  690. ath_setcurmode(sc, ath_chan2mode(&sc->sc_curchan));
  691. ath_update_txpow(sc);
  692. if (sc->sc_beacons)
  693. ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
  694. ath9k_hw_set_interrupts(ah, sc->sc_imask);
  695. /* Restart the txq */
  696. if (retry_tx) {
  697. int i;
  698. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  699. if (ATH_TXQ_SETUP(sc, i)) {
  700. spin_lock_bh(&sc->sc_txq[i].axq_lock);
  701. ath_txq_schedule(sc, &sc->sc_txq[i]);
  702. spin_unlock_bh(&sc->sc_txq[i].axq_lock);
  703. }
  704. }
  705. }
  706. return error;
  707. }
  708. int ath_suspend(struct ath_softc *sc)
  709. {
  710. struct ath_hal *ah = sc->sc_ah;
  711. /* No I/O if device has been surprise removed */
  712. if (sc->sc_invalid)
  713. return -EIO;
  714. /* Shut off the interrupt before setting sc->sc_invalid to '1' */
  715. ath9k_hw_set_interrupts(ah, 0);
  716. /* XXX: we must make sure h/w will not generate any interrupt
  717. * before setting the invalid flag. */
  718. sc->sc_invalid = 1;
  719. /* disable HAL and put h/w to sleep */
  720. ath9k_hw_disable(sc->sc_ah);
  721. ath9k_hw_configpcipowersave(sc->sc_ah, 1);
  722. return 0;
  723. }
  724. /* Interrupt handler. Most of the actual processing is deferred.
  725. * It's the caller's responsibility to ensure the chip is awake. */
  726. irqreturn_t ath_isr(int irq, void *dev)
  727. {
  728. struct ath_softc *sc = dev;
  729. struct ath_hal *ah = sc->sc_ah;
  730. enum ath9k_int status;
  731. bool sched = false;
  732. do {
  733. if (sc->sc_invalid) {
  734. /*
  735. * The hardware is not ready/present, don't
  736. * touch anything. Note this can happen early
  737. * on if the IRQ is shared.
  738. */
  739. return IRQ_NONE;
  740. }
  741. if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
  742. return IRQ_NONE;
  743. }
  744. /*
  745. * Figure out the reason(s) for the interrupt. Note
  746. * that the hal returns a pseudo-ISR that may include
  747. * bits we haven't explicitly enabled so we mask the
  748. * value to insure we only process bits we requested.
  749. */
  750. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  751. status &= sc->sc_imask; /* discard unasked-for bits */
  752. /*
  753. * If there are no status bits set, then this interrupt was not
  754. * for me (should have been caught above).
  755. */
  756. if (!status)
  757. return IRQ_NONE;
  758. sc->sc_intrstatus = status;
  759. if (status & ATH9K_INT_FATAL) {
  760. /* need a chip reset */
  761. sched = true;
  762. } else if (status & ATH9K_INT_RXORN) {
  763. /* need a chip reset */
  764. sched = true;
  765. } else {
  766. if (status & ATH9K_INT_SWBA) {
  767. /* schedule a tasklet for beacon handling */
  768. tasklet_schedule(&sc->bcon_tasklet);
  769. }
  770. if (status & ATH9K_INT_RXEOL) {
  771. /*
  772. * NB: the hardware should re-read the link when
  773. * RXE bit is written, but it doesn't work
  774. * at least on older hardware revs.
  775. */
  776. sched = true;
  777. }
  778. if (status & ATH9K_INT_TXURN)
  779. /* bump tx trigger level */
  780. ath9k_hw_updatetxtriglevel(ah, true);
  781. /* XXX: optimize this */
  782. if (status & ATH9K_INT_RX)
  783. sched = true;
  784. if (status & ATH9K_INT_TX)
  785. sched = true;
  786. if (status & ATH9K_INT_BMISS)
  787. sched = true;
  788. /* carrier sense timeout */
  789. if (status & ATH9K_INT_CST)
  790. sched = true;
  791. if (status & ATH9K_INT_MIB) {
  792. /*
  793. * Disable interrupts until we service the MIB
  794. * interrupt; otherwise it will continue to
  795. * fire.
  796. */
  797. ath9k_hw_set_interrupts(ah, 0);
  798. /*
  799. * Let the hal handle the event. We assume
  800. * it will clear whatever condition caused
  801. * the interrupt.
  802. */
  803. ath9k_hw_procmibevent(ah, &sc->sc_halstats);
  804. ath9k_hw_set_interrupts(ah, sc->sc_imask);
  805. }
  806. if (status & ATH9K_INT_TIM_TIMER) {
  807. if (!(ah->ah_caps.hw_caps &
  808. ATH9K_HW_CAP_AUTOSLEEP)) {
  809. /* Clear RxAbort bit so that we can
  810. * receive frames */
  811. ath9k_hw_setrxabort(ah, 0);
  812. sched = true;
  813. }
  814. }
  815. }
  816. } while (0);
  817. if (sched) {
  818. /* turn off every interrupt except SWBA */
  819. ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
  820. tasklet_schedule(&sc->intr_tq);
  821. }
  822. return IRQ_HANDLED;
  823. }
  824. /* Deferred interrupt processing */
  825. static void ath9k_tasklet(unsigned long data)
  826. {
  827. struct ath_softc *sc = (struct ath_softc *)data;
  828. u32 status = sc->sc_intrstatus;
  829. if (status & ATH9K_INT_FATAL) {
  830. /* need a chip reset */
  831. ath_reset(sc, false);
  832. return;
  833. } else {
  834. if (status &
  835. (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
  836. /* XXX: fill me in */
  837. /*
  838. if (status & ATH9K_INT_RXORN) {
  839. }
  840. if (status & ATH9K_INT_RXEOL) {
  841. }
  842. */
  843. spin_lock_bh(&sc->sc_rxflushlock);
  844. ath_rx_tasklet(sc, 0);
  845. spin_unlock_bh(&sc->sc_rxflushlock);
  846. }
  847. /* XXX: optimize this */
  848. if (status & ATH9K_INT_TX)
  849. ath_tx_tasklet(sc);
  850. /* XXX: fill me in */
  851. /*
  852. if (status & ATH9K_INT_BMISS) {
  853. }
  854. if (status & (ATH9K_INT_TIM | ATH9K_INT_DTIMSYNC)) {
  855. if (status & ATH9K_INT_TIM) {
  856. }
  857. if (status & ATH9K_INT_DTIMSYNC) {
  858. }
  859. }
  860. */
  861. }
  862. /* re-enable hardware interrupt */
  863. ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
  864. }
  865. int ath_init(u16 devid, struct ath_softc *sc)
  866. {
  867. struct ath_hal *ah = NULL;
  868. int status;
  869. int error = 0, i;
  870. int csz = 0;
  871. u32 rd;
  872. /* XXX: hardware will not be ready until ath_open() being called */
  873. sc->sc_invalid = 1;
  874. sc->sc_debug = DBG_DEFAULT;
  875. DPRINTF(sc, ATH_DBG_CONFIG, "%s: devid 0x%x\n", __func__, devid);
  876. /* Initialize tasklet */
  877. tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
  878. tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
  879. (unsigned long)sc);
  880. /*
  881. * Cache line size is used to size and align various
  882. * structures used to communicate with the hardware.
  883. */
  884. bus_read_cachesize(sc, &csz);
  885. /* XXX assert csz is non-zero */
  886. sc->sc_cachelsz = csz << 2; /* convert to bytes */
  887. spin_lock_init(&sc->sc_resetlock);
  888. ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
  889. if (ah == NULL) {
  890. DPRINTF(sc, ATH_DBG_FATAL,
  891. "%s: unable to attach hardware; HAL status %u\n",
  892. __func__, status);
  893. error = -ENXIO;
  894. goto bad;
  895. }
  896. sc->sc_ah = ah;
  897. /* Get the chipset-specific aggr limit. */
  898. sc->sc_rtsaggrlimit = ah->ah_caps.rts_aggr_limit;
  899. /* Get the hardware key cache size. */
  900. sc->sc_keymax = ah->ah_caps.keycache_size;
  901. if (sc->sc_keymax > ATH_KEYMAX) {
  902. DPRINTF(sc, ATH_DBG_KEYCACHE,
  903. "%s: Warning, using only %u entries in %u key cache\n",
  904. __func__, ATH_KEYMAX, sc->sc_keymax);
  905. sc->sc_keymax = ATH_KEYMAX;
  906. }
  907. /*
  908. * Reset the key cache since some parts do not
  909. * reset the contents on initial power up.
  910. */
  911. for (i = 0; i < sc->sc_keymax; i++)
  912. ath9k_hw_keyreset(ah, (u16) i);
  913. /*
  914. * Mark key cache slots associated with global keys
  915. * as in use. If we knew TKIP was not to be used we
  916. * could leave the +32, +64, and +32+64 slots free.
  917. * XXX only for splitmic.
  918. */
  919. for (i = 0; i < IEEE80211_WEP_NKID; i++) {
  920. set_bit(i, sc->sc_keymap);
  921. set_bit(i + 32, sc->sc_keymap);
  922. set_bit(i + 64, sc->sc_keymap);
  923. set_bit(i + 32 + 64, sc->sc_keymap);
  924. }
  925. /*
  926. * Collect the channel list using the default country
  927. * code and including outdoor channels. The 802.11 layer
  928. * is resposible for filtering this list based on settings
  929. * like the phy mode.
  930. */
  931. rd = ah->ah_currentRD;
  932. error = ath_setup_channels(sc);
  933. if (error)
  934. goto bad;
  935. /* default to STA mode */
  936. sc->sc_opmode = ATH9K_M_MONITOR;
  937. /* Setup rate tables */
  938. ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
  939. ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
  940. /* NB: setup here so ath_rate_update is happy */
  941. ath_setcurmode(sc, ATH9K_MODE_11A);
  942. /*
  943. * Allocate hardware transmit queues: one queue for
  944. * beacon frames and one data queue for each QoS
  945. * priority. Note that the hal handles reseting
  946. * these queues at the needed time.
  947. */
  948. sc->sc_bhalq = ath_beaconq_setup(ah);
  949. if (sc->sc_bhalq == -1) {
  950. DPRINTF(sc, ATH_DBG_FATAL,
  951. "%s: unable to setup a beacon xmit queue\n", __func__);
  952. error = -EIO;
  953. goto bad2;
  954. }
  955. sc->sc_cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
  956. if (sc->sc_cabq == NULL) {
  957. DPRINTF(sc, ATH_DBG_FATAL,
  958. "%s: unable to setup CAB xmit queue\n", __func__);
  959. error = -EIO;
  960. goto bad2;
  961. }
  962. sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
  963. ath_cabq_update(sc);
  964. for (i = 0; i < ARRAY_SIZE(sc->sc_haltype2q); i++)
  965. sc->sc_haltype2q[i] = -1;
  966. /* Setup data queues */
  967. /* NB: ensure BK queue is the lowest priority h/w queue */
  968. if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
  969. DPRINTF(sc, ATH_DBG_FATAL,
  970. "%s: unable to setup xmit queue for BK traffic\n",
  971. __func__);
  972. error = -EIO;
  973. goto bad2;
  974. }
  975. if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
  976. DPRINTF(sc, ATH_DBG_FATAL,
  977. "%s: unable to setup xmit queue for BE traffic\n",
  978. __func__);
  979. error = -EIO;
  980. goto bad2;
  981. }
  982. if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
  983. DPRINTF(sc, ATH_DBG_FATAL,
  984. "%s: unable to setup xmit queue for VI traffic\n",
  985. __func__);
  986. error = -EIO;
  987. goto bad2;
  988. }
  989. if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
  990. DPRINTF(sc, ATH_DBG_FATAL,
  991. "%s: unable to setup xmit queue for VO traffic\n",
  992. __func__);
  993. error = -EIO;
  994. goto bad2;
  995. }
  996. sc->sc_rc = ath_rate_attach(ah);
  997. if (sc->sc_rc == NULL) {
  998. error = EIO;
  999. goto bad2;
  1000. }
  1001. if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
  1002. ATH9K_CIPHER_TKIP, NULL)) {
  1003. /*
  1004. * Whether we should enable h/w TKIP MIC.
  1005. * XXX: if we don't support WME TKIP MIC, then we wouldn't
  1006. * report WMM capable, so it's always safe to turn on
  1007. * TKIP MIC in this case.
  1008. */
  1009. ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
  1010. 0, 1, NULL);
  1011. }
  1012. /*
  1013. * Check whether the separate key cache entries
  1014. * are required to handle both tx+rx MIC keys.
  1015. * With split mic keys the number of stations is limited
  1016. * to 27 otherwise 59.
  1017. */
  1018. if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
  1019. ATH9K_CIPHER_TKIP, NULL)
  1020. && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
  1021. ATH9K_CIPHER_MIC, NULL)
  1022. && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
  1023. 0, NULL))
  1024. sc->sc_splitmic = 1;
  1025. /* turn on mcast key search if possible */
  1026. if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
  1027. (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
  1028. 1, NULL);
  1029. sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
  1030. sc->sc_config.txpowlimit_override = 0;
  1031. /* 11n Capabilities */
  1032. if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
  1033. sc->sc_txaggr = 1;
  1034. sc->sc_rxaggr = 1;
  1035. }
  1036. sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
  1037. sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
  1038. /* Configuration for rx chain detection */
  1039. sc->sc_rxchaindetect_ref = 0;
  1040. sc->sc_rxchaindetect_thresh5GHz = 35;
  1041. sc->sc_rxchaindetect_thresh2GHz = 35;
  1042. sc->sc_rxchaindetect_delta5GHz = 30;
  1043. sc->sc_rxchaindetect_delta2GHz = 30;
  1044. ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
  1045. sc->sc_defant = ath9k_hw_getdefantenna(ah);
  1046. ath9k_hw_getmac(ah, sc->sc_myaddr);
  1047. if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
  1048. ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
  1049. ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
  1050. ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
  1051. }
  1052. sc->sc_slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
  1053. /* initialize beacon slots */
  1054. for (i = 0; i < ARRAY_SIZE(sc->sc_bslot); i++)
  1055. sc->sc_bslot[i] = ATH_IF_ID_ANY;
  1056. /* save MISC configurations */
  1057. sc->sc_config.swBeaconProcess = 1;
  1058. #ifdef CONFIG_SLOW_ANT_DIV
  1059. /* range is 40 - 255, we use something in the middle */
  1060. ath_slow_ant_div_init(&sc->sc_antdiv, sc, 0x127);
  1061. #endif
  1062. return 0;
  1063. bad2:
  1064. /* cleanup tx queues */
  1065. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
  1066. if (ATH_TXQ_SETUP(sc, i))
  1067. ath_tx_cleanupq(sc, &sc->sc_txq[i]);
  1068. bad:
  1069. if (ah)
  1070. ath9k_hw_detach(ah);
  1071. return error;
  1072. }
  1073. void ath_deinit(struct ath_softc *sc)
  1074. {
  1075. struct ath_hal *ah = sc->sc_ah;
  1076. int i;
  1077. DPRINTF(sc, ATH_DBG_CONFIG, "%s\n", __func__);
  1078. ath_stop(sc);
  1079. if (!sc->sc_invalid)
  1080. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  1081. ath_rate_detach(sc->sc_rc);
  1082. /* cleanup tx queues */
  1083. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
  1084. if (ATH_TXQ_SETUP(sc, i))
  1085. ath_tx_cleanupq(sc, &sc->sc_txq[i]);
  1086. ath9k_hw_detach(ah);
  1087. }
  1088. /*******************/
  1089. /* Node Management */
  1090. /*******************/
  1091. struct ath_node *ath_node_attach(struct ath_softc *sc, u8 *addr, int if_id)
  1092. {
  1093. struct ath_vap *avp;
  1094. struct ath_node *an;
  1095. DECLARE_MAC_BUF(mac);
  1096. avp = sc->sc_vaps[if_id];
  1097. ASSERT(avp != NULL);
  1098. /* mac80211 sta_notify callback is from an IRQ context, so no sleep */
  1099. an = kmalloc(sizeof(struct ath_node), GFP_ATOMIC);
  1100. if (an == NULL)
  1101. return NULL;
  1102. memzero(an, sizeof(*an));
  1103. an->an_sc = sc;
  1104. memcpy(an->an_addr, addr, ETH_ALEN);
  1105. atomic_set(&an->an_refcnt, 1);
  1106. /* set up per-node tx/rx state */
  1107. ath_tx_node_init(sc, an);
  1108. ath_rx_node_init(sc, an);
  1109. ath_chainmask_sel_init(sc, an);
  1110. ath_chainmask_sel_timerstart(&an->an_chainmask_sel);
  1111. list_add(&an->list, &sc->node_list);
  1112. return an;
  1113. }
  1114. void ath_node_detach(struct ath_softc *sc, struct ath_node *an, bool bh_flag)
  1115. {
  1116. unsigned long flags;
  1117. DECLARE_MAC_BUF(mac);
  1118. ath_chainmask_sel_timerstop(&an->an_chainmask_sel);
  1119. an->an_flags |= ATH_NODE_CLEAN;
  1120. ath_tx_node_cleanup(sc, an, bh_flag);
  1121. ath_rx_node_cleanup(sc, an);
  1122. ath_tx_node_free(sc, an);
  1123. ath_rx_node_free(sc, an);
  1124. spin_lock_irqsave(&sc->node_lock, flags);
  1125. list_del(&an->list);
  1126. spin_unlock_irqrestore(&sc->node_lock, flags);
  1127. kfree(an);
  1128. }
  1129. /* Finds a node and increases the refcnt if found */
  1130. struct ath_node *ath_node_get(struct ath_softc *sc, u8 *addr)
  1131. {
  1132. struct ath_node *an = NULL, *an_found = NULL;
  1133. if (list_empty(&sc->node_list)) /* FIXME */
  1134. goto out;
  1135. list_for_each_entry(an, &sc->node_list, list) {
  1136. if (!compare_ether_addr(an->an_addr, addr)) {
  1137. atomic_inc(&an->an_refcnt);
  1138. an_found = an;
  1139. break;
  1140. }
  1141. }
  1142. out:
  1143. return an_found;
  1144. }
  1145. /* Decrements the refcnt and if it drops to zero, detach the node */
  1146. void ath_node_put(struct ath_softc *sc, struct ath_node *an, bool bh_flag)
  1147. {
  1148. if (atomic_dec_and_test(&an->an_refcnt))
  1149. ath_node_detach(sc, an, bh_flag);
  1150. }
  1151. /* Finds a node, doesn't increment refcnt. Caller must hold sc->node_lock */
  1152. struct ath_node *ath_node_find(struct ath_softc *sc, u8 *addr)
  1153. {
  1154. struct ath_node *an = NULL, *an_found = NULL;
  1155. if (list_empty(&sc->node_list))
  1156. return NULL;
  1157. list_for_each_entry(an, &sc->node_list, list)
  1158. if (!compare_ether_addr(an->an_addr, addr)) {
  1159. an_found = an;
  1160. break;
  1161. }
  1162. return an_found;
  1163. }
  1164. /*
  1165. * Set up New Node
  1166. *
  1167. * Setup driver-specific state for a newly associated node. This routine
  1168. * really only applies if compression or XR are enabled, there is no code
  1169. * covering any other cases.
  1170. */
  1171. void ath_newassoc(struct ath_softc *sc,
  1172. struct ath_node *an, int isnew, int isuapsd)
  1173. {
  1174. int tidno;
  1175. /* if station reassociates, tear down the aggregation state. */
  1176. if (!isnew) {
  1177. for (tidno = 0; tidno < WME_NUM_TID; tidno++) {
  1178. if (sc->sc_txaggr)
  1179. ath_tx_aggr_teardown(sc, an, tidno);
  1180. if (sc->sc_rxaggr)
  1181. ath_rx_aggr_teardown(sc, an, tidno);
  1182. }
  1183. }
  1184. an->an_flags = 0;
  1185. }
  1186. /**************/
  1187. /* Encryption */
  1188. /**************/
  1189. void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot)
  1190. {
  1191. ath9k_hw_keyreset(sc->sc_ah, keyix);
  1192. if (freeslot)
  1193. clear_bit(keyix, sc->sc_keymap);
  1194. }
  1195. int ath_keyset(struct ath_softc *sc,
  1196. u16 keyix,
  1197. struct ath9k_keyval *hk,
  1198. const u8 mac[ETH_ALEN])
  1199. {
  1200. bool status;
  1201. status = ath9k_hw_set_keycache_entry(sc->sc_ah,
  1202. keyix, hk, mac, false);
  1203. return status != false;
  1204. }
  1205. /***********************/
  1206. /* TX Power/Regulatory */
  1207. /***********************/
  1208. /*
  1209. * Set Transmit power in HAL
  1210. *
  1211. * This routine makes the actual HAL calls to set the new transmit power
  1212. * limit.
  1213. */
  1214. void ath_update_txpow(struct ath_softc *sc)
  1215. {
  1216. struct ath_hal *ah = sc->sc_ah;
  1217. u32 txpow;
  1218. if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
  1219. ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
  1220. /* read back in case value is clamped */
  1221. ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
  1222. sc->sc_curtxpow = txpow;
  1223. }
  1224. }
  1225. /* Return the current country and domain information */
  1226. void ath_get_currentCountry(struct ath_softc *sc,
  1227. struct ath9k_country_entry *ctry)
  1228. {
  1229. ath9k_regd_get_current_country(sc->sc_ah, ctry);
  1230. /* If HAL not specific yet, since it is band dependent,
  1231. * use the one we passed in. */
  1232. if (ctry->countryCode == CTRY_DEFAULT) {
  1233. ctry->iso[0] = 0;
  1234. ctry->iso[1] = 0;
  1235. } else if (ctry->iso[0] && ctry->iso[1]) {
  1236. if (!ctry->iso[2]) {
  1237. if (ath_outdoor)
  1238. ctry->iso[2] = 'O';
  1239. else
  1240. ctry->iso[2] = 'I';
  1241. }
  1242. }
  1243. }
  1244. /**************************/
  1245. /* Slow Antenna Diversity */
  1246. /**************************/
  1247. void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
  1248. struct ath_softc *sc,
  1249. int32_t rssitrig)
  1250. {
  1251. int trig;
  1252. /* antdivf_rssitrig can range from 40 - 0xff */
  1253. trig = (rssitrig > 0xff) ? 0xff : rssitrig;
  1254. trig = (rssitrig < 40) ? 40 : rssitrig;
  1255. antdiv->antdiv_sc = sc;
  1256. antdiv->antdivf_rssitrig = trig;
  1257. }
  1258. void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
  1259. u8 num_antcfg,
  1260. const u8 *bssid)
  1261. {
  1262. antdiv->antdiv_num_antcfg =
  1263. num_antcfg < ATH_ANT_DIV_MAX_CFG ?
  1264. num_antcfg : ATH_ANT_DIV_MAX_CFG;
  1265. antdiv->antdiv_state = ATH_ANT_DIV_IDLE;
  1266. antdiv->antdiv_curcfg = 0;
  1267. antdiv->antdiv_bestcfg = 0;
  1268. antdiv->antdiv_laststatetsf = 0;
  1269. memcpy(antdiv->antdiv_bssid, bssid, sizeof(antdiv->antdiv_bssid));
  1270. antdiv->antdiv_start = 1;
  1271. }
  1272. void ath_slow_ant_div_stop(struct ath_antdiv *antdiv)
  1273. {
  1274. antdiv->antdiv_start = 0;
  1275. }
  1276. static int32_t ath_find_max_val(int32_t *val,
  1277. u8 num_val, u8 *max_index)
  1278. {
  1279. u32 MaxVal = *val++;
  1280. u32 cur_index = 0;
  1281. *max_index = 0;
  1282. while (++cur_index < num_val) {
  1283. if (*val > MaxVal) {
  1284. MaxVal = *val;
  1285. *max_index = cur_index;
  1286. }
  1287. val++;
  1288. }
  1289. return MaxVal;
  1290. }
  1291. void ath_slow_ant_div(struct ath_antdiv *antdiv,
  1292. struct ieee80211_hdr *hdr,
  1293. struct ath_rx_status *rx_stats)
  1294. {
  1295. struct ath_softc *sc = antdiv->antdiv_sc;
  1296. struct ath_hal *ah = sc->sc_ah;
  1297. u64 curtsf = 0;
  1298. u8 bestcfg, curcfg = antdiv->antdiv_curcfg;
  1299. __le16 fc = hdr->frame_control;
  1300. if (antdiv->antdiv_start && ieee80211_is_beacon(fc)
  1301. && !compare_ether_addr(hdr->addr3, antdiv->antdiv_bssid)) {
  1302. antdiv->antdiv_lastbrssi[curcfg] = rx_stats->rs_rssi;
  1303. antdiv->antdiv_lastbtsf[curcfg] = ath9k_hw_gettsf64(sc->sc_ah);
  1304. curtsf = antdiv->antdiv_lastbtsf[curcfg];
  1305. } else {
  1306. return;
  1307. }
  1308. switch (antdiv->antdiv_state) {
  1309. case ATH_ANT_DIV_IDLE:
  1310. if ((antdiv->antdiv_lastbrssi[curcfg] <
  1311. antdiv->antdivf_rssitrig)
  1312. && ((curtsf - antdiv->antdiv_laststatetsf) >
  1313. ATH_ANT_DIV_MIN_IDLE_US)) {
  1314. curcfg++;
  1315. if (curcfg == antdiv->antdiv_num_antcfg)
  1316. curcfg = 0;
  1317. if (!ath9k_hw_select_antconfig(ah, curcfg)) {
  1318. antdiv->antdiv_bestcfg = antdiv->antdiv_curcfg;
  1319. antdiv->antdiv_curcfg = curcfg;
  1320. antdiv->antdiv_laststatetsf = curtsf;
  1321. antdiv->antdiv_state = ATH_ANT_DIV_SCAN;
  1322. }
  1323. }
  1324. break;
  1325. case ATH_ANT_DIV_SCAN:
  1326. if ((curtsf - antdiv->antdiv_laststatetsf) <
  1327. ATH_ANT_DIV_MIN_SCAN_US)
  1328. break;
  1329. curcfg++;
  1330. if (curcfg == antdiv->antdiv_num_antcfg)
  1331. curcfg = 0;
  1332. if (curcfg == antdiv->antdiv_bestcfg) {
  1333. ath_find_max_val(antdiv->antdiv_lastbrssi,
  1334. antdiv->antdiv_num_antcfg, &bestcfg);
  1335. if (!ath9k_hw_select_antconfig(ah, bestcfg)) {
  1336. antdiv->antdiv_bestcfg = bestcfg;
  1337. antdiv->antdiv_curcfg = bestcfg;
  1338. antdiv->antdiv_laststatetsf = curtsf;
  1339. antdiv->antdiv_state = ATH_ANT_DIV_IDLE;
  1340. }
  1341. } else {
  1342. if (!ath9k_hw_select_antconfig(ah, curcfg)) {
  1343. antdiv->antdiv_curcfg = curcfg;
  1344. antdiv->antdiv_laststatetsf = curtsf;
  1345. antdiv->antdiv_state = ATH_ANT_DIV_SCAN;
  1346. }
  1347. }
  1348. break;
  1349. }
  1350. }
  1351. /***********************/
  1352. /* Descriptor Handling */
  1353. /***********************/
  1354. /*
  1355. * Set up DMA descriptors
  1356. *
  1357. * This function will allocate both the DMA descriptor structure, and the
  1358. * buffers it contains. These are used to contain the descriptors used
  1359. * by the system.
  1360. */
  1361. int ath_descdma_setup(struct ath_softc *sc,
  1362. struct ath_descdma *dd,
  1363. struct list_head *head,
  1364. const char *name,
  1365. int nbuf,
  1366. int ndesc)
  1367. {
  1368. #define DS2PHYS(_dd, _ds) \
  1369. ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
  1370. #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
  1371. #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
  1372. struct ath_desc *ds;
  1373. struct ath_buf *bf;
  1374. int i, bsize, error;
  1375. DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA: %u buffers %u desc/buf\n",
  1376. __func__, name, nbuf, ndesc);
  1377. /* ath_desc must be a multiple of DWORDs */
  1378. if ((sizeof(struct ath_desc) % 4) != 0) {
  1379. DPRINTF(sc, ATH_DBG_FATAL, "%s: ath_desc not DWORD aligned\n",
  1380. __func__);
  1381. ASSERT((sizeof(struct ath_desc) % 4) == 0);
  1382. error = -ENOMEM;
  1383. goto fail;
  1384. }
  1385. dd->dd_name = name;
  1386. dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
  1387. /*
  1388. * Need additional DMA memory because we can't use
  1389. * descriptors that cross the 4K page boundary. Assume
  1390. * one skipped descriptor per 4K page.
  1391. */
  1392. if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
  1393. u32 ndesc_skipped =
  1394. ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
  1395. u32 dma_len;
  1396. while (ndesc_skipped) {
  1397. dma_len = ndesc_skipped * sizeof(struct ath_desc);
  1398. dd->dd_desc_len += dma_len;
  1399. ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
  1400. };
  1401. }
  1402. /* allocate descriptors */
  1403. dd->dd_desc = pci_alloc_consistent(sc->pdev,
  1404. dd->dd_desc_len,
  1405. &dd->dd_desc_paddr);
  1406. if (dd->dd_desc == NULL) {
  1407. error = -ENOMEM;
  1408. goto fail;
  1409. }
  1410. ds = dd->dd_desc;
  1411. DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA map: %p (%u) -> %llx (%u)\n",
  1412. __func__, dd->dd_name, ds, (u32) dd->dd_desc_len,
  1413. ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
  1414. /* allocate buffers */
  1415. bsize = sizeof(struct ath_buf) * nbuf;
  1416. bf = kmalloc(bsize, GFP_KERNEL);
  1417. if (bf == NULL) {
  1418. error = -ENOMEM;
  1419. goto fail2;
  1420. }
  1421. memzero(bf, bsize);
  1422. dd->dd_bufptr = bf;
  1423. INIT_LIST_HEAD(head);
  1424. for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
  1425. bf->bf_desc = ds;
  1426. bf->bf_daddr = DS2PHYS(dd, ds);
  1427. if (!(sc->sc_ah->ah_caps.hw_caps &
  1428. ATH9K_HW_CAP_4KB_SPLITTRANS)) {
  1429. /*
  1430. * Skip descriptor addresses which can cause 4KB
  1431. * boundary crossing (addr + length) with a 32 dword
  1432. * descriptor fetch.
  1433. */
  1434. while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
  1435. ASSERT((caddr_t) bf->bf_desc <
  1436. ((caddr_t) dd->dd_desc +
  1437. dd->dd_desc_len));
  1438. ds += ndesc;
  1439. bf->bf_desc = ds;
  1440. bf->bf_daddr = DS2PHYS(dd, ds);
  1441. }
  1442. }
  1443. list_add_tail(&bf->list, head);
  1444. }
  1445. return 0;
  1446. fail2:
  1447. pci_free_consistent(sc->pdev,
  1448. dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
  1449. fail:
  1450. memzero(dd, sizeof(*dd));
  1451. return error;
  1452. #undef ATH_DESC_4KB_BOUND_CHECK
  1453. #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
  1454. #undef DS2PHYS
  1455. }
  1456. /*
  1457. * Cleanup DMA descriptors
  1458. *
  1459. * This function will free the DMA block that was allocated for the descriptor
  1460. * pool. Since this was allocated as one "chunk", it is freed in the same
  1461. * manner.
  1462. */
  1463. void ath_descdma_cleanup(struct ath_softc *sc,
  1464. struct ath_descdma *dd,
  1465. struct list_head *head)
  1466. {
  1467. /* Free memory associated with descriptors */
  1468. pci_free_consistent(sc->pdev,
  1469. dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
  1470. INIT_LIST_HEAD(head);
  1471. kfree(dd->dd_bufptr);
  1472. memzero(dd, sizeof(*dd));
  1473. }
  1474. /*************/
  1475. /* Utilities */
  1476. /*************/
  1477. int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
  1478. {
  1479. int qnum;
  1480. switch (queue) {
  1481. case 0:
  1482. qnum = sc->sc_haltype2q[ATH9K_WME_AC_VO];
  1483. break;
  1484. case 1:
  1485. qnum = sc->sc_haltype2q[ATH9K_WME_AC_VI];
  1486. break;
  1487. case 2:
  1488. qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
  1489. break;
  1490. case 3:
  1491. qnum = sc->sc_haltype2q[ATH9K_WME_AC_BK];
  1492. break;
  1493. default:
  1494. qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
  1495. break;
  1496. }
  1497. return qnum;
  1498. }
  1499. int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
  1500. {
  1501. int qnum;
  1502. switch (queue) {
  1503. case ATH9K_WME_AC_VO:
  1504. qnum = 0;
  1505. break;
  1506. case ATH9K_WME_AC_VI:
  1507. qnum = 1;
  1508. break;
  1509. case ATH9K_WME_AC_BE:
  1510. qnum = 2;
  1511. break;
  1512. case ATH9K_WME_AC_BK:
  1513. qnum = 3;
  1514. break;
  1515. default:
  1516. qnum = -1;
  1517. break;
  1518. }
  1519. return qnum;
  1520. }
  1521. /*
  1522. * Expand time stamp to TSF
  1523. *
  1524. * Extend 15-bit time stamp from rx descriptor to
  1525. * a full 64-bit TSF using the current h/w TSF.
  1526. */
  1527. u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp)
  1528. {
  1529. u64 tsf;
  1530. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1531. if ((tsf & 0x7fff) < rstamp)
  1532. tsf -= 0x8000;
  1533. return (tsf & ~0x7fff) | rstamp;
  1534. }
  1535. /*
  1536. * Set Default Antenna
  1537. *
  1538. * Call into the HAL to set the default antenna to use. Not really valid for
  1539. * MIMO technology.
  1540. */
  1541. void ath_setdefantenna(void *context, u32 antenna)
  1542. {
  1543. struct ath_softc *sc = (struct ath_softc *)context;
  1544. struct ath_hal *ah = sc->sc_ah;
  1545. /* XXX block beacon interrupts */
  1546. ath9k_hw_setantenna(ah, antenna);
  1547. sc->sc_defant = antenna;
  1548. sc->sc_rxotherant = 0;
  1549. }
  1550. /*
  1551. * Set Slot Time
  1552. *
  1553. * This will wake up the chip if required, and set the slot time for the
  1554. * frame (maximum transmit time). Slot time is assumed to be already set
  1555. * in the ATH object member sc_slottime
  1556. */
  1557. void ath_setslottime(struct ath_softc *sc)
  1558. {
  1559. ath9k_hw_setslottime(sc->sc_ah, sc->sc_slottime);
  1560. sc->sc_updateslot = OK;
  1561. }